[PATCH 0/3] Tiger Lake: add workarounds

[PATCH 0/3] Tiger Lake: add workarounds

[Lucas De Marchi]

Same patches as extracted from https://patchwork.freedesktop.org/series/63670/
and rebased.

Michel Thierry (3):
  drm/i915/tgl: Introduce initial Tigerlake Workarounds
  drm/i915/tgl: Implement Wa_1604555607
  drm/i915/tgl: Implement Wa_1406941453

 drivers/gpu/drm/i915/gt/intel_lrc.c         |  2 +
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 52 +++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h             | 11 +++++
 drivers/gpu/drm/i915/intel_pm.c             |  4 +-
 drivers/gpu/drm/i915/intel_uncore.c         |  2 +-
 5 files changed, 66 insertions(+), 5 deletions(-)

-- 
2.21.0

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[PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Inherit workarounds from previous platforms that are still valid for
Tigerlake.

  WaPipelineFlushCoherentLines:tgl (changed register but has same name)
  WaSendPushConstantsFromMMIO:tgl
  WaAllowUMDToModifySamplerMode:tgl
  WaRsForcewakeAddDelayForAck:tgl

Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_lrc.c         |  2 ++
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
 drivers/gpu/drm/i915/i915_reg.h             |  3 ++
 drivers/gpu/drm/i915/intel_pm.c             |  4 ++-
 drivers/gpu/drm/i915/intel_uncore.c         |  2 +-
 5 files changed, 46 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 884dfc1cb033..893c58df8be0 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
 		return 0;
 
 	switch (INTEL_GEN(engine->i915)) {
+	case 12:
+		return 0;
 	case 11:
 		return 0;
 	case 10:
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 704ace01e7f5..a6eb9c6e87ec 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
 }
 
+static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
+				     struct i915_wa_list *wal)
+{
+}
+
 static void
 __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 			   struct i915_wa_list *wal,
@@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
 
 	wa_init_start(wal, name, engine->name);
 
-	if (IS_GEN(i915, 11))
+	if (IS_GEN(i915, 12))
+		tgl_ctx_workarounds_init(engine, wal);
+	else if (IS_GEN(i915, 11))
 		icl_ctx_workarounds_init(engine, wal);
 	else if (IS_CANNONLAKE(i915))
 		cnl_ctx_workarounds_init(engine, wal);
@@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
 		    GAMT_CHKN_DISABLE_L3_COH_PIPE);
 }
 
+static void
+tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
+{
+}
+
 static void
 gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-	if (IS_GEN(i915, 11))
+	if (IS_GEN(i915, 12))
+		tgl_gt_workarounds_init(i915, wal);
+	else if (IS_GEN(i915, 11))
 		icl_gt_workarounds_init(i915, wal);
 	else if (IS_CANNONLAKE(i915))
 		cnl_gt_workarounds_init(i915, wal);
@@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
 	}
 }
 
+static void tgl_whitelist_build(struct intel_engine_cs *engine)
+{
+	struct i915_wa_list *w = &engine->whitelist;
+
+	/* WaSendPushConstantsFromMMIO:tgl */
+	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
+
+	/* WaAllowUMDToModifySamplerMode:tgl */
+	whitelist_reg(w, GEN10_SAMPLER_MODE);
+}
+
 void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
@@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
 
 	wa_init_start(w, "whitelist", engine->name);
 
-	if (IS_GEN(i915, 11))
+	if (IS_GEN(i915, 12))
+		tgl_whitelist_build(engine);
+	else if (IS_GEN(i915, 11))
 		icl_whitelist_build(engine);
 	else if (IS_CANNONLAKE(i915))
 		cnl_whitelist_build(engine);
@@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
 	struct drm_i915_private *i915 = engine->i915;
 
+	if (IS_GEN(i915, 12)) {
+		/* WaPipelineFlushCoherentLines:tgl */
+		wa_write_or(wal,
+			    GEN12_L3SQCREG2,
+			    GEN12_LQSC_FLUSH_COHERENT_LINES);
+	}
+
 	if (IS_GEN(i915, 11)) {
 		/* This is not an Wa. Enable for better image quality */
 		wa_masked_en(wal,
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 24f2a52a2b42..54ea250000be 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7729,6 +7729,9 @@ enum {
 #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
 #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
 
+#define GEN12_L3SQCREG2				_MMIO(0xb104)
+#define  GEN12_LQSC_FLUSH_COHERENT_LINES	(1 << 24)
+
 /* GEN8 chicken */
 #define HDC_CHICKEN0				_MMIO(0x7300)
 #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 30399b245f07..63aecff195ce 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
  */
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
 {
-	if (IS_GEN(dev_priv, 11))
+	if (IS_GEN(dev_priv, 12))
+		dev_priv->display.init_clock_gating = nop_init_clock_gating;
+	else if (IS_GEN(dev_priv, 11))
 		dev_priv->display.init_clock_gating = icl_init_clock_gating;
 	else if (IS_CANNONLAKE(dev_priv))
 		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 475ab3d4d91d..cca046ff2e10 100644
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
 	 * the fallback ack.
 	 *
 	 * This workaround is described in HSDES #1604254524 and it's known as:
-	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
+	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
 	 * although the name is a bit misleading.
 	 */
 
-- 
2.21.0

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[PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
FF_MODE2 is part of the register state context, that's why it is
implemented here.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
 drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
 2 files changed, 12 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index a6eb9c6e87ec..3235ef355dfd 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
 static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
 				     struct i915_wa_list *wal)
 {
+	u32 val;
+
+	/* Wa_1604555607:tgl */
+	val = intel_uncore_read(engine->uncore, FF_MODE2);
+	val &= ~FF_MODE2_TDS_TIMER_MASK;
+	val |= FF_MODE2_TDS_TIMER_128;
+	wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
 }
 
 static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 54ea250000be..fbbb89f6ca2f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7771,6 +7771,11 @@ enum {
 #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU 	(1 << 15)
 #define   PER_PIXEL_ALPHA_BYPASS_EN		(1 << 7)
 
+#define FF_MODE2			_MMIO(0x6604)
+#define   FF_MODE2_TDS_TIMER_SHIFT	(16)
+#define   FF_MODE2_TDS_TIMER_128	(4 << FF_MODE2_TDS_TIMER_SHIFT)
+#define   FF_MODE2_TDS_TIMER_MASK	(0xff << FF_MODE2_TDS_TIMER_SHIFT)
+
 /* PCH */
 
 #define PCH_DISPLAY_BASE	0xc0000u
-- 
2.21.0

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[PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453

[Lucas De Marchi]

From: Michel Thierry <michel.thierry@intel.com>

Enable Small PL for power benefit.

Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demarchi@intel.com
---
 drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
 drivers/gpu/drm/i915/i915_reg.h             | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 3235ef355dfd..830ccd416a29 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -1279,6 +1279,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 		wa_write_or(wal,
 			    GEN12_L3SQCREG2,
 			    GEN12_LQSC_FLUSH_COHERENT_LINES);
+
+		/* Wa_1406941453:tgl */
+		wa_masked_en(wal,
+			     SAMPLER_MODE,
+			     SAMPLER_ENABLE_SMALL_PL);
 	}
 
 	if (IS_GEN(i915, 11)) {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index fbbb89f6ca2f..71efb37f54a3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8965,6 +8965,9 @@ enum {
 #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
 #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
 
+#define SAMPLER_MODE			_MMIO(0xe18c)
+#define   SAMPLER_ENABLE_SMALL_PL	(1 << 15)
+
 #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
 #define   FLOW_CONTROL_ENABLE		(1 << 15)
 #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
-- 
2.21.0

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Re: [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

[Chris Wilson]

Quoting Lucas De Marchi (2019-07-26 01:02:25)
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> FF_MODE2 is part of the register state context, that's why it is
> implemented here.
> 
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>  drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
>  2 files changed, 12 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index a6eb9c6e87ec..3235ef355dfd 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>                                      struct i915_wa_list *wal)
>  {
> +       u32 val;
> +
> +       /* Wa_1604555607:tgl */
> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> +       val |= FF_MODE2_TDS_TIMER_128;
> +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);

It will do a rmw on application, so you just need
	wa_write_masked_or(wal, FF_MODE2,
		           FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128);

>  }
>  
>  static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 54ea250000be..fbbb89f6ca2f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7771,6 +7771,11 @@ enum {
>  #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU     (1 << 15)
>  #define   PER_PIXEL_ALPHA_BYPASS_EN            (1 << 7)
>  
> +#define FF_MODE2                       _MMIO(0x6604)
> +#define   FF_MODE2_TDS_TIMER_SHIFT     (16)
> +#define   FF_MODE2_TDS_TIMER_128       (4 << FF_MODE2_TDS_TIMER_SHIFT)
> +#define   FF_MODE2_TDS_TIMER_MASK      (0xff << FF_MODE2_TDS_TIMER_SHIFT)

#define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
#define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
-Chris
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✓ Fi.CI.BAT: success for Tiger Lake: add workarounds

[Patchwork]

== Series Details ==

Series: Tiger Lake: add workarounds
URL   : https://patchwork.freedesktop.org/series/64274/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6557 -> Patchwork_13765
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/

Known issues
------------

  Here are the changes found in Patchwork_13765 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_create@basic-files:
    - fi-icl-u3:          [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#109100])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u3/igt@gem_ctx_create@basic-files.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-u3/igt@gem_ctx_create@basic-files.html

  * igt@i915_selftest@live_client:
    - fi-icl-dsi:         [PASS][3] -> [INCOMPLETE][4] ([fdo#107713])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_client.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-dsi/igt@i915_selftest@live_client.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-icl-u2:          [PASS][5] -> [FAIL][6] ([fdo#109483] / [fdo#109635 ])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-u2/igt@kms_chamelium@dp-edid-read.html

  
#### Possible fixes ####

  * igt@i915_selftest@live_blt:
    - fi-icl-dsi:         [DMESG-FAIL][7] ([fdo#110899]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-dsi/igt@i915_selftest@live_blt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-dsi/igt@i915_selftest@live_blt.html

  * igt@kms_busy@basic-flip-a:
    - fi-kbl-7567u:       [SKIP][9] ([fdo#109271] / [fdo#109278]) -> [PASS][10] +2 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-kbl-7567u/igt@kms_busy@basic-flip-a.html

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-kbl-7567u:       [WARN][11] ([fdo#109380]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-kbl-7567u/igt@kms_chamelium@common-hpd-after-suspend.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][13] ([fdo#103167]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-c:
    - fi-kbl-7567u:       [SKIP][15] ([fdo#109271]) -> [PASS][16] +23 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/fi-kbl-7567u/igt@kms_pipe_crc_basic@read-crc-pipe-c.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109380]: https://bugs.freedesktop.org/show_bug.cgi?id=109380
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#110899]: https://bugs.freedesktop.org/show_bug.cgi?id=110899


Participating hosts (53 -> 45)
------------------------------

  Additional (1): fi-pnv-d510 
  Missing    (9): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-cfl-8109u fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6557 -> Patchwork_13765

  CI-20190529: 20190529
  CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13765: 8cbecca9298f056e49ab192affdce16880baf9b8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8cbecca9298f drm/i915/tgl: Implement Wa_1406941453
603fa049e1f1 drm/i915/tgl: Implement Wa_1604555607
385a308bbf68 drm/i915/tgl: Introduce initial Tigerlake Workarounds

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/
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Re: [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

[Tvrtko Ursulin]

On 26/07/2019 01:10, Chris Wilson wrote:
> Quoting Lucas De Marchi (2019-07-26 01:02:25)
>> From: Michel Thierry <michel.thierry@intel.com>
>>
>> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
>> FF_MODE2 is part of the register state context, that's why it is
>> implemented here.
>>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>>   drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
>>   2 files changed, 12 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index a6eb9c6e87ec..3235ef355dfd 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>                                       struct i915_wa_list *wal)
>>   {
>> +       u32 val;
>> +
>> +       /* Wa_1604555607:tgl */
>> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
>> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
>> +       val |= FF_MODE2_TDS_TIMER_128;
>> +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> 
> It will do a rmw on application, so you just need
> 	wa_write_masked_or(wal, FF_MODE2,
> 		           FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128);

Not with ctx was unfortunately, no rmw there, just lri.

To be less misleading perhaps:

   wa_write(wal, FF_MODE2, val);

?

It only affects verification, do we want to verify the whole register or 
just the FF_MODE2_TDS_TIMER_MASK bits. Since the code reads it and sets 
it, it may want to check it whole.

Regards,

Tvrtko

> 
>>   }
>>   
>>   static void
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 54ea250000be..fbbb89f6ca2f 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7771,6 +7771,11 @@ enum {
>>   #define   PIXEL_ROUNDING_TRUNC_FB_PASSTHRU     (1 << 15)
>>   #define   PER_PIXEL_ALPHA_BYPASS_EN            (1 << 7)
>>   
>> +#define FF_MODE2                       _MMIO(0x6604)
>> +#define   FF_MODE2_TDS_TIMER_SHIFT     (16)
>> +#define   FF_MODE2_TDS_TIMER_128       (4 << FF_MODE2_TDS_TIMER_SHIFT)
>> +#define   FF_MODE2_TDS_TIMER_MASK      (0xff << FF_MODE2_TDS_TIMER_SHIFT)
> 
> #define FF_MODE2_TDS_TIMER_MASK REG_GENMASK(23, 16)
> #define FF_MODE2_TDS_TIMER_128 REG_FIELD_PREP(FF_MODE2_TDS_TIMER_MASK, 4)
> -Chris
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> 
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Re: [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-26 14:15:51)
> 
> On 26/07/2019 01:10, Chris Wilson wrote:
> > Quoting Lucas De Marchi (2019-07-26 01:02:25)
> >> From: Michel Thierry <michel.thierry@intel.com>
> >>
> >> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
> >> FF_MODE2 is part of the register state context, that's why it is
> >> implemented here.
> >>
> >> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> >> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> >> ---
> >>   drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
> >>   drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
> >>   2 files changed, 12 insertions(+)
> >>
> >> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> index a6eb9c6e87ec..3235ef355dfd 100644
> >> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> >> @@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >>   static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> >>                                       struct i915_wa_list *wal)
> >>   {
> >> +       u32 val;
> >> +
> >> +       /* Wa_1604555607:tgl */
> >> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
> >> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
> >> +       val |= FF_MODE2_TDS_TIMER_128;
> >> +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
> > 
> > It will do a rmw on application, so you just need
> >       wa_write_masked_or(wal, FF_MODE2,
> >                          FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128);
> 
> Not with ctx was unfortunately, no rmw there, just lri.

Odd that we read from outside the ctx then, no?

We can do rmw inside ctx_wa if we have to thanks to MI_MATH. Should we
start preparing for that nightmare? :)
-Chris
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Re: [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

[Tvrtko Ursulin]

On 26/07/2019 14:20, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-07-26 14:15:51)
>>
>> On 26/07/2019 01:10, Chris Wilson wrote:
>>> Quoting Lucas De Marchi (2019-07-26 01:02:25)
>>>> From: Michel Thierry <michel.thierry@intel.com>
>>>>
>>>> Implement Wa_1604555607 (set the DS pairing timer to 128 cycles).
>>>> FF_MODE2 is part of the register state context, that's why it is
>>>> implemented here.
>>>>
>>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>>>> ---
>>>>    drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +++++++
>>>>    drivers/gpu/drm/i915/i915_reg.h             | 5 +++++
>>>>    2 files changed, 12 insertions(+)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> index a6eb9c6e87ec..3235ef355dfd 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>>>> @@ -572,6 +572,13 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>>>    static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>>>                                        struct i915_wa_list *wal)
>>>>    {
>>>> +       u32 val;
>>>> +
>>>> +       /* Wa_1604555607:tgl */
>>>> +       val = intel_uncore_read(engine->uncore, FF_MODE2);
>>>> +       val &= ~FF_MODE2_TDS_TIMER_MASK;
>>>> +       val |= FF_MODE2_TDS_TIMER_128;
>>>> +       wa_write_masked_or(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val);
>>>
>>> It will do a rmw on application, so you just need
>>>        wa_write_masked_or(wal, FF_MODE2,
>>>                           FF_MODE2_TDS_TIMER_MASK, FF_MODE2_TDS_TIMER_128);
>>
>> Not with ctx was unfortunately, no rmw there, just lri.
> 
> Odd that we read from outside the ctx then, no?

Perhaps. We have to get the default value from somewhere. There is one 
like this already, GEN8_L3CNTLREG, from not too long ago.

> We can do rmw inside ctx_wa if we have to thanks to MI_MATH. Should we
> start preparing for that nightmare? :)

When you say preparing it makes it sounds complicated so I want to say 
no. But sure, if you have extra time go for it.

Regards,

Tvrtko
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Re: [PATCH 2/3] drm/i915/tgl: Implement Wa_1604555607

[Chris Wilson]

Quoting Tvrtko Ursulin (2019-07-26 14:34:56)
> 
> On 26/07/2019 14:20, Chris Wilson wrote:
> > We can do rmw inside ctx_wa if we have to thanks to MI_MATH. Should we
> > start preparing for that nightmare? :)
> 
> When you say preparing it makes it sounds complicated so I want to say 
> no. But sure, if you have extra time go for it.

The quick-and-dirty solution is to write the assembly routines by hand,
but Lionel mentioned that mesa might have a dsl we could use to create
MI_MATH routines.
-Chris
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✓ Fi.CI.IGT: success for Tiger Lake: add workarounds

[Patchwork]

== Series Details ==

Series: Tiger Lake: add workarounds
URL   : https://patchwork.freedesktop.org/series/64274/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6557_full -> Patchwork_13765_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13765_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_workarounds@suspend-resume-context:
    - shard-apl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#108566]) +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-apl6/igt@gem_workarounds@suspend-resume-context.html

  * igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen:
    - shard-snb:          [PASS][3] -> [SKIP][4] ([fdo#109271])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-snb4/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-snb5/igt@kms_cursor_crc@pipe-a-cursor-64x64-onscreen.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-iclb:         [PASS][5] -> [INCOMPLETE][6] ([fdo#107713]) +1 similar issue
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_cursor_legacy@cursor-vs-flip-legacy:
    - shard-hsw:          [PASS][7] -> [FAIL][8] ([fdo#103355])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-hsw6/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - shard-skl:          [PASS][9] -> [FAIL][10] ([fdo#103184] / [fdo#103232]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-skl2/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [PASS][11] -> [FAIL][12] ([fdo#105363])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl7/igt@kms_flip@flip-vs-expired-vblank.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip_tiling@flip-to-y-tiled:
    - shard-iclb:         [PASS][13] -> [FAIL][14] ([fdo#107931] / [fdo#108134])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb8/igt@kms_flip_tiling@flip-to-y-tiled.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb6/igt@kms_flip_tiling@flip-to-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render:
    - shard-iclb:         [PASS][15] -> [FAIL][16] ([fdo#103167]) +6 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-indfb-draw-render.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [PASS][17] -> [DMESG-WARN][18] ([fdo#108566]) +4 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][19] -> [SKIP][20] ([fdo#109642] / [fdo#111068])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb8/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][21] -> [FAIL][22] ([fdo#108341])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb3/igt@kms_psr@no_drrs.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_plane_move:
    - shard-iclb:         [PASS][23] -> [SKIP][24] ([fdo#109441]) +3 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb7/igt@kms_psr@psr2_sprite_plane_move.html

  * igt@kms_rotation_crc@multiplane-rotation:
    - shard-glk:          [PASS][25] -> [DMESG-FAIL][26] ([fdo#105763] / [fdo#106538])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk1/igt@kms_rotation_crc@multiplane-rotation.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-glk3/igt@kms_rotation_crc@multiplane-rotation.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][27] ([fdo#108566]) -> [PASS][28] +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl6/igt@gem_ctx_isolation@rcs0-s3.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          [SKIP][29] ([fdo#109271]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-snb6/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-snb2/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@kms_cursor_crc@pipe-b-cursor-suspend:
    - shard-skl:          [INCOMPLETE][31] ([fdo#110741]) -> [PASS][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][33] ([fdo#105363]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-skl:          [FAIL][35] ([fdo#105363]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl10/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-skl5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-skl:          [INCOMPLETE][37] ([fdo#109507]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl3/igt@kms_flip@flip-vs-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-skl7/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-kbl:          [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40] +1 similar issue
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-kbl4/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@modeset-vs-vblank-race:
    - shard-glk:          [FAIL][41] ([fdo#103060]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-glk9/igt@kms_flip@modeset-vs-vblank-race.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-glk6/igt@kms_flip@modeset-vs-vblank-race.html

  * igt@kms_frontbuffer_tracking@basic:
    - shard-iclb:         [FAIL][43] ([fdo#103167]) -> [PASS][44] +6 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb2/igt@kms_frontbuffer_tracking@basic.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb8/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
    - shard-skl:          [INCOMPLETE][45] ([fdo#104108]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][47] ([fdo#109441]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][49] ([fdo#99912]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-apl3/igt@kms_setmode@basic.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-apl6/igt@kms_setmode@basic.html
    - shard-hsw:          [FAIL][51] ([fdo#99912]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-hsw2/igt@kms_setmode@basic.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-hsw5/igt@kms_setmode@basic.html

  * igt@perf_pmu@busy-hang-bcs0:
    - shard-iclb:         [FAIL][53] -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb1/igt@perf_pmu@busy-hang-bcs0.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb6/igt@perf_pmu@busy-hang-bcs0.html

  * igt@perf_pmu@rc6-runtime-pm-long:
    - shard-iclb:         [FAIL][55] ([fdo#105010]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-iclb6/igt@perf_pmu@rc6-runtime-pm-long.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-iclb6/igt@perf_pmu@rc6-runtime-pm-long.html

  
#### Warnings ####

  * igt@kms_atomic_transition@6x-modeset-transitions-nonblocking:
    - shard-snb:          [SKIP][57] ([fdo#109271] / [fdo#109278]) -> [SKIP][58] ([fdo#109271])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6557/shard-snb4/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/shard-snb5/igt@kms_atomic_transition@6x-modeset-transitions-nonblocking.html

  
  [fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
  [fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
  [fdo#103355]: https://bugs.freedesktop.org/show_bug.cgi?id=103355
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#105010]: https://bugs.freedesktop.org/show_bug.cgi?id=105010
  [fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
  [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110741]: https://bugs.freedesktop.org/show_bug.cgi?id=110741
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (9 -> 9)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_6557 -> Patchwork_13765

  CI-20190529: 20190529
  CI_DRM_6557: 2ebd69f583d23b295265832f168e39427a8bd863 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5112: 7e4d10507088055413769a020dd674f52b4bc1b0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13765: 8cbecca9298f056e49ab192affdce16880baf9b8 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13765/
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Re: [PATCH 3/3] drm/i915/tgl: Implement Wa_1406941453

[Radhakrishna Sripada]

On Thu, Jul 25, 2019 at 05:02:26PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Enable Small PL for power benefit.
> 
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> Reviewed-by: Stuart Summers <stuart.summers@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Link: https://patchwork.freedesktop.org/patch/msgid/20190713010940.17711-18-lucas.demarchi@intel.com
> ---
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 5 +++++
>  drivers/gpu/drm/i915/i915_reg.h             | 3 +++
>  2 files changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 3235ef355dfd..830ccd416a29 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -1279,6 +1279,11 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  		wa_write_or(wal,
>  			    GEN12_L3SQCREG2,
>  			    GEN12_LQSC_FLUSH_COHERENT_LINES);
> +
> +		/* Wa_1406941453:tgl */
> +		wa_masked_en(wal,
> +			     SAMPLER_MODE,
> +			     SAMPLER_ENABLE_SMALL_PL);
>  	}
>  
>  	if (IS_GEN(i915, 11)) {
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index fbbb89f6ca2f..71efb37f54a3 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8965,6 +8965,9 @@ enum {
>  #define   GEN9_DG_MIRROR_FIX_ENABLE	(1 << 5)
>  #define   GEN9_CCS_TLB_PREFETCH_ENABLE	(1 << 3)
>  
> +#define SAMPLER_MODE			_MMIO(0xe18c)
> +#define   SAMPLER_ENABLE_SMALL_PL	(1 << 15)
> +
>  #define GEN8_ROW_CHICKEN		_MMIO(0xe4f0)
>  #define   FLOW_CONTROL_ENABLE		(1 << 15)
>  #define   PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE	(1 << 8)
> -- 
> 2.21.0
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds

[Radhakrishna Sripada]

On Thu, Jul 25, 2019 at 05:02:24PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Inherit workarounds from previous platforms that are still valid for
> Tigerlake.
> 
>   WaPipelineFlushCoherentLines:tgl (changed register but has same name)
>   WaSendPushConstantsFromMMIO:tgl
>   WaAllowUMDToModifySamplerMode:tgl
>   WaRsForcewakeAddDelayForAck:tgl
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Reviewed-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c         |  2 ++
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h             |  3 ++
>  drivers/gpu/drm/i915/intel_pm.c             |  4 ++-
>  drivers/gpu/drm/i915/intel_uncore.c         |  2 +-
>  5 files changed, 46 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 884dfc1cb033..893c58df8be0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  		return 0;
>  
>  	switch (INTEL_GEN(engine->i915)) {
> +	case 12:
> +		return 0;
>  	case 11:
>  		return 0;
>  	case 10:
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..a6eb9c6e87ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
>  }
>  
> +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> +				     struct i915_wa_list *wal)
> +{
> +}
> +
>  static void
>  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  			   struct i915_wa_list *wal,
> @@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  
>  	wa_init_start(wal, name, engine->name);
>  
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_ctx_workarounds_init(engine, wal);
> +	else if (IS_GEN(i915, 11))
>  		icl_ctx_workarounds_init(engine, wal);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_ctx_workarounds_init(engine, wal);
> @@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		    GAMT_CHKN_DISABLE_L3_COH_PIPE);
>  }
>  
> +static void
> +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> +}
> +
>  static void
>  gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_gt_workarounds_init(i915, wal);
> +	else if (IS_GEN(i915, 11))
>  		icl_gt_workarounds_init(i915, wal);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_gt_workarounds_init(i915, wal);
> @@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  	}
>  }
>  
> +static void tgl_whitelist_build(struct intel_engine_cs *engine)
> +{
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	/* WaSendPushConstantsFromMMIO:tgl */
> +	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
> +
> +	/* WaAllowUMDToModifySamplerMode:tgl */
> +	whitelist_reg(w, GEN10_SAMPLER_MODE);
> +}
> +
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
> @@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  
>  	wa_init_start(w, "whitelist", engine->name);
>  
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_whitelist_build(engine);
> +	else if (IS_GEN(i915, 11))
>  		icl_whitelist_build(engine);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_whitelist_build(engine);
> @@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
>  
> +	if (IS_GEN(i915, 12)) {
> +		/* WaPipelineFlushCoherentLines:tgl */
> +		wa_write_or(wal,
> +			    GEN12_L3SQCREG2,
> +			    GEN12_LQSC_FLUSH_COHERENT_LINES);
> +	}
> +
>  	if (IS_GEN(i915, 11)) {
>  		/* This is not an Wa. Enable for better image quality */
>  		wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24f2a52a2b42..54ea250000be 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7729,6 +7729,9 @@ enum {
>  #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
>  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>  
> +#define GEN12_L3SQCREG2				_MMIO(0xb104)
> +#define  GEN12_LQSC_FLUSH_COHERENT_LINES	(1 << 24)
> +
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				_MMIO(0x7300)
>  #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 30399b245f07..63aecff195ce 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>   */
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_GEN(dev_priv, 11))
> +	if (IS_GEN(dev_priv, 12))
> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +	else if (IS_GEN(dev_priv, 11))
>  		dev_priv->display.init_clock_gating = icl_init_clock_gating;
>  	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 475ab3d4d91d..cca046ff2e10 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
>  	 * the fallback ack.
>  	 *
>  	 * This workaround is described in HSDES #1604254524 and it's known as:
> -	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
>  	 * although the name is a bit misleading.
>  	 */
>  
> -- 
> 2.21.0
> 
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Re: [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds

[Radhakrishna Sripada]

On Thu, Jul 25, 2019 at 05:02:24PM -0700, Lucas De Marchi wrote:
> From: Michel Thierry <michel.thierry@intel.com>
> 
> Inherit workarounds from previous platforms that are still valid for
> Tigerlake.
> 
>   WaPipelineFlushCoherentLines:tgl (changed register but has same name)
>   WaSendPushConstantsFromMMIO:tgl
>   WaAllowUMDToModifySamplerMode:tgl
>   WaRsForcewakeAddDelayForAck:tgl
> 
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_lrc.c         |  2 ++
>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_reg.h             |  3 ++
>  drivers/gpu/drm/i915/intel_pm.c             |  4 ++-
>  drivers/gpu/drm/i915/intel_uncore.c         |  2 +-
>  5 files changed, 46 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 884dfc1cb033..893c58df8be0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>  		return 0;
>  
>  	switch (INTEL_GEN(engine->i915)) {
> +	case 12:
> +		return 0;
>  	case 11:
>  		return 0;
>  	case 10:
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 704ace01e7f5..a6eb9c6e87ec 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>  			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
>  }
>  
> +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> +				     struct i915_wa_list *wal)
> +{
> +}
> +
>  static void
>  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  			   struct i915_wa_list *wal,
> @@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>  
>  	wa_init_start(wal, name, engine->name);
>  
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_ctx_workarounds_init(engine, wal);
> +	else if (IS_GEN(i915, 11))
>  		icl_ctx_workarounds_init(engine, wal);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_ctx_workarounds_init(engine, wal);
> @@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  		    GAMT_CHKN_DISABLE_L3_COH_PIPE);
>  }
>  
> +static void
> +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
> +{
> +}
> +
>  static void
>  gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>  {
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_gt_workarounds_init(i915, wal);
> +	else if (IS_GEN(i915, 11))
>  		icl_gt_workarounds_init(i915, wal);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_gt_workarounds_init(i915, wal);
> @@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>  	}
>  }
>  
> +static void tgl_whitelist_build(struct intel_engine_cs *engine)
> +{
> +	struct i915_wa_list *w = &engine->whitelist;
> +
> +	/* WaSendPushConstantsFromMMIO:tgl */
> +	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
> +
> +	/* WaAllowUMDToModifySamplerMode:tgl */
> +	whitelist_reg(w, GEN10_SAMPLER_MODE);
Are there user space consumers for the above 2 workarounds?
ICL does not seem to carry them.

- Radhakrishna(RK) Sripada
> +}
> +
>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
> @@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>  
>  	wa_init_start(w, "whitelist", engine->name);
>  
> -	if (IS_GEN(i915, 11))
> +	if (IS_GEN(i915, 12))
> +		tgl_whitelist_build(engine);
> +	else if (IS_GEN(i915, 11))
>  		icl_whitelist_build(engine);
>  	else if (IS_CANNONLAKE(i915))
>  		cnl_whitelist_build(engine);
> @@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
>  	struct drm_i915_private *i915 = engine->i915;
>  
> +	if (IS_GEN(i915, 12)) {
> +		/* WaPipelineFlushCoherentLines:tgl */
> +		wa_write_or(wal,
> +			    GEN12_L3SQCREG2,
> +			    GEN12_LQSC_FLUSH_COHERENT_LINES);
> +	}
> +
>  	if (IS_GEN(i915, 11)) {
>  		/* This is not an Wa. Enable for better image quality */
>  		wa_masked_en(wal,
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 24f2a52a2b42..54ea250000be 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7729,6 +7729,9 @@ enum {
>  #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
>  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>  
> +#define GEN12_L3SQCREG2				_MMIO(0xb104)
> +#define  GEN12_LQSC_FLUSH_COHERENT_LINES	(1 << 24)
> +
>  /* GEN8 chicken */
>  #define HDC_CHICKEN0				_MMIO(0x7300)
>  #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 30399b245f07..63aecff195ce 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>   */
>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>  {
> -	if (IS_GEN(dev_priv, 11))
> +	if (IS_GEN(dev_priv, 12))
> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
> +	else if (IS_GEN(dev_priv, 11))
>  		dev_priv->display.init_clock_gating = icl_init_clock_gating;
>  	else if (IS_CANNONLAKE(dev_priv))
>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
> index 475ab3d4d91d..cca046ff2e10 100644
> --- a/drivers/gpu/drm/i915/intel_uncore.c
> +++ b/drivers/gpu/drm/i915/intel_uncore.c
> @@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
>  	 * the fallback ack.
>  	 *
>  	 * This workaround is described in HSDES #1604254524 and it's known as:
> -	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
>  	 * although the name is a bit misleading.
>  	 */
>  
> -- 
> 2.21.0
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH 1/3] drm/i915/tgl: Introduce initial Tigerlake Workarounds

[Lucas De Marchi]

On Tue, Aug 13, 2019 at 11:07:54AM -0700, Radhakrishna Sripada wrote:
>On Thu, Jul 25, 2019 at 05:02:24PM -0700, Lucas De Marchi wrote:
>> From: Michel Thierry <michel.thierry@intel.com>
>>
>> Inherit workarounds from previous platforms that are still valid for
>> Tigerlake.
>>
>>   WaPipelineFlushCoherentLines:tgl (changed register but has same name)
>>   WaSendPushConstantsFromMMIO:tgl
>>   WaAllowUMDToModifySamplerMode:tgl
>>   WaRsForcewakeAddDelayForAck:tgl
>>
>> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
>> ---
>>  drivers/gpu/drm/i915/gt/intel_lrc.c         |  2 ++
>>  drivers/gpu/drm/i915/gt/intel_workarounds.c | 40 +++++++++++++++++++--
>>  drivers/gpu/drm/i915/i915_reg.h             |  3 ++
>>  drivers/gpu/drm/i915/intel_pm.c             |  4 ++-
>>  drivers/gpu/drm/i915/intel_uncore.c         |  2 +-
>>  5 files changed, 46 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> index 884dfc1cb033..893c58df8be0 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> @@ -2069,6 +2069,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
>>  		return 0;
>>
>>  	switch (INTEL_GEN(engine->i915)) {
>> +	case 12:
>> +		return 0;
>>  	case 11:
>>  		return 0;
>>  	case 10:
>> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> index 704ace01e7f5..a6eb9c6e87ec 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
>> @@ -569,6 +569,11 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
>>  			  GEN11_SAMPLER_ENABLE_HEADLESS_MSG);
>>  }
>>
>> +static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
>> +				     struct i915_wa_list *wal)
>> +{
>> +}
>> +
>>  static void
>>  __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>>  			   struct i915_wa_list *wal,
>> @@ -581,7 +586,9 @@ __intel_engine_init_ctx_wa(struct intel_engine_cs *engine,
>>
>>  	wa_init_start(wal, name, engine->name);
>>
>> -	if (IS_GEN(i915, 11))
>> +	if (IS_GEN(i915, 12))
>> +		tgl_ctx_workarounds_init(engine, wal);
>> +	else if (IS_GEN(i915, 11))
>>  		icl_ctx_workarounds_init(engine, wal);
>>  	else if (IS_CANNONLAKE(i915))
>>  		cnl_ctx_workarounds_init(engine, wal);
>> @@ -890,10 +897,17 @@ icl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  		    GAMT_CHKN_DISABLE_L3_COH_PIPE);
>>  }
>>
>> +static void
>> +tgl_gt_workarounds_init(struct drm_i915_private *i915, struct i915_wa_list *wal)
>> +{
>> +}
>> +
>>  static void
>>  gt_init_workarounds(struct drm_i915_private *i915, struct i915_wa_list *wal)
>>  {
>> -	if (IS_GEN(i915, 11))
>> +	if (IS_GEN(i915, 12))
>> +		tgl_gt_workarounds_init(i915, wal);
>> +	else if (IS_GEN(i915, 11))
>>  		icl_gt_workarounds_init(i915, wal);
>>  	else if (IS_CANNONLAKE(i915))
>>  		cnl_gt_workarounds_init(i915, wal);
>> @@ -1183,6 +1197,17 @@ static void icl_whitelist_build(struct intel_engine_cs *engine)
>>  	}
>>  }
>>
>> +static void tgl_whitelist_build(struct intel_engine_cs *engine)
>> +{
>> +	struct i915_wa_list *w = &engine->whitelist;
>> +
>> +	/* WaSendPushConstantsFromMMIO:tgl */
>> +	whitelist_reg(w, COMMON_SLICE_CHICKEN2);
>> +
>> +	/* WaAllowUMDToModifySamplerMode:tgl */
>> +	whitelist_reg(w, GEN10_SAMPLER_MODE);
>Are there user space consumers for the above 2 workarounds?
>ICL does not seem to carry them.

I don't think so. At least *I* was not involved with any. My main
interest here was actually to add the infra for TGL (aka remove the
warning) and inherit the WAs carried over from ICL. If they are not
valid for ICL because there is not user, could you send a patch for ICL?

I will send a new patch without these.

thanks
Lucas De Marchi

>
>- Radhakrishna(RK) Sripada
>> +}
>> +
>>  void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>>  {
>>  	struct drm_i915_private *i915 = engine->i915;
>> @@ -1190,7 +1215,9 @@ void intel_engine_init_whitelist(struct intel_engine_cs *engine)
>>
>>  	wa_init_start(w, "whitelist", engine->name);
>>
>> -	if (IS_GEN(i915, 11))
>> +	if (IS_GEN(i915, 12))
>> +		tgl_whitelist_build(engine);
>> +	else if (IS_GEN(i915, 11))
>>  		icl_whitelist_build(engine);
>>  	else if (IS_CANNONLAKE(i915))
>>  		cnl_whitelist_build(engine);
>> @@ -1240,6 +1267,13 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>>  {
>>  	struct drm_i915_private *i915 = engine->i915;
>>
>> +	if (IS_GEN(i915, 12)) {
>> +		/* WaPipelineFlushCoherentLines:tgl */
>> +		wa_write_or(wal,
>> +			    GEN12_L3SQCREG2,
>> +			    GEN12_LQSC_FLUSH_COHERENT_LINES);
>> +	}
>> +
>>  	if (IS_GEN(i915, 11)) {
>>  		/* This is not an Wa. Enable for better image quality */
>>  		wa_masked_en(wal,
>> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>> index 24f2a52a2b42..54ea250000be 100644
>> --- a/drivers/gpu/drm/i915/i915_reg.h
>> +++ b/drivers/gpu/drm/i915/i915_reg.h
>> @@ -7729,6 +7729,9 @@ enum {
>>  #define  GEN8_LQSC_RO_PERF_DIS			(1 << 27)
>>  #define  GEN8_LQSC_FLUSH_COHERENT_LINES		(1 << 21)
>>
>> +#define GEN12_L3SQCREG2				_MMIO(0xb104)
>> +#define  GEN12_LQSC_FLUSH_COHERENT_LINES	(1 << 24)
>> +
>>  /* GEN8 chicken */
>>  #define HDC_CHICKEN0				_MMIO(0x7300)
>>  #define CNL_HDC_CHICKEN0			_MMIO(0xE5F0)
>> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
>> index 30399b245f07..63aecff195ce 100644
>> --- a/drivers/gpu/drm/i915/intel_pm.c
>> +++ b/drivers/gpu/drm/i915/intel_pm.c
>> @@ -9608,7 +9608,9 @@ static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
>>   */
>>  void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
>>  {
>> -	if (IS_GEN(dev_priv, 11))
>> +	if (IS_GEN(dev_priv, 12))
>> +		dev_priv->display.init_clock_gating = nop_init_clock_gating;
>> +	else if (IS_GEN(dev_priv, 11))
>>  		dev_priv->display.init_clock_gating = icl_init_clock_gating;
>>  	else if (IS_CANNONLAKE(dev_priv))
>>  		dev_priv->display.init_clock_gating = cnl_init_clock_gating;
>> diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
>> index 475ab3d4d91d..cca046ff2e10 100644
>> --- a/drivers/gpu/drm/i915/intel_uncore.c
>> +++ b/drivers/gpu/drm/i915/intel_uncore.c
>> @@ -144,7 +144,7 @@ fw_domain_wait_ack_with_fallback(const struct intel_uncore_forcewake_domain *d,
>>  	 * the fallback ack.
>>  	 *
>>  	 * This workaround is described in HSDES #1604254524 and it's known as:
>> -	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl
>> +	 * WaRsForcewakeAddDelayForAck:skl,bxt,kbl,glk,cfl,cnl,icl,tgl
>>  	 * although the name is a bit misleading.
>>  	 */
>>
>> --
>> 2.21.0
>>
>> _______________________________________________
>> Intel-gfx mailing list
>> Intel-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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