[igt-dev] [RFC PATCH 0/4] Basic LMEM support in IGT

[igt-dev] [RFC PATCH 0/4] Basic LMEM support in IGT

[Lukasz Kalamarz]

With ongoing effort to enable LMEM in i915 we need to be sure, that
IGTs are going in par with those changes. This patch series introduce
basic test coverage of new API's intoruduced in kernel series.

Lukasz Kalamarz (4):
  lib/i915/gem_mman: add mmap_offset support
  lib/i915/intel_memory_region: Add lib to manage memory regions
  tests/i915/gem_mmap_offset: Add new API test for gem_mmap_offset
  tests/i915/gem_exec_basic: Iterate over all memory regions

 lib/Makefile.sources           |   2 +
 lib/i915/gem_mman.c            | 188 +++++++++++++++++++++++++++----
 lib/i915/gem_mman.h            |  37 ++++++-
 lib/i915/intel_memory_region.c | 164 +++++++++++++++++++++++++++
 lib/i915/intel_memory_region.h | 112 +++++++++++++++++++
 lib/ioctl_wrappers.h           |   1 +
 lib/meson.build                |   1 +
 tests/Makefile.sources         |   3 +
 tests/i915/gem_exec_basic.c    | 138 ++++++++++++++++++-----
 tests/i915/gem_mmap_offset.c   | 197 +++++++++++++++++++++++++++++++++
 tests/meson.build              |   1 +
 11 files changed, 794 insertions(+), 50 deletions(-)
 create mode 100644 lib/i915/intel_memory_region.c
 create mode 100644 lib/i915/intel_memory_region.h
 create mode 100644 tests/i915/gem_mmap_offset.c

-- 
2.20.1

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[igt-dev] [RFC PATCH 1/4] lib/i915/gem_mman: add mmap_offset support

[Lukasz Kalamarz]

With introduction of LMEM concept new IOCTL call were implemented
- gem_mmap_offset. This patch add support in IGT for it.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 lib/i915/gem_mman.c | 188 ++++++++++++++++++++++++++++++++++++++------
 lib/i915/gem_mman.h |  37 ++++++++-
 2 files changed, 202 insertions(+), 23 deletions(-)

diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
index 3cf9a6bb..2b28a67c 100644
--- a/lib/i915/gem_mman.c
+++ b/lib/i915/gem_mman.c
@@ -40,6 +40,27 @@
 #define VG(x) do {} while (0)
 #endif
 
+#define LOCAL_I915_PARAM_MMAP_OFFSET_VERSION 54
+
+bool gem_has_mmap_offset(int fd)
+{
+	static int has_mmap_offset = -1;
+
+	if (has_mmap_offset == -1) {
+		struct drm_i915_getparam gp;
+
+		has_mmap_offset = 0;
+
+		memset(&gp, 0, sizeof(gp));
+		gp.param = LOCAL_I915_PARAM_MMAP_OFFSET_VERSION;
+		gp.value = &has_mmap_offset;
+		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+	}
+
+	return has_mmap_offset > 0;
+}
+
+
 /**
  * __gem_mmap__gtt:
  * @fd: open i915 drm file descriptor
@@ -106,35 +127,80 @@ bool gem_mmap__has_wc(int fd)
 	static int has_wc = -1;
 
 	if (has_wc == -1) {
-		struct drm_i915_getparam gp;
-		int mmap_version = -1;
-		int gtt_version = -1;
 
 		has_wc = 0;
 
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_GTT_VERSION;
-		gp.value = &gtt_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		memset(&gp, 0, sizeof(gp));
-		gp.param = I915_PARAM_MMAP_VERSION;
-		gp.value = &mmap_version;
-		ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
-
-		/* Do we have the new mmap_ioctl with DOMAIN_WC? */
-		if (mmap_version >= 1 && gtt_version >= 2) {
-			struct drm_i915_gem_mmap arg;
+		/* Do we have the new mmap_offset ioctl? */
+		if (gem_has_mmap_offset(fd)) {
+			struct local_i915_gem_mmap_offset arg;
 
 			/* Does this device support wc-mmaps ? */
 			memset(&arg, 0, sizeof(arg));
 			arg.handle = gem_create(fd, 4096);
 			arg.offset = 0;
-			arg.size = 4096;
-			arg.flags = I915_MMAP_WC;
-			has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
+			arg.flags = LOCAL_I915_MMAP_OFFSET_WC;
+			has_wc = igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET,
+					   &arg) == 0;
+			gem_close(fd, arg.handle);
+		} else {
+			struct drm_i915_getparam gp;
+			int mmap_version = -1;
+			int gtt_version = -1;
+
+			memset(&gp, 0, sizeof(gp));
+			gp.param = I915_PARAM_MMAP_GTT_VERSION;
+			gp.value = &gtt_version;
+			ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+			memset(&gp, 0, sizeof(gp));
+			gp.param = I915_PARAM_MMAP_VERSION;
+			gp.value = &mmap_version;
+			ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
+
+			/* Do we have the mmap_ioctl with DOMAIN_WC? */
+			if (mmap_version >= 1 && gtt_version >= 2) {
+				struct drm_i915_gem_mmap arg;
+
+				/* Does this device support wc-mmaps ? */
+				memset(&arg, 0, sizeof(arg));
+				arg.handle = gem_create(fd, 4096);
+				arg.offset = 0;
+				arg.size = 4096;
+				arg.flags = I915_MMAP_WC;
+				has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP,
+						   &arg) == 0;
+				gem_close(fd, arg.handle);
+			}
+		}
+
+		errno = 0;
+	}
+
+	return has_wc > 0;
+}
+
+bool gem_mmap_offset__has_wc(int fd)
+{
+	static int has_wc = -1;
+
+	if (has_wc == -1) {
+
+		has_wc = 0;
+
+		/* Do we have the new mmap_offset ioctl? */
+		if (gem_has_mmap_offset(fd)) {
+			struct local_i915_gem_mmap_offset arg;
+
+			/* Does this device support wc-mmaps ? */
+			memset(&arg, 0, sizeof(arg));
+			arg.handle = gem_create(fd, 4096);
+			arg.offset = 0;
+			arg.flags = LOCAL_I915_MMAP_OFFSET_WC;
+			has_wc = igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET,
+					   &arg) == 0;
 			gem_close(fd, arg.handle);
 		}
+
 		errno = 0;
 	}
 
@@ -157,8 +223,8 @@ bool gem_mmap__has_wc(int fd)
  *
  * Returns: A pointer to the created memory mapping, NULL on failure.
  */
-static void
-*__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned int prot, uint64_t flags)
+void *__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+		 unsigned int prot, uint64_t flags)
 {
 	struct drm_i915_gem_mmap arg;
 
@@ -177,6 +243,43 @@ static void
 	return from_user_pointer(arg.addr_ptr);
 }
 
+/**
+ * __gem_mmap_offset:
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ * @flags: flags used to determine caching
+ *
+ * Similar to __gem_mmap but use MMAP_OFFSET IOCTL.
+ *
+ * Returns: A pointer to the created memory mapping, NULL on failure.
+ */
+void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+			unsigned int prot, uint64_t flags)
+{
+	struct local_i915_gem_mmap_offset arg;
+	void *ptr;
+
+	memset(&arg, 0, sizeof(arg));
+	arg.handle = handle;
+	arg.offset = offset;
+	arg.flags = flags;
+
+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET, &arg))
+		return NULL;
+
+	ptr = mmap64(0, size, prot, MAP_SHARED, fd, arg.offset);
+
+	if (ptr == MAP_FAILED)
+		ptr = NULL;
+	else
+		errno = 0;
+
+	return ptr;
+}
+
 /**
  * __gem_mmap__wc:
  * @fd: open i915 drm file descriptor
@@ -194,7 +297,10 @@ static void
  */
 void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
-	return __gem_mmap(fd, handle, offset, size, prot, I915_MMAP_WC);
+	if (gem_has_mmap_offset(fd))
+		return __gem_mmap_offset(fd, handle, offset, size, prot, LOCAL_I915_MMAP_OFFSET_WC);
+	else
+		return __gem_mmap(fd, handle, offset, size, prot, I915_MMAP_WC);
 }
 
 /**
@@ -216,6 +322,43 @@ void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsi
 	return ptr;
 }
 
+/**
+ * __gem_mmap_offset__wc:
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ *
+ * Similar to __gem_mmap__wc but this time we use MMAP_OFFSET IOCTL.
+ *
+ * Returns: A pointer to the created memory mapping, NULL on failure.
+ */
+void *__gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
+{
+	return __gem_mmap_offset(fd, handle, offset, size, prot, LOCAL_I915_MMAP_OFFSET_WC);
+}
+
+/**
+ * gem_mmap_offset__wc:
+ * @fd: open i915 drm file descriptor
+ * @handle: gem buffer object handle
+ * @offset: offset in the gem buffer of the mmap arena
+ * @size: size of the mmap arena
+ * @prot: memory protection bits as used by mmap()
+ *
+ * Like __gem_mmap_offset__wc() except we assert on failure.
+ *
+ * Returns: A pointer to the created memory mapping
+ */
+void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
+{
+	void *ptr = __gem_mmap_offset__wc(fd, handle, offset, size, prot);
+
+	igt_assert(ptr);
+	return ptr;
+}
+
 /**
  * __gem_mmap__cpu:
  * @fd: open i915 drm file descriptor
@@ -249,6 +392,7 @@ void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, u
 void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
 {
 	void *ptr = __gem_mmap__cpu(fd, handle, offset, size, prot);
+
 	igt_assert(ptr);
 	return ptr;
 }
diff --git a/lib/i915/gem_mman.h b/lib/i915/gem_mman.h
index f7242ed7..cddf2698 100644
--- a/lib/i915/gem_mman.h
+++ b/lib/i915/gem_mman.h
@@ -25,19 +25,54 @@
 #ifndef GEM_MMAN_H
 #define GEM_MMAN_H
 
+#define LOCAL_I915_GEM_MMAP_OFFSET       DRM_I915_GEM_MMAP_GTT
+#define  LOCAL_IOCTL_I915_GEM_MMAP_OFFSET         DRM_IOWR(DRM_COMMAND_BASE + LOCAL_I915_GEM_MMAP_OFFSET, struct local_i915_gem_mmap_offset)
+
+struct local_i915_gem_mmap_offset {
+	/** Handle for the object being mapped. */
+	__u32 handle;
+	__u32 pad;
+	/**
+	 * Fake offset to use for subsequent mmap call
+	 *
+	 * This is a fixed-size type for 32/64 compatibility.
+	 */
+	__u64 offset;
+	/**
+	 * Flags for extended behaviour.
+	 *
+	 * It is mandatory that either one of the _WC/_WB flags
+	 * should be passed here.
+	 */
+	__u64 flags;
+#define LOCAL_I915_MMAP_OFFSET_WC (1 << 0)
+#define LOCAL_I915_MMAP_OFFSET_WB (1 << 1)
+#define LOCAL_I915_MMAP_OFFSET_UC (1 << 2)
+#define LOCAL_I915_MMAP_OFFSET_FLAGS \
+	(LOCAL_I915_MMAP_OFFSET_WC | LOCAL_I915_MMAP_OFFSET_WB | LOCAL_I915_MMAP_OFFSET_UC)
+};
+
+bool gem_has_mmap_offset(int fd);
+
 void *gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
 void *gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 
 bool gem_mmap__has_wc(int fd);
+bool gem_mmap_offset__has_wc(int fd);
 void *gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
-
+void *gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 #ifndef I915_GEM_DOMAIN_WC
 #define I915_GEM_DOMAIN_WC 0x80
 #endif
 
+void *__gem_mmap(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+		 unsigned int prot, uint64_t flags);
+void *__gem_mmap_offset(int fd, uint32_t handle, uint64_t offset, uint64_t size,
+			 unsigned int prot, uint64_t flags);
 void *__gem_mmap__gtt(int fd, uint32_t handle, uint64_t size, unsigned prot);
 void *__gem_mmap__cpu(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
+void *__gem_mmap_offset__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot);
 
 int gem_munmap(void *ptr, uint64_t size);
 
-- 
2.20.1

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[igt-dev] [RFC PATCH 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Lukasz Kalamarz]

LMEM series introduced concept of memory_regions. This patch implement
helper functions that allow user to manage them in more convenient way.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 lib/Makefile.sources           |   2 +
 lib/i915/intel_memory_region.c | 164 +++++++++++++++++++++++++++++++++
 lib/i915/intel_memory_region.h | 112 ++++++++++++++++++++++
 lib/ioctl_wrappers.h           |   1 +
 lib/meson.build                |   1 +
 5 files changed, 280 insertions(+)
 create mode 100644 lib/i915/intel_memory_region.c
 create mode 100644 lib/i915/intel_memory_region.h

diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index e16de86e..c5dbdeaf 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -17,6 +17,8 @@ lib_source_list =	 	\
 	i915/gem_mman.h	\
 	i915/gem_vm.c	\
 	i915/gem_vm.h	\
+	i915/intel_memory_region.c	\
+	i915/intel_memory_region.h	\
 	i915_3d.h		\
 	i915_reg.h		\
 	i915_pciids.h		\
diff --git a/lib/i915/intel_memory_region.c b/lib/i915/intel_memory_region.c
new file mode 100644
index 00000000..f6978000
--- /dev/null
+++ b/lib/i915/intel_memory_region.c
@@ -0,0 +1,164 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include <signal.h>
+#include <sys/ioctl.h>
+#include <sys/time.h>
+
+#include "intel_reg.h"
+#include "drmtest.h"
+#include "ioctl_wrappers.h"
+#include "igt_dummyload.h"
+#include "igt_gt.h"
+#include "intel_chipset.h"
+
+#include "i915/intel_memory_region.h"
+
+#define i915_query_items(fd, items, n_items) do { \
+		igt_assert_eq(__i915_query_items(fd, items, n_items), 0); \
+		errno = 0; \
+	} while (0)
+#define i915_query_items_err(fd, items, n_items, err) do { \
+		igt_assert_eq(__i915_query_items(fd, items, n_items), -err); \
+	} while (0)
+
+static int
+__i915_query(int fd, struct drm_i915_query *q)
+{
+	if (igt_ioctl(fd, DRM_IOCTL_I915_QUERY, q))
+		return -errno;
+	return 0;
+}
+
+static int
+__i915_query_items(int fd, struct drm_i915_query_item *items, uint32_t n_items)
+{
+	struct drm_i915_query q = {
+		.num_items = n_items,
+		.items_ptr = to_user_pointer(items),
+	};
+	return __i915_query(fd, &q);
+}
+
+bool gem_has_query_support(int fd)
+{
+	struct drm_i915_query query = {};
+
+	return __i915_query(fd, &query) == 0;
+}
+
+const struct intel_memory_region intel_memory_regions[] = {
+	{ "SMEM", LOCAL_I915_SYSTEM_MEMORY, INTEL_MEMORY_REGION_ID(LOCAL_I915_SYSTEM_MEMORY)},
+	{ "LMEM", LOCAL_I915_DEVICE_MEMORY, INTEL_MEMORY_REGION_ID(LOCAL_I915_DEVICE_MEMORY)},
+	{ NULL, 0, 0}
+};
+
+/**
+ *  gem_get_page_size:
+ *  @fd: open i915 drm file descriptor
+ *  @mem_region_type: used memory_region type
+ *
+ *  With introduction of LMEM we observe different page sizes for those two
+ *  memory regions. Without this helper function we may be prone to forget
+ *  about setting proper page size.
+ */
+uint32_t gem_get_batch_size(int fd, uint8_t mem_region_type)
+{
+	return (mem_region_type == LOCAL_I915_DEVICE_MEMORY) ? 65536 : 4096;
+}
+
+/**
+ * gem_get_query_memory_regions:
+ * @fd: open i915 drm file descriptor
+ *
+ * This function wraps query mechanism for memory regions.
+ *
+ * Returns: Filled struct with available memory regions.
+ */
+struct local_i915_query_memory_region_info *gem_get_query_memory_regions(int fd)
+{
+	struct drm_i915_query_item item;
+	struct local_i915_query_memory_region_info *query_info;
+
+	memset(&item, 0, sizeof(item));
+	item.query_id = LOCAL_I915_QUERY_MEMREGION_INFO;
+	i915_query_items(fd, &item, 1);
+
+	query_info = calloc(1, item.length);
+
+	item.data_ptr = to_user_pointer(query_info);
+	i915_query_items(fd, &item, 1);
+
+	return query_info;
+}
+
+/**
+ * gem_bo_set_memory_region:
+ * @fd: open i915 drm file descriptor
+ * @handle: buffer object handle
+ * @id: memory region id
+ *
+ * Wrapper function on IOCTL_I915_GEM_OBJECT_SETPARAM. It sets object to be
+ * migrated into @id memory region.
+ *
+ * Returns: errno
+ */
+int gem_bo_set_memory_region(int fd, int handle, uint32_t id)
+{
+	struct local_i915_gem_object_param obj;
+	int err = 0;
+
+	memset(&obj, 0, sizeof(obj));
+	obj.handle = handle;
+	obj.size = 1;
+	obj.param = LOCAL_I915_PARAM_MEMORY_REGION | LOCAL_I915_OBJECT_PARAM;
+	obj.data = to_user_pointer(&id);
+
+	if (igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_OBJECT_SETPARAM, &obj)) {
+		err = -errno;
+		errno = 0;
+	}
+
+	return err;
+}
+/**
+ * gem_find_memory_region_in_query:
+ * @query_info: query result of memory regions
+ * @num_regions: number of memory regions from @query_info
+ * @id: memory region id
+ *
+ * This function iterate over @num_regions of memory regions obtained by
+ * @query_info to find if memory region with given @id is available.
+ *
+ * Returns: true if memory region was found. Otherwise false.
+ */
+bool gem_find_memory_region_in_query(struct local_i915_query_memory_region_info *query_info,
+				     uint8_t num_regions, uint32_t id)
+{
+	for (int i = 0; i < num_regions; i++) {
+		if (query_info->regions[i].id == id)
+			return true;
+	}
+
+	return false;
+}
diff --git a/lib/i915/intel_memory_region.h b/lib/i915/intel_memory_region.h
new file mode 100644
index 00000000..dd04bed4
--- /dev/null
+++ b/lib/i915/intel_memory_region.h
@@ -0,0 +1,112 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+#include "benchmarks/ilog2.h"
+
+#ifndef INTEL_MEMORY_REGION_H
+#define INTEL_MEMORY_REGION_H
+
+#define LOCAL_I915_QUERY_MEMREGION_INFO   3
+
+struct local_i915_memory_region_info {
+
+	/** Base type of a region */
+#define LOCAL_I915_SYSTEM_MEMORY         0
+#define LOCAL_I915_DEVICE_MEMORY         1
+
+	/** The region id is encoded in a layout which makes it possible to
+	 * retrieve the following information:
+	 *
+	 *  Base type: log2(ID >> 16)
+	 */
+	__u32 id;
+
+	/** Reserved field. MBZ */
+	__u32 rsvd0;
+
+	/** Unused for now. MBZ */
+	__u64 flags;
+
+	__u64 size;
+
+	/** Reserved fields must be cleared to zero. */
+	__u64 rsvd1[4];
+};
+
+struct local_i915_query_memory_region_info {
+
+	/** Number of struct drm_i915_memory_region_info structs */
+	__u32 num_regions;
+
+	/** MBZ */
+	__u32 rsvd[3];
+
+	struct local_i915_memory_region_info regions[];
+};
+
+#define INTEL_MEMORY_TYPE_SHIFT 16
+
+#define INTEL_MEMORY_REGION_ID(type) \
+			((BIT((type) + INTEL_MEMORY_TYPE_SHIFT)) | BIT(0))
+#define MEMORY_TYPE_FROM_REGION(r) (ilog2(r >> INTEL_MEMORY_TYPE_SHIFT))
+
+extern const struct intel_memory_region {
+	const char *region_name;
+	uint8_t mem_region_type;
+	uint32_t id;
+} intel_memory_regions[];
+
+bool gem_has_query_support(int fd);
+
+uint32_t gem_get_batch_size(int fd, uint8_t mem_region_type);
+
+struct local_i915_query_memory_region_info *gem_get_query_memory_regions(int fd);
+
+bool gem_find_memory_region_in_query(struct local_i915_query_memory_region_info *query_info,
+				     uint8_t num_regions, uint32_t id);
+
+#define LOCAL_I915_GEM_OBJECT_SETPARAM   DRM_I915_GEM_CONTEXT_SETPARAM
+#define LOCAL_IOCTL_I915_GEM_OBJECT_SETPARAM     DRM_IOWR(DRM_COMMAND_BASE + LOCAL_I915_GEM_OBJECT_SETPARAM, struct local_i915_gem_object_param)
+
+struct local_i915_gem_object_param {
+	/** Handle for the object */
+	__u32 handle;
+
+	__u32 size;
+
+	/** Set the memory region for the object listed in preference order
+	 *  as an array of region ids within data. To force an object
+	 *  to a particular memory region, set the region as the sole entry.
+	 *
+	 *  Valid region ids are derived from the id field of
+	 *  struct drm_i915_memory_region_info.
+	 *  See struct drm_i915_query_memory_region_info.
+	 */
+#define LOCAL_I915_OBJECT_PARAM  (1ull<<32)
+#define LOCAL_I915_PARAM_MEMORY_REGION 0x1
+
+	__u64 param;
+
+	__u64 data;
+};
+int gem_bo_set_memory_region(int fd, int handle, uint32_t id);
+#endif /* INTEL_MEMORY_REGION_H */
diff --git a/lib/ioctl_wrappers.h b/lib/ioctl_wrappers.h
index 03211c97..f2091295 100644
--- a/lib/ioctl_wrappers.h
+++ b/lib/ioctl_wrappers.h
@@ -38,6 +38,7 @@
 
 #include "i915/gem_context.h"
 #include "i915/gem_scheduler.h"
+#include "i915/intel_memory_region.h"
 
 /**
  * igt_ioctl:
diff --git a/lib/meson.build b/lib/meson.build
index 157624e7..52d214b1 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -7,6 +7,7 @@ lib_sources = [
 	'i915/gem_ring.c',
 	'i915/gem_mman.c',
 	'i915/gem_vm.c',
+	'i915/intel_memory_region.c',
 	'igt_color_encoding.c',
 	'igt_debugfs.c',
 	'igt_device.c',
-- 
2.20.1

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[igt-dev] [RFC PATCH 3/4] tests/i915/gem_mmap_offset: Add new API test for gem_mmap_offset

[Lukasz Kalamarz]

This test is a copy/paste of few gem_mmap subtests, due to good
coverage in previous one. We also need to be sure that we cover
all available memory regions.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 tests/Makefile.sources       |   3 +
 tests/i915/gem_mmap_offset.c | 197 +++++++++++++++++++++++++++++++++++
 tests/meson.build            |   1 +
 3 files changed, 201 insertions(+)
 create mode 100644 tests/i915/gem_mmap_offset.c

diff --git a/tests/Makefile.sources b/tests/Makefile.sources
index 250dbd33..cd7daf4f 100644
--- a/tests/Makefile.sources
+++ b/tests/Makefile.sources
@@ -307,6 +307,9 @@ gem_mmap_SOURCES = i915/gem_mmap.c
 TESTS_progs += gem_mmap_gtt
 gem_mmap_gtt_SOURCES = i915/gem_mmap_gtt.c
 
+TESTS_progs += gem_mmap_offset
+gem_mmap_offset_SOURCES = i915/gem_mmap_offset.c
+
 TESTS_progs += gem_mmap_offset_exhaustion
 gem_mmap_offset_exhaustion_SOURCES = i915/gem_mmap_offset_exhaustion.c
 
diff --git a/tests/i915/gem_mmap_offset.c b/tests/i915/gem_mmap_offset.c
new file mode 100644
index 00000000..8c5ed17e
--- /dev/null
+++ b/tests/i915/gem_mmap_offset.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
+ * IN THE SOFTWARE.
+ */
+
+#include "igt.h"
+#include <errno.h>
+#include <sys/stat.h>
+#include <sys/ioctl.h>
+#include "drm.h"
+
+IGT_TEST_DESCRIPTION("Basic MMAP_OFFSET IOCTL tests for mem regions\n");
+
+int fd;
+
+static const char * const mmap_offset_flags[] = {
+	[LOCAL_I915_MMAP_OFFSET_WC] = "wc",
+	[LOCAL_I915_MMAP_OFFSET_WB] = "wb",
+	[LOCAL_I915_MMAP_OFFSET_UC] = "uc"
+};
+
+static int mmap_offset_ioctl(int i915, struct local_i915_gem_mmap_offset *arg)
+{
+	int err = 0;
+
+	if (igt_ioctl(i915, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET, arg))
+		err = -errno;
+
+	errno = 0;
+	return err;
+}
+
+igt_main
+{
+	uint8_t *addr;
+	uint32_t obj_size, batch_size;
+	uint8_t mem_type;
+	uint32_t id;
+	uint32_t num_regions;
+	int ret;
+	const struct intel_memory_region *mr;
+	struct local_i915_query_memory_region_info *query_info;
+
+	igt_fixture {
+		fd = drm_open_driver(DRIVER_INTEL);
+		igt_require(gem_has_mmap_offset(fd));
+
+		query_info = gem_get_query_memory_regions(fd);
+		igt_assert(query_info);
+		num_regions = query_info->num_regions;
+	}
+
+	for (mr = intel_memory_regions; mr->region_name; mr++) {
+		mem_type = mr->mem_region_type;
+		id = mr->id;
+
+		batch_size = gem_get_batch_size(fd, mem_type);
+		obj_size = 4 * batch_size;
+
+		igt_subtest_f("bad-object-%s", mr->region_name) {
+			uint32_t real_handle = gem_create(fd, batch_size);
+			uint32_t handles[20];
+			int i = 0;
+
+			ret = -1;
+
+			ret = gem_find_memory_region_in_query(query_info,
+							      num_regions, id);
+			igt_require(ret);
+
+			ret = gem_bo_set_memory_region(fd, real_handle, id);
+			igt_assert_eq(ret, 0);
+
+			handles[i++] = 0xdeadbeef;
+			for (int bit = 0; bit < 16; bit++)
+				handles[i++] = real_handle | (1 << (bit + 16));
+			handles[i] = real_handle + 1;
+
+			for (; i < 0; i--) {
+				struct local_i915_gem_mmap_offset arg = {
+					.handle = handles[i],
+					.flags = LOCAL_I915_MMAP_OFFSET_WB,
+				};
+
+				igt_debug("Trying to set memory region\n");
+				ret = gem_bo_set_memory_region(fd, arg.handle,
+							       id);
+				igt_assert_eq(ret, -EINVAL);
+
+				igt_debug("Trying MMAP IOCTL with handle %x\n",
+					  handles[i]);
+				igt_assert_eq(mmap_offset_ioctl(fd, &arg),
+					      -EINVAL);
+			}
+
+			gem_close(fd, real_handle);
+		}
+
+		for (unsigned flags = 0; flags < LOCAL_I915_MMAP_OFFSET_FLAGS + 1; flags++) {
+
+			igt_subtest_f("basic-%s-%s", mmap_offset_flags[flags],
+				      mr->region_name) {
+				struct local_i915_gem_mmap_offset arg = {
+					.handle = gem_create(fd, obj_size),
+					.flags = flags,
+				};
+
+				uint8_t *expected;
+				uint8_t *buf;
+
+				ret = gem_find_memory_region_in_query(query_info,
+								      num_regions,
+								      id);
+				igt_require(ret);
+
+				ret = gem_bo_set_memory_region(fd, arg.handle,
+							       id);
+				igt_assert_eq(ret, 0);
+
+				igt_assert_eq(mmap_offset_ioctl(fd, &arg), 0);
+				addr = mmap64(0, obj_size, PROT_READ | PROT_WRITE,
+					      MAP_SHARED, fd, arg.offset);
+				igt_assert(addr != MAP_FAILED);
+
+				igt_info("Testing contents of newly created object.\n");
+				expected = calloc(obj_size, sizeof(expected));
+				memset(expected, 0, obj_size * sizeof(expected));
+				igt_assert_eq(memcmp(addr, expected, obj_size), 0);
+				free(expected);
+
+				igt_info("Testing coherency of writes and mmap reads.\n");
+				buf = calloc(obj_size, sizeof(buf));
+				memset(buf, 0, obj_size * sizeof(buf));
+				memset(buf + 1024, 0x01, 1024);
+				gem_write(fd, arg.handle, 0, buf, obj_size);
+				igt_assert_eq(memcmp(buf, addr, obj_size), 0);
+
+				igt_info("Testing that mapping stays after close\n");
+				gem_close(fd, arg.handle);
+				igt_assert_eq(memcmp(buf, addr, obj_size), 0);
+				free(buf);
+
+				igt_info("Testing unmapping\n");
+				munmap(addr, obj_size);
+			}
+
+			igt_subtest_f("short-mmap-%s-%s", mmap_offset_flags[flags],
+				      mr->region_name) {
+				uint32_t handle = gem_create(fd, obj_size);
+
+				ret = -1;
+
+				ret = gem_find_memory_region_in_query(query_info,
+								      num_regions,
+								      id);
+
+				igt_require(ret);
+
+				ret = gem_bo_set_memory_region(fd, handle, id);
+				igt_assert_eq(ret, 0);
+
+				igt_assert(obj_size > batch_size);
+
+				addr = __gem_mmap_offset(fd, handle, 0,
+							 batch_size, PROT_WRITE,
+							 flags);
+				memset(addr, 0, batch_size);
+				munmap(addr, batch_size);
+
+				gem_close(fd, handle);
+			}
+		}
+	}
+
+	igt_fixture {
+		free(query_info);
+		close(fd);
+	}
+}
diff --git a/tests/meson.build b/tests/meson.build
index 34a74025..236aaede 100644
--- a/tests/meson.build
+++ b/tests/meson.build
@@ -167,6 +167,7 @@ i915_progs = [
 	'gem_media_vme',
 	'gem_mmap',
 	'gem_mmap_gtt',
+	'gem_mmap_offset',
 	'gem_mmap_offset_exhaustion',
 	'gem_mmap_wc',
 	'gem_partial_pwrite_pread',
-- 
2.20.1

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[igt-dev] [RFC PATCH 4/4] tests/i915/gem_exec_basic: Iterate over all memory regions

[Lukasz Kalamarz]

As a part of local memory effort we need to make sure, that basic
scenarios are covered for every available memory region. This patch is
an attempt for this problem. If it will be accepted it will be
replicated on each test that can benefit from it.

Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
---
 tests/i915/gem_exec_basic.c | 138 +++++++++++++++++++++++++++++-------
 1 file changed, 111 insertions(+), 27 deletions(-)

diff --git a/tests/i915/gem_exec_basic.c b/tests/i915/gem_exec_basic.c
index 1287860b..69a8c991 100644
--- a/tests/i915/gem_exec_basic.c
+++ b/tests/i915/gem_exec_basic.c
@@ -25,12 +25,29 @@
 
 IGT_TEST_DESCRIPTION("Basic sanity check of execbuf-ioctl rings.");
 
-static uint32_t batch_create(int fd)
+struct set_param_args {
+	struct local_i915_query_memory_region_info *query_info;
+	uint32_t num_regions;
+	uint32_t mem_type;
+	uint32_t id;
+	uint32_t batch_size;
+	bool set_param;
+};
+
+static uint32_t batch_create(int fd, struct set_param_args *spa)
 {
 	const uint32_t bbe = MI_BATCH_BUFFER_END;
 	uint32_t handle;
 
-	handle = gem_create(fd, 4096);
+	handle = gem_create(fd, spa->batch_size);
+
+	if (spa->set_param == true) {
+		int ret = -1;
+
+		ret = gem_bo_set_memory_region(fd, handle, spa->id);
+		igt_assert_eq(ret, 0);
+	}
+
 	gem_write(fd, handle, 0, &bbe, sizeof(bbe));
 
 	return handle;
@@ -42,16 +59,24 @@ static void batch_fini(int fd, uint32_t handle)
 	gem_close(fd, handle);
 }
 
-static void noop(int fd, uint64_t flags)
+static void noop(int fd, uint64_t flags, struct set_param_args *spa)
 {
 	struct drm_i915_gem_execbuffer2 execbuf;
 	struct drm_i915_gem_exec_object2 exec;
+	int ret = -1;
 
 	gem_require_ring(fd, flags);
 
+	if (spa->set_param == true) {
+		ret = gem_find_memory_region_in_query(spa->query_info,
+						      spa->num_regions,
+						      spa->id);
+		igt_require(ret);
+	}
+
 	memset(&exec, 0, sizeof(exec));
 
-	exec.handle = batch_create(fd);
+	exec.handle = batch_create(fd, spa);
 
 	memset(&execbuf, 0, sizeof(execbuf));
 	execbuf.buffers_ptr = to_user_pointer(&exec);
@@ -62,47 +87,70 @@ static void noop(int fd, uint64_t flags)
 	batch_fini(fd, exec.handle);
 }
 
-static void readonly(int fd, uint64_t flags)
+static void readonly(int fd, uint64_t flags, struct set_param_args *spa)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 exec;
+	int ret = -1;
 
 	gem_require_ring(fd, flags);
 
-	memset(&exec, 0, sizeof(exec));
-	exec.handle = batch_create(fd);
+	if (spa->set_param == true) {
+		ret = gem_find_memory_region_in_query(spa->query_info,
+						      spa->num_regions,
+						      spa->id);
+		igt_require(ret);
+	}
 
-	execbuf = mmap(NULL, 4096, PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);
+	memset(&exec, 0, sizeof(exec));
+	exec.handle = batch_create(fd, spa);
+
+	execbuf = mmap(NULL, spa->batch_size, PROT_WRITE,
+		       MAP_ANON | MAP_PRIVATE, -1, 0);
 	igt_assert(execbuf != NULL);
 
 	execbuf->buffers_ptr = to_user_pointer(&exec);
 	execbuf->buffer_count = 1;
 	execbuf->flags = flags;
-	igt_assert(mprotect(execbuf, 4096, PROT_READ) == 0);
+	igt_assert(mprotect(execbuf, spa->batch_size, PROT_READ) == 0);
 
 	gem_execbuf(fd, execbuf);
 
-	munmap(execbuf, 4096);
+	munmap(execbuf, spa->batch_size);
 
 	batch_fini(fd, exec.handle);
 }
 
-static void gtt(int fd, uint64_t flags)
+static void gtt(int fd, uint64_t flags, struct set_param_args *spa)
 {
 	struct drm_i915_gem_execbuffer2 *execbuf;
 	struct drm_i915_gem_exec_object2 *exec;
 	uint32_t handle;
+	int ret = -1;
 
 	gem_require_ring(fd, flags);
 
-	handle = gem_create(fd, 4096);
+
+	if (spa->set_param == true) {
+		ret = gem_find_memory_region_in_query(spa->query_info,
+						      spa->num_regions,
+						      spa->id);
+		igt_require(ret);
+	}
+
+	handle = gem_create(fd, spa->batch_size);
+
+	if (spa->set_param == true) {
+		ret = gem_bo_set_memory_region(fd, handle, spa->id);
+		igt_assert_eq(ret, 0);
+	}
 
 	gem_set_domain(fd, handle, I915_GEM_DOMAIN_GTT, I915_GEM_DOMAIN_GTT);
-	execbuf = gem_mmap__gtt(fd, handle, 4096, PROT_WRITE);
+	execbuf = gem_mmap__gtt(fd, handle, spa->batch_size, PROT_WRITE);
 	exec = (struct drm_i915_gem_exec_object2 *)(execbuf + 1);
 	gem_close(fd, handle);
 
-	exec->handle = batch_create(fd);
+	exec->handle = batch_create(fd, spa);
 
 	execbuf->buffers_ptr = to_user_pointer(exec);
 	execbuf->buffer_count = 1;
@@ -111,36 +159,38 @@ static void gtt(int fd, uint64_t flags)
 	gem_execbuf(fd, execbuf);
 
 	batch_fini(fd, exec->handle);
-	munmap(execbuf, 4096);
+	munmap(execbuf, spa->batch_size);
 }
 
-static void all(int i915)
+static void all(int i915, struct set_param_args *spa)
 {
 	const struct intel_execution_engine2 *e;
 
 	__for_each_physical_engine(i915, e)
-		noop(i915, e->flags);
+		noop(i915, e->flags, spa);
 }
 
-static void readonly_all(int i915)
+static void readonly_all(int i915, struct set_param_args *spa)
 {
 	const struct intel_execution_engine2 *e;
 
 	__for_each_physical_engine(i915, e)
-		readonly(i915, e->flags);
+		readonly(i915, e->flags, spa);
 }
 
-static void gtt_all(int i915)
+static void gtt_all(int i915, struct set_param_args *spa)
 {
 	const struct intel_execution_engine2 *e;
 
 	__for_each_physical_engine(i915, e)
-		gtt(i915, e->flags);
+		gtt(i915, e->flags, spa);
 }
 
 igt_main
 {
 	const struct intel_execution_engine2 *e;
+	const struct intel_memory_region *mr;
+	struct set_param_args spa;
 	int fd = -1;
 
 	igt_fixture {
@@ -148,27 +198,61 @@ igt_main
 		igt_require_gem(fd);
 
 		igt_fork_hang_detector(fd);
+
+		spa.query_info = gem_get_query_memory_regions(fd);
+		igt_assert(spa.query_info);
+		spa.num_regions = spa.query_info->num_regions;
 	}
 
+	spa.batch_size = 4096;
+	spa.set_param = false;
+
 	igt_subtest("basic-all")
-		all(fd);
+		all(fd, &spa);
 
 	igt_subtest("readonly-all")
-		readonly_all(fd);
+		readonly_all(fd, &spa);
 
 	igt_subtest("gtt-all")
-		gtt_all(fd);
+		gtt_all(fd, &spa);
 
 	__for_each_physical_engine(fd, e) {
 		igt_subtest_f("basic-%s", e->name)
-			noop(fd, e->flags);
+			noop(fd, e->flags, &spa);
 		igt_subtest_f("readonly-%s", e->name)
-			readonly(fd, e->flags);
+			readonly(fd, e->flags, &spa);
 		igt_subtest_f("gtt-%s", e->name)
-			gtt(fd, e->flags);
+			gtt(fd, e->flags, &spa);
+	}
+
+	spa.set_param = true;
+	for (mr = intel_memory_regions; mr->region_name; mr++) {
+		spa.mem_type = mr->mem_region_type;
+		spa.id = mr->id;
+		spa.batch_size = gem_get_batch_size(fd, spa.mem_type);
+
+		igt_subtest_f("basic-%s-all", mr->region_name)
+			all(fd, &spa);
+
+		igt_subtest_f("readonly-%s-all", mr->region_name)
+			readonly_all(fd, &spa);
+
+		igt_subtest_f("gtt-%s-all", mr->region_name)
+			gtt_all(fd, &spa);
+
+		__for_each_physical_engine(fd, e) {
+			igt_subtest_f("basic-%s-%s", mr->region_name, e->name)
+				noop(fd, e->flags, &spa);
+			igt_subtest_f("readonly-%s-%s", mr->region_name,
+				      e->name)
+				readonly(fd, e->flags, &spa);
+			igt_subtest_f("gtt-%s-%s", mr->region_name, e->name)
+				gtt(fd, e->flags, &spa);
+		}
 	}
 
 	igt_fixture {
+		free(spa.query_info);
 		igt_stop_hang_detector();
 		close(fd);
 	}
-- 
2.20.1

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Re: [igt-dev] [RFC PATCH 1/4] lib/i915/gem_mman: add mmap_offset support

[Chris Wilson]

Quoting Lukasz Kalamarz (2019-08-14 11:21:37)
> With introduction of LMEM concept new IOCTL call were implemented
> - gem_mmap_offset. This patch add support in IGT for it.
> 
> Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> ---
>  lib/i915/gem_mman.c | 188 ++++++++++++++++++++++++++++++++++++++------
>  lib/i915/gem_mman.h |  37 ++++++++-
>  2 files changed, 202 insertions(+), 23 deletions(-)
> 
> diff --git a/lib/i915/gem_mman.c b/lib/i915/gem_mman.c
> index 3cf9a6bb..2b28a67c 100644
> --- a/lib/i915/gem_mman.c
> +++ b/lib/i915/gem_mman.c
> @@ -40,6 +40,27 @@
>  #define VG(x) do {} while (0)
>  #endif
>  
> +#define LOCAL_I915_PARAM_MMAP_OFFSET_VERSION 54
> +
> +bool gem_has_mmap_offset(int fd)
> +{
> +       static int has_mmap_offset = -1;
> +
> +       if (has_mmap_offset == -1) {

How many times do I have to say that I am sorry for introducing static
here. It was to cut down on strace spam, but no one should be repeatedly
checking, so please don't cargo cult it. It doesn't bode well.
-Chris
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Re: [igt-dev] [RFC PATCH 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Chris Wilson]

Quoting Lukasz Kalamarz (2019-08-14 11:21:38)
> +/**
> + *  gem_get_page_size:
> + *  @fd: open i915 drm file descriptor
> + *  @mem_region_type: used memory_region type
> + *
> + *  With introduction of LMEM we observe different page sizes for those two
> + *  memory regions. Without this helper function we may be prone to forget
> + *  about setting proper page size.
> + */
> +uint32_t gem_get_batch_size(int fd, uint8_t mem_region_type)
> +{
> +       return (mem_region_type == LOCAL_I915_DEVICE_MEMORY) ? 65536 : 4096;

You have to be kidding me. This, this constitutes a forward thinking uAPI?
-Chris
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[igt-dev] ✗ Fi.CI.BAT: failure for Basic LMEM support in IGT

[Patchwork]

== Series Details ==

Series: Basic LMEM support in IGT
URL   : https://patchwork.freedesktop.org/series/65171/
State : failure

== Summary ==

CI Bug Log - changes from IGT_5134 -> IGTPW_3346
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with IGTPW_3346 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_3346, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/65171/revisions/1/mbox/

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_3346:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_basic@basic-all:
    - fi-cfl-guc:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-cfl-guc/igt@gem_exec_basic@basic-all.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-cfl-guc/igt@gem_exec_basic@basic-all.html
    - fi-hsw-4770r:       [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-hsw-4770r/igt@gem_exec_basic@basic-all.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-hsw-4770r/igt@gem_exec_basic@basic-all.html
    - fi-glk-dsi:         [PASS][5] -> [FAIL][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-glk-dsi/igt@gem_exec_basic@basic-all.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-glk-dsi/igt@gem_exec_basic@basic-all.html
    - fi-skl-gvtdvm:      [PASS][7] -> [FAIL][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-gvtdvm/igt@gem_exec_basic@basic-all.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-gvtdvm/igt@gem_exec_basic@basic-all.html
    - fi-kbl-8809g:       [PASS][9] -> [FAIL][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-kbl-8809g/igt@gem_exec_basic@basic-all.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-kbl-8809g/igt@gem_exec_basic@basic-all.html
    - fi-bdw-gvtdvm:      [PASS][11] -> [FAIL][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bdw-gvtdvm/igt@gem_exec_basic@basic-all.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bdw-gvtdvm/igt@gem_exec_basic@basic-all.html
    - fi-bdw-5557u:       [PASS][13] -> [FAIL][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bdw-5557u/igt@gem_exec_basic@basic-all.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bdw-5557u/igt@gem_exec_basic@basic-all.html
    - fi-kbl-7567u:       [PASS][15] -> [FAIL][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-kbl-7567u/igt@gem_exec_basic@basic-all.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-kbl-7567u/igt@gem_exec_basic@basic-all.html
    - fi-whl-u:           [PASS][17] -> [FAIL][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-whl-u/igt@gem_exec_basic@basic-all.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-whl-u/igt@gem_exec_basic@basic-all.html
    - fi-snb-2520m:       [PASS][19] -> [FAIL][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-snb-2520m/igt@gem_exec_basic@basic-all.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-snb-2520m/igt@gem_exec_basic@basic-all.html
    - fi-hsw-4770:        [PASS][21] -> [FAIL][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-hsw-4770/igt@gem_exec_basic@basic-all.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-hsw-4770/igt@gem_exec_basic@basic-all.html
    - fi-bxt-dsi:         [PASS][23] -> [FAIL][24]
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bxt-dsi/igt@gem_exec_basic@basic-all.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bxt-dsi/igt@gem_exec_basic@basic-all.html
    - fi-skl-iommu:       [PASS][25] -> [FAIL][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-iommu/igt@gem_exec_basic@basic-all.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-iommu/igt@gem_exec_basic@basic-all.html
    - fi-icl-u2:          [PASS][27] -> [FAIL][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-u2/igt@gem_exec_basic@basic-all.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-u2/igt@gem_exec_basic@basic-all.html
    - fi-cml-u2:          [PASS][29] -> [FAIL][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-cml-u2/igt@gem_exec_basic@basic-all.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-cml-u2/igt@gem_exec_basic@basic-all.html
    - fi-byt-n2820:       [PASS][31] -> [FAIL][32]
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-byt-n2820/igt@gem_exec_basic@basic-all.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-byt-n2820/igt@gem_exec_basic@basic-all.html
    - fi-ivb-3770:        [PASS][33] -> [FAIL][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-ivb-3770/igt@gem_exec_basic@basic-all.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-ivb-3770/igt@gem_exec_basic@basic-all.html
    - fi-bsw-n3050:       [PASS][35] -> [FAIL][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bsw-n3050/igt@gem_exec_basic@basic-all.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bsw-n3050/igt@gem_exec_basic@basic-all.html
    - fi-ilk-650:         [PASS][37] -> [FAIL][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-ilk-650/igt@gem_exec_basic@basic-all.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-ilk-650/igt@gem_exec_basic@basic-all.html
    - fi-icl-u3:          [PASS][39] -> [FAIL][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-u3/igt@gem_exec_basic@basic-all.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-u3/igt@gem_exec_basic@basic-all.html
    - fi-skl-lmem:        [PASS][41] -> [FAIL][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-lmem/igt@gem_exec_basic@basic-all.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-lmem/igt@gem_exec_basic@basic-all.html
    - fi-bxt-j4205:       [PASS][43] -> [FAIL][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bxt-j4205/igt@gem_exec_basic@basic-all.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bxt-j4205/igt@gem_exec_basic@basic-all.html
    - fi-snb-2600:        [PASS][45] -> [FAIL][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-snb-2600/igt@gem_exec_basic@basic-all.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-snb-2600/igt@gem_exec_basic@basic-all.html
    - fi-skl-6770hq:      [PASS][47] -> [FAIL][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-6770hq/igt@gem_exec_basic@basic-all.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-6770hq/igt@gem_exec_basic@basic-all.html
    - fi-bsw-kefka:       [PASS][49] -> [FAIL][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bsw-kefka/igt@gem_exec_basic@basic-all.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bsw-kefka/igt@gem_exec_basic@basic-all.html
    - fi-blb-e6850:       [PASS][51] -> [FAIL][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-blb-e6850/igt@gem_exec_basic@basic-all.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-blb-e6850/igt@gem_exec_basic@basic-all.html
    - fi-skl-6260u:       [PASS][53] -> [FAIL][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-6260u/igt@gem_exec_basic@basic-all.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-6260u/igt@gem_exec_basic@basic-all.html
    - fi-gdg-551:         [PASS][55] -> [FAIL][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-gdg-551/igt@gem_exec_basic@basic-all.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-gdg-551/igt@gem_exec_basic@basic-all.html
    - fi-kbl-r:           [PASS][57] -> [FAIL][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-kbl-r/igt@gem_exec_basic@basic-all.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-kbl-r/igt@gem_exec_basic@basic-all.html
    - fi-cfl-8109u:       [PASS][59] -> [FAIL][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-cfl-8109u/igt@gem_exec_basic@basic-all.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-cfl-8109u/igt@gem_exec_basic@basic-all.html
    - fi-kbl-guc:         [PASS][61] -> [FAIL][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-kbl-guc/igt@gem_exec_basic@basic-all.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-kbl-guc/igt@gem_exec_basic@basic-all.html
    - fi-pnv-d510:        [PASS][63] -> [FAIL][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-pnv-d510/igt@gem_exec_basic@basic-all.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-pnv-d510/igt@gem_exec_basic@basic-all.html
    - fi-skl-6600u:       [PASS][65] -> [FAIL][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-6600u/igt@gem_exec_basic@basic-all.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-6600u/igt@gem_exec_basic@basic-all.html
    - fi-bwr-2160:        [PASS][67] -> [FAIL][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-bwr-2160/igt@gem_exec_basic@basic-all.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-bwr-2160/igt@gem_exec_basic@basic-all.html
    - fi-skl-guc:         [PASS][69] -> [FAIL][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-guc/igt@gem_exec_basic@basic-all.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-guc/igt@gem_exec_basic@basic-all.html
    - fi-apl-guc:         [PASS][71] -> [FAIL][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-apl-guc/igt@gem_exec_basic@basic-all.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-apl-guc/igt@gem_exec_basic@basic-all.html
    - fi-elk-e7500:       [PASS][73] -> [FAIL][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-elk-e7500/igt@gem_exec_basic@basic-all.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-elk-e7500/igt@gem_exec_basic@basic-all.html
    - fi-skl-6700k2:      [PASS][75] -> [FAIL][76]
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-skl-6700k2/igt@gem_exec_basic@basic-all.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-skl-6700k2/igt@gem_exec_basic@basic-all.html
    - fi-byt-j1900:       [PASS][77] -> [FAIL][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-byt-j1900/igt@gem_exec_basic@basic-all.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-byt-j1900/igt@gem_exec_basic@basic-all.html
    - fi-cfl-8700k:       [PASS][79] -> [FAIL][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-cfl-8700k/igt@gem_exec_basic@basic-all.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-cfl-8700k/igt@gem_exec_basic@basic-all.html
    - fi-cml-u:           [PASS][81] -> [FAIL][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-cml-u/igt@gem_exec_basic@basic-all.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-cml-u/igt@gem_exec_basic@basic-all.html
    - fi-kbl-x1275:       [PASS][83] -> [FAIL][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-kbl-x1275/igt@gem_exec_basic@basic-all.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-kbl-x1275/igt@gem_exec_basic@basic-all.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * igt@gem_exec_basic@basic-all:
    - {fi-icl-u4}:        [PASS][85] -> [FAIL][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-u4/igt@gem_exec_basic@basic-all.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-u4/igt@gem_exec_basic@basic-all.html
    - {fi-icl-dsi}:       [PASS][87] -> [FAIL][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-dsi/igt@gem_exec_basic@basic-all.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-dsi/igt@gem_exec_basic@basic-all.html
    - {fi-icl-guc}:       [PASS][89] -> [FAIL][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-guc/igt@gem_exec_basic@basic-all.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-guc/igt@gem_exec_basic@basic-all.html

  
Known issues
------------

  Here are the changes found in IGTPW_3346 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_requests:
    - fi-byt-j1900:       [PASS][91] -> [INCOMPLETE][92] ([fdo#102657])
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-byt-j1900/igt@i915_selftest@live_requests.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-byt-j1900/igt@i915_selftest@live_requests.html

  
#### Possible fixes ####

  * igt@gem_ctx_switch@rcs0:
    - {fi-icl-guc}:       [FAIL][93] ([fdo#110946]) -> [PASS][94]
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-guc/igt@gem_ctx_switch@rcs0.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-guc/igt@gem_ctx_switch@rcs0.html

  * igt@gem_exec_fence@nb-await-default:
    - fi-icl-u3:          [DMESG-WARN][95] ([fdo#107724]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-u3/igt@gem_exec_fence@nb-await-default.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-u3/igt@gem_exec_fence@nb-await-default.html

  * igt@gem_exec_suspend@basic-s4-devices:
    - fi-blb-e6850:       [INCOMPLETE][97] ([fdo#107718]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html

  * igt@i915_selftest@live_hangcheck:
    - {fi-icl-guc}:       [INCOMPLETE][99] ([fdo#107713] / [fdo#108569]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-guc/igt@i915_selftest@live_hangcheck.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-guc/igt@i915_selftest@live_hangcheck.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u2:          [FAIL][101] ([fdo#103167]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
#### Warnings ####

  * igt@kms_chamelium@vga-edid-read:
    - fi-icl-u2:          [FAIL][103] ([fdo#109483]) -> [SKIP][104] ([fdo#109309])
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5134/fi-icl-u2/igt@kms_chamelium@vga-edid-read.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/fi-icl-u2/igt@kms_chamelium@vga-edid-read.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102657]: https://bugs.freedesktop.org/show_bug.cgi?id=102657
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
  [fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#110946]: https://bugs.freedesktop.org/show_bug.cgi?id=110946


Participating hosts (53 -> 45)
------------------------------

  Missing    (8): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * IGT: IGT_5134 -> IGTPW_3346

  CI_DRM_6706: 57b60ae5ac6b9d384440562785c2581f6ee8330f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_3346: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/
  IGT_5134: 81df2f22385bc275975cf199d962eed9bc10f916 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools



== Testlist changes ==

+igt@gem_exec_basic@basic-lmem-all
+igt@gem_exec_basic@basic-lmem-bcs0
+igt@gem_exec_basic@basic-lmem-rcs0
+igt@gem_exec_basic@basic-lmem-vcs0
+igt@gem_exec_basic@basic-lmem-vcs1
+igt@gem_exec_basic@basic-lmem-vcs2
+igt@gem_exec_basic@basic-lmem-vecs0
+igt@gem_exec_basic@basic-smem-all
+igt@gem_exec_basic@basic-smem-bcs0
+igt@gem_exec_basic@basic-smem-rcs0
+igt@gem_exec_basic@basic-smem-vcs0
+igt@gem_exec_basic@basic-smem-vcs1
+igt@gem_exec_basic@basic-smem-vcs2
+igt@gem_exec_basic@basic-smem-vecs0
+igt@gem_exec_basic@gtt-lmem-all
+igt@gem_exec_basic@gtt-lmem-bcs0
+igt@gem_exec_basic@gtt-lmem-rcs0
+igt@gem_exec_basic@gtt-lmem-vcs0
+igt@gem_exec_basic@gtt-lmem-vcs1
+igt@gem_exec_basic@gtt-lmem-vcs2
+igt@gem_exec_basic@gtt-lmem-vecs0
+igt@gem_exec_basic@gtt-smem-all
+igt@gem_exec_basic@gtt-smem-bcs0
+igt@gem_exec_basic@gtt-smem-rcs0
+igt@gem_exec_basic@gtt-smem-vcs0
+igt@gem_exec_basic@gtt-smem-vcs1
+igt@gem_exec_basic@gtt-smem-vcs2
+igt@gem_exec_basic@gtt-smem-vecs0
+igt@gem_exec_basic@readonly-lmem-all
+igt@gem_exec_basic@readonly-lmem-bcs0
+igt@gem_exec_basic@readonly-lmem-rcs0
+igt@gem_exec_basic@readonly-lmem-vcs0
+igt@gem_exec_basic@readonly-lmem-vcs1
+igt@gem_exec_basic@readonly-lmem-vcs2
+igt@gem_exec_basic@readonly-lmem-vecs0
+igt@gem_exec_basic@readonly-smem-all
+igt@gem_exec_basic@readonly-smem-bcs0
+igt@gem_exec_basic@readonly-smem-rcs0
+igt@gem_exec_basic@readonly-smem-vcs0
+igt@gem_exec_basic@readonly-smem-vcs1
+igt@gem_exec_basic@readonly-smem-vcs2
+igt@gem_exec_basic@readonly-smem-vecs0
+igt@gem_mmap_offset@bad-object-smem

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3346/
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Re: [igt-dev] [RFC PATCH 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Joonas Lahtinen]

Quoting Chris Wilson (2019-08-14 13:31:10)
> Quoting Lukasz Kalamarz (2019-08-14 11:21:38)
> > +/**
> > + *  gem_get_page_size:
> > + *  @fd: open i915 drm file descriptor
> > + *  @mem_region_type: used memory_region type
> > + *
> > + *  With introduction of LMEM we observe different page sizes for those two
> > + *  memory regions. Without this helper function we may be prone to forget
> > + *  about setting proper page size.
> > + */
> > +uint32_t gem_get_batch_size(int fd, uint8_t mem_region_type)
> > +{
> > +       return (mem_region_type == LOCAL_I915_DEVICE_MEMORY) ? 65536 : 4096;
> 
> You have to be kidding me. This, this constitutes a forward thinking uAPI?

We should be just fine requesting the minimum BO size we need, letting the KMD
round the sizes up and reading back the created BO size.

(Now that the regression has been fixed, too :) )

So the code logic needs to be updated to follow that.

Regards, Joonas
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Re: [igt-dev] [RFC PATCH 1/4] lib/i915/gem_mman: add mmap_offset support

[Joonas Lahtinen]

Quoting Lukasz Kalamarz (2019-08-14 13:21:37)
> With introduction of LMEM concept new IOCTL call were implemented
> - gem_mmap_offset. This patch add support in IGT for it.
> 
> Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
> Signed-off-by: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Matthew Auld <matthew.auld@intel.com>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>

<SNIP>

> @@ -106,35 +127,80 @@ bool gem_mmap__has_wc(int fd)
>         static int has_wc = -1;
>  
>         if (has_wc == -1) {
> -               struct drm_i915_getparam gp;
> -               int mmap_version = -1;
> -               int gtt_version = -1;
>  
>                 has_wc = 0;
>  
> -               memset(&gp, 0, sizeof(gp));
> -               gp.param = I915_PARAM_MMAP_GTT_VERSION;
> -               gp.value = &gtt_version;
> -               ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> -
> -               memset(&gp, 0, sizeof(gp));
> -               gp.param = I915_PARAM_MMAP_VERSION;
> -               gp.value = &mmap_version;
> -               ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp);
> -
> -               /* Do we have the new mmap_ioctl with DOMAIN_WC? */
> -               if (mmap_version >= 1 && gtt_version >= 2) {
> -                       struct drm_i915_gem_mmap arg;
> +               /* Do we have the new mmap_offset ioctl? */
> +               if (gem_has_mmap_offset(fd)) {
> +                       struct local_i915_gem_mmap_offset arg;
>  
>                         /* Does this device support wc-mmaps ? */
>                         memset(&arg, 0, sizeof(arg));
>                         arg.handle = gem_create(fd, 4096);
>                         arg.offset = 0;
> -                       arg.size = 4096;
> -                       arg.flags = I915_MMAP_WC;
> -                       has_wc = igt_ioctl(fd, DRM_IOCTL_I915_GEM_MMAP, &arg) == 0;
> +                       arg.flags = LOCAL_I915_MMAP_OFFSET_WC;
> +                       has_wc = igt_ioctl(fd, LOCAL_IOCTL_I915_GEM_MMAP_OFFSET,
> +                                          &arg) == 0;
> +                       gem_close(fd, arg.handle);

This is duplicated at gem_mmap_offset__has_wc()

This logic shouldn't be needed either, if we have mmap_offset, we'll
have WC support. What this logic checks is if default placed object will
support WC mmap, which is very different from what this function
originally did.

<SNIP>

> +bool gem_mmap_offset__has_wc(int fd)
> +{

Ditto, shouldn't be needed ever.

<SNIP>

> @@ -194,7 +297,10 @@ static void
>   */
>  void *__gem_mmap__wc(int fd, uint32_t handle, uint64_t offset, uint64_t size, unsigned prot)
>  {
> -       return __gem_mmap(fd, handle, offset, size, prot, I915_MMAP_WC);
> +       if (gem_has_mmap_offset(fd))
> +               return __gem_mmap_offset(fd, handle, offset, size, prot, LOCAL_I915_MMAP_OFFSET_WC);

Again, there is code duplication below (__gem_mmap_offset__wc).

> +       else
> +               return __gem_mmap(fd, handle, offset, size, prot, I915_MMAP_WC);

The naming also gets confusing when we have nesting multiplexers.

I would assume us to want to flatten the code:

	if (has_mmap_offset())
		return __gem_mmap_offset__wc()
	else
		return __gem_mmap_gtt__wc()

That probably requires some renames.

Regards, Joonas
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Re: [igt-dev] [RFC PATCH 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Joonas Lahtinen]

+ Abdiel/intel-gfx

Quoting Joonas Lahtinen (2019-08-14 15:46:01)
> Quoting Chris Wilson (2019-08-14 13:31:10)
> > Quoting Lukasz Kalamarz (2019-08-14 11:21:38)
> > > +/**
> > > + *  gem_get_page_size:
> > > + *  @fd: open i915 drm file descriptor
> > > + *  @mem_region_type: used memory_region type
> > > + *
> > > + *  With introduction of LMEM we observe different page sizes for those two
> > > + *  memory regions. Without this helper function we may be prone to forget
> > > + *  about setting proper page size.
> > > + */
> > > +uint32_t gem_get_batch_size(int fd, uint8_t mem_region_type)
> > > +{
> > > +       return (mem_region_type == LOCAL_I915_DEVICE_MEMORY) ? 65536 : 4096;
> > 
> > You have to be kidding me. This, this constitutes a forward thinking uAPI?
> 
> We should be just fine requesting the minimum BO size we need, letting the KMD
> round the sizes up and reading back the created BO size.
> 
> (Now that the regression has been fixed, too :) )
> 
> So the code logic needs to be updated to follow that.

On a second thought we may be better off rounding the backing storage
size up transparently.

I guess the prime question is why would the userspace/IGT care for
actual backing storage size?

Abdiel/Matt, how painful would it be to round the backing storage size
up, irrespective of the BO size?

Regards, Joonas
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Re: [igt-dev] [RFC PATCH 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Joonas Lahtinen]

+ Abdiel/intel-gfx

Quoting Joonas Lahtinen (2019-08-14 15:46:01)
> Quoting Chris Wilson (2019-08-14 13:31:10)
> > Quoting Lukasz Kalamarz (2019-08-14 11:21:38)
> > > +/**
> > > + *  gem_get_page_size:
> > > + *  @fd: open i915 drm file descriptor
> > > + *  @mem_region_type: used memory_region type
> > > + *
> > > + *  With introduction of LMEM we observe different page sizes for those two
> > > + *  memory regions. Without this helper function we may be prone to forget
> > > + *  about setting proper page size.
> > > + */
> > > +uint32_t gem_get_batch_size(int fd, uint8_t mem_region_type)
> > > +{
> > > +       return (mem_region_type == LOCAL_I915_DEVICE_MEMORY) ? 65536 : 4096;
> > 
> > You have to be kidding me. This, this constitutes a forward thinking uAPI?
> 
> We should be just fine requesting the minimum BO size we need, letting the KMD
> round the sizes up and reading back the created BO size.
> 
> (Now that the regression has been fixed, too :) )
> 
> So the code logic needs to be updated to follow that.

On a second thought we may be better off rounding the backing storage
size up transparently.

I guess the prime question is why would the userspace/IGT care for
actual backing storage size?

Abdiel/Matt, how painful would it be to round the backing storage size
up, irrespective of the BO size?

Regards, Joonas
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Re: [igt-dev] [RFC PATCH 1/4] lib/i915/gem_mman: add mmap_offset support

[Chris Wilson]

Quoting Joonas Lahtinen (2019-08-14 14:19:12)
> This logic shouldn't be needed either, if we have mmap_offset, we'll
> have WC support. What this logic checks is if default placed object will
> support WC mmap, which is very different from what this function
> originally did.

Fwiw, that's not always true. Once you know which ioctl you have,
you need to query the WC flags to verify the processor supports WC
access. With Xen even recent processors may be lacking a few essentials.
-Chris
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Re: [igt-dev] [RFC PATCH 2/4] lib/i915/intel_memory_region: Add lib to manage memory regions

[Kempczynski, Zbigniew]

On Wed, 2019-08-14 at 12:21 +0200, Lukasz Kalamarz wrote:

I know it is a little bit outdated review, but I've some comments
as I haven't seen update.

<cut>
> +/**
> + * gem_find_memory_region_in_query:
> + * @query_info: query result of memory regions
> + * @num_regions: number of memory regions from @query_info
> + * @id: memory region id
> + *
> + * This function iterate over @num_regions of memory regions obtained by
> + * @query_info to find if memory region with given @id is available.
> + *
> + * Returns: true if memory region was found. Otherwise false.
> + */
> +bool gem_find_memory_region_in_query(struct
> local_i915_query_memory_region_info *query_info,
> +				     uint8_t num_regions, uint32_t id)
> +{
> +	for (int i = 0; i < num_regions; i++) {
> +		if (query_info->regions[i].id == id)
> +			return true;
> +	}
> +
> +	return false;
> +}

I think this function should be called a little bit different, likely:

bool gem_is_memory_region_exist(...) or sth.

Your name suggest you'll return some region, not bool. 

Zbigniew
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Re: [igt-dev] [RFC PATCH 1/4] lib/i915/gem_mman: add mmap_offset support

[Kempczynski, Zbigniew]

On Wed, 2019-08-14 at 11:28 +0100, Chris Wilson wrote:
> Quoting Lukasz Kalamarz (2019-08-14 11:21:37)
> > +#define LOCAL_I915_PARAM_MMAP_OFFSET_VERSION 54
> > +
> > +bool gem_has_mmap_offset(int fd)
> > +{
> > +       static int has_mmap_offset = -1;
> > +
> > +       if (has_mmap_offset == -1) {
> 
> How many times do I have to say that I am sorry for introducing static
> here. It was to cut down on strace spam, but no one should be repeatedly
> checking, so please don't cargo cult it. It doesn't bode well.
> -Chris

What's wrong with this optimization technique? Is that possible for single
i915 driver we got different results? Only reason I see would be to have
two different GPU's with different generations, but it is impossible?

Zbigniew
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Re: [igt-dev] [RFC PATCH 1/4] lib/i915/gem_mman: add mmap_offset support

[Chris Wilson]

Quoting Kempczynski, Zbigniew (2019-10-22 07:42:59)
> On Wed, 2019-08-14 at 11:28 +0100, Chris Wilson wrote:
> > Quoting Lukasz Kalamarz (2019-08-14 11:21:37)
> > > +#define LOCAL_I915_PARAM_MMAP_OFFSET_VERSION 54
> > > +
> > > +bool gem_has_mmap_offset(int fd)
> > > +{
> > > +       static int has_mmap_offset = -1;
> > > +
> > > +       if (has_mmap_offset == -1) {
> > 
> > How many times do I have to say that I am sorry for introducing static
> > here. It was to cut down on strace spam, but no one should be repeatedly
> > checking, so please don't cargo cult it. It doesn't bode well.
> > -Chris
> 
> What's wrong with this optimization technique? Is that possible for single
> i915 driver we got different results? Only reason I see would be to have
> two different GPU's with different generations, but it is impossible?

The world has changed and that is now very possible.
-Chris
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