* [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers
@ 2019-09-10 8:15 ` KONRAD Frederic
0 siblings, 0 replies; 6+ messages in thread
From: KONRAD Frederic @ 2019-09-10 8:15 UTC (permalink / raw)
To: qemu-devel
Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, KONRAD Frederic, Alistair Francis
While debugging an application with GDB the following might happen:
(gdb) return
Make xxx return now? (y or n) y
Could not fetch register "fflags"; remote failure reply 'E14'
This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
number (8). It should use the csr_register_map in order to reach the
riscv_cpu_get_fflags callback.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
target/riscv/gdbstub.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 27be932..ded140e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
+ 0, 0);
if (result == 0) {
return gdb_get_regl(mem_buf, val);
}
@@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
+ val, -1);
if (result == 0) {
return sizeof(target_ulong);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-riscv] [PATCH v1] gdbstub: riscv: fix the fflags registers
@ 2019-09-10 8:15 ` KONRAD Frederic
0 siblings, 0 replies; 6+ messages in thread
From: KONRAD Frederic @ 2019-09-10 8:15 UTC (permalink / raw)
To: qemu-devel
Cc: KONRAD Frederic, Palmer Dabbelt, Alistair Francis,
Sagar Karandikar, Bastian Koppelmann, open list:RISC-V TCG CPUs
While debugging an application with GDB the following might happen:
(gdb) return
Make xxx return now? (y or n) y
Could not fetch register "fflags"; remote failure reply 'E14'
This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
number (8). It should use the csr_register_map in order to reach the
riscv_cpu_get_fflags callback.
Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
---
target/riscv/gdbstub.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index 27be932..ded140e 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
+ 0, 0);
if (result == 0) {
return gdb_get_regl(mem_buf, val);
}
@@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
* register 33, so we recalculate the map index.
* This also works for CSR_FRM and CSR_FCSR.
*/
- result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
+ result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
+ val, -1);
if (result == 0) {
return sizeof(target_ulong);
}
--
1.8.3.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers
2019-09-10 8:15 ` [Qemu-riscv] " KONRAD Frederic
@ 2019-09-13 21:20 ` Palmer Dabbelt
-1 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2019-09-13 21:20 UTC (permalink / raw)
To: frederic.konrad
Cc: open list:RISC-V TCG CPUs, sagark, Bastian Koppelmann,
qemu-devel, frederic.konrad, Alistair Francis
On Tue, 10 Sep 2019 01:15:41 PDT (-0700), frederic.konrad@adacore.com wrote:
> While debugging an application with GDB the following might happen:
>
> (gdb) return
> Make xxx return now? (y or n) y
> Could not fetch register "fflags"; remote failure reply 'E14'
>
> This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
> number (8). It should use the csr_register_map in order to reach the
> riscv_cpu_get_fflags callback.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> target/riscv/gdbstub.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be932..ded140e 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
> + 0, 0);
> if (result == 0) {
> return gdb_get_regl(mem_buf, val);
> }
> @@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
> + val, -1);
> if (result == 0) {
> return sizeof(target_ulong);
> }
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
I just tagged a fixed version of my PR, but I'll include this in the next one.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-riscv] [PATCH v1] gdbstub: riscv: fix the fflags registers
@ 2019-09-13 21:20 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2019-09-13 21:20 UTC (permalink / raw)
To: frederic.konrad
Cc: qemu-devel, frederic.konrad, Alistair Francis, sagark,
Bastian Koppelmann, open list:RISC-V TCG CPUs
On Tue, 10 Sep 2019 01:15:41 PDT (-0700), frederic.konrad@adacore.com wrote:
> While debugging an application with GDB the following might happen:
>
> (gdb) return
> Make xxx return now? (y or n) y
> Could not fetch register "fflags"; remote failure reply 'E14'
>
> This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
> number (8). It should use the csr_register_map in order to reach the
> riscv_cpu_get_fflags callback.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
> ---
> target/riscv/gdbstub.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be932..ded140e 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
> + 0, 0);
> if (result == 0) {
> return gdb_get_regl(mem_buf, val);
> }
> @@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
> + val, -1);
> if (result == 0) {
> return sizeof(target_ulong);
> }
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
I just tagged a fixed version of my PR, but I'll include this in the next one.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers
2019-09-10 8:15 ` [Qemu-riscv] " KONRAD Frederic
@ 2019-09-16 21:29 ` Alistair Francis
-1 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2019-09-16 21:29 UTC (permalink / raw)
To: KONRAD Frederic
Cc: open list:RISC-V TCG CPUs, Sagar Karandikar, Bastian Koppelmann,
Palmer Dabbelt, qemu-devel@nongnu.org Developers,
Alistair Francis
On Tue, Sep 10, 2019 at 1:16 AM KONRAD Frederic
<frederic.konrad@adacore.com> wrote:
>
> While debugging an application with GDB the following might happen:
>
> (gdb) return
> Make xxx return now? (y or n) y
> Could not fetch register "fflags"; remote failure reply 'E14'
>
> This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
> number (8). It should use the csr_register_map in order to reach the
> riscv_cpu_get_fflags callback.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/gdbstub.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be932..ded140e 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
> + 0, 0);
> if (result == 0) {
> return gdb_get_regl(mem_buf, val);
> }
> @@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
> + val, -1);
> if (result == 0) {
> return sizeof(target_ulong);
> }
> --
> 1.8.3.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-riscv] [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers
@ 2019-09-16 21:29 ` Alistair Francis
0 siblings, 0 replies; 6+ messages in thread
From: Alistair Francis @ 2019-09-16 21:29 UTC (permalink / raw)
To: KONRAD Frederic
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V TCG CPUs,
Sagar Karandikar, Bastian Koppelmann, Palmer Dabbelt,
Alistair Francis
On Tue, Sep 10, 2019 at 1:16 AM KONRAD Frederic
<frederic.konrad@adacore.com> wrote:
>
> While debugging an application with GDB the following might happen:
>
> (gdb) return
> Make xxx return now? (y or n) y
> Could not fetch register "fflags"; remote failure reply 'E14'
>
> This is because riscv_gdb_get_fpu calls riscv_csrrw_debug with a wrong csr
> number (8). It should use the csr_register_map in order to reach the
> riscv_cpu_get_fflags callback.
>
> Signed-off-by: KONRAD Frederic <frederic.konrad@adacore.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> target/riscv/gdbstub.c | 6 ++++--
> 1 file changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index 27be932..ded140e 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val,
> + 0, 0);
> if (result == 0) {
> return gdb_get_regl(mem_buf, val);
> }
> @@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n)
> * register 33, so we recalculate the map index.
> * This also works for CSR_FRM and CSR_FCSR.
> */
> - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1);
> + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL,
> + val, -1);
> if (result == 0) {
> return sizeof(target_ulong);
> }
> --
> 1.8.3.1
>
>
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-09-16 21:35 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-10 8:15 [Qemu-devel] [PATCH v1] gdbstub: riscv: fix the fflags registers KONRAD Frederic
2019-09-10 8:15 ` [Qemu-riscv] " KONRAD Frederic
2019-09-13 21:20 ` [Qemu-devel] " Palmer Dabbelt
2019-09-13 21:20 ` [Qemu-riscv] " Palmer Dabbelt
2019-09-16 21:29 ` [Qemu-devel] " Alistair Francis
2019-09-16 21:29 ` [Qemu-riscv] " Alistair Francis
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.