* [v3][PATCH 0/3] adding gamma state checker for icl+ platforms
@ 2019-09-19 18:17 Swati Sharma
2019-09-19 18:17 ` [v3][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma
` (5 more replies)
0 siblings, 6 replies; 10+ messages in thread
From: Swati Sharma @ 2019-09-19 18:17 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal
In this patch series, added state checker to validate gamma lut values
for icelake+ platforms. It's extension of the
patch series https://patchwork.freedesktop.org/patch/328246/?series=58039
which enabled the basic infrastructure and state checker for
legacy platforms.
Major changes done in patch 2, details in commit message.
Swati Sharma (3):
drm/i915/color: Fix formatting issues
drm/i915/color: Extract icl_read_luts()
FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
drivers/gpu/drm/i915/display/intel_color.c | 252 +++++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_reg.h | 7 +
2 files changed, 226 insertions(+), 33 deletions(-)
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* [v3][PATCH 1/3] drm/i915/color: Fix formatting issues
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
@ 2019-09-19 18:17 ` Swati Sharma
2019-09-20 11:54 ` Jani Nikula
2019-09-19 18:17 ` [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma
` (4 subsequent siblings)
5 siblings, 1 reply; 10+ messages in thread
From: Swati Sharma @ 2019-09-19 18:17 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal
Fixed few formatting issues in multi-segmented load_lut().
v3: -style nitting [Jani]
-balanced parentheses moved from patch 2 to 1 [Jani]
-subject prefix change [Jani]
-added commit message [Jani]
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 34 ++++++++++++++----------------
1 file changed, 16 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 318308d..765482d 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
u32 i;
/*
- * Every entry in the multi-segment LUT is corresponding to a superfine
- * segment step which is 1/(8 * 128 * 256).
+ * Program Super Fine segment (let's call it seg1)...
*
- * Superfine segment has 9 entries, corresponding to values
- * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
+ * Super Fine segment's step is 1/(8 * 128 * 256) and it has
+ * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
+ * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
*/
I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
@@ -837,17 +837,17 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
u32 i;
/*
- *
* Program Fine segment (let's call it seg2)...
*
- * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256)
- * ... 256/(128*256). So in order to program fine segment of LUT we
- * need to pick every 8'th entry in LUT, and program 256 indexes.
+ * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
+ * ... 256/(128 * 256). So in order to program fine segment of LUT we
+ * need to pick every 8th entry in the LUT, and program 256 indexes.
*
* PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
- * with seg2[0] being unused by the hardware.
+ * seg2[0] being unused by the hardware.
*/
I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
for (i = 1; i < 257; i++) {
entry = &lut[i * 8];
I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
@@ -857,8 +857,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
/*
* Program Coarse segment (let's call it seg3)...
*
- * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
- * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
+ * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
+ * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
* above, we need to pick every (8 * 128)th entry in LUT, and
* program 256 of those.
*
@@ -890,12 +890,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
case GAMMA_MODE_MODE_8BIT:
i9xx_load_luts(crtc_state);
break;
-
case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
icl_program_gamma_superfine_segment(crtc_state);
icl_program_gamma_multi_segment(crtc_state);
break;
-
default:
bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
ivb_load_lut_ext_max(crtc);
@@ -1788,16 +1786,16 @@ void intel_color_init(struct intel_crtc *crtc)
else
dev_priv->display.color_commit = ilk_color_commit;
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
- else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
+ } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
- } else if (INTEL_GEN(dev_priv) >= 8)
+ } else if (INTEL_GEN(dev_priv) >= 8) {
dev_priv->display.load_luts = bdw_load_luts;
- else if (INTEL_GEN(dev_priv) >= 7)
+ } else if (INTEL_GEN(dev_priv) >= 7) {
dev_priv->display.load_luts = ivb_load_luts;
- else {
+ } else {
dev_priv->display.load_luts = ilk_load_luts;
dev_priv->display.read_luts = ilk_read_luts;
}
--
1.9.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts()
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
2019-09-19 18:17 ` [v3][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma
@ 2019-09-19 18:17 ` Swati Sharma
2019-09-20 10:24 ` Jani Nikula
2019-09-20 12:06 ` Jani Nikula
2019-09-19 18:17 ` [v3][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
` (3 subsequent siblings)
5 siblings, 2 replies; 10+ messages in thread
From: Swati Sharma @ 2019-09-19 18:17 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal
For icl+, have hw read out to create hw blob of gamma
lut values. icl+ platforms supports multi segmented gamma
mode by default, add hw lut creation for this mode.
This will be used to validate gamma programming using dsb
(display state buffer) which is a tgl specific feature.
Following are the main changes done in this patch:
1. gamma_enable checks made specific to platform func()
since icl doeesn't support that and enable gamma through mode
2. lut[0] and lut[8] enteries should be same superfine and coarse;
superfine and fine segments respectively, checked twice-no harm
3. Removed temporary lut
4. Coarse segment interpolated gamma values loop start from 2
instead of 0, since actual h/w values started getting overrided.
v2: -readout code for multisegmented gamma has to come
up with some intermediate entries that aren't preserved
in hardware (Jani N)
-linear interpolation (Ville)
-moved common code to check gamma_enable to specific funcs,
since icl doesn't support that
v3: -use u16 instead of __u16 [Jani N]
-used single lut [Jani N]
-improved and more readable for loops [Jani N]
-read values directly to actual locations and then fill gaps [Jani N]
-moved cleaning to patch 1 [Jani N]
-renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
make it similar to icl_load_luts()
-renamed icl_compute_interpolated_gamma_blob() to
icl_compute_interpolated_gamma_lut_values() more sensible, I guess
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 216 +++++++++++++++++++++++++++--
drivers/gpu/drm/i915/i915_reg.h | 7 +
2 files changed, 208 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 765482d..ad548ce 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
switch (crtc_state->gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
@@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
return 0;
@@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
return 10;
else
@@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
{
+ if (!crtc_state->gamma_enable)
+ return 0;
+
switch (crtc_state->gamma_mode) {
case GAMMA_MODE_MODE_8BIT:
return 8;
@@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
}
}
+static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
+ return 0;
+
+ switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
+ case GAMMA_MODE_MODE_8BIT:
+ return 8;
+ case GAMMA_MODE_MODE_10BIT:
+ return 10;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ return 16;
+ default:
+ MISSING_CASE(crtc_state->gamma_mode);
+ return 0;
+ }
+
+}
+
int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
- if (!crtc_state->gamma_enable)
- return 0;
-
if (HAS_GMCH(dev_priv)) {
if (IS_CHERRYVIEW(dev_priv))
return chv_gamma_precision(crtc_state);
else
return i9xx_gamma_precision(crtc_state);
} else {
- if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
+ if (INTEL_GEN(dev_priv) >= 11)
+ return icl_gamma_precision(crtc_state);
+ else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
return glk_gamma_precision(crtc_state);
else if (IS_IRONLAKE(dev_priv))
return ilk_gamma_precision(crtc_state);
@@ -1464,6 +1494,30 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
return true;
}
+static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
+ struct drm_color_lut *lut2,
+ int lut_size, u32 err)
+{
+ int i;
+
+ for (i = 0; i < 9; i++) {
+ if (!err_check(&lut1[i], &lut2[i], err))
+ return false;
+ }
+
+ for (i = 1; i < 257; i++) {
+ if (!err_check(&lut1[i * 8], &lut2[i * 8], err))
+ return false;
+ }
+
+ for (i = 0; i < 256; i++) {
+ if (!err_check(&lut1[i * 8 * 128], &lut2[i * 8 * 128], err))
+ return false;
+ }
+
+ return true;
+}
+
bool intel_color_lut_equal(struct drm_property_blob *blob1,
struct drm_property_blob *blob2,
u32 gamma_mode, u32 bit_precision)
@@ -1482,16 +1536,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
lut_size2 = drm_color_lut_size(blob2);
/* check sw and hw lut size */
- switch (gamma_mode) {
- case GAMMA_MODE_MODE_8BIT:
- case GAMMA_MODE_MODE_10BIT:
- if (lut_size1 != lut_size2)
- return false;
- break;
- default:
- MISSING_CASE(gamma_mode);
- return false;
- }
+ if (lut_size1 != lut_size2)
+ return false;
lut1 = blob1->data;
lut2 = blob2->data;
@@ -1499,13 +1545,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
err = 0xffff >> bit_precision;
/* check sw and hw lut entry to be equal */
- switch (gamma_mode) {
+ switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
case GAMMA_MODE_MODE_8BIT:
case GAMMA_MODE_MODE_10BIT:
if (!intel_color_lut_entry_equal(lut1, lut2,
lut_size2, err))
return false;
break;
+ case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
+ if (!intel_color_lut_entry_multi_equal(lut1, lut2,
+ lut_size2, err))
+ return false;
+ break;
default:
MISSING_CASE(gamma_mode);
return false;
@@ -1745,6 +1796,140 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
}
+static u16 cal_step_size(u16 end_val, u16 start_val, int steps)
+{
+ return ((end_val - start_val) / steps);
+}
+
+static struct drm_color_lut *
+icl_compute_interpolated_gamma_lut_values(struct drm_color_lut *lut, u32 lut_size)
+{
+ u16 red_step_size, green_step_size, blue_step_size;
+ int start, end, steps;
+ int i, j;
+
+ for (i = 1; i < 257 - 1; i++) {
+ start = i * 8;
+ end = (i + 1) * 8;
+ steps = end - start;
+
+ red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
+ green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
+ blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
+
+ for (j = start + 1; j < end; j++) {
+ lut[j].red = lut[j - 1].red + red_step_size;
+ lut[j].green = lut[j - 1].green + green_step_size;
+ lut[j].blue = lut[j - 1].blue + blue_step_size;
+
+ i++;
+ }
+ }
+
+ for (i = 2; i < 256 - 1; i++) {
+ start = i * 8 * 128;
+ end = (i + 1) * 8 * 128;
+ steps = end - start;
+
+ red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
+ green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
+ blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
+
+ for (j = start + 1; j < end; j++) {
+ lut[j].red = lut[j - 1].red + red_step_size;
+ lut[j].green = lut[j - 1].green + green_step_size;
+ lut[j].blue = lut[j - 1].blue + blue_step_size;
+
+ i++;
+ }
+ }
+
+ return lut;
+}
+
+static struct drm_property_blob *
+icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+ enum pipe pipe = crtc->pipe;
+ struct drm_property_blob *blob;
+ struct drm_color_lut *blob_data;
+ u32 i, val1, val2;
+
+ blob = drm_property_create_blob(&dev_priv->drm,
+ sizeof(struct drm_color_lut) * lut_size,
+ NULL);
+ if (IS_ERR(blob))
+ return NULL;
+
+ blob_data = blob->data;
+
+ I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 0; i < 9; i++) {
+ val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
+
+ blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+ blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+ blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+ }
+
+ I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
+
+ for (i = 1; i < 257; i++) {
+ val1 = I915_READ(PREC_PAL_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i * 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+ blob_data[i * 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+ blob_data[i * 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+ }
+
+ for (i = 0; i < 256; i++) {
+ val1 = I915_READ(PREC_PAL_DATA(pipe));
+ val2 = I915_READ(PREC_PAL_DATA(pipe));
+
+ blob_data[i * 8 * 128].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
+ blob_data[i * 8 * 128].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
+ blob_data[i * 8 * 128].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
+ }
+
+ blob_data[lut_size - 1].red = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
+ I915_READ(PREC_PAL_GC_MAX(pipe, 0)));
+ blob_data[lut_size - 1].green = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
+ I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
+ blob_data[lut_size - 1].blue = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
+ I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
+
+ blob_data = icl_compute_interpolated_gamma_lut_values(blob_data, lut_size);
+
+ return blob;
+}
+
+static void icl_read_luts(struct intel_crtc_state *crtc_state)
+{
+ if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_8BIT)
+ crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
+ else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
+ GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
+ crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
+ else
+ crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+}
+
void intel_color_init(struct intel_crtc *crtc)
{
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1788,6 +1973,7 @@ void intel_color_init(struct intel_crtc *crtc)
if (INTEL_GEN(dev_priv) >= 11) {
dev_priv->display.load_luts = icl_load_luts;
+ dev_priv->display.read_luts = icl_read_luts;
} else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
dev_priv->display.load_luts = glk_load_luts;
dev_priv->display.read_luts = glk_read_luts;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index bf37ece..844dd62 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10378,6 +10378,7 @@ enum skl_power_gate {
#define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
#define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
+#define PREC_PAL_GC_MAX_RGB_MASK REG_GENMASK(15, 0)
#define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
#define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
@@ -10401,6 +10402,12 @@ enum skl_power_gate {
#define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
#define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
+#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
+#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
+#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
+#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
+#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
+#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
#define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
_PAL_PREC_MULTI_SEG_INDEX_A, \
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [v3][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
2019-09-19 18:17 ` [v3][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma
2019-09-19 18:17 ` [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma
@ 2019-09-19 18:17 ` Swati Sharma
2019-09-19 20:55 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev3) Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 10+ messages in thread
From: Swati Sharma @ 2019-09-19 18:17 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula, daniel.vetter, ankit.k.nautiyal
Only to print hw and sw lut values/channel.
Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
---
drivers/gpu/drm/i915/display/intel_color.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ad548ce..a7a2fa0 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1475,6 +1475,8 @@ int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_stat
static bool err_check(struct drm_color_lut *lut1,
struct drm_color_lut *lut2, u32 err)
{
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);
+
return ((abs((long)lut2->red - lut1->red)) <= err) &&
((abs((long)lut2->blue - lut1->blue)) <= err) &&
((abs((long)lut2->green - lut1->green)) <= err);
--
1.9.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev3)
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
` (2 preceding siblings ...)
2019-09-19 18:17 ` [v3][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
@ 2019-09-19 20:55 ` Patchwork
2019-09-19 21:18 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-20 9:41 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-09-19 20:55 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev3)
URL : https://patchwork.freedesktop.org/series/66811/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f22d03d7e022 drm/i915/color: Fix formatting issues
9f36da572c33 drm/i915/color: Extract icl_read_luts()
-:20: WARNING:TYPO_SPELLING: 'overrided' may be misspelled - perhaps 'overridden'?
#20:
instead of 0, since actual h/w values started getting overrided.
-:105: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#105: FILE: drivers/gpu/drm/i915/display/intel_color.c:1451:
+
+}
-:294: WARNING:LONG_LINE: line over 100 characters
#294: FILE: drivers/gpu/drm/i915/display/intel_color.c:1891:
+ blob_data[i * 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
-:304: WARNING:LONG_LINE: line over 100 characters
#304: FILE: drivers/gpu/drm/i915/display/intel_color.c:1901:
+ blob_data[i * 8 * 128].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
-:306: WARNING:LONG_LINE: line over 100 characters
#306: FILE: drivers/gpu/drm/i915/display/intel_color.c:1903:
+ blob_data[i * 8 * 128].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
-:307: WARNING:LONG_LINE: line over 100 characters
#307: FILE: drivers/gpu/drm/i915/display/intel_color.c:1904:
+ REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
-:308: WARNING:LONG_LINE: line over 100 characters
#308: FILE: drivers/gpu/drm/i915/display/intel_color.c:1905:
+ blob_data[i * 8 * 128].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
total: 0 errors, 6 warnings, 1 checks, 312 lines checked
9f1eb7e98ab1 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
-:18: WARNING:LONG_LINE: line over 100 characters
#18: FILE: drivers/gpu/drm/i915/display/intel_color.c:1478:
+ DRM_DEBUG_KMS("hw_lut->red=0x%x sw_lut->red=0x%x hw_lut->blue=0x%x sw_lut->blue=0x%x hw_lut->green=0x%x sw_lut->green=0x%x", lut2->red, lut1->red, lut2->blue, lut1->blue, lut2->green, lut1->green);
total: 0 errors, 1 warnings, 0 checks, 8 lines checked
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✓ Fi.CI.BAT: success for adding gamma state checker for icl+ platforms (rev3)
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
` (3 preceding siblings ...)
2019-09-19 20:55 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev3) Patchwork
@ 2019-09-19 21:18 ` Patchwork
2019-09-20 9:41 ` ✗ Fi.CI.IGT: failure " Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-09-19 21:18 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev3)
URL : https://patchwork.freedesktop.org/series/66811/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_6925 -> Patchwork_14463
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/
Known issues
------------
Here are the changes found in Patchwork_14463 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-blb-e6850: [PASS][1] -> [INCOMPLETE][2] ([fdo#107718])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
* igt@gem_mmap@basic-small-bo:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-icl-u3/igt@gem_mmap@basic-small-bo.html
* igt@i915_module_load@reload:
- fi-icl-u3: [PASS][5] -> [DMESG-WARN][6] ([fdo#107724] / [fdo#111214])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@i915_module_load@reload.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-icl-u3/igt@i915_module_load@reload.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [PASS][7] -> [DMESG-FAIL][8] ([fdo#111678])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
* igt@kms_frontbuffer_tracking@basic:
- fi-hsw-peppy: [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
#### Possible fixes ####
* igt@gem_cpu_reloc@basic:
- fi-bxt-dsi: [INCOMPLETE][11] ([fdo#103927]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-bxt-dsi/igt@gem_cpu_reloc@basic.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-bxt-dsi/igt@gem_cpu_reloc@basic.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [FAIL][13] ([fdo#109483]) -> [PASS][14] +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_frontbuffer_tracking@basic:
- fi-icl-u2: [FAIL][15] ([fdo#103167]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@prime_vgem@basic-busy-default:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +2 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/fi-icl-u3/igt@prime_vgem@basic-busy-default.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/fi-icl-u3/igt@prime_vgem@basic-busy-default.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#106350]: https://bugs.freedesktop.org/show_bug.cgi?id=106350
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
[fdo#111214]: https://bugs.freedesktop.org/show_bug.cgi?id=111214
[fdo#111562]: https://bugs.freedesktop.org/show_bug.cgi?id=111562
[fdo#111597]: https://bugs.freedesktop.org/show_bug.cgi?id=111597
[fdo#111678]: https://bugs.freedesktop.org/show_bug.cgi?id=111678
[fdo#111739]: https://bugs.freedesktop.org/show_bug.cgi?id=111739
Participating hosts (53 -> 47)
------------------------------
Additional (1): fi-pnv-d510
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6925 -> Patchwork_14463
CI-20190529: 20190529
CI_DRM_6925: ccd2c9cb3fd35f9654cdf6743bdecfb489fba70a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5193: 924e5c59dbb82938e743efd6b0812eeb5760b70d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14463: 9f1eb7e98ab1feba06e058f72f72d1953fc9900f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9f1eb7e98ab1 FOR_TESTING_ONLY: Print rgb values of hw and sw blobs
9f36da572c33 drm/i915/color: Extract icl_read_luts()
f22d03d7e022 drm/i915/color: Fix formatting issues
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* ✗ Fi.CI.IGT: failure for adding gamma state checker for icl+ platforms (rev3)
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
` (4 preceding siblings ...)
2019-09-19 21:18 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-09-20 9:41 ` Patchwork
5 siblings, 0 replies; 10+ messages in thread
From: Patchwork @ 2019-09-20 9:41 UTC (permalink / raw)
To: Swati Sharma; +Cc: intel-gfx
== Series Details ==
Series: adding gamma state checker for icl+ platforms (rev3)
URL : https://patchwork.freedesktop.org/series/66811/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_6925_full -> Patchwork_14463_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14463_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14463_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14463_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_color@pipe-a-degamma:
- shard-iclb: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb6/igt@kms_color@pipe-a-degamma.html
* igt@kms_color@pipe-b-gamma:
- shard-iclb: [PASS][2] -> [DMESG-WARN][3] +10 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb6/igt@kms_color@pipe-b-gamma.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb7/igt@kms_color@pipe-b-gamma.html
#### Warnings ####
* igt@kms_color@pipe-b-ctm-0-25:
- shard-iclb: [FAIL][4] ([fdo#110920]) -> [DMESG-FAIL][5] +5 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@kms_color@pipe-b-ctm-0-25.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb8/igt@kms_color@pipe-b-ctm-0-25.html
* igt@kms_color@pipe-c-degamma:
- shard-iclb: [FAIL][6] ([fdo#104782]) -> [DMESG-FAIL][7] +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_color@pipe-c-degamma.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb8/igt@kms_color@pipe-c-degamma.html
Known issues
------------
Here are the changes found in Patchwork_14463_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@rcs0-s3:
- shard-skl: [PASS][8] -> [INCOMPLETE][9] ([fdo#104108])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl2/igt@gem_ctx_isolation@rcs0-s3.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl1/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][10] -> [SKIP][11] ([fdo#110841])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_ctx_shared@q-smoketest-bsd2:
- shard-iclb: [PASS][12] -> [SKIP][13] ([fdo#109276]) +6 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@gem_ctx_shared@q-smoketest-bsd2.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb5/igt@gem_ctx_shared@q-smoketest-bsd2.html
* igt@gem_exec_schedule@preempt-queue-contexts-bsd:
- shard-iclb: [PASS][14] -> [SKIP][15] ([fdo#111325])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@gem_exec_schedule@preempt-queue-contexts-bsd.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@gem_exec_schedule@preempt-queue-contexts-bsd.html
* igt@i915_selftest@live_execlists:
- shard-skl: [PASS][16] -> [DMESG-FAIL][17] ([fdo#111108])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl10/igt@i915_selftest@live_execlists.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl8/igt@i915_selftest@live_execlists.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: [PASS][18] -> [FAIL][19] ([fdo#105363])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-glk4/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
- shard-iclb: [PASS][20] -> [FAIL][21] ([fdo#103167]) +2 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][22] -> [DMESG-WARN][23] ([fdo#108566]) +2 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][24] -> [FAIL][25] ([fdo#108145])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_psr2_su@page_flip:
- shard-iclb: [PASS][26] -> [SKIP][27] ([fdo#109642] / [fdo#111068])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_psr2_su@page_flip.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb3/igt@kms_psr2_su@page_flip.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][28] -> [SKIP][29] ([fdo#109441])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@kms_psr@psr2_basic.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb5/igt@kms_psr@psr2_basic.html
#### Possible fixes ####
* igt@gem_exec_schedule@preempt-contexts-bsd2:
- shard-iclb: [SKIP][30] ([fdo#109276]) -> [PASS][31] +13 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@gem_exec_schedule@preempt-contexts-bsd2.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html
* igt@gem_exec_schedule@preempt-hang-bsd:
- shard-iclb: [SKIP][32] ([fdo#111325]) -> [PASS][33] +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb2/igt@gem_exec_schedule@preempt-hang-bsd.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb5/igt@gem_exec_schedule@preempt-hang-bsd.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][34] ([fdo#108566]) -> [PASS][35] +5 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-apl8/igt@i915_suspend@fence-restore-tiled2untiled.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-apl7/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_busy@basic-modeset-a:
- shard-iclb: [INCOMPLETE][36] ([fdo#107713]) -> [PASS][37] +1 similar issue
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb7/igt@kms_busy@basic-modeset-a.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb8/igt@kms_busy@basic-modeset-a.html
* igt@kms_busy@extended-modeset-hang-oldfb-render-a:
- shard-kbl: [DMESG-WARN][38] -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-kbl2/igt@kms_busy@extended-modeset-hang-oldfb-render-a.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-kbl2/igt@kms_busy@extended-modeset-hang-oldfb-render-a.html
* igt@kms_flip@flip-vs-suspend:
- shard-hsw: [INCOMPLETE][40] ([fdo#103540]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-hsw5/igt@kms_flip@flip-vs-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-hsw2/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: [FAIL][42] ([fdo#103167]) -> [PASS][43] +3 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
* igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
- shard-skl: [FAIL][44] ([fdo#108145]) -> [PASS][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][46] ([fdo#108341]) -> [PASS][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb1/igt@kms_psr@no_drrs.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb6/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_plane_move:
- shard-iclb: [SKIP][48] ([fdo#109441]) -> [PASS][49] +2 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html
* igt@kms_vblank@pipe-c-ts-continuation-modeset:
- shard-kbl: [DMESG-WARN][50] ([fdo#103313]) -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-modeset.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-kbl2/igt@kms_vblank@pipe-c-ts-continuation-modeset.html
* igt@perf@blocking:
- shard-skl: [FAIL][52] ([fdo#110728]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-skl9/igt@perf@blocking.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-skl8/igt@perf@blocking.html
#### Warnings ####
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][54] ([fdo#109349]) -> [DMESG-WARN][55] ([fdo#107724])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6925/shard-iclb5/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110728]: https://bugs.freedesktop.org/show_bug.cgi?id=110728
[fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
[fdo#110920]: https://bugs.freedesktop.org/show_bug.cgi?id=110920
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111108]: https://bugs.freedesktop.org/show_bug.cgi?id=111108
[fdo#111325]: https://bugs.freedesktop.org/show_bug.cgi?id=111325
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_6925 -> Patchwork_14463
CI-20190529: 20190529
CI_DRM_6925: ccd2c9cb3fd35f9654cdf6743bdecfb489fba70a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5193: 924e5c59dbb82938e743efd6b0812eeb5760b70d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14463: 9f1eb7e98ab1feba06e058f72f72d1953fc9900f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14463/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts()
2019-09-19 18:17 ` [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma
@ 2019-09-20 10:24 ` Jani Nikula
2019-09-20 12:06 ` Jani Nikula
1 sibling, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2019-09-20 10:24 UTC (permalink / raw)
To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal
On Thu, 19 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl specific feature.
>
> Following are the main changes done in this patch:
> 1. gamma_enable checks made specific to platform func()
> since icl doeesn't support that and enable gamma through mode
> 2. lut[0] and lut[8] enteries should be same superfine and coarse;
> superfine and fine segments respectively, checked twice-no harm
> 3. Removed temporary lut
> 4. Coarse segment interpolated gamma values loop start from 2
> instead of 0, since actual h/w values started getting overrided.
>
> v2: -readout code for multisegmented gamma has to come
> up with some intermediate entries that aren't preserved
> in hardware (Jani N)
> -linear interpolation (Ville)
> -moved common code to check gamma_enable to specific funcs,
> since icl doesn't support that
> v3: -use u16 instead of __u16 [Jani N]
> -used single lut [Jani N]
> -improved and more readable for loops [Jani N]
> -read values directly to actual locations and then fill gaps [Jani N]
> -moved cleaning to patch 1 [Jani N]
> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
> make it similar to icl_load_luts()
> -renamed icl_compute_interpolated_gamma_blob() to
> icl_compute_interpolated_gamma_lut_values() more sensible, I guess
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 216 +++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +
> 2 files changed, 208 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 765482d..ad548ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> }
> }
>
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +
> +}
> +
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> else
> return i9xx_gamma_precision(crtc_state);
> } else {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_gamma_precision(crtc_state);
> + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> return glk_gamma_precision(crtc_state);
> else if (IS_IRONLAKE(dev_priv))
> return ilk_gamma_precision(crtc_state);
> @@ -1464,6 +1494,30 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
> return true;
> }
>
> +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
> + struct drm_color_lut *lut2,
> + int lut_size, u32 err)
> +{
> + int i;
> +
> + for (i = 0; i < 9; i++) {
> + if (!err_check(&lut1[i], &lut2[i], err))
> + return false;
> + }
> +
> + for (i = 1; i < 257; i++) {
> + if (!err_check(&lut1[i * 8], &lut2[i * 8], err))
> + return false;
> + }
> +
> + for (i = 0; i < 256; i++) {
> + if (!err_check(&lut1[i * 8 * 128], &lut2[i * 8 * 128], err))
> + return false;
> + }
So apparently we're facing some issues with the readout of the relevant
registers. I suggest we wrap the above two loops in
#if 0
#endif
with a comment explaining why.
I don't much like this, but having *some* validation of this is better
than *no* validation.
BR,
Jani.
> +
> + return true;
> +}
> +
> bool intel_color_lut_equal(struct drm_property_blob *blob1,
> struct drm_property_blob *blob2,
> u32 gamma_mode, u32 bit_precision)
> @@ -1482,16 +1536,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> lut_size2 = drm_color_lut_size(blob2);
>
> /* check sw and hw lut size */
> - switch (gamma_mode) {
> - case GAMMA_MODE_MODE_8BIT:
> - case GAMMA_MODE_MODE_10BIT:
> - if (lut_size1 != lut_size2)
> - return false;
> - break;
> - default:
> - MISSING_CASE(gamma_mode);
> - return false;
> - }
> + if (lut_size1 != lut_size2)
> + return false;
>
> lut1 = blob1->data;
> lut2 = blob2->data;
> @@ -1499,13 +1545,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> err = 0xffff >> bit_precision;
>
> /* check sw and hw lut entry to be equal */
> - switch (gamma_mode) {
> + switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
> case GAMMA_MODE_MODE_8BIT:
> case GAMMA_MODE_MODE_10BIT:
> if (!intel_color_lut_entry_equal(lut1, lut2,
> lut_size2, err))
> return false;
> break;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + if (!intel_color_lut_entry_multi_equal(lut1, lut2,
> + lut_size2, err))
> + return false;
> + break;
> default:
> MISSING_CASE(gamma_mode);
> return false;
> @@ -1745,6 +1796,140 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
> crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> }
>
> +static u16 cal_step_size(u16 end_val, u16 start_val, int steps)
> +{
> + return ((end_val - start_val) / steps);
> +}
> +
> +static struct drm_color_lut *
> +icl_compute_interpolated_gamma_lut_values(struct drm_color_lut *lut, u32 lut_size)
> +{
> + u16 red_step_size, green_step_size, blue_step_size;
> + int start, end, steps;
> + int i, j;
> +
> + for (i = 1; i < 257 - 1; i++) {
> + start = i * 8;
> + end = (i + 1) * 8;
> + steps = end - start;
> +
> + red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
> + green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
> + blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
> +
> + for (j = start + 1; j < end; j++) {
> + lut[j].red = lut[j - 1].red + red_step_size;
> + lut[j].green = lut[j - 1].green + green_step_size;
> + lut[j].blue = lut[j - 1].blue + blue_step_size;
> +
> + i++;
> + }
> + }
> +
> + for (i = 2; i < 256 - 1; i++) {
> + start = i * 8 * 128;
> + end = (i + 1) * 8 * 128;
> + steps = end - start;
> +
> + red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
> + green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
> + blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
> +
> + for (j = start + 1; j < end; j++) {
> + lut[j].red = lut[j - 1].red + red_step_size;
> + lut[j].green = lut[j - 1].green + green_step_size;
> + lut[j].blue = lut[j - 1].blue + blue_step_size;
> +
> + i++;
> + }
> + }
> +
> + return lut;
> +}
> +
> +static struct drm_property_blob *
> +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_lut *blob_data;
> + u32 i, val1, val2;
> +
> + blob = drm_property_create_blob(&dev_priv->drm,
> + sizeof(struct drm_color_lut) * lut_size,
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + blob_data = blob->data;
> +
> + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> + for (i = 0; i < 9; i++) {
> + val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> +
> + blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> + for (i = 1; i < 257; i++) {
> + val1 = I915_READ(PREC_PAL_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> + blob_data[i * 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i * 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i * 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + for (i = 0; i < 256; i++) {
> + val1 = I915_READ(PREC_PAL_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> + blob_data[i * 8 * 128].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i * 8 * 128].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i * 8 * 128].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + blob_data[lut_size - 1].red = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 0)));
> + blob_data[lut_size - 1].green = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> + blob_data[lut_size - 1].blue = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> +
> + blob_data = icl_compute_interpolated_gamma_lut_values(blob_data, lut_size);
> +
> + return blob;
> +}
> +
> +static void icl_read_luts(struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_8BIT)
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
> + crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
> + else
> + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> +}
> +
> void intel_color_init(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1788,6 +1973,7 @@ void intel_color_init(struct intel_crtc *crtc)
>
> if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> + dev_priv->display.read_luts = icl_read_luts;
> } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ece..844dd62 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10378,6 +10378,7 @@ enum skl_power_gate {
>
> #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
> +#define PREC_PAL_GC_MAX_RGB_MASK REG_GENMASK(15, 0)
> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
> @@ -10401,6 +10402,12 @@ enum skl_power_gate {
>
> #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
> #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
> +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
> +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
> +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
> +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
> +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
> +#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
>
> #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
> _PAL_PREC_MULTI_SEG_INDEX_A, \
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v3][PATCH 1/3] drm/i915/color: Fix formatting issues
2019-09-19 18:17 ` [v3][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma
@ 2019-09-20 11:54 ` Jani Nikula
0 siblings, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2019-09-20 11:54 UTC (permalink / raw)
To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal
On Thu, 19 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> Fixed few formatting issues in multi-segmented load_lut().
>
> v3: -style nitting [Jani]
> -balanced parentheses moved from patch 2 to 1 [Jani]
> -subject prefix change [Jani]
> -added commit message [Jani]
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 34 ++++++++++++++----------------
> 1 file changed, 16 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 318308d..765482d 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -807,11 +807,11 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> u32 i;
>
> /*
> - * Every entry in the multi-segment LUT is corresponding to a superfine
> - * segment step which is 1/(8 * 128 * 256).
> + * Program Super Fine segment (let's call it seg1)...
> *
> - * Superfine segment has 9 entries, corresponding to values
> - * 0, 1/(8 * 128 * 256), 2/(8 * 128 * 256) .... 8/(8 * 128 * 256).
> + * Super Fine segment's step is 1/(8 * 128 * 256) and it has
> + * 9 entries, corresponding to values 0, 1/(8 * 128 * 256),
> + * 2/(8 * 128 * 256) ... 8/(8 * 128 * 256).
> */
> I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
>
> @@ -837,17 +837,17 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> u32 i;
>
> /*
> - *
> * Program Fine segment (let's call it seg2)...
> *
> - * Fine segment's step is 1/(128 * 256) ie 1/(128 * 256), 2/(128*256)
> - * ... 256/(128*256). So in order to program fine segment of LUT we
> - * need to pick every 8'th entry in LUT, and program 256 indexes.
> + * Fine segment's step is 1/(128 * 256) i.e. 1/(128 * 256), 2/(128 * 256)
> + * ... 256/(128 * 256). So in order to program fine segment of LUT we
> + * need to pick every 8th entry in the LUT, and program 256 indexes.
> *
> * PAL_PREC_INDEX[0] and PAL_PREC_INDEX[1] map to seg2[1],
> - * with seg2[0] being unused by the hardware.
> + * seg2[0] being unused by the hardware.
> */
> I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> for (i = 1; i < 257; i++) {
> entry = &lut[i * 8];
> I915_WRITE(PREC_PAL_DATA(pipe), ilk_lut_12p4_ldw(entry));
> @@ -857,8 +857,8 @@ static u32 ilk_lut_12p4_ldw(const struct drm_color_lut *color)
> /*
> * Program Coarse segment (let's call it seg3)...
> *
> - * Coarse segment's starts from index 0 and it's step is 1/256 ie 0,
> - * 1/256, 2/256 ...256/256. As per the description of each entry in LUT
> + * Coarse segment starts from index 0 and it's step is 1/256 ie 0,
> + * 1/256, 2/256 ... 256/256. As per the description of each entry in LUT
> * above, we need to pick every (8 * 128)th entry in LUT, and
> * program 256 of those.
> *
> @@ -890,12 +890,10 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
> case GAMMA_MODE_MODE_8BIT:
> i9xx_load_luts(crtc_state);
> break;
> -
> case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> icl_program_gamma_superfine_segment(crtc_state);
> icl_program_gamma_multi_segment(crtc_state);
> break;
> -
> default:
> bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
> ivb_load_lut_ext_max(crtc);
> @@ -1788,16 +1786,16 @@ void intel_color_init(struct intel_crtc *crtc)
> else
> dev_priv->display.color_commit = ilk_color_commit;
>
> - if (INTEL_GEN(dev_priv) >= 11)
> + if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> - else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> + } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> - } else if (INTEL_GEN(dev_priv) >= 8)
> + } else if (INTEL_GEN(dev_priv) >= 8) {
> dev_priv->display.load_luts = bdw_load_luts;
> - else if (INTEL_GEN(dev_priv) >= 7)
> + } else if (INTEL_GEN(dev_priv) >= 7) {
> dev_priv->display.load_luts = ivb_load_luts;
> - else {
> + } else {
> dev_priv->display.load_luts = ilk_load_luts;
> dev_priv->display.read_luts = ilk_read_luts;
> }
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts()
2019-09-19 18:17 ` [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma
2019-09-20 10:24 ` Jani Nikula
@ 2019-09-20 12:06 ` Jani Nikula
1 sibling, 0 replies; 10+ messages in thread
From: Jani Nikula @ 2019-09-20 12:06 UTC (permalink / raw)
To: Swati Sharma, intel-gfx; +Cc: daniel.vetter, ankit.k.nautiyal
On Thu, 19 Sep 2019, Swati Sharma <swati2.sharma@intel.com> wrote:
> For icl+, have hw read out to create hw blob of gamma
> lut values. icl+ platforms supports multi segmented gamma
> mode by default, add hw lut creation for this mode.
>
> This will be used to validate gamma programming using dsb
> (display state buffer) which is a tgl specific feature.
>
> Following are the main changes done in this patch:
> 1. gamma_enable checks made specific to platform func()
> since icl doeesn't support that and enable gamma through mode
> 2. lut[0] and lut[8] enteries should be same superfine and coarse;
> superfine and fine segments respectively, checked twice-no harm
> 3. Removed temporary lut
> 4. Coarse segment interpolated gamma values loop start from 2
> instead of 0, since actual h/w values started getting overrided.
>
> v2: -readout code for multisegmented gamma has to come
> up with some intermediate entries that aren't preserved
> in hardware (Jani N)
> -linear interpolation (Ville)
> -moved common code to check gamma_enable to specific funcs,
> since icl doesn't support that
> v3: -use u16 instead of __u16 [Jani N]
> -used single lut [Jani N]
> -improved and more readable for loops [Jani N]
> -read values directly to actual locations and then fill gaps [Jani N]
> -moved cleaning to patch 1 [Jani N]
> -renamed icl_read_lut_multi_seg() to icl_read_lut_multi_segment to
> make it similar to icl_load_luts()
> -renamed icl_compute_interpolated_gamma_blob() to
> icl_compute_interpolated_gamma_lut_values() more sensible, I guess
>
> Signed-off-by: Swati Sharma <swati2.sharma@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_color.c | 216 +++++++++++++++++++++++++++--
> drivers/gpu/drm/i915/i915_reg.h | 7 +
> 2 files changed, 208 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 765482d..ad548ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1371,6 +1371,9 @@ static int icl_color_check(struct intel_crtc_state *crtc_state)
>
> static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1384,6 +1387,9 @@ static int i9xx_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if ((crtc_state->csc_mode & CSC_POSITION_BEFORE_GAMMA) == 0)
> return 0;
>
> @@ -1400,6 +1406,9 @@ static int ilk_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> return 10;
> else
> @@ -1408,6 +1417,9 @@ static int chv_gamma_precision(const struct intel_crtc_state *crtc_state)
>
> static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> {
> + if (!crtc_state->gamma_enable)
> + return 0;
> +
> switch (crtc_state->gamma_mode) {
> case GAMMA_MODE_MODE_8BIT:
> return 8;
> @@ -1419,21 +1431,39 @@ static int glk_gamma_precision(const struct intel_crtc_state *crtc_state)
> }
> }
>
> +static int icl_gamma_precision(const struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & POST_CSC_GAMMA_ENABLE) == 0)
> + return 0;
> +
> + switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
> + case GAMMA_MODE_MODE_8BIT:
> + return 8;
> + case GAMMA_MODE_MODE_10BIT:
> + return 10;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + return 16;
> + default:
> + MISSING_CASE(crtc_state->gamma_mode);
> + return 0;
> + }
> +
> +}
> +
> int intel_color_get_gamma_bit_precision(const struct intel_crtc_state *crtc_state)
> {
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>
> - if (!crtc_state->gamma_enable)
> - return 0;
> -
> if (HAS_GMCH(dev_priv)) {
> if (IS_CHERRYVIEW(dev_priv))
> return chv_gamma_precision(crtc_state);
> else
> return i9xx_gamma_precision(crtc_state);
> } else {
> - if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> + if (INTEL_GEN(dev_priv) >= 11)
> + return icl_gamma_precision(crtc_state);
> + else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv))
> return glk_gamma_precision(crtc_state);
> else if (IS_IRONLAKE(dev_priv))
> return ilk_gamma_precision(crtc_state);
> @@ -1464,6 +1494,30 @@ static bool intel_color_lut_entry_equal(struct drm_color_lut *lut1,
> return true;
> }
>
> +static bool intel_color_lut_entry_multi_equal(struct drm_color_lut *lut1,
> + struct drm_color_lut *lut2,
> + int lut_size, u32 err)
> +{
> + int i;
> +
> + for (i = 0; i < 9; i++) {
> + if (!err_check(&lut1[i], &lut2[i], err))
> + return false;
> + }
> +
> + for (i = 1; i < 257; i++) {
> + if (!err_check(&lut1[i * 8], &lut2[i * 8], err))
> + return false;
> + }
> +
> + for (i = 0; i < 256; i++) {
> + if (!err_check(&lut1[i * 8 * 128], &lut2[i * 8 * 128], err))
> + return false;
> + }
> +
> + return true;
> +}
> +
> bool intel_color_lut_equal(struct drm_property_blob *blob1,
> struct drm_property_blob *blob2,
> u32 gamma_mode, u32 bit_precision)
> @@ -1482,16 +1536,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> lut_size2 = drm_color_lut_size(blob2);
>
> /* check sw and hw lut size */
> - switch (gamma_mode) {
> - case GAMMA_MODE_MODE_8BIT:
> - case GAMMA_MODE_MODE_10BIT:
> - if (lut_size1 != lut_size2)
> - return false;
> - break;
> - default:
> - MISSING_CASE(gamma_mode);
> - return false;
> - }
> + if (lut_size1 != lut_size2)
> + return false;
>
> lut1 = blob1->data;
> lut2 = blob2->data;
> @@ -1499,13 +1545,18 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
> err = 0xffff >> bit_precision;
>
> /* check sw and hw lut entry to be equal */
> - switch (gamma_mode) {
> + switch (gamma_mode & GAMMA_MODE_MODE_MASK) {
> case GAMMA_MODE_MODE_8BIT:
> case GAMMA_MODE_MODE_10BIT:
> if (!intel_color_lut_entry_equal(lut1, lut2,
> lut_size2, err))
> return false;
> break;
> + case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
> + if (!intel_color_lut_entry_multi_equal(lut1, lut2,
> + lut_size2, err))
> + return false;
> + break;
> default:
> MISSING_CASE(gamma_mode);
> return false;
> @@ -1745,6 +1796,140 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
> crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> }
>
> +static u16 cal_step_size(u16 end_val, u16 start_val, int steps)
> +{
> + return ((end_val - start_val) / steps);
> +}
> +
> +static struct drm_color_lut *
> +icl_compute_interpolated_gamma_lut_values(struct drm_color_lut *lut, u32 lut_size)
> +{
> + u16 red_step_size, green_step_size, blue_step_size;
> + int start, end, steps;
> + int i, j;
> +
> + for (i = 1; i < 257 - 1; i++) {
> + start = i * 8;
> + end = (i + 1) * 8;
> + steps = end - start;
> +
> + red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
> + green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
> + blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
> +
> + for (j = start + 1; j < end; j++) {
> + lut[j].red = lut[j - 1].red + red_step_size;
> + lut[j].green = lut[j - 1].green + green_step_size;
> + lut[j].blue = lut[j - 1].blue + blue_step_size;
> +
> + i++;
Why would this be needed?
> + }
> + }
> +
> + for (i = 2; i < 256 - 1; i++) {
> + start = i * 8 * 128;
> + end = (i + 1) * 8 * 128;
> + steps = end - start;
> +
> + red_step_size = cal_step_size(lut[end].red, lut[start].red, steps);
> + green_step_size = cal_step_size(lut[end].green, lut[start].green, steps);
> + blue_step_size = cal_step_size(lut[end].blue, lut[start].blue, steps);
> +
> + for (j = start + 1; j < end; j++) {
> + lut[j].red = lut[j - 1].red + red_step_size;
> + lut[j].green = lut[j - 1].green + green_step_size;
> + lut[j].blue = lut[j - 1].blue + blue_step_size;
> +
> + i++;
Ditto.
I think everything else checks out. With those fixed,
Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> + }
> + }
> +
> + return lut;
> +}
> +
> +static struct drm_property_blob *
> +icl_read_lut_multi_segment(const struct intel_crtc_state *crtc_state)
> +{
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + int lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> + enum pipe pipe = crtc->pipe;
> + struct drm_property_blob *blob;
> + struct drm_color_lut *blob_data;
> + u32 i, val1, val2;
> +
> + blob = drm_property_create_blob(&dev_priv->drm,
> + sizeof(struct drm_color_lut) * lut_size,
> + NULL);
> + if (IS_ERR(blob))
> + return NULL;
> +
> + blob_data = blob->data;
> +
> + I915_WRITE(PREC_PAL_MULTI_SEG_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> + for (i = 0; i < 9; i++) {
> + val1 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_MULTI_SEG_DATA(pipe));
> +
> + blob_data[i].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + I915_WRITE(PREC_PAL_INDEX(pipe), PAL_PREC_AUTO_INCREMENT);
> +
> + for (i = 1; i < 257; i++) {
> + val1 = I915_READ(PREC_PAL_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> + blob_data[i * 8].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i * 8].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i * 8].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + for (i = 0; i < 256; i++) {
> + val1 = I915_READ(PREC_PAL_DATA(pipe));
> + val2 = I915_READ(PREC_PAL_DATA(pipe));
> +
> + blob_data[i * 8 * 128].red = REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_RED_LDW_MASK, val1);
> + blob_data[i * 8 * 128].green = REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_GREEN_LDW_MASK, val1);
> + blob_data[i * 8 * 128].blue = REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_UDW_MASK, val2) << 6 |
> + REG_FIELD_GET(PAL_PREC_MULTI_SEG_BLUE_LDW_MASK, val1);
> + }
> +
> + blob_data[lut_size - 1].red = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 0)));
> + blob_data[lut_size - 1].green = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> + blob_data[lut_size - 1].blue = REG_FIELD_GET(PREC_PAL_GC_MAX_RGB_MASK,
> + I915_READ(PREC_PAL_GC_MAX(pipe, 1)));
> +
> + blob_data = icl_compute_interpolated_gamma_lut_values(blob_data, lut_size);
> +
> + return blob;
> +}
> +
> +static void icl_read_luts(struct intel_crtc_state *crtc_state)
> +{
> + if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_8BIT)
> + crtc_state->base.gamma_lut = i9xx_read_lut_8(crtc_state);
> + else if ((crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) ==
> + GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED)
> + crtc_state->base.gamma_lut = icl_read_lut_multi_segment(crtc_state);
> + else
> + crtc_state->base.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> +}
> +
> void intel_color_init(struct intel_crtc *crtc)
> {
> struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1788,6 +1973,7 @@ void intel_color_init(struct intel_crtc *crtc)
>
> if (INTEL_GEN(dev_priv) >= 11) {
> dev_priv->display.load_luts = icl_load_luts;
> + dev_priv->display.read_luts = icl_read_luts;
> } else if (IS_CANNONLAKE(dev_priv) || IS_GEMINILAKE(dev_priv)) {
> dev_priv->display.load_luts = glk_load_luts;
> dev_priv->display.read_luts = glk_read_luts;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bf37ece..844dd62 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10378,6 +10378,7 @@ enum skl_power_gate {
>
> #define PREC_PAL_INDEX(pipe) _MMIO_PIPE(pipe, _PAL_PREC_INDEX_A, _PAL_PREC_INDEX_B)
> #define PREC_PAL_DATA(pipe) _MMIO_PIPE(pipe, _PAL_PREC_DATA_A, _PAL_PREC_DATA_B)
> +#define PREC_PAL_GC_MAX_RGB_MASK REG_GENMASK(15, 0)
> #define PREC_PAL_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_GC_MAX_A, _PAL_PREC_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT_GC_MAX_A, _PAL_PREC_EXT_GC_MAX_B) + (i) * 4)
> #define PREC_PAL_EXT2_GC_MAX(pipe, i) _MMIO(_PIPE(pipe, _PAL_PREC_EXT2_GC_MAX_A, _PAL_PREC_EXT2_GC_MAX_B) + (i) * 4)
> @@ -10401,6 +10402,12 @@ enum skl_power_gate {
>
> #define _PAL_PREC_MULTI_SEG_DATA_A 0x4A40C
> #define _PAL_PREC_MULTI_SEG_DATA_B 0x4AC0C
> +#define PAL_PREC_MULTI_SEG_RED_LDW_MASK REG_GENMASK(29, 24)
> +#define PAL_PREC_MULTI_SEG_RED_UDW_MASK REG_GENMASK(29, 20)
> +#define PAL_PREC_MULTI_SEG_GREEN_LDW_MASK REG_GENMASK(19, 14)
> +#define PAL_PREC_MULTI_SEG_GREEN_UDW_MASK REG_GENMASK(19, 10)
> +#define PAL_PREC_MULTI_SEG_BLUE_LDW_MASK REG_GENMASK(9, 4)
> +#define PAL_PREC_MULTI_SEG_BLUE_UDW_MASK REG_GENMASK(9, 0)
>
> #define PREC_PAL_MULTI_SEG_INDEX(pipe) _MMIO_PIPE(pipe, \
> _PAL_PREC_MULTI_SEG_INDEX_A, \
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2019-09-20 12:06 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-09-19 18:17 [v3][PATCH 0/3] adding gamma state checker for icl+ platforms Swati Sharma
2019-09-19 18:17 ` [v3][PATCH 1/3] drm/i915/color: Fix formatting issues Swati Sharma
2019-09-20 11:54 ` Jani Nikula
2019-09-19 18:17 ` [v3][PATCH 2/3] drm/i915/color: Extract icl_read_luts() Swati Sharma
2019-09-20 10:24 ` Jani Nikula
2019-09-20 12:06 ` Jani Nikula
2019-09-19 18:17 ` [v3][PATCH 3/3] FOR_TESTING_ONLY: Print rgb values of hw and sw blobs Swati Sharma
2019-09-19 20:55 ` ✗ Fi.CI.CHECKPATCH: warning for adding gamma state checker for icl+ platforms (rev3) Patchwork
2019-09-19 21:18 ` ✓ Fi.CI.BAT: success " Patchwork
2019-09-20 9:41 ` ✗ Fi.CI.IGT: failure " Patchwork
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