All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH 00/15] Adding NV12 support
@ 2018-01-15  3:18 Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
                   ` (19 more replies)
  0 siblings, 20 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

This patch series is adding NV12 support for Broxton display after rebasing on
latest drm-tip.
Initial series of the patches can be found here:
https://lists.freedesktop.org/archives/intel-gfx/2015-May/066786.html

Previous revision history:
The first version of patches were reviewed when floated by Chandra in 2015
but currently there was a design change with respect to
- the way fb offset is handled
- the way rotation is handled
Current NV12 patch series has been ported as per the
current changes on drm-tip

Review comments from Ville (12th June 2017) have been addressed Review
comments from Clinton A Taylor (7th July 2017) have been addressed

Review comments from Clinton A Taylor (10th July 2017)
	have been addressed. Had missed out tested-by/reviewed-by in the patches.

	Fixed that error in this series.
	Review comments from Ville (11th July 2017) addressed.
	Review comments from Paauwe, Bob (29th July 2017) addressed.

Update from rev 28 Aug 2017
	Rebased the series.
	Tested with IGT for rotation, sprite and tiling combinations.
	IGT Links:
	https://patchwork.kernel.org/patch/9995943/
	https://patchwork.kernel.org/patch/9995945/

Update from last rev (Jan 4th 2018):
	Rebased the series.
	Review comments by Maarten are addressed in this series.

Patches are tested (dependent on) watermark necessary changes
https://patchwork.freedesktop.org/series/33439/

Chandra Konduru (6):
  drm/i915: Set scaler mode for NV12
  drm/i915: Update format_is_yuv() to include NV12
  drm/i915: Upscale scaler max scale for NV12
  drm/i915: Add NV12 as supported format for primary plane
  drm/i915: Add NV12 as supported format for sprite plane
  drm/i915: Add NV12 support to intel_framebuffer_init

Mahesh Kumar (9):
  drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  drm/i915/skl+: refactor WM calculation for NV12
  drm/i915/skl+: add NV12 in skl_format_to_fourcc
  drm/i915/skl+: support verification of DDB HW state for NV12
  drm/i915/skl+: NV12 related changes for WM
  drm/i915/skl+: pass skl_wm_level struct to wm compute func
  drm/i915/skl+: make sure higher latency level has higher wm value
  drm/i915/skl+: nv12 workaround disable WM level 1-7
  drm/i915/skl: split skl_compute_ddb function

 drivers/gpu/drm/i915/i915_drv.h      |   9 +-
 drivers/gpu/drm/i915/i915_reg.h      |   1 +
 drivers/gpu/drm/i915/intel_atomic.c  |   8 +-
 drivers/gpu/drm/i915/intel_display.c |  71 ++++--
 drivers/gpu/drm/i915/intel_drv.h     |   8 +-
 drivers/gpu/drm/i915/intel_pm.c      | 433 ++++++++++++++++++++++-------------
 drivers/gpu/drm/i915/intel_sprite.c  |  34 ++-
 7 files changed, 374 insertions(+), 190 deletions(-)

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-20  0:39   ` kbuild test robot
  2018-01-15  3:18 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
                   ` (18 subsequent siblings)
  19 siblings, 1 reply; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Current code calculates DDB for planar formats in such a way that we
store DDB of plane-0 in plane 1 & vice-versa.
In order to make this clean this patch refactors WM/DDB calculation for
NV12 planar formats.

v2: Addressed review comments by Maarten

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |   4 +-
 drivers/gpu/drm/i915/intel_drv.h |   1 +
 drivers/gpu/drm/i915/intel_pm.c  | 121 ++++++++++++++++++++-------------------
 3 files changed, 64 insertions(+), 62 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 8d9fde8..5b01c54 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1433,8 +1433,8 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
 }
 
 struct skl_ddb_allocation {
-	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/uv */
-	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
+	struct skl_ddb_entry plane[I915_MAX_PIPES][I915_MAX_PLANES]; /* packed/y */
+	struct skl_ddb_entry uv_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
 struct skl_ddb_values {
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 275c489..a057c67 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -592,6 +592,7 @@ struct intel_pipe_wm {
 struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level trans_wm;
+	bool is_nv12;
 };
 
 struct skl_pipe_wm {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b4cb21d..b8a769d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4004,9 +4004,9 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 static unsigned int
 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 			     const struct drm_plane_state *pstate,
-			     int y)
+			     const int plane)
 {
-	struct intel_plane *plane = to_intel_plane(pstate->plane);
+	struct intel_plane *intel_plane = to_intel_plane(pstate->plane);
 	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
 	uint32_t data_rate;
 	uint32_t width = 0, height = 0;
@@ -4020,9 +4020,9 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	fb = pstate->fb;
 	format = fb->format->format;
 
-	if (plane->id == PLANE_CURSOR)
+	if (intel_plane->id == PLANE_CURSOR)
 		return 0;
-	if (y && format != DRM_FORMAT_NV12)
+	if (plane == 1 && format != DRM_FORMAT_NV12)
 		return 0;
 
 	/*
@@ -4033,19 +4033,14 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
 	width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	height = drm_rect_height(&intel_pstate->base.src) >> 16;
 
-	/* for planar format */
-	if (format == DRM_FORMAT_NV12) {
-		if (y)  /* y-plane data rate */
-			data_rate = width * height *
-				fb->format->cpp[0];
-		else    /* uv-plane data rate */
-			data_rate = (width / 2) * (height / 2) *
-				fb->format->cpp[1];
-	} else {
-		/* for packed formats */
-		data_rate = width * height * fb->format->cpp[0];
+	/* UV plane does 1/2 pixel sub-sampling */
+	if (plane == 1 && format == DRM_FORMAT_NV12) {
+		width /= 2;
+		height /= 2;
 	}
 
+	data_rate = width * height * fb->format->cpp[plane];
+
 	down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate);
 
 	return mul_round_up_u32_fixed16(data_rate, down_scale_amount);
@@ -4058,8 +4053,8 @@ skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
  */
 static unsigned int
 skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
-				 unsigned *plane_data_rate,
-				 unsigned *plane_y_data_rate)
+				 unsigned int *plane_data_rate,
+				 unsigned int *uv_plane_data_rate)
 {
 	struct drm_crtc_state *cstate = &intel_cstate->base;
 	struct drm_atomic_state *state = cstate->state;
@@ -4075,17 +4070,17 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 		enum plane_id plane_id = to_intel_plane(plane)->id;
 		unsigned int rate;
 
-		/* packed/uv */
+		/* packed/y */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 0);
 		plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 
-		/* y-plane */
+		/* uv-plane */
 		rate = skl_plane_relative_data_rate(intel_cstate,
 						    pstate, 1);
-		plane_y_data_rate[plane_id] = rate;
+		uv_plane_data_rate[plane_id] = rate;
 
 		total_data_rate += rate;
 	}
@@ -4094,8 +4089,7 @@ skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
 }
 
 static uint16_t
-skl_ddb_min_alloc(const struct drm_plane_state *pstate,
-		  const int y)
+skl_ddb_min_alloc(const struct drm_plane_state *pstate, const int plane)
 {
 	struct drm_framebuffer *fb = pstate->fb;
 	struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
@@ -4106,8 +4100,8 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
 	if (WARN_ON(!fb))
 		return 0;
 
-	/* For packed formats, no y-plane, return 0 */
-	if (y && fb->format->format != DRM_FORMAT_NV12)
+	/* For packed formats, and uv-plane, return 0 */
+	if (plane == 1 && fb->format->format != DRM_FORMAT_NV12)
 		return 0;
 
 	/* For Non Y-tile return 8-blocks */
@@ -4126,15 +4120,12 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
 	src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
 
 	/* Halve UV plane width and height for NV12 */
-	if (fb->format->format == DRM_FORMAT_NV12 && !y) {
+	if (plane == 1) {
 		src_w /= 2;
 		src_h /= 2;
 	}
 
-	if (fb->format->format == DRM_FORMAT_NV12 && !y)
-		plane_bpp = fb->format->cpp[1];
-	else
-		plane_bpp = fb->format->cpp[0];
+	plane_bpp = fb->format->cpp[plane];
 
 	if (drm_rotation_90_or_270(pstate->rotation)) {
 		switch (plane_bpp) {
@@ -4162,7 +4153,7 @@ skl_ddb_min_alloc(const struct drm_plane_state *pstate,
 
 static void
 skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
-		 uint16_t *minimum, uint16_t *y_minimum)
+		 uint16_t *minimum, uint16_t *uv_minimum)
 {
 	const struct drm_plane_state *pstate;
 	struct drm_plane *plane;
@@ -4177,7 +4168,7 @@ skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
 			continue;
 
 		minimum[plane_id] = skl_ddb_min_alloc(pstate, 0);
-		y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
+		uv_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1);
 	}
 
 	minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
@@ -4195,17 +4186,17 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
 	uint16_t alloc_size, start;
 	uint16_t minimum[I915_MAX_PLANES] = {};
-	uint16_t y_minimum[I915_MAX_PLANES] = {};
+	uint16_t uv_minimum[I915_MAX_PLANES] = {};
 	unsigned int total_data_rate;
 	enum plane_id plane_id;
 	int num_active;
-	unsigned plane_data_rate[I915_MAX_PLANES] = {};
-	unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
+	unsigned int plane_data_rate[I915_MAX_PLANES] = {};
+	unsigned int uv_plane_data_rate[I915_MAX_PLANES] = {};
 	uint16_t total_min_blocks = 0;
 
 	/* Clear the partitioning for disabled planes. */
 	memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
-	memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
+	memset(ddb->uv_plane[pipe], 0, sizeof(ddb->uv_plane[pipe]));
 
 	if (WARN_ON(!state))
 		return 0;
@@ -4220,7 +4211,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	if (alloc_size == 0)
 		return 0;
 
-	skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
+	skl_ddb_calc_min(cstate, num_active, minimum, uv_minimum);
 
 	/*
 	 * 1. Allocate the mininum required blocks for each active plane
@@ -4230,7 +4221,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
 		total_min_blocks += minimum[plane_id];
-		total_min_blocks += y_minimum[plane_id];
+		total_min_blocks += uv_minimum[plane_id];
 	}
 
 	if (total_min_blocks > alloc_size) {
@@ -4252,14 +4243,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 	 */
 	total_data_rate = skl_get_total_relative_data_rate(cstate,
 							   plane_data_rate,
-							   plane_y_data_rate);
+							   uv_plane_data_rate);
 	if (total_data_rate == 0)
 		return 0;
 
 	start = alloc->start;
 	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-		unsigned int data_rate, y_data_rate;
-		uint16_t plane_blocks, y_plane_blocks = 0;
+		unsigned int data_rate, uv_data_rate;
+		uint16_t plane_blocks, uv_plane_blocks;
 
 		if (plane_id == PLANE_CURSOR)
 			continue;
@@ -4283,21 +4274,20 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
 
 		start += plane_blocks;
 
-		/*
-		 * allocation for y_plane part of planar format:
-		 */
-		y_data_rate = plane_y_data_rate[plane_id];
+		/* Allocate DDB for UV plane for planar format/NV12 */
+		uv_data_rate = uv_plane_data_rate[plane_id];
 
-		y_plane_blocks = y_minimum[plane_id];
-		y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
+		uv_plane_blocks = uv_minimum[plane_id];
+		uv_plane_blocks += div_u64((uint64_t)alloc_size * uv_data_rate,
 					total_data_rate);
 
-		if (y_data_rate) {
-			ddb->y_plane[pipe][plane_id].start = start;
-			ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks;
+		if (uv_data_rate) {
+			ddb->uv_plane[pipe][plane_id].start = start;
+			ddb->uv_plane[pipe][plane_id].end = start +
+								uv_plane_blocks;
 		}
 
-		start += y_plane_blocks;
+		start += uv_plane_blocks;
 	}
 
 	return 0;
@@ -4425,8 +4415,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	}
 
-	wp->cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] :
-							    fb->format->cpp[0];
+	wp->cpp = fb->format->cpp[0];
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
@@ -4618,6 +4607,9 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 			return ret;
 	}
 
+	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
+		wm->is_nv12 = true;
+
 	return 0;
 }
 
@@ -4788,10 +4780,19 @@ static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
 
-	skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
-			    &ddb->plane[pipe][plane_id]);
-	skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id),
-			    &ddb->y_plane[pipe][plane_id]);
+	if (wm->is_nv12) {
+		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+					&ddb->uv_plane[pipe][plane_id]);
+		skl_ddb_entry_write(dev_priv,
+				    PLANE_NV12_BUF_CFG(pipe, plane_id),
+				    &ddb->plane[pipe][plane_id]);
+	} else {
+		skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
+					&ddb->plane[pipe][plane_id]);
+		/* No NV12 buffer allocation for non NV12 pixel formats */
+		skl_ddb_entry_write(dev_priv,
+				    PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
+	}
 }
 
 static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
@@ -4906,8 +4907,8 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 
 		if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id],
 					&new_ddb->plane[pipe][plane_id]) &&
-		    skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id],
-					&new_ddb->y_plane[pipe][plane_id]))
+		    skl_ddb_entry_equal(&cur_ddb->uv_plane[pipe][plane_id],
+					&new_ddb->uv_plane[pipe][plane_id]))
 			continue;
 
 		plane_state = drm_atomic_get_plane_state(state, plane);
@@ -5001,8 +5002,8 @@ skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
 		     struct skl_ddb_values *src,
 		     enum pipe pipe)
 {
-	memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
-	       sizeof(dst->ddb.y_plane[pipe]));
+	memcpy(dst->ddb.uv_plane[pipe], src->ddb.uv_plane[pipe],
+	       sizeof(dst->ddb.uv_plane[pipe]));
 	memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
 	       sizeof(dst->ddb.plane[pipe]));
 }
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
                   ` (17 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx

From: Mahesh Kumar <mahesh1.kumar@intel.com>

NV12 requires WM calculation for UV plane as well.
UV plane WM should also fulfill all the WM related restrictions.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  1 +
 drivers/gpu/drm/i915/intel_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c  | 54 ++++++++++++++++++++++++++++++++--------
 3 files changed, 45 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5b01c54..38b731d 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1452,6 +1452,7 @@ struct skl_wm_level {
 struct skl_wm_params {
 	bool x_tiled, y_tiled;
 	bool rc_surface;
+	bool is_nv12;
 	uint32_t width;
 	uint8_t cpp;
 	uint32_t plane_pixel_rate;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index adceaf3..0f8eb93 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -591,6 +591,7 @@ struct intel_pipe_wm {
 
 struct skl_plane_wm {
 	struct skl_wm_level wm[8];
+	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
 	bool is_nv12;
 };
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 34432da..c9e1f42 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4413,7 +4413,7 @@ static int
 skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 			    struct intel_crtc_state *cstate,
 			    const struct intel_plane_state *intel_pstate,
-			    struct skl_wm_params *wp)
+			    struct skl_wm_params *wp, int plane_num)
 {
 	struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane);
 	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4426,6 +4426,12 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	if (!intel_wm_plane_visible(cstate, intel_pstate))
 		return 0;
 
+	/* only NV12 format has two planes */
+	if (plane_num == 1 && fb->format->format != DRM_FORMAT_NV12) {
+		DRM_DEBUG_KMS("Non NV12 format have single plane\n");
+		return -EINVAL;
+	}
+
 	wp->y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED ||
 		      fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
 		      fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
@@ -4433,6 +4439,7 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 	wp->x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED;
 	wp->rc_surface = fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 			 fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+	wp->is_nv12 = fb->format->format == DRM_FORMAT_NV12;
 
 	if (plane->id == PLANE_CURSOR) {
 		wp->width = intel_pstate->base.crtc_w;
@@ -4445,7 +4452,10 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		wp->width = drm_rect_width(&intel_pstate->base.src) >> 16;
 	}
 
-	wp->cpp = fb->format->cpp[0];
+	if (plane_num == 1 && wp->is_nv12)
+		wp->width /= 2;
+
+	wp->cpp = fb->format->cpp[plane_num];
 	wp->plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate,
 							     intel_pstate);
 
@@ -4606,7 +4616,8 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 		      struct intel_crtc_state *cstate,
 		      const struct intel_plane_state *intel_pstate,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_plane_wm *wm)
+		      struct skl_plane_wm *wm,
+		      int plane_num)
 {
 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_plane *plane = intel_pstate->base.plane;
@@ -4614,15 +4625,20 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	uint16_t ddb_blocks;
 	enum pipe pipe = intel_crtc->pipe;
 	int level, max_level = ilk_wm_max_level(dev_priv);
+	enum plane_id plane_id = intel_plane->id;
 	int ret;
 
 	if (WARN_ON(!intel_pstate->base.fb))
 		return -EINVAL;
 
-	ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]);
+	if (plane_num == 0)
+		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
+	else
+		ddb_blocks = skl_ddb_entry_size(&ddb->uv_plane[pipe][plane_id]);
 
 	for (level = 0; level <= max_level; level++) {
-		struct skl_wm_level *result = &wm->wm[level];
+		struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
+							  &wm->wm[level];
 
 		ret = skl_compute_plane_wm(dev_priv,
 					   cstate,
@@ -4637,9 +4653,6 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 			return ret;
 	}
 
-	if (intel_pstate->base.fb->format->format == DRM_FORMAT_NV12)
-		wm->is_nv12 = true;
-
 	return 0;
 }
 
@@ -4748,20 +4761,39 @@ static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
 
 		wm = &pipe_wm->planes[plane_id];
 		ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][plane_id]);
-		memset(&wm_params, 0, sizeof(struct skl_wm_params));
 
 		ret = skl_compute_plane_wm_params(dev_priv, cstate,
-						  intel_pstate, &wm_params);
+						  intel_pstate, &wm_params, 0);
 		if (ret)
 			return ret;
 
 		ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
-					    intel_pstate, &wm_params, wm);
+					    intel_pstate, &wm_params, wm, 0);
 		if (ret)
 			return ret;
+
 		skl_compute_transition_wm(cstate, &wm_params, &wm->wm[0],
 					  ddb_blocks, &wm->trans_wm);
+
+		/* uv plane watermarks must also be validated for NV12 */
+		if (wm_params.is_nv12) {
+			memset(&wm_params, 0, sizeof(struct skl_wm_params));
+			wm->is_nv12 = true;
+
+			ret = skl_compute_plane_wm_params(dev_priv, cstate,
+							  intel_pstate,
+							  &wm_params, 1);
+			if (ret)
+				return ret;
+
+			ret = skl_compute_wm_levels(dev_priv, ddb, cstate,
+						    intel_pstate, &wm_params,
+						    wm, 1);
+			if (ret)
+				return ret;
+		}
 	}
+
 	pipe_wm->linetime = skl_compute_linetime_wm(cstate);
 
 	return 0;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-17 11:43   ` Mika Kahola
  2018-01-15  3:18 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
                   ` (16 subsequent siblings)
  19 siblings, 1 reply; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Add support of recognizing DRM_FORMAT_NV12 from plane_format
register value.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 02bf31d..1345796 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2612,6 +2612,8 @@ static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 	switch (format) {
 	case PLANE_CTL_FORMAT_RGB_565:
 		return DRM_FORMAT_RGB565;
+	case PLANE_CTL_FORMAT_NV12:
+		return DRM_FORMAT_NV12;
 	default:
 	case PLANE_CTL_FORMAT_XRGB_8888:
 		if (rgb_order) {
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (2 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 04/15] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
                   ` (15 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx

From: Mahesh Kumar <mahesh1.kumar@intel.com>

skl_wm_values struct contains values of pipe/plane DDB only.
so rename it for better readability of code. Similarly
skl_copy_wm_for_pipe copies DDB values.

s/skl_wm_values/skl_ddb_values
s/skl_copy_wm_for_pipe/skl_copy_ddb_for_pipe

Changes since V1:
 - also change name of skl_copy_wm_for_pipe

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h  |  4 ++--
 drivers/gpu/drm/i915/intel_drv.h |  2 +-
 drivers/gpu/drm/i915/intel_pm.c  | 14 +++++++-------
 3 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index a689396..8d9fde8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1437,7 +1437,7 @@ struct skl_ddb_allocation {
 	struct skl_ddb_entry y_plane[I915_MAX_PIPES][I915_MAX_PLANES];
 };
 
-struct skl_wm_values {
+struct skl_ddb_values {
 	unsigned dirty_pipes;
 	struct skl_ddb_allocation ddb;
 };
@@ -2131,7 +2131,7 @@ struct drm_i915_private {
 		/* current hardware state */
 		union {
 			struct ilk_wm_values hw;
-			struct skl_wm_values skl_hw;
+			struct skl_ddb_values skl_hw;
 			struct vlv_wm_values vlv;
 			struct g4x_wm_values g4x;
 		};
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 731dc36..275c489 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -476,7 +476,7 @@ struct intel_atomic_state {
 	bool skip_intermediate_wm;
 
 	/* Gen9+ only */
-	struct skl_wm_values wm_results;
+	struct skl_ddb_values wm_results;
 
 	struct i915_sw_fence commit_ready;
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db79a8..b4cb21d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4997,8 +4997,8 @@ skl_compute_ddb(struct drm_atomic_state *state)
 }
 
 static void
-skl_copy_wm_for_pipe(struct skl_wm_values *dst,
-		     struct skl_wm_values *src,
+skl_copy_ddb_for_pipe(struct skl_ddb_values *dst,
+		     struct skl_ddb_values *src,
 		     enum pipe pipe)
 {
 	memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
@@ -5050,7 +5050,7 @@ skl_compute_wm(struct drm_atomic_state *state)
 	struct drm_crtc *crtc;
 	struct drm_crtc_state *cstate;
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_wm_values *results = &intel_state->wm_results;
+	struct skl_ddb_values *results = &intel_state->wm_results;
 	struct drm_device *dev = state->dev;
 	struct skl_pipe_wm *pipe_wm;
 	bool changed = false;
@@ -5152,8 +5152,8 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
 	struct drm_device *dev = intel_crtc->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct skl_wm_values *results = &state->wm_results;
-	struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
+	struct skl_ddb_values *results = &state->wm_results;
+	struct skl_ddb_values *hw_vals = &dev_priv->wm.skl_hw;
 	enum pipe pipe = intel_crtc->pipe;
 
 	if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
@@ -5164,7 +5164,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
 	if (cstate->base.active_changed)
 		skl_atomic_update_crtc_wm(state, cstate);
 
-	skl_copy_wm_for_pipe(hw_vals, results, pipe);
+	skl_copy_ddb_for_pipe(hw_vals, results, pipe);
 
 	mutex_unlock(&dev_priv->wm.wm_mutex);
 }
@@ -5296,7 +5296,7 @@ void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
 void skl_wm_get_hw_state(struct drm_device *dev)
 {
 	struct drm_i915_private *dev_priv = to_i915(dev);
-	struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
+	struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
 	struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
 	struct drm_crtc *crtc;
 	struct intel_crtc *intel_crtc;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (4 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 04/15] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
                   ` (13 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx

From: Mahesh Kumar <mahesh1.kumar@intel.com>

DDB allocation optimization algorithm requires/assumes ddb allocation for
any memory C-state level DDB value to be as high as level below.
Render decompression requires level WM to be as high as wm level-0.
This patch fulfils both the requirements.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5800b5b..9ed507a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4514,6 +4514,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
+				const struct skl_wm_level *result_prev,
 				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
@@ -4579,6 +4580,15 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		} else {
 			res_blocks++;
 		}
+
+		/*
+		 * Make sure result blocks for higher latency levels are atleast
+		 * as high as level below.
+		 * Assumption in DDB algorithm optimization for special cases.
+		 * Also covers Display WA #1125 for RC.
+		 */
+		if (result_prev->plane_res_b > res_blocks)
+			res_blocks = result_prev->plane_res_b;
 	}
 
 	if (res_blocks >= ddb_allocation || res_lines > 31) {
@@ -4637,6 +4647,13 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = plane_num ? &wm->uv_wm[level] :
 							  &wm->wm[level];
+		struct skl_wm_level *result_prev;
+
+		if (level)
+			result_prev = plane_num ? &wm->uv_wm[level - 1] :
+						  &wm->wm[level - 1];
+		else
+			result_prev = plane_num ? &wm->uv_wm[0] : &wm->wm[0];
 
 		ret = skl_compute_plane_wm(dev_priv,
 					   cstate,
@@ -4644,6 +4661,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
+					   result_prev,
 					   result);
 		if (ret)
 			return ret;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 04/15] drm/i915/skl+: support verification of DDB HW state for NV12
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (3 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
                   ` (14 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Mahesh Kumar <mahesh1.kumar@intel.com>

NV12 formats have two registers for DDB. Verify both the registers for
NV12 during verify_wm_state.

v2: Addressed review comments by Maarten.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c |  2 +-
 drivers/gpu/drm/i915/intel_drv.h     |  1 +
 drivers/gpu/drm/i915/intel_pm.c      | 50 ++++++++++++++++++++++++++++--------
 3 files changed, 42 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 1345796..2ceea21 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2607,7 +2607,7 @@ static int i9xx_format_to_fourcc(int format)
 	}
 }
 
-static int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha)
 {
 	switch (format) {
 	case PLANE_CTL_FORMAT_RGB_565:
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index a057c67..adceaf3 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1591,6 +1591,7 @@ u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
 		     unsigned int rotation);
 int skl_check_plane_surface(struct intel_plane_state *plane_state);
 int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
+int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
 
 /* intel_csr.c */
 void intel_csr_ucode_init(struct drm_i915_private *);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b8a769d..34432da 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3820,6 +3820,43 @@ static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
 		entry->end += 1;
 }
 
+static void
+skl_ddb_get_hw_plane_state(struct drm_i915_private *dev_priv,
+			   const enum pipe pipe,
+			   const enum plane_id plane_id,
+			   struct skl_ddb_allocation *ddb /* out */)
+{
+	u32 val, val2 = 0;
+	int fourcc, pixel_format;
+
+	/* Cursor doesn't support NV12, so no extra calculation needed */
+	if (plane_id == PLANE_CURSOR) {
+		val = I915_READ(CUR_BUF_CFG(pipe));
+		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+		return;
+	}
+
+	val = I915_READ(PLANE_CTL(pipe, plane_id));
+
+	/* No DDB allocated for disabled planes */
+	if (!(val & PLANE_CTL_ENABLE))
+		return;
+
+	pixel_format = val & PLANE_CTL_FORMAT_MASK;
+	fourcc = skl_format_to_fourcc(pixel_format,
+				      val & PLANE_CTL_ORDER_RGBX,
+				      val & PLANE_CTL_ALPHA_MASK);
+
+	val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
+	val2 = I915_READ(PLANE_NV12_BUF_CFG(pipe, plane_id));
+
+	if (fourcc == DRM_FORMAT_NV12) {
+		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val2);
+		skl_ddb_entry_init_from_hw(&ddb->uv_plane[pipe][plane_id], val);
+	} else
+		skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
+}
+
 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 			  struct skl_ddb_allocation *ddb /* out */)
 {
@@ -3836,16 +3873,9 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 		if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
 			continue;
 
-		for_each_plane_id_on_crtc(crtc, plane_id) {
-			u32 val;
-
-			if (plane_id != PLANE_CURSOR)
-				val = I915_READ(PLANE_BUF_CFG(pipe, plane_id));
-			else
-				val = I915_READ(CUR_BUF_CFG(pipe));
-
-			skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val);
-		}
+		for_each_plane_id_on_crtc(crtc, plane_id)
+			skl_ddb_get_hw_plane_state(dev_priv, pipe,
+						   plane_id, ddb);
 
 		intel_display_power_put(dev_priv, power_domain);
 	}
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (5 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
                   ` (12 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Mahesh Kumar <mahesh1.kumar@intel.com>

Display Workaround #0826 (SKL:ALL BXT:ALL) & #1059(CNL:A)
Hardware sometimes fails to wake memory from pkg C states fetching the
last few lines of planar YUV 420 (NV12) planes. This causes
intermittent underflow and corruption.
WA: Disable package C states or do not enable latency levels 1 through 7
(WM1 - WM7) on NV12 planes.

v2: Addressed review comments by Maarten.

Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9ed507a..4d9c210 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4611,6 +4611,17 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
+	/*
+	 * Display WA #826 (SKL:ALL, BXT:ALL) & #1059 (CNL:A)
+	 * disable wm level 1-7 on NV12 planes
+	 */
+	if (wp->is_nv12 && (level >= 1) &&
+		(IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
+		 IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_A0))) {
+		result->plane_en = false;
+		return 0;
+	}
+
 	result->plane_res_b = res_blocks;
 	result->plane_res_l = res_lines;
 	result->plane_en = true;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 10/15] drm/i915: Set scaler mode for NV12
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (7 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
                   ` (10 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch sets appropriate scaler mode for NV12 format.
In this mode, skylake scaler does either chroma-upsampling or
chroma-upsampling and resolution scaling

v2: Review comments from Ville addressed
NV12 case to be checked first for setting
the scaler

v3: Rebased (me)

v4: Rebased (me)

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)
Restricting the NV12 change for scaler to BXT and KBL
in this series.

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h     | 1 +
 drivers/gpu/drm/i915/intel_atomic.c | 8 +++++++-
 2 files changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index f773f22..5f00b47 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -6656,6 +6656,7 @@ enum {
 #define PS_SCALER_MODE_MASK (3 << 28)
 #define PS_SCALER_MODE_DYN  (0 << 28)
 #define PS_SCALER_MODE_HQ  (1 << 28)
+#define PS_SCALER_MODE_NV12 (2 << 28)
 #define PS_PLANE_SEL_MASK  (7 << 25)
 #define PS_PLANE_SEL(plane) (((plane) + 1) << 25)
 #define PS_FILTER_MASK         (3 << 23)
diff --git a/drivers/gpu/drm/i915/intel_atomic.c b/drivers/gpu/drm/i915/intel_atomic.c
index d452c32..ecba7c7 100644
--- a/drivers/gpu/drm/i915/intel_atomic.c
+++ b/drivers/gpu/drm/i915/intel_atomic.c
@@ -327,7 +327,13 @@ int intel_atomic_setup_scalers(struct drm_i915_private *dev_priv,
 		}
 
 		/* set scaler mode */
-		if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
+		if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+			plane_state && plane_state->base.fb &&
+			plane_state->base.fb->format->format ==
+			DRM_FORMAT_NV12) {
+			scaler_state->scalers[*scaler_id].mode =
+				PS_SCALER_MODE_NV12;
+		} else if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
 			scaler_state->scalers[*scaler_id].mode = 0;
 		} else if (num_scalers_need == 1 && intel_crtc->pipe != PIPE_C) {
 			/*
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (6 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
                   ` (11 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This patch splits skl_compute_wm/ddb functions into two parts.
One adds all affected pipes after the commit to atomic_state structure
and second part does compute the DDB.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 157 ++++++++++++++++++++++------------------
 1 file changed, 88 insertions(+), 69 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4d9c210..3b9871d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -5009,69 +5009,16 @@ skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
 static int
 skl_compute_ddb(struct drm_atomic_state *state)
 {
-	struct drm_device *dev = state->dev;
-	struct drm_i915_private *dev_priv = to_i915(dev);
+	const struct drm_i915_private *dev_priv = to_i915(state->dev);
 	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct intel_crtc *intel_crtc;
 	struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
-	uint32_t realloc_pipes = pipes_modified(state);
-	int ret;
-
-	/*
-	 * If this is our first atomic update following hardware readout,
-	 * we can't trust the DDB that the BIOS programmed for us.  Let's
-	 * pretend that all pipes switched active status so that we'll
-	 * ensure a full DDB recompute.
-	 */
-	if (dev_priv->wm.distrust_bios_wm) {
-		ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
-				       state->acquire_ctx);
-		if (ret)
-			return ret;
-
-		intel_state->active_pipe_changes = ~0;
-
-		/*
-		 * We usually only initialize intel_state->active_crtcs if we
-		 * we're doing a modeset; make sure this field is always
-		 * initialized during the sanitization process that happens
-		 * on the first commit too.
-		 */
-		if (!intel_state->modeset)
-			intel_state->active_crtcs = dev_priv->active_crtcs;
-	}
-
-	/*
-	 * If the modeset changes which CRTC's are active, we need to
-	 * recompute the DDB allocation for *all* active pipes, even
-	 * those that weren't otherwise being modified in any way by this
-	 * atomic commit.  Due to the shrinking of the per-pipe allocations
-	 * when new active CRTC's are added, it's possible for a pipe that
-	 * we were already using and aren't changing at all here to suddenly
-	 * become invalid if its DDB needs exceeds its new allocation.
-	 *
-	 * Note that if we wind up doing a full DDB recompute, we can't let
-	 * any other display updates race with this transaction, so we need
-	 * to grab the lock on *all* CRTC's.
-	 */
-	if (intel_state->active_pipe_changes) {
-		realloc_pipes = ~0;
-		intel_state->wm_results.dirty_pipes = ~0;
-	}
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *cstate;
+	int ret, i;
 
-	/*
-	 * We're not recomputing for the pipes not included in the commit, so
-	 * make sure we start with the current state.
-	 */
 	memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
 
-	for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
-		struct intel_crtc_state *cstate;
-
-		cstate = intel_atomic_get_crtc_state(state, intel_crtc);
-		if (IS_ERR(cstate))
-			return PTR_ERR(cstate);
-
+	for_each_new_intel_crtc_in_state(intel_state, crtc, cstate, i) {
 		ret = skl_allocate_pipe_ddb(cstate, ddb);
 		if (ret)
 			return ret;
@@ -5133,23 +5080,23 @@ skl_print_wm_changes(const struct drm_atomic_state *state)
 }
 
 static int
-skl_compute_wm(struct drm_atomic_state *state)
+skl_ddb_add_affected_pipes(struct drm_atomic_state *state, bool *changed)
 {
-	struct drm_crtc *crtc;
-	struct drm_crtc_state *cstate;
-	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
-	struct skl_ddb_values *results = &intel_state->wm_results;
 	struct drm_device *dev = state->dev;
-	struct skl_pipe_wm *pipe_wm;
-	bool changed = false;
+	const struct drm_i915_private *dev_priv = to_i915(dev);
+	const struct drm_crtc *crtc;
+	const struct drm_crtc_state *cstate;
+	struct intel_crtc *intel_crtc;
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	uint32_t realloc_pipes = pipes_modified(state);
 	int ret, i;
 
 	/*
 	 * When we distrust bios wm we always need to recompute to set the
 	 * expected DDB allocations for each CRTC.
 	 */
-	if (to_i915(dev)->wm.distrust_bios_wm)
-		changed = true;
+	if (dev_priv->wm.distrust_bios_wm)
+		*changed = true;
 
 	/*
 	 * If this transaction isn't actually touching any CRTC's, don't
@@ -5160,14 +5107,86 @@ skl_compute_wm(struct drm_atomic_state *state)
 	 * hold _all_ CRTC state mutexes.
 	 */
 	for_each_new_crtc_in_state(state, crtc, cstate, i)
-		changed = true;
+		*changed = true;
 
-	if (!changed)
+	if (!*changed)
 		return 0;
 
+	/*
+	 * If this is our first atomic update following hardware readout,
+	 * we can't trust the DDB that the BIOS programmed for us.  Let's
+	 * pretend that all pipes switched active status so that we'll
+	 * ensure a full DDB recompute.
+	 */
+	if (dev_priv->wm.distrust_bios_wm) {
+		ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
+				       state->acquire_ctx);
+		if (ret)
+			return ret;
+
+		intel_state->active_pipe_changes = ~0;
+
+		/*
+		 * We usually only initialize intel_state->active_crtcs if we
+		 * we're doing a modeset; make sure this field is always
+		 * initialized during the sanitization process that happens
+		 * on the first commit too.
+		 */
+		if (!intel_state->modeset)
+			intel_state->active_crtcs = dev_priv->active_crtcs;
+	}
+
+	/*
+	 * If the modeset changes which CRTC's are active, we need to
+	 * recompute the DDB allocation for *all* active pipes, even
+	 * those that weren't otherwise being modified in any way by this
+	 * atomic commit.  Due to the shrinking of the per-pipe allocations
+	 * when new active CRTC's are added, it's possible for a pipe that
+	 * we were already using and aren't changing at all here to suddenly
+	 * become invalid if its DDB needs exceeds its new allocation.
+	 *
+	 * Note that if we wind up doing a full DDB recompute, we can't let
+	 * any other display updates race with this transaction, so we need
+	 * to grab the lock on *all* CRTC's.
+	 */
+	if (intel_state->active_pipe_changes) {
+		realloc_pipes = ~0;
+		intel_state->wm_results.dirty_pipes = ~0;
+	}
+
+	/*
+	 * We're not recomputing for the pipes not included in the commit, so
+	 * make sure we start with the current state.
+	 */
+	for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
+		struct intel_crtc_state *cstate;
+
+		cstate = intel_atomic_get_crtc_state(state, intel_crtc);
+		if (IS_ERR(cstate))
+			return PTR_ERR(cstate);
+	}
+
+	return 0;
+}
+
+static int
+skl_compute_wm(struct drm_atomic_state *state)
+{
+	struct drm_crtc *crtc;
+	struct drm_crtc_state *cstate;
+	struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
+	struct skl_ddb_values *results = &intel_state->wm_results;
+	struct skl_pipe_wm *pipe_wm;
+	bool changed = false;
+	int ret, i;
+
 	/* Clear all dirty flags */
 	results->dirty_pipes = 0;
 
+	ret = skl_ddb_add_affected_pipes(state, &changed);
+	if (ret || !changed)
+		return ret;
+
 	ret = skl_compute_ddb(state);
 	if (ret)
 		return ret;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (8 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
                   ` (9 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx

From: Mahesh Kumar <mahesh1.kumar@intel.com>

This will reduce number of arguments required to be passed in
skl_compute_plane_wm function.

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c9e1f42..5800b5b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4514,9 +4514,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 				uint16_t ddb_allocation,
 				int level,
 				const struct skl_wm_params *wp,
-				uint16_t *out_blocks, /* out */
-				uint8_t *out_lines, /* out */
-				bool *enabled /* out */)
+				struct skl_wm_level *result /* out */)
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
 	uint32_t latency = dev_priv->wm.skl_latency[level];
@@ -4529,7 +4527,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 
 	if (latency == 0 ||
 	    !intel_wm_plane_visible(cstate, intel_pstate)) {
-		*enabled = false;
+		result->plane_en = false;
 		return 0;
 	}
 
@@ -4584,7 +4582,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 	}
 
 	if (res_blocks >= ddb_allocation || res_lines > 31) {
-		*enabled = false;
+		result->plane_en = false;
 
 		/*
 		 * If there are no valid level 0 watermarks, then we can't
@@ -4603,9 +4601,9 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 		}
 	}
 
-	*out_blocks = res_blocks;
-	*out_lines = res_lines;
-	*enabled = true;
+	result->plane_res_b = res_blocks;
+	result->plane_res_l = res_lines;
+	result->plane_en = true;
 
 	return 0;
 }
@@ -4646,9 +4644,7 @@ skl_compute_wm_levels(const struct drm_i915_private *dev_priv,
 					   ddb_blocks,
 					   level,
 					   wm_params,
-					   &result->plane_res_b,
-					   &result->plane_res_l,
-					   &result->plane_en);
+					   result);
 		if (ret)
 			return ret;
 	}
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (9 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
                   ` (8 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch updates scaler max limit support for NV12

v2: Rebased (me)

v3: Rebased (me)

v4: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v5: Addressed review comments from Ville and rebased
- calculation of max_scale to be made
less convoluted by splitting it up a bit
- Indentation errors to be fixed in the series

v6: Rebased (me)
Fixed review comments from Paauwe, Bob J
Previous version, where a split of calculation
was done, was wrong. Fixed that issue here.

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 33 +++++++++++++++++++++++----------
 drivers/gpu/drm/i915/intel_drv.h     |  3 ++-
 drivers/gpu/drm/i915/intel_sprite.c  |  3 ++-
 3 files changed, 27 insertions(+), 12 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2ceea21..6efe9aa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3405,6 +3405,8 @@ static u32 skl_plane_ctl_format(uint32_t pixel_format)
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_UYVY;
 	case DRM_FORMAT_VYUY:
 		return PLANE_CTL_FORMAT_YUV422 | PLANE_CTL_YUV422_VYUY;
+	case DRM_FORMAT_NV12:
+		return PLANE_CTL_FORMAT_NV12;
 	default:
 		MISSING_CASE(pixel_format);
 	}
@@ -4628,7 +4630,8 @@ static void cpt_verify_modeset(struct drm_device *dev, int pipe)
 static int
 skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 		  unsigned int scaler_user, int *scaler_id,
-		  int src_w, int src_h, int dst_w, int dst_h)
+		  int src_w, int src_h, int dst_w, int dst_h,
+		  uint32_t pixel_format)
 {
 	struct intel_crtc_scaler_state *scaler_state =
 		&crtc_state->scaler_state;
@@ -4644,7 +4647,8 @@ skl_update_scaler(struct intel_crtc_state *crtc_state, bool force_detach,
 	 * the 90/270 degree plane rotation cases (to match the
 	 * GTT mapping), hence no need to account for rotation here.
 	 */
-	need_scaling = src_w != dst_w || src_h != dst_h;
+	need_scaling = src_w != dst_w || src_h != dst_h ||
+		(pixel_format == DRM_FORMAT_NV12);
 
 	if (crtc_state->ycbcr420 && scaler_user == SKL_CRTC_INDEX)
 		need_scaling = true;
@@ -4723,7 +4727,7 @@ int skl_update_scaler_crtc(struct intel_crtc_state *state)
 	return skl_update_scaler(state, !state->base.active, SKL_CRTC_INDEX,
 		&state->scaler_state.scaler_id,
 		state->pipe_src_w, state->pipe_src_h,
-		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay);
+		adjusted_mode->crtc_hdisplay, adjusted_mode->crtc_vdisplay, 0);
 }
 
 /**
@@ -4753,7 +4757,8 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 				drm_rect_width(&plane_state->base.src) >> 16,
 				drm_rect_height(&plane_state->base.src) >> 16,
 				drm_rect_width(&plane_state->base.dst),
-				drm_rect_height(&plane_state->base.dst));
+				drm_rect_height(&plane_state->base.dst),
+				fb ? fb->format->format : 0);
 
 	if (ret || plane_state->scaler_id < 0)
 		return ret;
@@ -4779,6 +4784,7 @@ static int skl_update_scaler_plane(struct intel_crtc_state *crtc_state,
 	case DRM_FORMAT_YVYU:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
+	case DRM_FORMAT_NV12:
 		break;
 	default:
 		DRM_DEBUG_KMS("[PLANE:%d:%s] FB:%d unsupported scaling format 0x%x\n",
@@ -12703,11 +12709,12 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
 }
 
 int
-skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state)
+skl_max_scale(struct intel_crtc *intel_crtc,
+	struct intel_crtc_state *crtc_state, uint32_t pixel_format)
 {
 	struct drm_i915_private *dev_priv;
-	int max_scale;
-	int crtc_clock, max_dotclk;
+	int max_scale, mult;
+	int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
 
 	if (!intel_crtc || !crtc_state->base.enable)
 		return DRM_PLANE_HELPER_NO_SCALING;
@@ -12729,8 +12736,10 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state
 	 *            or
 	 *    cdclk/crtc_clock
 	 */
-	max_scale = min((1 << 16) * 3 - 1,
-			(1 << 8) * ((max_dotclk << 8) / crtc_clock));
+	mult = pixel_format == DRM_FORMAT_NV12 ? 2 : 3;
+	tmpclk1 = (1 << 16) * mult - 1;
+	tmpclk2 = (1 << 8) * ((max_dotclk << 8) / crtc_clock);
+	max_scale = min(tmpclk1, tmpclk2);
 
 	return max_scale;
 }
@@ -12751,7 +12760,11 @@ intel_check_primary_plane(struct intel_plane *plane,
 		/* use scaler when colorkey is not required */
 		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 			min_scale = 1;
-			max_scale = skl_max_scale(to_intel_crtc(crtc), crtc_state);
+			max_scale = skl_max_scale(to_intel_crtc(crtc),
+						crtc_state,
+						state->base.fb ?
+						state->base.fb->format->format :
+						0);
 		}
 		can_position = true;
 	}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 0f8eb93..aaa55df 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1577,7 +1577,8 @@ void intel_mode_from_pipe_config(struct drm_display_mode *mode,
 				 struct intel_crtc_state *pipe_config);
 
 int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state);
+int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
+	uint32_t pixel_format);
 
 static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
 {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 58f56de..09732ae 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -897,7 +897,8 @@ intel_check_sprite_plane(struct intel_plane *plane,
 		if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
 			can_scale = 1;
 			min_scale = 1;
-			max_scale = skl_max_scale(crtc, crtc_state);
+			max_scale = skl_max_scale(crtc, crtc_state,
+						fb->format->format);
 		} else {
 			can_scale = 0;
 			min_scale = DRM_PLANE_HELPER_NO_SCALING;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (10 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
                   ` (7 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for
primary plane

v2: Rebased (Chandra Konduru)

v3: Rebased (me)

v4: Review comments by Ville addressed
Removed the skl_primary_formats_with_nv12 and
added NV12 case in existing skl_primary_formats

v5: Rebased (me)

v6: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v7: Review comments by Ville addressed
	Restricting the NV12 for BXT and on PIPE A and B
Rebased (me)

v8: Rebased (me)
Modified restricting the NV12 support for both BXT and KBL.

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 26 ++++++++++++++++++++++++--
 1 file changed, 24 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 6efe9aa..88bc750 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -106,6 +106,22 @@ static const uint64_t skl_format_modifiers_ccs[] = {
 	DRM_FORMAT_MOD_INVALID
 };
 
+static const uint32_t nv12_primary_formats[] = {
+	DRM_FORMAT_C8,
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_XRGB2101010,
+	DRM_FORMAT_XBGR2101010,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 /* Cursor formats */
 static const uint32_t intel_cursor_formats[] = {
 	DRM_FORMAT_ARGB8888,
@@ -13180,8 +13196,14 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
 		primary->disable_plane = skl_disable_plane;
 		primary->get_hw_state = skl_plane_get_hw_state;
 	} else if (INTEL_GEN(dev_priv) >= 9) {
-		intel_primary_formats = skl_primary_formats;
-		num_formats = ARRAY_SIZE(skl_primary_formats);
+		if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+			((pipe == PIPE_A || pipe == PIPE_B))) {
+			intel_primary_formats = nv12_primary_formats;
+			num_formats = ARRAY_SIZE(nv12_primary_formats);
+		} else {
+			intel_primary_formats = skl_primary_formats;
+			num_formats = ARRAY_SIZE(skl_primary_formats);
+		}
 		if (pipe < PIPE_C)
 			modifiers = skl_format_modifiers_ccs;
 		else
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (11 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
                   ` (6 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to format_is_yuv() function
for sprite planes.

v2:
-Use intel_ prefix for format_is_yuv (Ville)

v3: Rebased (me)

v4: Rebased and addressed review comments from Clinton A Taylor.
"static function in intel_sprite.c is not available
to the primary plane functions".
Changed commit message - function modified for
sprite planes.

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.

v6: Rebased (me)

v7: Rebased (me)

v8: Rebased (me)

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index dd485f5..58f56de 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -42,13 +42,14 @@
 #include "i915_drv.h"
 
 static bool
-format_is_yuv(uint32_t format)
+intel_format_is_yuv(uint32_t format)
 {
 	switch (format) {
 	case DRM_FORMAT_YUYV:
 	case DRM_FORMAT_UYVY:
 	case DRM_FORMAT_VYUY:
 	case DRM_FORMAT_YVYU:
+	case DRM_FORMAT_NV12:
 		return true;
 	default:
 		return false;
@@ -352,7 +353,7 @@ chv_update_csc(struct intel_plane *plane, uint32_t format)
 	enum plane_id plane_id = plane->id;
 
 	/* Seems RGB data bypasses the CSC always */
-	if (!format_is_yuv(format))
+	if (!intel_format_is_yuv(format))
 		return;
 
 	/*
@@ -974,7 +975,7 @@ intel_check_sprite_plane(struct intel_plane *plane,
 		src_y = src->y1 >> 16;
 		src_h = drm_rect_height(src) >> 16;
 
-		if (format_is_yuv(fb->format->format)) {
+		if (intel_format_is_yuv(fb->format->format)) {
 			src_x &= ~1;
 			src_w &= ~1;
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (12 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
                   ` (5 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 to list of supported formats for sprite plane.

v2: Rebased (me)

v3: Review comments by Ville addressed
- Removed skl_plane_formats_with_nv12 and added
NV12 case in existing skl_plane_formats
- Added the 10bpc RGB formats

v4: Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Removed 10bit RGB formats added previously with NV12 series

v5: Missed the Tested-by/Reviewed-by in the previous series
Adding the same to commit message in this version.
Addressed review comments from Clinton A Taylor
"Why are we adding 10 bit RGB formats with the NV12 series patches?
Trying to set XR30 or AB30 results in error returned even though
the modes are advertised for the planes"
- Previous version has 10bit RGB format removed from VLV formats
by mistake. Fixing that in this version.
Removed 10bit RGB formats added previously with NV12 series
for SKL.

v6: Addressed review comments by Ville
Restricting the NV12 to BXT and PIPE A and B

v7: Rebased (me)

v8: Rebased (me)
Restricting NV12 changes to BXT and KBL
Restricting NV12 changes for plane 0 (overlay)

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_sprite.c | 24 +++++++++++++++++++++---
 1 file changed, 21 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 09732ae..1d35a18 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1279,6 +1279,19 @@ static const struct drm_plane_funcs intel_sprite_plane_funcs = {
         .format_mod_supported = intel_sprite_plane_format_mod_supported,
 };
 
+static uint32_t nv12_plane_formats[] = {
+	DRM_FORMAT_RGB565,
+	DRM_FORMAT_ABGR8888,
+	DRM_FORMAT_ARGB8888,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_XRGB8888,
+	DRM_FORMAT_YUYV,
+	DRM_FORMAT_YVYU,
+	DRM_FORMAT_UYVY,
+	DRM_FORMAT_VYUY,
+	DRM_FORMAT_NV12,
+};
+
 struct intel_plane *
 intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 			  enum pipe pipe, int plane)
@@ -1323,9 +1336,14 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
 		intel_plane->update_plane = skl_update_plane;
 		intel_plane->disable_plane = skl_disable_plane;
 		intel_plane->get_hw_state = skl_plane_get_hw_state;
-
-		plane_formats = skl_plane_formats;
-		num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		if ((IS_BROXTON(dev_priv) || IS_KABYLAKE(dev_priv)) &&
+			(pipe == PIPE_A || pipe == PIPE_B) && plane == 0) {
+			plane_formats = nv12_plane_formats;
+			num_plane_formats = ARRAY_SIZE(nv12_plane_formats);
+		} else {
+			plane_formats = skl_plane_formats;
+			num_plane_formats = ARRAY_SIZE(skl_plane_formats);
+		}
 		modifiers = skl_plane_format_modifiers;
 	} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 		intel_plane->can_scale = false;
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (13 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
@ 2018-01-15  3:18 ` Vidya Srinivas
  2018-01-18 14:21   ` Maarten Lankhorst
                     ` (2 more replies)
  2018-01-15  3:49 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev5) Patchwork
                   ` (4 subsequent siblings)
  19 siblings, 3 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-15  3:18 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 88bc750..db42448 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_NV12:
+		if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+		      drm_get_format_name(mode_cmd->pixel_format,
+				&format_name));
+			goto err;
+		}
+		break;
 	default:
 		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* ✓ Fi.CI.BAT: success for Adding NV12 support (rev5)
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (14 preceding siblings ...)
  2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
@ 2018-01-15  3:49 ` Patchwork
  2018-01-15  4:55 ` ✓ Fi.CI.IGT: " Patchwork
                   ` (3 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2018-01-15  3:49 UTC (permalink / raw)
  To: Vidya Srinivas; +Cc: intel-gfx

== Series Details ==

Series: Adding NV12 support (rev5)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

Series 28103v5 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/5/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-warn -> PASS       (fi-elk-e7500) fdo#103989 +1

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:423s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:422s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:484s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:281s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:464s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:464s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:276s
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:391s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:399s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:416s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:450s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:415s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:586s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:527s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:396s
fi-bxt-dsi failed to collect. IGT log at Patchwork_7663/fi-bxt-dsi/igt.log
fi-bxt-j4205 failed to connect after reboot
fi-cfl-s2 failed to collect. IGT log at Patchwork_7663/fi-cfl-s2/igt.log
fi-glk-1 failed to collect. IGT log at Patchwork_7663/fi-glk-1/igt.log
fi-kbl-7560u failed to collect. IGT log at Patchwork_7663/fi-kbl-7560u/igt.log
fi-kbl-7567u failed to collect. IGT log at Patchwork_7663/fi-kbl-7567u/igt.log
fi-kbl-r failed to collect. IGT log at Patchwork_7663/fi-kbl-r/igt.log
fi-skl-6260u failed to collect. IGT log at Patchwork_7663/fi-skl-6260u/igt.log
fi-skl-6700hq failed to connect after reboot
fi-skl-6700k2 failed to collect. IGT log at Patchwork_7663/fi-skl-6700k2/igt.log
fi-skl-6770hq failed to collect. IGT log at Patchwork_7663/fi-skl-6770hq/igt.log

53240c7f68af57b5b470158d6cafe5eed4ed9743 drm-tip: 2018y-01m-14d-16h-38m-35s UTC integration manifest
c55d5d09d833 drm/i915: Add NV12 support to intel_framebuffer_init
4fda17afbf80 drm/i915: Add NV12 as supported format for sprite plane
3598957b5900 drm/i915: Add NV12 as supported format for primary plane
d82acc481065 drm/i915: Upscale scaler max scale for NV12
74cbaae3449c drm/i915: Update format_is_yuv() to include NV12
24a7bcb42cfd drm/i915: Set scaler mode for NV12
6dd4969a56de drm/i915/skl: split skl_compute_ddb function
4720d5e7c1fc drm/i915/skl+: nv12 workaround disable WM level 1-7
8f5a1d69ccc3 drm/i915/skl+: make sure higher latency level has higher wm value
9dabaa3e5bc3 drm/i915/skl+: pass skl_wm_level struct to wm compute func
bddec573e7ca drm/i915/skl+: NV12 related changes for WM
3a630e91d4a0 drm/i915/skl+: support verification of DDB HW state for NV12
cff341c9a554 drm/i915/skl+: add NV12 in skl_format_to_fourcc
ca8aa855fd41 drm/i915/skl+: refactor WM calculation for NV12
916fd6344a86 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7663/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* ✓ Fi.CI.IGT: success for Adding NV12 support (rev5)
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (15 preceding siblings ...)
  2018-01-15  3:49 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev5) Patchwork
@ 2018-01-15  4:55 ` Patchwork
  2018-01-15  8:47 ` ✓ Fi.CI.BAT: " Patchwork
                   ` (2 subsequent siblings)
  19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2018-01-15  4:55 UTC (permalink / raw)
  To: Vidya Srinivas; +Cc: intel-gfx

== Series Details ==

Series: Adding NV12 support (rev5)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

Test kms_flip:
        Subgroup flip-vs-absolute-wf_vblank-interruptible:
                pass       -> FAIL       (shard-snb) fdo#100368
        Subgroup vblank-vs-modeset-suspend:
                pass       -> SKIP       (shard-snb) fdo#102365
        Subgroup dpms-off-confusion-interruptible:
                incomplete -> PASS       (shard-hsw)
Test kms_cursor_crc:
        Subgroup cursor-64x64-suspend:
                incomplete -> PASS       (shard-hsw) fdo#103540 +1

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540

shard-hsw        total:2713 pass:1537 dwarn:1   dfail:0   fail:11  skip:1164 time:9100s
shard-snb        total:2713 pass:1309 dwarn:1   dfail:0   fail:11  skip:1392 time:7823s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7663/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* ✓ Fi.CI.BAT: success for Adding NV12 support (rev5)
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (16 preceding siblings ...)
  2018-01-15  4:55 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-01-15  8:47 ` Patchwork
  2018-01-15 10:39   ` Saarinen, Jani
  2018-01-15  9:44 ` ✓ Fi.CI.IGT: " Patchwork
  2018-01-15 12:35 ` ✗ Fi.CI.BAT: failure " Patchwork
  19 siblings, 1 reply; 33+ messages in thread
From: Patchwork @ 2018-01-15  8:47 UTC (permalink / raw)
  To: Vidya Srinivas; +Cc: intel-gfx

== Series Details ==

Series: Adding NV12 support (rev5)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

Series 28103v5 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/5/mbox/

Test debugfs_test:
        Subgroup read_all_entries:
                dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989
Test gem_ringfill:
        Subgroup basic-default:
                skip       -> PASS       (fi-bsw-n3050)

fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:421s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:428s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:371s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:484s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:459s
fi-elk-e7500     total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45 
fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:390s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:401s
fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:417s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:449s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:579s
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:522s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:397s
fi-bxt-dsi failed to collect. IGT log at Patchwork_7664/fi-bxt-dsi/igt.log
fi-bxt-j4205 failed to connect after reboot
fi-cfl-s2 failed to collect. IGT log at Patchwork_7664/fi-cfl-s2/igt.log
fi-gdg-551 failed to collect. IGT log at Patchwork_7664/fi-gdg-551/igt.log
fi-glk-1 failed to collect. IGT log at Patchwork_7664/fi-glk-1/igt.log
fi-glk-dsi failed to collect. IGT log at Patchwork_7664/fi-glk-dsi/igt.log
fi-kbl-7500u failed to collect. IGT log at Patchwork_7664/fi-kbl-7500u/igt.log
fi-kbl-7560u failed to collect. IGT log at Patchwork_7664/fi-kbl-7560u/igt.log
fi-kbl-7567u failed to collect. IGT log at Patchwork_7664/fi-kbl-7567u/igt.log
fi-kbl-r failed to collect. IGT log at Patchwork_7664/fi-kbl-r/igt.log
fi-skl-6260u failed to collect. IGT log at Patchwork_7664/fi-skl-6260u/igt.log
fi-skl-6600u failed to collect. IGT log at Patchwork_7664/fi-skl-6600u/igt.log
fi-skl-6700hq failed to collect. IGT log at Patchwork_7664/fi-skl-6700hq/igt.log
fi-skl-6700k2 failed to collect. IGT log at Patchwork_7664/fi-skl-6700k2/igt.log
fi-skl-6770hq failed to collect. IGT log at Patchwork_7664/fi-skl-6770hq/igt.log
fi-skl-gvtdvm failed to collect. IGT log at Patchwork_7664/fi-skl-gvtdvm/igt.log

e96cbac0c1751d045065a49bf20ea134739e2dbb drm-tip: 2018y-01m-15d-05h-55m-36s UTC integration manifest
d19f9064681f drm/i915: Add NV12 support to intel_framebuffer_init
420b315f2392 drm/i915: Add NV12 as supported format for sprite plane
4f54f455147b drm/i915: Add NV12 as supported format for primary plane
e521e0b5b531 drm/i915: Upscale scaler max scale for NV12
e8d508d50d81 drm/i915: Update format_is_yuv() to include NV12
a449444b4453 drm/i915: Set scaler mode for NV12
2c6f947a9b2e drm/i915/skl: split skl_compute_ddb function
21c70676d051 drm/i915/skl+: nv12 workaround disable WM level 1-7
855807a0e29b drm/i915/skl+: make sure higher latency level has higher wm value
f6c1e1570324 drm/i915/skl+: pass skl_wm_level struct to wm compute func
e7d0a3539737 drm/i915/skl+: NV12 related changes for WM
411196b713cb drm/i915/skl+: support verification of DDB HW state for NV12
d3531892bd0a drm/i915/skl+: add NV12 in skl_format_to_fourcc
e1790b4eb0a4 drm/i915/skl+: refactor WM calculation for NV12
21ece85a2cb6 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7664/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* ✓ Fi.CI.IGT: success for Adding NV12 support (rev5)
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (17 preceding siblings ...)
  2018-01-15  8:47 ` ✓ Fi.CI.BAT: " Patchwork
@ 2018-01-15  9:44 ` Patchwork
  2018-01-15 12:35 ` ✗ Fi.CI.BAT: failure " Patchwork
  19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2018-01-15  9:44 UTC (permalink / raw)
  To: Vidya Srinivas; +Cc: intel-gfx

== Series Details ==

Series: Adding NV12 support (rev5)
URL   : https://patchwork.freedesktop.org/series/28103/
State : success

== Summary ==

Test gem_tiled_swapping:
        Subgroup non-threaded:
                incomplete -> PASS       (shard-hsw) fdo#104218 +1
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-a:
                pass       -> SKIP       (shard-hsw) fdo#103375 +1
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-offscren-pri-shrfb-draw-blt:
                fail       -> PASS       (shard-snb) fdo#101623

fdo#104218 https://bugs.freedesktop.org/show_bug.cgi?id=104218
fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
fdo#101623 https://bugs.freedesktop.org/show_bug.cgi?id=101623

shard-hsw        total:2698 pass:1528 dwarn:1   dfail:0   fail:9   skip:1159 time:8797s
shard-snb        total:2713 pass:1311 dwarn:1   dfail:0   fail:10  skip:1391 time:7897s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7664/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: ✓ Fi.CI.BAT: success for Adding NV12 support (rev5)
  2018-01-15  8:47 ` ✓ Fi.CI.BAT: " Patchwork
@ 2018-01-15 10:39   ` Saarinen, Jani
  0 siblings, 0 replies; 33+ messages in thread
From: Saarinen, Jani @ 2018-01-15 10:39 UTC (permalink / raw)
  To: intel-gfx, Srinivas, Vidya

Hi. 
> -----Original Message-----
> From: Intel-gfx [mailto:intel-gfx-bounces@lists.freedesktop.org] On Behalf
> Of Patchwork
> Sent: maanantai 15. tammikuuta 2018 10.47
> To: Srinivas, Vidya <vidya.srinivas@intel.com>
> Cc: intel-gfx@lists.freedesktop.org
> Subject: [Intel-gfx] ✓ Fi.CI.BAT: success for Adding NV12 support (rev5)
> 
> == Series Details ==
> 
> Series: Adding NV12 support (rev5)
> URL   : https://patchwork.freedesktop.org/series/28103/
> State : success
> 
> == Summary ==
> 
> Series 28103v5 Adding NV12 support
> https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/5/mbox/
> 
> Test debugfs_test:
>         Subgroup read_all_entries:
>                 dmesg-warn -> DMESG-FAIL (fi-elk-e7500) fdo#103989 Test
> gem_ringfill:
>         Subgroup basic-default:
>                 skip       -> PASS       (fi-bsw-n3050)
> 
> fdo#103989 https://bugs.freedesktop.org/show_bug.cgi?id=103989
> 
> fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21
> time:421s
> fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24
> time:428s
> fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64
> time:371s
> fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46
> time:484s
> fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105
> time:280s
> fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:468s
> fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39
> time:459s
> fi-elk-e7500     total:224  pass:168  dwarn:9   dfail:1   fail:0   skip:45
> fi-hsw-4770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27
> time:390s
> fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27
> time:401s
> fi-ilk-650       total:288  pass:228  dwarn:0   dfail:0   fail:0   skip:60  time:417s
> fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29
> time:449s
> fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:412s
> fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65
> time:579s
> fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40
> time:522s
> fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40
> time:397s
> fi-bxt-dsi failed to collect. IGT log at Patchwork_7664/fi-bxt-dsi/igt.log
> fi-bxt-j4205 failed to connect after reboot
> fi-cfl-s2 failed to collect. IGT log at Patchwork_7664/fi-cfl-s2/igt.log
> fi-gdg-551 failed to collect. IGT log at Patchwork_7664/fi-gdg-551/igt.log
> fi-glk-1 failed to collect. IGT log at Patchwork_7664/fi-glk-1/igt.log fi-glk-dsi
> failed to collect. IGT log at Patchwork_7664/fi-glk-dsi/igt.log fi-kbl-7500u
> failed to collect. IGT log at Patchwork_7664/fi-kbl-7500u/igt.log
> fi-kbl-7560u failed to collect. IGT log at Patchwork_7664/fi-kbl-7560u/igt.log
> fi-kbl-7567u failed to collect. IGT log at Patchwork_7664/fi-kbl-7567u/igt.log
> fi-kbl-r failed to collect. IGT log at Patchwork_7664/fi-kbl-r/igt.log fi-skl-
> 6260u failed to collect. IGT log at Patchwork_7664/fi-skl-6260u/igt.log
> fi-skl-6600u failed to collect. IGT log at Patchwork_7664/fi-skl-6600u/igt.log
> fi-skl-6700hq failed to collect. IGT log at Patchwork_7664/fi-skl-
> 6700hq/igt.log
> fi-skl-6700k2 failed to collect. IGT log at Patchwork_7664/fi-skl-
> 6700k2/igt.log
> fi-skl-6770hq failed to collect. IGT log at Patchwork_7664/fi-skl-
> 6770hq/igt.log
> fi-skl-gvtdvm failed to collect. IGT log at Patchwork_7664/fi-skl-
> gvtdvm/igt.log

I see this very alarming that all gen9+ systems eg. has issues booting up. 
This also now 2nd time in a row. So not really considering this as success.
 
> e96cbac0c1751d045065a49bf20ea134739e2dbb drm-tip: 2018y-01m-15d-
> 05h-55m-36s UTC integration manifest d19f9064681f drm/i915: Add NV12
> support to intel_framebuffer_init
> 420b315f2392 drm/i915: Add NV12 as supported format for sprite plane
> 4f54f455147b drm/i915: Add NV12 as supported format for primary plane
> e521e0b5b531 drm/i915: Upscale scaler max scale for NV12
> e8d508d50d81 drm/i915: Update format_is_yuv() to include NV12
> a449444b4453 drm/i915: Set scaler mode for NV12 2c6f947a9b2e
> drm/i915/skl: split skl_compute_ddb function
> 21c70676d051 drm/i915/skl+: nv12 workaround disable WM level 1-7
> 855807a0e29b drm/i915/skl+: make sure higher latency level has higher wm
> value
> f6c1e1570324 drm/i915/skl+: pass skl_wm_level struct to wm compute func
> e7d0a3539737 drm/i915/skl+: NV12 related changes for WM 411196b713cb
> drm/i915/skl+: support verification of DDB HW state for NV12
> d3531892bd0a drm/i915/skl+: add NV12 in skl_format_to_fourcc
> e1790b4eb0a4 drm/i915/skl+: refactor WM calculation for NV12
> 21ece85a2cb6 drm/i915/skl+: rename skl_wm_values struct to
> skl_ddb_values
> 
> == Logs ==
> 
> For more details see: https://intel-gfx-ci.01.org/tree/drm-
> tip/Patchwork_7664/issues.html


Jani Saarinen
Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo


_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* ✗ Fi.CI.BAT: failure for Adding NV12 support (rev5)
  2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
                   ` (18 preceding siblings ...)
  2018-01-15  9:44 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-01-15 12:35 ` Patchwork
  19 siblings, 0 replies; 33+ messages in thread
From: Patchwork @ 2018-01-15 12:35 UTC (permalink / raw)
  To: Vidya Srinivas; +Cc: intel-gfx

== Series Details ==

Series: Adding NV12 support (rev5)
URL   : https://patchwork.freedesktop.org/series/28103/
State : failure

== Summary ==

Series 28103v5 Adding NV12 support
https://patchwork.freedesktop.org/api/1.0/series/28103/revisions/5/mbox/

Test core_auth:
        Subgroup basic-auth:
                pass       -> INCOMPLETE (fi-skl-6700hq)
                pass       -> INCOMPLETE (fi-kbl-7500u)
Test debugfs_test:
        Subgroup read_all_entries:
                incomplete -> PASS       (fi-snb-2520m) fdo#103713

fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713

fi-bdw-5557u     total:288  pass:267  dwarn:0   dfail:0   fail:0   skip:21  time:418s
fi-bdw-gvtdvm    total:288  pass:264  dwarn:0   dfail:0   fail:0   skip:24  time:425s
fi-blb-e6850     total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:372s
fi-bsw-n3050     total:288  pass:242  dwarn:0   dfail:0   fail:0   skip:46  time:487s
fi-bwr-2160      total:288  pass:183  dwarn:0   dfail:0   fail:0   skip:105 time:280s
fi-byt-j1900     total:288  pass:253  dwarn:0   dfail:0   fail:0   skip:35  time:470s
fi-byt-n2820     total:288  pass:249  dwarn:0   dfail:0   fail:0   skip:39  time:466s
fi-elk-e7500     total:224  pass:168  dwarn:10  dfail:0   fail:0   skip:45 
fi-gdg-551       total:288  pass:179  dwarn:0   dfail:0   fail:1   skip:108 time:271s
fi-hsw-4770r     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:401s
fi-ivb-3520m     total:288  pass:259  dwarn:0   dfail:0   fail:0   skip:29  time:459s
fi-ivb-3770      total:288  pass:255  dwarn:0   dfail:0   fail:0   skip:33  time:413s
fi-kbl-7500u     total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
fi-pnv-d510      total:288  pass:222  dwarn:1   dfail:0   fail:0   skip:65  time:581s
fi-skl-6700hq    total:1    pass:0    dwarn:0   dfail:0   fail:0   skip:0  
fi-snb-2520m     total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:529s
fi-snb-2600      total:288  pass:248  dwarn:0   dfail:0   fail:0   skip:40  time:400s
fi-bxt-dsi failed to collect. IGT log at Patchwork_7672/fi-bxt-dsi/igt.log
fi-bxt-j4205 failed to connect after reboot
fi-cfl-s2 failed to collect. IGT log at Patchwork_7672/fi-cfl-s2/igt.log
fi-cnl-y2 failed to collect. IGT log at Patchwork_7672/fi-cnl-y2/igt.log
fi-glk-1 failed to collect. IGT log at Patchwork_7672/fi-glk-1/igt.log
fi-glk-dsi failed to collect. IGT log at Patchwork_7672/fi-glk-dsi/igt.log
fi-kbl-7560u failed to collect. IGT log at Patchwork_7672/fi-kbl-7560u/igt.log
fi-kbl-7567u failed to collect. IGT log at Patchwork_7672/fi-kbl-7567u/igt.log
fi-kbl-r failed to collect. IGT log at Patchwork_7672/fi-kbl-r/igt.log
fi-skl-6260u failed to collect. IGT log at Patchwork_7672/fi-skl-6260u/igt.log
fi-skl-6600u failed to collect. IGT log at Patchwork_7672/fi-skl-6600u/igt.log
fi-skl-6700k2 failed to collect. IGT log at Patchwork_7672/fi-skl-6700k2/igt.log
fi-skl-6770hq failed to collect. IGT log at Patchwork_7672/fi-skl-6770hq/igt.log
fi-skl-gvtdvm failed to collect. IGT log at Patchwork_7672/fi-skl-gvtdvm/igt.log

254125b984264731491e1eafbe58bc50e84a032d drm-tip: 2018y-01m-15d-09h-31m-31s UTC integration manifest
27f05af422f7 drm/i915: Add NV12 support to intel_framebuffer_init
e558e7ff13c6 drm/i915: Add NV12 as supported format for sprite plane
0b6028045fd5 drm/i915: Add NV12 as supported format for primary plane
bbbf0943fbfc drm/i915: Upscale scaler max scale for NV12
6063e680c38e drm/i915: Update format_is_yuv() to include NV12
2132b64159d1 drm/i915: Set scaler mode for NV12
41861f10a416 drm/i915/skl: split skl_compute_ddb function
9e0b5f63e088 drm/i915/skl+: nv12 workaround disable WM level 1-7
20e661c2375f drm/i915/skl+: make sure higher latency level has higher wm value
04965e783bba drm/i915/skl+: pass skl_wm_level struct to wm compute func
366ef9c698e5 drm/i915/skl+: NV12 related changes for WM
412b4e9f13d4 drm/i915/skl+: support verification of DDB HW state for NV12
535f80001279 drm/i915/skl+: add NV12 in skl_format_to_fourcc
b151bacc823e drm/i915/skl+: refactor WM calculation for NV12
eabc0f15ba55 drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_7672/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc
  2018-01-15  3:18 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
@ 2018-01-17 11:43   ` Mika Kahola
  0 siblings, 0 replies; 33+ messages in thread
From: Mika Kahola @ 2018-01-17 11:43 UTC (permalink / raw)
  To: Vidya Srinivas, intel-gfx

On Sun, 2018-01-21 at 03:15 +0530, Vidya Srinivas wrote:
> From: Mahesh Kumar <mahesh1.kumar@intel.com>
> 
> Add support of recognizing DRM_FORMAT_NV12 from plane_format
> register value.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 02bf31d..1345796 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2612,6 +2612,8 @@ static int skl_format_to_fourcc(int format,
> bool rgb_order, bool alpha)
>  	switch (format) {
>  	case PLANE_CTL_FORMAT_RGB_565:
>  		return DRM_FORMAT_RGB565;
> +	case PLANE_CTL_FORMAT_NV12:
> +		return DRM_FORMAT_NV12;
>  	default:
>  	case PLANE_CTL_FORMAT_XRGB_8888:
>  		if (rgb_order) {
-- 
Mika Kahola - Intel OTC

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
@ 2018-01-18 14:21   ` Maarten Lankhorst
  2018-01-18 14:49     ` Maarten Lankhorst
  2018-01-29 11:41   ` Maarten Lankhorst
  2018-01-29 17:17   ` Maarten Lankhorst
  2 siblings, 1 reply; 33+ messages in thread
From: Maarten Lankhorst @ 2018-01-18 14:21 UTC (permalink / raw)
  To: Vidya Srinivas, intel-gfx

Op 20-01-18 om 22:45 schreef Vidya Srinivas:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 as supported format
> to intel_framebuffer_init and performs various checks.
>
> v2:
> -Fix an issue in checks added (Chandra Konduru)
>
> v3: rebased (me)
>
> v4: Review comments by Ville addressed
> Added platform check for NV12 in intel_framebuffer_init
> Removed offset checks for NV12 case
>
> v5: Addressed review comments by Clinton A Taylor
> This NV12 support only correctly works on SKL.
> Plane color space conversion is different on GLK and later platforms
> causing the colors to display incorrectly.
> Ville's plane color space property patch series
> in review will fix this issue.
> - Restricted the NV12 case in intel_framebuffer_init to
> SKL and BXT only.
>
> v6: Rebased (me)
>
> v7: Addressed review comments by Ville
> Restricting the NV12 to BXT for now.
>
> v8: Rebased (me)
> Restricting the NV12 changes to BXT and KBL for now.
>
> v9: Rebased (me)
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 88bc750..db42448 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  		break;
> +	case DRM_FORMAT_NV12:
> +		if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +		      drm_get_format_name(mode_cmd->pixel_format,
> +				&format_name));
> +			goto err;
> +		}
> +		break;
I started implementing the IGT side of this but as far as I can tell, the specification will allow you to set different handles for each plane. But intel doesn't support this right now..

Could this assumption be fixed first? There's nothing stopping the drm core or applications from having separate buffer objects, and for blitting it would make sense to have a R8 plane for Y', and a R8G8 plane for Cb'Cr'

Probably needs i915 to compile with something like below, then handling all corner cases..
---
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 39c3bfa74d67..4eeb94fbfdd6 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -186,7 +186,7 @@ enum intel_output_type {
 
 struct intel_framebuffer {
 	struct drm_framebuffer base;
-	struct drm_i915_gem_object *obj;
+	struct drm_i915_gem_object *objs[2];
 	struct intel_rotation_info rot_info;
 
 	/* for each plane in the normal GTT view */
@@ -996,7 +996,7 @@ struct cxsr_latency {
 #define to_intel_framebuffer(x) container_of(x, struct intel_framebuffer, base)
 #define to_intel_plane(x) container_of(x, struct intel_plane, base)
 #define to_intel_plane_state(x) container_of(x, struct intel_plane_state, base)
-#define intel_fb_obj(x) (x ? to_intel_framebuffer(x)->obj : NULL)
+#define intel_fb_obj(x, n) (x ? to_intel_framebuffer(x)->objs[n] : NULL)
 
 struct intel_hdmi {
 	i915_reg_t hdmi_reg;

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-18 14:21   ` Maarten Lankhorst
@ 2018-01-18 14:49     ` Maarten Lankhorst
  0 siblings, 0 replies; 33+ messages in thread
From: Maarten Lankhorst @ 2018-01-18 14:49 UTC (permalink / raw)
  To: Vidya Srinivas, intel-gfx

Op 18-01-18 om 15:21 schreef Maarten Lankhorst:
> Op 20-01-18 om 22:45 schreef Vidya Srinivas:
>> From: Chandra Konduru <chandra.konduru@intel.com>
>>
>> This patch adds NV12 as supported format
>> to intel_framebuffer_init and performs various checks.
>>
>> v2:
>> -Fix an issue in checks added (Chandra Konduru)
>>
>> v3: rebased (me)
>>
>> v4: Review comments by Ville addressed
>> Added platform check for NV12 in intel_framebuffer_init
>> Removed offset checks for NV12 case
>>
>> v5: Addressed review comments by Clinton A Taylor
>> This NV12 support only correctly works on SKL.
>> Plane color space conversion is different on GLK and later platforms
>> causing the colors to display incorrectly.
>> Ville's plane color space property patch series
>> in review will fix this issue.
>> - Restricted the NV12 case in intel_framebuffer_init to
>> SKL and BXT only.
>>
>> v6: Rebased (me)
>>
>> v7: Addressed review comments by Ville
>> Restricting the NV12 to BXT for now.
>>
>> v8: Rebased (me)
>> Restricting the NV12 changes to BXT and KBL for now.
>>
>> v9: Rebased (me)
>>
>> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
>> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
>> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
>> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
>> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
>> ---
>>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>>  1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
>> index 88bc750..db42448 100644
>> --- a/drivers/gpu/drm/i915/intel_display.c
>> +++ b/drivers/gpu/drm/i915/intel_display.c
>> @@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>>  			goto err;
>>  		}
>>  		break;
>> +	case DRM_FORMAT_NV12:
>> +		if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
>> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>> +		      drm_get_format_name(mode_cmd->pixel_format,
>> +				&format_name));
>> +			goto err;
>> +		}
>> +		break;
> I started implementing the IGT side of this but as far as I can tell, the specification will allow you to set different handles for each plane. But intel doesn't support this right now..
>
> Could this assumption be fixed first? There's nothing stopping the drm core or applications from having separate buffer objects, and for blitting it would make sense to have a R8 plane for Y', and a R8G8 plane for Cb'Cr'
>
> Probably needs i915 to compile with something like below, then handling all corner cases..
Never mind, seems this is a hardware limitation that bo for plane2 must be higher mapped than plane1 so having separate bo's won't do much. And there was already a check for handles[i] == handles[0].
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12
  2018-01-15  3:18 ` [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
@ 2018-01-20  0:39   ` kbuild test robot
  0 siblings, 0 replies; 33+ messages in thread
From: kbuild test robot @ 2018-01-20  0:39 UTC (permalink / raw)
  Cc: intel-gfx, kbuild-all, Vidya Srinivas

Hi Mahesh,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on v4.15-rc8 next-20180119]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Vidya-Srinivas/Adding-NV12-support/20180120-064213
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
reproduce:
        # apt-get install sparse
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/i915/intel_pm.c:4794:73: sparse: Using plain integer as NULL pointer

vim +4794 drivers/gpu/drm/i915/intel_pm.c

  4764	
  4765	static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
  4766				       const struct skl_plane_wm *wm,
  4767				       const struct skl_ddb_allocation *ddb,
  4768				       enum plane_id plane_id)
  4769	{
  4770		struct drm_crtc *crtc = &intel_crtc->base;
  4771		struct drm_device *dev = crtc->dev;
  4772		struct drm_i915_private *dev_priv = to_i915(dev);
  4773		int level, max_level = ilk_wm_max_level(dev_priv);
  4774		enum pipe pipe = intel_crtc->pipe;
  4775	
  4776		for (level = 0; level <= max_level; level++) {
  4777			skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
  4778					   &wm->wm[level]);
  4779		}
  4780		skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
  4781				   &wm->trans_wm);
  4782	
  4783		if (wm->is_nv12) {
  4784			skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
  4785						&ddb->uv_plane[pipe][plane_id]);
  4786			skl_ddb_entry_write(dev_priv,
  4787					    PLANE_NV12_BUF_CFG(pipe, plane_id),
  4788					    &ddb->plane[pipe][plane_id]);
  4789		} else {
  4790			skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id),
  4791						&ddb->plane[pipe][plane_id]);
  4792			/* No NV12 buffer allocation for non NV12 pixel formats */
  4793			skl_ddb_entry_write(dev_priv,
> 4794					    PLANE_NV12_BUF_CFG(pipe, plane_id), 0x0);
  4795		}
  4796	}
  4797	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
  2018-01-18 14:21   ` Maarten Lankhorst
@ 2018-01-29 11:41   ` Maarten Lankhorst
  2018-01-30  4:53     ` Srinivas, Vidya
  2018-01-29 17:17   ` Maarten Lankhorst
  2 siblings, 1 reply; 33+ messages in thread
From: Maarten Lankhorst @ 2018-01-29 11:41 UTC (permalink / raw)
  To: Vidya Srinivas, intel-gfx

Op 20-01-18 om 22:45 schreef Vidya Srinivas:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 as supported format
> to intel_framebuffer_init and performs various checks.
>
> v2:
> -Fix an issue in checks added (Chandra Konduru)
>
> v3: rebased (me)
>
> v4: Review comments by Ville addressed
> Added platform check for NV12 in intel_framebuffer_init
> Removed offset checks for NV12 case
>
> v5: Addressed review comments by Clinton A Taylor
> This NV12 support only correctly works on SKL.
> Plane color space conversion is different on GLK and later platforms
> causing the colors to display incorrectly.
> Ville's plane color space property patch series
> in review will fix this issue.
> - Restricted the NV12 case in intel_framebuffer_init to
> SKL and BXT only.
>
> v6: Rebased (me)
>
> v7: Addressed review comments by Ville
> Restricting the NV12 to BXT for now.
>
> v8: Rebased (me)
> Restricting the NV12 changes to BXT and KBL for now.
>
> v9: Rebased (me)
>
> Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 88bc750..db42448 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
>  			goto err;
>  		}
>  		break;
> +	case DRM_FORMAT_NV12:
> +		if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
> +			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> +		      drm_get_format_name(mode_cmd->pixel_format,
> +				&format_name));
> +			goto err;
> +		}
> +		break;
>  	default:
>  		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
>  			      drm_get_format_name(mode_cmd->pixel_format, &format_name));

Hey,

When implementing this for IGT I've noticed a small gap in documentation, which will definitely need clarification somewhere. intel_framebuffer_init is probably good enough since it's specific to how intel works internally..
The Yf tiling mode depends on BPP, is it correct to say that plane 0 has 8 bpp and plane 1 16 bpp for tiling calculations?

What bpp is used?

Are macroblock sizes always the same for Y and UV?

~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
  2018-01-18 14:21   ` Maarten Lankhorst
  2018-01-29 11:41   ` Maarten Lankhorst
@ 2018-01-29 17:17   ` Maarten Lankhorst
  2018-01-30  4:05     ` Srinivas, Vidya
  2 siblings, 1 reply; 33+ messages in thread
From: Maarten Lankhorst @ 2018-01-29 17:17 UTC (permalink / raw)
  To: Vidya Srinivas, intel-gfx

Op 20-01-18 om 22:45 schreef Vidya Srinivas:
> From: Chandra Konduru <chandra.konduru@intel.com>
>
> This patch adds NV12 as supported format
> to intel_framebuffer_init and performs various checks.
>
> v2:
> -Fix an issue in checks added (Chandra Konduru)
>
> v3: rebased (me)
>
> v4: Review comments by Ville addressed
> Added platform check for NV12 in intel_framebuffer_init
> Removed offset checks for NV12 case
>
> v5: Addressed review comments by Clinton A Taylor
> This NV12 support only correctly works on SKL.
> Plane color space conversion is different on GLK and later platforms
> causing the colors to display incorrectly.
> Ville's plane color space property patch series
> in review will fix this issue.
> - Restricted the NV12 case in intel_framebuffer_init to
> SKL and BXT only.
>
> v6: Rebased (me)
>
> v7: Addressed review comments by Ville
> Restricting the NV12 to BXT for now.
>
> v8: Rebased (me)
> Restricting the NV12 changes to BXT and KBL for now.
>
> v9: Rebased (me)
Hey,

Has NV12 been tested at all on skylake with rotation?

y_min_scanlines = 16 for 90°/270° rotation with cpp=1
skl_needs_memory_bw_wa() doubles the scanlines required,
which will trigger the following error quite easily when patching kms_rotation_crc to use NV12:

[   67.049190] [drm:skl_compute_wm_levels [i915]] Requested display configuration exceeds system watermark limitations
[   67.049212] [drm:skl_compute_wm_levels [i915]] [PLANE:28:plane 1A] blocks required = 161/572, lines required = 32/31

If we violate the spec for the workaround, by using 31 lines instead of 32 for 90/270
rotation, the tests work but this needs to be solved first before we can move forward.

~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-29 17:17   ` Maarten Lankhorst
@ 2018-01-30  4:05     ` Srinivas, Vidya
  2018-01-30  6:16       ` Kumar, Mahesh
  0 siblings, 1 reply; 33+ messages in thread
From: Srinivas, Vidya @ 2018-01-30  4:05 UTC (permalink / raw)
  To: Maarten Lankhorst, intel-gfx



> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> Sent: Monday, January 29, 2018 10:47 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add NV12 support to
> intel_framebuffer_init
> 
> Op 20-01-18 om 22:45 schreef Vidya Srinivas:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 as supported format to intel_framebuffer_init and
> > performs various checks.
> >
> > v2:
> > -Fix an issue in checks added (Chandra Konduru)
> >
> > v3: rebased (me)
> >
> > v4: Review comments by Ville addressed Added platform check for NV12
> > in intel_framebuffer_init Removed offset checks for NV12 case
> >
> > v5: Addressed review comments by Clinton A Taylor This NV12 support
> > only correctly works on SKL.
> > Plane color space conversion is different on GLK and later platforms
> > causing the colors to display incorrectly.
> > Ville's plane color space property patch series in review will fix
> > this issue.
> > - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT
> > only.
> >
> > v6: Rebased (me)
> >
> > v7: Addressed review comments by Ville Restricting the NV12 to BXT for
> > now.
> >
> > v8: Rebased (me)
> > Restricting the NV12 changes to BXT and KBL for now.
> >
> > v9: Rebased (me)
> Hey,
> 
> Has NV12 been tested at all on skylake with rotation?
> 
> y_min_scanlines = 16 for 90°/270° rotation with cpp=1
> skl_needs_memory_bw_wa() doubles the scanlines required, which will
> trigger the following error quite easily when patching kms_rotation_crc to
> use NV12:
> 
> [   67.049190] [drm:skl_compute_wm_levels [i915]] Requested display
> configuration exceeds system watermark limitations [   67.049212]
> [drm:skl_compute_wm_levels [i915]] [PLANE:28:plane 1A] blocks required =
> 161/572, lines required = 32/31
> 
> If we violate the spec for the workaround, by using 31 lines instead of 32 for
> 90/270 rotation, the tests work but this needs to be solved first before we
> can move forward.
> 
We came across many such scenarios during NV12 testing on BXT. During downscaling,
the "Max supported pixel clock with scaling exceeded" is seen if the user layer tries to downscale
much. And rotation, as you mentioned we have seen such messages. We discussed the same during the meeting
long back and mentioned that if we remove the limitations, it works. But as per discussion, if limitations are removed, it may work,
but there may be certain conditions where it may not work. Hence we concluded that some such cases are expected not to work.
However, I will discuss once again with Mahesh Kumar (CC) who works on WM implementation to re-confirm on the same.

> ~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-29 11:41   ` Maarten Lankhorst
@ 2018-01-30  4:53     ` Srinivas, Vidya
  0 siblings, 0 replies; 33+ messages in thread
From: Srinivas, Vidya @ 2018-01-30  4:53 UTC (permalink / raw)
  To: Maarten Lankhorst, intel-gfx



> -----Original Message-----
> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
> Sent: Monday, January 29, 2018 5:12 PM
> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
> gfx@lists.freedesktop.org
> Subject: Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add NV12 support to
> intel_framebuffer_init
> 
> Op 20-01-18 om 22:45 schreef Vidya Srinivas:
> > From: Chandra Konduru <chandra.konduru@intel.com>
> >
> > This patch adds NV12 as supported format to intel_framebuffer_init and
> > performs various checks.
> >
> > v2:
> > -Fix an issue in checks added (Chandra Konduru)
> >
> > v3: rebased (me)
> >
> > v4: Review comments by Ville addressed Added platform check for NV12
> > in intel_framebuffer_init Removed offset checks for NV12 case
> >
> > v5: Addressed review comments by Clinton A Taylor This NV12 support
> > only correctly works on SKL.
> > Plane color space conversion is different on GLK and later platforms
> > causing the colors to display incorrectly.
> > Ville's plane color space property patch series in review will fix
> > this issue.
> > - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT
> > only.
> >
> > v6: Rebased (me)
> >
> > v7: Addressed review comments by Ville Restricting the NV12 to BXT for
> > now.
> >
> > v8: Rebased (me)
> > Restricting the NV12 changes to BXT and KBL for now.
> >
> > v9: Rebased (me)
> >
> > Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
> > Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
> > Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
> > Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 88bc750..db42448 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct
> intel_framebuffer *intel_fb,
> >  			goto err;
> >  		}
> >  		break;
> > +	case DRM_FORMAT_NV12:
> > +		if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
> > +			DRM_DEBUG_KMS("unsupported pixel format:
> %s\n",
> > +		      drm_get_format_name(mode_cmd->pixel_format,
> > +				&format_name));
> > +			goto err;
> > +		}
> > +		break;
> >  	default:
> >  		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
> >  			      drm_get_format_name(mode_cmd-
> >pixel_format, &format_name));
> 
> Hey,
> 
> When implementing this for IGT I've noticed a small gap in documentation,
> which will definitely need clarification somewhere. intel_framebuffer_init is
> probably good enough since it's specific to how intel works internally..
> The Yf tiling mode depends on BPP, is it correct to say that plane 0 has 8 bpp
> and plane 1 16 bpp for tiling calculations?
> 
> What bpp is used?
> 
> Are macroblock sizes always the same for Y and UV?

I think, under display buffer programming it is mentioned that: For NV12 Bpp is 1 for Y and 2 for UV.
This is for all SKL+, it says.
> 
> ~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-30  4:05     ` Srinivas, Vidya
@ 2018-01-30  6:16       ` Kumar, Mahesh
  2018-01-30  9:50         ` Maarten Lankhorst
  0 siblings, 1 reply; 33+ messages in thread
From: Kumar, Mahesh @ 2018-01-30  6:16 UTC (permalink / raw)
  To: Srinivas, Vidya, Maarten Lankhorst, intel-gfx

Hi,

On 1/30/2018 9:35 AM, Srinivas, Vidya wrote:
>
>> -----Original Message-----
>> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>> Sent: Monday, January 29, 2018 10:47 PM
>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
>> gfx@lists.freedesktop.org
>> Subject: Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add NV12 support to
>> intel_framebuffer_init
>>
>> Op 20-01-18 om 22:45 schreef Vidya Srinivas:
>>> From: Chandra Konduru <chandra.konduru@intel.com>
>>>
>>> This patch adds NV12 as supported format to intel_framebuffer_init and
>>> performs various checks.
>>>
>>> v2:
>>> -Fix an issue in checks added (Chandra Konduru)
>>>
>>> v3: rebased (me)
>>>
>>> v4: Review comments by Ville addressed Added platform check for NV12
>>> in intel_framebuffer_init Removed offset checks for NV12 case
>>>
>>> v5: Addressed review comments by Clinton A Taylor This NV12 support
>>> only correctly works on SKL.
>>> Plane color space conversion is different on GLK and later platforms
>>> causing the colors to display incorrectly.
>>> Ville's plane color space property patch series in review will fix
>>> this issue.
>>> - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT
>>> only.
>>>
>>> v6: Rebased (me)
>>>
>>> v7: Addressed review comments by Ville Restricting the NV12 to BXT for
>>> now.
>>>
>>> v8: Rebased (me)
>>> Restricting the NV12 changes to BXT and KBL for now.
>>>
>>> v9: Rebased (me)
>> Hey,
>>
>> Has NV12 been tested at all on skylake with rotation?
>>
>> y_min_scanlines = 16 for 90°/270° rotation with cpp=1
>> skl_needs_memory_bw_wa() doubles the scanlines required, which will
>> trigger the following error quite easily when patching kms_rotation_crc to
>> use NV12:
>>
>> [   67.049190] [drm:skl_compute_wm_levels [i915]] Requested display
>> configuration exceeds system watermark limitations [   67.049212]
>> [drm:skl_compute_wm_levels [i915]] [PLANE:28:plane 1A] blocks required =
>> 161/572, lines required = 32/31
>>
>> If we violate the spec for the workaround, by using 31 lines instead of 32 for
>> 90/270 rotation, the tests work but this needs to be solved first before we
>> can move forward.
We are hitting this issue due to memory_bw_wa (this is applicable for 
GEN-9 only) & we are applying WA irrespective of it's required or not.
I had plan to apply this WA based on our discussion, but it never 
materialized :(
https://www.spinics.net/lists/intel-gfx/msg124872.html

> We came across many such scenarios during NV12 testing on BXT. During downscaling,
> the "Max supported pixel clock with scaling exceeded" is seen if the user layer tries to downscale
> much. And rotation, as you mentioned we have seen such messages. We discussed the same during the meeting
> long back and mentioned that if we remove the limitations, it works. But as per discussion, if limitations are removed, it may work,
> but there may be certain conditions where it may not work. Hence we concluded that some such cases are expected not to work.
Either we can conclude that as a limitation (as expected behavior) OR we 
can enable WA only when it's required (as discussed, assuming all the 
planes are enabled with max supported scaling to avoid taking mutex in 
each flip). what you say?

-Mahesh
> However, I will discuss once again with Mahesh Kumar (CC) who works on WM implementation to re-confirm on the same.
>
>> ~Maarten

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 33+ messages in thread
* Re: [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-30  6:16       ` Kumar, Mahesh
@ 2018-01-30  9:50         ` Maarten Lankhorst
  0 siblings, 0 replies; 33+ messages in thread
From: Maarten Lankhorst @ 2018-01-30  9:50 UTC (permalink / raw)
  To: Kumar, Mahesh, Srinivas, Vidya, intel-gfx

Op 30-01-18 om 07:16 schreef Kumar, Mahesh:
> Hi,
>
> On 1/30/2018 9:35 AM, Srinivas, Vidya wrote:
>>
>>> -----Original Message-----
>>> From: Maarten Lankhorst [mailto:maarten.lankhorst@linux.intel.com]
>>> Sent: Monday, January 29, 2018 10:47 PM
>>> To: Srinivas, Vidya <vidya.srinivas@intel.com>; intel-
>>> gfx@lists.freedesktop.org
>>> Subject: Re: [Intel-gfx] [PATCH 15/15] drm/i915: Add NV12 support to
>>> intel_framebuffer_init
>>>
>>> Op 20-01-18 om 22:45 schreef Vidya Srinivas:
>>>> From: Chandra Konduru <chandra.konduru@intel.com>
>>>>
>>>> This patch adds NV12 as supported format to intel_framebuffer_init and
>>>> performs various checks.
>>>>
>>>> v2:
>>>> -Fix an issue in checks added (Chandra Konduru)
>>>>
>>>> v3: rebased (me)
>>>>
>>>> v4: Review comments by Ville addressed Added platform check for NV12
>>>> in intel_framebuffer_init Removed offset checks for NV12 case
>>>>
>>>> v5: Addressed review comments by Clinton A Taylor This NV12 support
>>>> only correctly works on SKL.
>>>> Plane color space conversion is different on GLK and later platforms
>>>> causing the colors to display incorrectly.
>>>> Ville's plane color space property patch series in review will fix
>>>> this issue.
>>>> - Restricted the NV12 case in intel_framebuffer_init to SKL and BXT
>>>> only.
>>>>
>>>> v6: Rebased (me)
>>>>
>>>> v7: Addressed review comments by Ville Restricting the NV12 to BXT for
>>>> now.
>>>>
>>>> v8: Rebased (me)
>>>> Restricting the NV12 changes to BXT and KBL for now.
>>>>
>>>> v9: Rebased (me)
>>> Hey,
>>>
>>> Has NV12 been tested at all on skylake with rotation?
>>>
>>> y_min_scanlines = 16 for 90°/270° rotation with cpp=1
>>> skl_needs_memory_bw_wa() doubles the scanlines required, which will
>>> trigger the following error quite easily when patching kms_rotation_crc to
>>> use NV12:
>>>
>>> [   67.049190] [drm:skl_compute_wm_levels [i915]] Requested display
>>> configuration exceeds system watermark limitations [   67.049212]
>>> [drm:skl_compute_wm_levels [i915]] [PLANE:28:plane 1A] blocks required =
>>> 161/572, lines required = 32/31
>>>
>>> If we violate the spec for the workaround, by using 31 lines instead of 32 for
>>> 90/270 rotation, the tests work but this needs to be solved first before we
>>> can move forward.
> We are hitting this issue due to memory_bw_wa (this is applicable for GEN-9 only) & we are applying WA irrespective of it's required or not.
> I had plan to apply this WA based on our discussion, but it never materialized :(
> https://www.spinics.net/lists/intel-gfx/msg124872.html
>
>> We came across many such scenarios during NV12 testing on BXT. During downscaling,
>> the "Max supported pixel clock with scaling exceeded" is seen if the user layer tries to downscale
>> much. And rotation, as you mentioned we have seen such messages. We discussed the same during the meeting
>> long back and mentioned that if we remove the limitations, it works. But as per discussion, if limitations are removed, it may work,
>> but there may be certain conditions where it may not work. Hence we concluded that some such cases are expected not to work.
> Either we can conclude that as a limitation (as expected behavior) OR we can enable WA only when it's required (as discussed, assuming all the planes are enabled with max supported scaling to avoid taking mutex in each flip). what you say? 

I think both. We should enable the wa only when required, but also make sure we have sufficient
testing that we know whether the below patch would break. It's still almost doubling, 1.9375x
the original values for 8 bit planes, but this falls within the wm limitation checks.
---
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 26132fa6ebce..23623d1a8569 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4693,7 +4693,9 @@ skl_compute_plane_wm_params(const struct drm_i915_private *dev_priv,
 		wp->y_min_scanlines = 4;
 	}
 
-	if (apply_memory_bw_wa)
+	if (apply_memory_bw_wa && wp->y_min_scanlines == 16)
+		wp->y_min_scanlines = 31;
+	else if (apply_memory_bw_wa)
 		wp->y_min_scanlines *= 2;
 
 	wp->plane_bytes_per_line = wp->width * wp->cpp;

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
* [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init
  2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
@ 2018-01-04 10:44 ` Vidya Srinivas
  0 siblings, 0 replies; 33+ messages in thread
From: Vidya Srinivas @ 2018-01-04 10:44 UTC (permalink / raw)
  To: intel-gfx; +Cc: Vidya Srinivas

From: Chandra Konduru <chandra.konduru@intel.com>

This patch adds NV12 as supported format
to intel_framebuffer_init and performs various checks.

v2:
-Fix an issue in checks added (Chandra Konduru)

v3: rebased (me)

v4: Review comments by Ville addressed
Added platform check for NV12 in intel_framebuffer_init
Removed offset checks for NV12 case

v5: Addressed review comments by Clinton A Taylor
This NV12 support only correctly works on SKL.
Plane color space conversion is different on GLK and later platforms
causing the colors to display incorrectly.
Ville's plane color space property patch series
in review will fix this issue.
- Restricted the NV12 case in intel_framebuffer_init to
SKL and BXT only.

v6: Rebased (me)

v7: Addressed review comments by Ville
Restricting the NV12 to BXT for now.

v8: Rebased (me)
Restricting the NV12 changes to BXT and KBL for now.

v9: Rebased (me)

Tested-by: Clinton Taylor <clinton.a.taylor@intel.com>
Reviewed-by: Clinton Taylor <clinton.a.taylor@intel.com>
Signed-off-by: Chandra Konduru <chandra.konduru@intel.com>
Signed-off-by: Nabendu Maiti <nabendu.bikash.maiti@intel.com>
Signed-off-by: Vidya Srinivas <vidya.srinivas@intel.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 4b92e41..30c6da5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14005,6 +14005,14 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
 			goto err;
 		}
 		break;
+	case DRM_FORMAT_NV12:
+		if (!IS_BROXTON(dev_priv) && !IS_KABYLAKE(dev_priv)) {
+			DRM_DEBUG_KMS("unsupported pixel format: %s\n",
+		      drm_get_format_name(mode_cmd->pixel_format,
+				&format_name));
+			goto err;
+		}
+		break;
 	default:
 		DRM_DEBUG_KMS("unsupported pixel format: %s\n",
 			      drm_get_format_name(mode_cmd->pixel_format, &format_name));
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 33+ messages in thread
end of thread, other threads:[~2018-01-30  9:50 UTC | newest]

Thread overview: 33+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-01-15  3:18 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-15  3:18 ` [PATCH 02/15] drm/i915/skl+: refactor WM calculation for NV12 Vidya Srinivas
2018-01-20  0:39   ` kbuild test robot
2018-01-15  3:18 ` [PATCH 05/15] drm/i915/skl+: NV12 related changes for WM Vidya Srinivas
2018-01-15  3:18 ` [PATCH 03/15] drm/i915/skl+: add NV12 in skl_format_to_fourcc Vidya Srinivas
2018-01-17 11:43   ` Mika Kahola
2018-01-15  3:18 ` [PATCH 01/15] drm/i915/skl+: rename skl_wm_values struct to skl_ddb_values Vidya Srinivas
2018-01-15  3:18 ` [PATCH 04/15] drm/i915/skl+: support verification of DDB HW state for NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 07/15] drm/i915/skl+: make sure higher latency level has higher wm value Vidya Srinivas
2018-01-15  3:18 ` [PATCH 08/15] drm/i915/skl+: nv12 workaround disable WM level 1-7 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 09/15] drm/i915/skl: split skl_compute_ddb function Vidya Srinivas
2018-01-15  3:18 ` [PATCH 10/15] drm/i915: Set scaler mode for NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 06/15] drm/i915/skl+: pass skl_wm_level struct to wm compute func Vidya Srinivas
2018-01-15  3:18 ` [PATCH 12/15] drm/i915: Upscale scaler max scale for NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 13/15] drm/i915: Add NV12 as supported format for primary plane Vidya Srinivas
2018-01-15  3:18 ` [PATCH 11/15] drm/i915: Update format_is_yuv() to include NV12 Vidya Srinivas
2018-01-15  3:18 ` [PATCH 14/15] drm/i915: Add NV12 as supported format for sprite plane Vidya Srinivas
2018-01-15  3:18 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas
2018-01-18 14:21   ` Maarten Lankhorst
2018-01-18 14:49     ` Maarten Lankhorst
2018-01-29 11:41   ` Maarten Lankhorst
2018-01-30  4:53     ` Srinivas, Vidya
2018-01-29 17:17   ` Maarten Lankhorst
2018-01-30  4:05     ` Srinivas, Vidya
2018-01-30  6:16       ` Kumar, Mahesh
2018-01-30  9:50         ` Maarten Lankhorst
2018-01-15  3:49 ` ✓ Fi.CI.BAT: success for Adding NV12 support (rev5) Patchwork
2018-01-15  4:55 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-15  8:47 ` ✓ Fi.CI.BAT: " Patchwork
2018-01-15 10:39   ` Saarinen, Jani
2018-01-15  9:44 ` ✓ Fi.CI.IGT: " Patchwork
2018-01-15 12:35 ` ✗ Fi.CI.BAT: failure " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2018-01-04 10:44 [PATCH 00/15] Adding NV12 support Vidya Srinivas
2018-01-04 10:44 ` [PATCH 15/15] drm/i915: Add NV12 support to intel_framebuffer_init Vidya Srinivas

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.