* [PATCH 1/2] drm/i915/perf: store the associated engine of a stream
@ 2019-10-10 7:27 Chris Wilson
2019-10-10 7:27 ` [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore Chris Wilson
` (2 more replies)
0 siblings, 3 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-10 7:27 UTC (permalink / raw)
To: intel-gfx
From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
We'll use this information later to verify that a client trying to
reconfigure the stream does so on the right engine. For now, we want to
pull the knowledge of which engine we use into a central property.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 30 ++++++++++++++++++++++----
drivers/gpu/drm/i915/i915_perf_types.h | 5 +++++
2 files changed, 31 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 5a34cad7d824..1a5c6591b9bb 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -197,6 +197,7 @@
#include "gem/i915_gem_context.h"
#include "gem/i915_gem_pm.h"
+#include "gt/intel_engine_user.h"
#include "gt/intel_lrc_reg.h"
#include "i915_drv.h"
@@ -347,6 +348,7 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
* @oa_format: An OA unit HW report format
* @oa_periodic: Whether to enable periodic OA unit sampling
* @oa_period_exponent: The OA unit sampling period is derived from this
+ * @engine: The engine (typically rcs0) being monitored by the OA unit
*
* As read_properties_unlocked() enumerates and validates the properties given
* to open a stream of metrics the configuration is built up in the structure
@@ -363,6 +365,8 @@ struct perf_open_properties {
int oa_format;
bool oa_periodic;
int oa_period_exponent;
+
+ struct intel_engine_cs *engine;
};
static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
@@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
int err;
for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
- if (ce->engine->class != RENDER_CLASS)
+ if (ce->engine != stream->engine) /* first match! */
continue;
/*
@@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
int format_size;
int ret;
- /* If the sysfs metrics/ directory wasn't registered for some
+ if (!props->engine) {
+ DRM_DEBUG("OA engine not specified\n");
+ return -EINVAL;
+ }
+
+ /*
+ * If the sysfs metrics/ directory wasn't registered for some
* reason then don't let userspace try their luck with config
* IDs
*/
@@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return -ENODEV;
}
- /* To avoid the complexity of having to accurately filter
+ /*
+ * To avoid the complexity of having to accurately filter
* counter reports and marshal to the appropriate client
* we currently only allow exclusive access
*/
@@ -2160,6 +2171,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
return -EINVAL;
}
+ stream->engine = props->engine;
+ stream->gt = stream->engine->gt;
+
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
format_size = perf->oa_formats[props->oa_format].size;
@@ -2711,7 +2725,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
}
stream->perf = perf;
- stream->gt = &perf->i915->gt;
stream->ctx = specific_ctx;
ret = i915_oa_stream_init(stream, param, props);
@@ -2796,6 +2809,15 @@ static int read_properties_unlocked(struct i915_perf *perf,
return -EINVAL;
}
+ /* At the moment we only support using i915-perf on the RCS. */
+ props->engine = intel_engine_lookup_user(perf->i915,
+ I915_ENGINE_CLASS_RENDER,
+ 0);
+ if (!props->engine) {
+ DRM_DEBUG("No RENDER-capable engines\n");
+ return -EINVAL;
+ }
+
/* Considering that ID = 0 is reserved and assuming that we don't
* (currently) expect any configurations to ever specify duplicate
* values for a particular property ID then the last _PROP_MAX value is
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 2d17059d32ee..82cd3b295037 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -140,6 +140,11 @@ struct i915_perf_stream {
*/
intel_wakeref_t wakeref;
+ /**
+ * @engine: Engine associated with this performance stream.
+ */
+ struct intel_engine_cs *engine;
+
/**
* @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
* properties given when opening a stream, representing the contents
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore
2019-10-10 7:27 [PATCH 1/2] drm/i915/perf: store the associated engine of a stream Chris Wilson
@ 2019-10-10 7:27 ` Chris Wilson
2019-10-10 14:58 ` Lionel Landwerlin
2019-10-10 9:11 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/perf: store the associated engine of a stream Patchwork
2019-10-10 14:57 ` [PATCH 1/2] " Lionel Landwerlin
2 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2019-10-10 7:27 UTC (permalink / raw)
To: intel-gfx
Now that we have the engine stored in i915_perf, we have a means of
accessing intel_gt should we require it. However, we are currently only
using the intel_gt to find the right intel_uncore, so replace our
i915_perf.gt pointer with the more useful i915_perf.uncore.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
drivers/gpu/drm/i915/i915_perf.c | 48 +++++++++++++-------------
drivers/gpu/drm/i915/i915_perf_types.h | 4 +--
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 1a5c6591b9bb..77c3cef64548 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -419,14 +419,14 @@ static int get_oa_config(struct i915_perf *perf,
static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
}
static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
@@ -656,7 +656,7 @@ static int gen8_append_oa_reports(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
@@ -866,7 +866,7 @@ static int gen8_oa_read(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus;
int ret;
@@ -945,7 +945,7 @@ static int gen7_append_oa_reports(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
int report_size = stream->oa_buffer.format_size;
u8 *oa_buf_base = stream->oa_buffer.vaddr;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
@@ -1077,7 +1077,7 @@ static int gen7_oa_read(struct i915_perf_stream *stream,
size_t count,
size_t *offset)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 oastatus1;
int ret;
@@ -1352,8 +1352,8 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
free_oa_buffer(stream);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
+ intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
+ intel_runtime_pm_put(stream->uncore->rpm, stream->wakeref);
if (stream->ctx)
oa_put_render_ctx_id(stream);
@@ -1368,7 +1368,7 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
unsigned long flags;
@@ -1416,7 +1416,7 @@ static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
unsigned long flags;
@@ -1565,7 +1565,7 @@ static void delay_after_mux(void)
static int hsw_enable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
const struct i915_oa_config *oa_config = stream->oa_config;
/*
@@ -1594,7 +1594,7 @@ static int hsw_enable_metric_set(struct i915_perf_stream *stream)
static void hsw_disable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
intel_uncore_rmw(uncore, GEN6_UCGCTL1,
GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
@@ -1911,7 +1911,7 @@ static int gen8_configure_all_contexts(struct i915_perf_stream *stream,
static int gen8_enable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
const struct i915_oa_config *oa_config = stream->oa_config;
int ret;
@@ -1964,7 +1964,7 @@ static int gen8_enable_metric_set(struct i915_perf_stream *stream)
static void gen8_disable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
/* Reset all contexts' slices/subslices configurations. */
gen8_configure_all_contexts(stream, NULL);
@@ -1974,7 +1974,7 @@ static void gen8_disable_metric_set(struct i915_perf_stream *stream)
static void gen10_disable_metric_set(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
/* Reset all contexts' slices/subslices configurations. */
gen8_configure_all_contexts(stream, NULL);
@@ -1985,7 +1985,7 @@ static void gen10_disable_metric_set(struct i915_perf_stream *stream)
static void gen7_oa_enable(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
struct i915_gem_context *ctx = stream->ctx;
u32 ctx_id = stream->specific_ctx_id;
bool periodic = stream->periodic;
@@ -2015,7 +2015,7 @@ static void gen7_oa_enable(struct i915_perf_stream *stream)
static void gen8_oa_enable(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
u32 report_format = stream->oa_buffer.format;
/*
@@ -2060,7 +2060,7 @@ static void i915_oa_stream_enable(struct i915_perf_stream *stream)
static void gen7_oa_disable(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
intel_uncore_write(uncore, GEN7_OACONTROL, 0);
if (intel_wait_for_register(uncore,
@@ -2071,7 +2071,7 @@ static void gen7_oa_disable(struct i915_perf_stream *stream)
static void gen8_oa_disable(struct i915_perf_stream *stream)
{
- struct intel_uncore *uncore = stream->gt->uncore;
+ struct intel_uncore *uncore = stream->uncore;
intel_uncore_write(uncore, GEN8_OACONTROL, 0);
if (intel_wait_for_register(uncore,
@@ -2172,7 +2172,7 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
}
stream->engine = props->engine;
- stream->gt = stream->engine->gt;
+ stream->uncore = stream->engine->gt->uncore;
stream->sample_size = sizeof(struct drm_i915_perf_record_header);
@@ -2218,8 +2218,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
* In our case we are expecting that taking pm + FORCEWAKE
* references will effectively disable RC6.
*/
- stream->wakeref = intel_runtime_pm_get(stream->gt->uncore->rpm);
- intel_uncore_forcewake_get(stream->gt->uncore, FORCEWAKE_ALL);
+ stream->wakeref = intel_runtime_pm_get(stream->uncore->rpm);
+ intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
ret = alloc_oa_buffer(stream);
if (ret)
@@ -2251,8 +2251,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
err_oa_buf_alloc:
put_oa_config(stream->oa_config);
- intel_uncore_forcewake_put(stream->gt->uncore, FORCEWAKE_ALL);
- intel_runtime_pm_put(stream->gt->uncore->rpm, stream->wakeref);
+ intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
+ intel_runtime_pm_put(stream->uncore->rpm, stream->wakeref);
err_config:
if (stream->ctx)
diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
index 82cd3b295037..a91ae2d1a543 100644
--- a/drivers/gpu/drm/i915/i915_perf_types.h
+++ b/drivers/gpu/drm/i915/i915_perf_types.h
@@ -130,9 +130,9 @@ struct i915_perf_stream {
struct i915_perf *perf;
/**
- * @gt: intel_gt container
+ * @uncore: mmio access path
*/
- struct intel_gt *gt;
+ struct intel_uncore *uncore;
/**
* @wakeref: As we keep the device awake while the perf stream is
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/perf: store the associated engine of a stream
2019-10-10 7:27 [PATCH 1/2] drm/i915/perf: store the associated engine of a stream Chris Wilson
2019-10-10 7:27 ` [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore Chris Wilson
@ 2019-10-10 9:11 ` Patchwork
2019-10-10 14:57 ` [PATCH 1/2] " Lionel Landwerlin
2 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2019-10-10 9:11 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: store the associated engine of a stream
URL : https://patchwork.freedesktop.org/series/67828/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7047 -> Patchwork_14743
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14743 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14743, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14743:
### IGT changes ###
#### Possible regressions ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-icl-u3: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-icl-u3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
Known issues
------------
Here are the changes found in Patchwork_14743 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_basic@create-fd-close:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@gem_basic@create-fd-close.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-icl-u3/igt@gem_basic@create-fd-close.html
* igt@i915_selftest@live_coherency:
- fi-glk-dsi: [PASS][5] -> [TIMEOUT][6] ([fdo#111944])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-glk-dsi/igt@i915_selftest@live_coherency.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-glk-dsi/igt@i915_selftest@live_coherency.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_flink_basic@basic:
- fi-icl-u3: [DMESG-WARN][9] ([fdo#107724]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7047/fi-icl-u3/igt@gem_flink_basic@basic.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/fi-icl-u3/igt@gem_flink_basic@basic.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111880]: https://bugs.freedesktop.org/show_bug.cgi?id=111880
[fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
Participating hosts (51 -> 46)
------------------------------
Additional (3): fi-byt-j1900 fi-bsw-n3050 fi-pnv-d510
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-icl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7047 -> Patchwork_14743
CI-20190529: 20190529
CI_DRM_7047: 23ba5b1f97d3d114d30eead1ca95d5a846a9027c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5220: 1e38e32d721210a780198c8293a6b8c8e881df68 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14743: fde6feb63d256644e1aec3c32f7e27c2f15ff5e5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fde6feb63d25 drm/i915/perf: Store shortcut to intel_uncore
af90528ae3bb drm/i915/perf: store the associated engine of a stream
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14743/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915/perf: store the associated engine of a stream
2019-10-10 7:27 [PATCH 1/2] drm/i915/perf: store the associated engine of a stream Chris Wilson
2019-10-10 7:27 ` [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore Chris Wilson
2019-10-10 9:11 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/perf: store the associated engine of a stream Patchwork
@ 2019-10-10 14:57 ` Lionel Landwerlin
2019-10-10 15:04 ` Chris Wilson
2 siblings, 1 reply; 6+ messages in thread
From: Lionel Landwerlin @ 2019-10-10 14:57 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 10/10/2019 10:27, Chris Wilson wrote:
> From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
> We'll use this information later to verify that a client trying to
> reconfigure the stream does so on the right engine. For now, we want to
> pull the knowledge of which engine we use into a central property.
>
> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Your changes look fine :
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Thanks!
> ---
> drivers/gpu/drm/i915/i915_perf.c | 30 ++++++++++++++++++++++----
> drivers/gpu/drm/i915/i915_perf_types.h | 5 +++++
> 2 files changed, 31 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index 5a34cad7d824..1a5c6591b9bb 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -197,6 +197,7 @@
>
> #include "gem/i915_gem_context.h"
> #include "gem/i915_gem_pm.h"
> +#include "gt/intel_engine_user.h"
> #include "gt/intel_lrc_reg.h"
>
> #include "i915_drv.h"
> @@ -347,6 +348,7 @@ static const struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = {
> * @oa_format: An OA unit HW report format
> * @oa_periodic: Whether to enable periodic OA unit sampling
> * @oa_period_exponent: The OA unit sampling period is derived from this
> + * @engine: The engine (typically rcs0) being monitored by the OA unit
> *
> * As read_properties_unlocked() enumerates and validates the properties given
> * to open a stream of metrics the configuration is built up in the structure
> @@ -363,6 +365,8 @@ struct perf_open_properties {
> int oa_format;
> bool oa_periodic;
> int oa_period_exponent;
> +
> + struct intel_engine_cs *engine;
> };
>
> static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
> @@ -1205,7 +1209,7 @@ static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
> int err;
>
> for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
> - if (ce->engine->class != RENDER_CLASS)
> + if (ce->engine != stream->engine) /* first match! */
> continue;
>
> /*
> @@ -2127,7 +2131,13 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> int format_size;
> int ret;
>
> - /* If the sysfs metrics/ directory wasn't registered for some
> + if (!props->engine) {
> + DRM_DEBUG("OA engine not specified\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * If the sysfs metrics/ directory wasn't registered for some
> * reason then don't let userspace try their luck with config
> * IDs
> */
> @@ -2146,7 +2156,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> return -ENODEV;
> }
>
> - /* To avoid the complexity of having to accurately filter
> + /*
> + * To avoid the complexity of having to accurately filter
> * counter reports and marshal to the appropriate client
> * we currently only allow exclusive access
> */
> @@ -2160,6 +2171,9 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream,
> return -EINVAL;
> }
>
> + stream->engine = props->engine;
> + stream->gt = stream->engine->gt;
> +
> stream->sample_size = sizeof(struct drm_i915_perf_record_header);
>
> format_size = perf->oa_formats[props->oa_format].size;
> @@ -2711,7 +2725,6 @@ i915_perf_open_ioctl_locked(struct i915_perf *perf,
> }
>
> stream->perf = perf;
> - stream->gt = &perf->i915->gt;
> stream->ctx = specific_ctx;
>
> ret = i915_oa_stream_init(stream, param, props);
> @@ -2796,6 +2809,15 @@ static int read_properties_unlocked(struct i915_perf *perf,
> return -EINVAL;
> }
>
> + /* At the moment we only support using i915-perf on the RCS. */
> + props->engine = intel_engine_lookup_user(perf->i915,
> + I915_ENGINE_CLASS_RENDER,
> + 0);
> + if (!props->engine) {
> + DRM_DEBUG("No RENDER-capable engines\n");
> + return -EINVAL;
> + }
> +
> /* Considering that ID = 0 is reserved and assuming that we don't
> * (currently) expect any configurations to ever specify duplicate
> * values for a particular property ID then the last _PROP_MAX value is
> diff --git a/drivers/gpu/drm/i915/i915_perf_types.h b/drivers/gpu/drm/i915/i915_perf_types.h
> index 2d17059d32ee..82cd3b295037 100644
> --- a/drivers/gpu/drm/i915/i915_perf_types.h
> +++ b/drivers/gpu/drm/i915/i915_perf_types.h
> @@ -140,6 +140,11 @@ struct i915_perf_stream {
> */
> intel_wakeref_t wakeref;
>
> + /**
> + * @engine: Engine associated with this performance stream.
> + */
> + struct intel_engine_cs *engine;
> +
> /**
> * @sample_flags: Flags representing the `DRM_I915_PERF_PROP_SAMPLE_*`
> * properties given when opening a stream, representing the contents
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore
2019-10-10 7:27 ` [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore Chris Wilson
@ 2019-10-10 14:58 ` Lionel Landwerlin
0 siblings, 0 replies; 6+ messages in thread
From: Lionel Landwerlin @ 2019-10-10 14:58 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 10/10/2019 10:27, Chris Wilson wrote:
> Now that we have the engine stored in i915_perf, we have a means of
> accessing intel_gt should we require it. However, we are currently only
> using the intel_gt to find the right intel_uncore, so replace our
> i915_perf.gt pointer with the more useful i915_perf.uncore.
>
> Signed-off-by: Chris Wilson<chris@chris-wilson.co.uk>
> Cc: Lionel Landwerlin<lionel.g.landwerlin@intel.com>
> ---
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/i915/perf: store the associated engine of a stream
2019-10-10 14:57 ` [PATCH 1/2] " Lionel Landwerlin
@ 2019-10-10 15:04 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2019-10-10 15:04 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
Quoting Lionel Landwerlin (2019-10-10 15:57:32)
> On 10/10/2019 10:27, Chris Wilson wrote:
> > From: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> >
> > We'll use this information later to verify that a client trying to
> > reconfigure the stream does so on the right engine. For now, we want to
> > pull the knowledge of which engine we use into a central property.
> >
> > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>
>
> Your changes look fine :
>
> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
And the queue gradually shrinks.
-Chris
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-10-10 15:04 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-10 7:27 [PATCH 1/2] drm/i915/perf: store the associated engine of a stream Chris Wilson
2019-10-10 7:27 ` [PATCH 2/2] drm/i915/perf: Store shortcut to intel_uncore Chris Wilson
2019-10-10 14:58 ` Lionel Landwerlin
2019-10-10 9:11 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/perf: store the associated engine of a stream Patchwork
2019-10-10 14:57 ` [PATCH 1/2] " Lionel Landwerlin
2019-10-10 15:04 ` Chris Wilson
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