* [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
@ 2019-10-11 13:39 Mika Kuoppala
2019-10-11 13:39 ` [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Mika Kuoppala @ 2019-10-11 13:39 UTC (permalink / raw)
To: intel-gfx
Aim for completeness and invalidate also the ro parts
in l3 cache. This might allow to get rid of the preparser
disable/enable workaround on invalidation path.
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index b0227ab2fe1b..8c8e6bf824a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -230,6 +230,7 @@
#define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
#define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
+#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
#define PIPE_CONTROL_NOTIFY (1<<8)
#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b00499cc7586..c6fbc723566f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3213,6 +3213,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
+ flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush
2019-10-11 13:39 [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
@ 2019-10-11 13:39 ` Mika Kuoppala
2019-10-11 18:13 ` Chris Wilson
2019-10-11 18:15 ` Chris Wilson
2019-10-11 13:39 ` [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround Mika Kuoppala
` (3 subsequent siblings)
4 siblings, 2 replies; 9+ messages in thread
From: Mika Kuoppala @ 2019-10-11 13:39 UTC (permalink / raw)
To: intel-gfx
Add hdc pipeline flush to ensure memory state is coherent
in L3 when we are done.
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 8c8e6bf824a9..696b6495b0da 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -232,6 +232,7 @@
#define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
#define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
+#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
#define PIPE_CONTROL_NOTIFY (1<<8)
#define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
#define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index c6fbc723566f..967e5b2e5e80 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3188,6 +3188,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
flags |= PIPE_CONTROL_FLUSH_ENABLE;
+ flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
flags |= PIPE_CONTROL_STORE_DATA_INDEX;
flags |= PIPE_CONTROL_QW_WRITE;
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround
2019-10-11 13:39 [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
2019-10-11 13:39 ` [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
@ 2019-10-11 13:39 ` Mika Kuoppala
2019-10-11 18:19 ` Chris Wilson
2019-10-11 15:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Mika Kuoppala @ 2019-10-11 13:39 UTC (permalink / raw)
To: intel-gfx
In order to ensure constant caches are invalidated
properly with a0, we need extra hdc flush after invalidation.
References: HSDES#1604544889
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 967e5b2e5e80..8db86772d8d4 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3236,6 +3236,24 @@ static int gen12_emit_flush_render(struct i915_request *request,
*cs++ = preparser_disable(false);
intel_ring_advance(request, cs);
+
+ /*
+ * Workaround constant cache invalidation issue
+ * for tgl:a0, #1604544889
+ */
+ flags = 0;
+ flags |= PIPE_CONTROL_CS_STALL;
+ flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
+
+ flags |= PIPE_CONTROL_STORE_DATA_INDEX;
+ flags |= PIPE_CONTROL_QW_WRITE;
+
+ cs = intel_ring_begin(request, 6);
+ if (IS_ERR(cs))
+ return PTR_ERR(cs);
+
+ cs = gen8_emit_pipe_control(cs, flags, LRC_PPHWSP_SCRATCH_ADDR);
+ intel_ring_advance(request, cs);
}
return 0;
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
2019-10-11 13:39 [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
2019-10-11 13:39 ` [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
2019-10-11 13:39 ` [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround Mika Kuoppala
@ 2019-10-11 15:24 ` Patchwork
2019-10-11 15:53 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-11 18:15 ` [PATCH 1/3] " Chris Wilson
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-10-11 15:24 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
URL : https://patchwork.freedesktop.org/series/67912/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9438571a7abe drm/i915/tgl: Include ro parts of l3 to invalidate
-:21: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#21: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:233:
+#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
^
total: 0 errors, 0 warnings, 1 checks, 14 lines checked
8ed9c38c7c44 drm/i915/tgl: Add HDC Pipeline Flush
-:19: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#19: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:235:
+#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
^
total: 0 errors, 0 warnings, 1 checks, 14 lines checked
2855d8f17591 drm/i915/tgl: Add extra hdc flush workaround
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✗ Fi.CI.BAT: failure for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
2019-10-11 13:39 [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
` (2 preceding siblings ...)
2019-10-11 15:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Patchwork
@ 2019-10-11 15:53 ` Patchwork
2019-10-11 18:15 ` [PATCH 1/3] " Chris Wilson
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-10-11 15:53 UTC (permalink / raw)
To: Mika Kuoppala; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
URL : https://patchwork.freedesktop.org/series/67912/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7064 -> Patchwork_14769
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_14769 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_14769, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_14769:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_execlists:
- fi-cfl-8700k: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-cfl-8700k/igt@i915_selftest@live_execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-cfl-8700k/igt@i915_selftest@live_execlists.html
Known issues
------------
Here are the changes found in Patchwork_14769 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_reloc@basic-gtt-cpu-noreloc:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-icl-u3/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-icl-u3/igt@gem_exec_reloc@basic-gtt-cpu-noreloc.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s4-devices:
- fi-blb-e6850: [INCOMPLETE][5] ([fdo#107718]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-blb-e6850/igt@gem_exec_suspend@basic-s4-devices.html
* igt@gem_mmap_gtt@basic-read:
- {fi-icl-dsi}: [DMESG-WARN][7] ([fdo#106107]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-icl-dsi/igt@gem_mmap_gtt@basic-read.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-icl-dsi/igt@gem_mmap_gtt@basic-read.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-cfl-8109u: [INCOMPLETE][9] -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-cfl-8109u/igt@i915_module_load@reload-with-fault-injection.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-cfl-8109u/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_coherency:
- fi-glk-dsi: [TIMEOUT][11] ([fdo#111944]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-glk-dsi/igt@i915_selftest@live_coherency.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-glk-dsi/igt@i915_selftest@live_coherency.html
* igt@i915_selftest@live_workarounds:
- fi-skl-6600u: [DMESG-FAIL][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-skl-6600u/igt@i915_selftest@live_workarounds.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-skl-6600u/igt@i915_selftest@live_workarounds.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@prime_self_import@basic-llseek-size:
- fi-icl-u3: [DMESG-WARN][17] ([fdo#107724]) -> [PASS][18] +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7064/fi-icl-u3/igt@prime_self_import@basic-llseek-size.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/fi-icl-u3/igt@prime_self_import@basic-llseek-size.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
[fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111867]: https://bugs.freedesktop.org/show_bug.cgi?id=111867
[fdo#111944]: https://bugs.freedesktop.org/show_bug.cgi?id=111944
Participating hosts (47 -> 43)
------------------------------
Additional (2): fi-bsw-n3050 fi-pnv-d510
Missing (6): fi-hsw-4200u fi-tgl-u2 fi-byt-squawks fi-bsw-cyan fi-icl-y fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7064 -> Patchwork_14769
CI-20190529: 20190529
CI_DRM_7064: 8369232b3509a230b2d4cbd9548a8d5db444a3f2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5221: 280734ceacde4ff52c6bd5a9e3d664f77f76b85d @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_14769: 2855d8f175916ab2756e0293775fac8aa03ede46 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2855d8f17591 drm/i915/tgl: Add extra hdc flush workaround
8ed9c38c7c44 drm/i915/tgl: Add HDC Pipeline Flush
9438571a7abe drm/i915/tgl: Include ro parts of l3 to invalidate
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14769/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush
2019-10-11 13:39 ` [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
@ 2019-10-11 18:13 ` Chris Wilson
2019-10-11 18:15 ` Chris Wilson
1 sibling, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2019-10-11 18:13 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-11 14:39:10)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 8c8e6bf824a9..696b6495b0da 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -232,6 +232,7 @@
> #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
> #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
> #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
> #define PIPE_CONTROL_NOTIFY (1<<8)
> #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
> #define PIPE_CONTROL_DC_FLUSH_ENABLE (1<<5)
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index c6fbc723566f..967e5b2e5e80 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3188,6 +3188,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
> flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
> flags |= PIPE_CONTROL_DC_FLUSH_ENABLE;
> flags |= PIPE_CONTROL_FLUSH_ENABLE;
> + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
Adding a flush here has no effect, see gen12_fini_breadcrumbs_rcs.
>
> flags |= PIPE_CONTROL_QW_WRITE;
> --
> 2.17.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate
2019-10-11 13:39 [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
` (3 preceding siblings ...)
2019-10-11 15:53 ` ✗ Fi.CI.BAT: failure " Patchwork
@ 2019-10-11 18:15 ` Chris Wilson
4 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2019-10-11 18:15 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-11 14:39:09)
> Aim for completeness and invalidate also the ro parts
> in l3 cache. This might allow to get rid of the preparser
> disable/enable workaround on invalidation path.
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index b0227ab2fe1b..8c8e6bf824a9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -230,6 +230,7 @@
> #define PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH (1<<12) /* gen6+ */
> #define PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE (1<<11) /* MBZ on ILK */
> #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
> +#define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
Ack.
> #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> #define PIPE_CONTROL_NOTIFY (1<<8)
> #define PIPE_CONTROL_FLUSH_ENABLE (1<<7) /* gen7+ */
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b00499cc7586..c6fbc723566f 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3213,6 +3213,7 @@ static int gen12_emit_flush_render(struct i915_request *request,
> flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
> flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
> + flags |= PIPE_CONTROL_L3_RO_CACHE_INVALIDATE;
>
> flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> flags |= PIPE_CONTROL_QW_WRITE;
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush
2019-10-11 13:39 ` [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
2019-10-11 18:13 ` Chris Wilson
@ 2019-10-11 18:15 ` Chris Wilson
1 sibling, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2019-10-11 18:15 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-11 14:39:10)
> Add hdc pipeline flush to ensure memory state is coherent
> in L3 when we are done.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 1 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 1 +
> 2 files changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 8c8e6bf824a9..696b6495b0da 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -232,6 +232,7 @@
> #define PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE (1<<10) /* GM45+ only */
> #define PIPE_CONTROL_L3_RO_CACHE_INVALIDATE (1<<10) /* gen12 */
> #define PIPE_CONTROL_INDIRECT_STATE_DISABLE (1<<9)
> +#define PIPE_CONTROL_HDC_PIPELINE_FLUSH (1<<9) /* gen 12 */
Ack. Just need to tweak usage.
-Chris
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround
2019-10-11 13:39 ` [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround Mika Kuoppala
@ 2019-10-11 18:19 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2019-10-11 18:19 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2019-10-11 14:39:11)
> In order to ensure constant caches are invalidated
> properly with a0, we need extra hdc flush after invalidation.
>
> References: HSDES#1604544889
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_lrc.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 967e5b2e5e80..8db86772d8d4 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -3236,6 +3236,24 @@ static int gen12_emit_flush_render(struct i915_request *request,
>
> *cs++ = preparser_disable(false);
> intel_ring_advance(request, cs);
> +
> + /*
> + * Workaround constant cache invalidation issue
> + * for tgl:a0, #1604544889
Do we have IS_TGL_REVID() yet? They should act as a reminder to remove
them later.
> + */
> + flags = 0;
> + flags |= PIPE_CONTROL_CS_STALL;
> + flags |= PIPE_CONTROL_HDC_PIPELINE_FLUSH;
> +
> + flags |= PIPE_CONTROL_STORE_DATA_INDEX;
> + flags |= PIPE_CONTROL_QW_WRITE;
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-10-11 18:19 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-11 13:39 [PATCH 1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Mika Kuoppala
2019-10-11 13:39 ` [PATCH 2/3] drm/i915/tgl: Add HDC Pipeline Flush Mika Kuoppala
2019-10-11 18:13 ` Chris Wilson
2019-10-11 18:15 ` Chris Wilson
2019-10-11 13:39 ` [PATCH 3/3] drm/i915/tgl: Add extra hdc flush workaround Mika Kuoppala
2019-10-11 18:19 ` Chris Wilson
2019-10-11 15:24 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/3] drm/i915/tgl: Include ro parts of l3 to invalidate Patchwork
2019-10-11 15:53 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-11 18:15 ` [PATCH 1/3] " Chris Wilson
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