* [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
Changes since v1 [0]:
- Removed patch reintroducing DO_UPCAST() use (thuth)
- Took various patches out to reduce series (thuth)
- Added review tags (thanks all for reviewing!)
$ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respectively
001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets'
002/20:[0011] [FC] 'piix4: add Reset Control Register'
003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified in datasheet'
004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in datasheet'
007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in datasheet'
008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in datasheet'
009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array dynamically'
010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()'
011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers'
013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers'
016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h'
017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c'
019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as 'i440fx''
020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
Previous cover:
This series is a rework of "piix4: cleanup and improvements" [1]
from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
Still trying to remove the strong X86/PC dependency 2 years later,
one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge.
The i440FX northbridge is only used by the PC machine, while the
PIIX southbridge is also used by the Malta MIPS machine.
This is also a step forward using KConfig with the Malta board.
Without this split, it was impossible to compile the Malta without
pulling various X86 pieces of code.
The overall design cleanup is not yet perfect, but enough to post
as a series.
Now that the PIIX3 code is extracted, the code duplication with the
PIIX4 chipset is obvious. Not worth improving for now because it
isn't broken.
[0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
Based-on: <20191018133547.10936-1-philmd@redhat.com>
mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of rtc_init()
https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
Hervé Poussineau (5):
piix4: Add the Reset Control Register
piix4: Add a i8259 Interrupt Controller as specified in datasheet
piix4: Rename PIIX4 object to piix4-isa
piix4: Add a i8257 DMA Controller as specified in datasheet
piix4: Add a i8254 PIT Controller as specified in datasheet
Philippe Mathieu-Daudé (15):
MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
Revert "irq: introduce qemu_irq_proxy()"
piix4: Add a MC146818 RTC Controller as specified in datasheet
hw/mips/mips_malta: Create IDE hard drive array dynamically
hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
hw/pci-host/piix: Extract piix3_create()
hw/pci-host/piix: Move RCR_IOPORT register definition
hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
hw/pci-host/piix: Fix code style issues
hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
hw/pci-host/i440fx: Remove the last PIIX3 traces
MAINTAINERS | 14 +-
hw/acpi/pcihp.c | 2 +-
hw/acpi/piix4.c | 42 +--
hw/core/irq.c | 14 -
hw/i386/Kconfig | 3 +-
hw/i386/acpi-build.c | 5 +-
hw/i386/pc_piix.c | 10 +-
hw/i386/xen/xen-hvm.c | 5 +-
hw/intc/apic_common.c | 49 ----
hw/isa/Kconfig | 4 +
hw/isa/Makefile.objs | 1 +
hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
hw/isa/piix4.c | 151 ++++++++++-
hw/mips/gt64xxx_pci.c | 5 +-
hw/mips/mips_malta.c | 46 +---
hw/pci-host/Kconfig | 3 +-
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
hw/timer/i8254_common.c | 40 ---
include/hw/acpi/piix4.h | 6 -
include/hw/i386/pc.h | 37 ---
include/hw/irq.h | 5 -
include/hw/isa/isa.h | 2 +
include/hw/pci-host/i440fx.h | 36 +++
include/hw/southbridge/piix.h | 74 ++++++
stubs/pci-host-piix.c | 3 +-
26 files changed, 699 insertions(+), 683 deletions(-)
create mode 100644 hw/isa/piix3.c
rename hw/pci-host/{piix.c => i440fx.c} (58%)
delete mode 100644 include/hw/acpi/piix4.h
create mode 100644 include/hw/pci-host/i440fx.h
create mode 100644 include/hw/southbridge/piix.h
--
2.21.0
^ permalink raw reply [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
Changes since v1 [0]:
- Removed patch reintroducing DO_UPCAST() use (thuth)
- Took various patches out to reduce series (thuth)
- Added review tags (thanks all for reviewing!)
$ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
Key:
[----] : patches are identical
[####] : number of functional differences between upstream/downstream patch
[down] : patch is downstream-only
The flags [FC] indicate (F)unctional and (C)ontextual differences, respectively
001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets'
002/20:[0011] [FC] 'piix4: add Reset Control Register'
003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified in datasheet'
004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in datasheet'
007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in datasheet'
008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in datasheet'
009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array dynamically'
010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()'
011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers'
013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers'
016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h'
017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c'
019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as 'i440fx''
020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
Previous cover:
This series is a rework of "piix4: cleanup and improvements" [1]
from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
Still trying to remove the strong X86/PC dependency 2 years later,
one step at a time.
Here we split the PIIX3 southbridge from i440FX northbridge.
The i440FX northbridge is only used by the PC machine, while the
PIIX southbridge is also used by the Malta MIPS machine.
This is also a step forward using KConfig with the Malta board.
Without this split, it was impossible to compile the Malta without
pulling various X86 pieces of code.
The overall design cleanup is not yet perfect, but enough to post
as a series.
Now that the PIIX3 code is extracted, the code duplication with the
PIIX4 chipset is obvious. Not worth improving for now because it
isn't broken.
[0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
[2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
Based-on: <20191018133547.10936-1-philmd@redhat.com>
mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of rtc_init()
https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
Hervé Poussineau (5):
piix4: Add the Reset Control Register
piix4: Add a i8259 Interrupt Controller as specified in datasheet
piix4: Rename PIIX4 object to piix4-isa
piix4: Add a i8257 DMA Controller as specified in datasheet
piix4: Add a i8254 PIT Controller as specified in datasheet
Philippe Mathieu-Daudé (15):
MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
Revert "irq: introduce qemu_irq_proxy()"
piix4: Add a MC146818 RTC Controller as specified in datasheet
hw/mips/mips_malta: Create IDE hard drive array dynamically
hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
hw/pci-host/piix: Extract piix3_create()
hw/pci-host/piix: Move RCR_IOPORT register definition
hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
hw/pci-host/piix: Fix code style issues
hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
hw/pci-host/i440fx: Remove the last PIIX3 traces
MAINTAINERS | 14 +-
hw/acpi/pcihp.c | 2 +-
hw/acpi/piix4.c | 42 +--
hw/core/irq.c | 14 -
hw/i386/Kconfig | 3 +-
hw/i386/acpi-build.c | 5 +-
hw/i386/pc_piix.c | 10 +-
hw/i386/xen/xen-hvm.c | 5 +-
hw/intc/apic_common.c | 49 ----
hw/isa/Kconfig | 4 +
hw/isa/Makefile.objs | 1 +
hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
hw/isa/piix4.c | 151 ++++++++++-
hw/mips/gt64xxx_pci.c | 5 +-
hw/mips/mips_malta.c | 46 +---
hw/pci-host/Kconfig | 3 +-
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
hw/timer/i8254_common.c | 40 ---
include/hw/acpi/piix4.h | 6 -
include/hw/i386/pc.h | 37 ---
include/hw/irq.h | 5 -
include/hw/isa/isa.h | 2 +
include/hw/pci-host/i440fx.h | 36 +++
include/hw/southbridge/piix.h | 74 ++++++
stubs/pci-host-piix.c | 3 +-
26 files changed, 699 insertions(+), 683 deletions(-)
create mode 100644 hw/isa/piix3.c
rename hw/pci-host/{piix.c => i440fx.c} (58%)
delete mode 100644 include/hw/acpi/piix4.h
create mode 100644 include/hw/pci-host/i440fx.h
create mode 100644 include/hw/southbridge/piix.h
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* [PATCH v2 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The PIIX4 Southbridge is not used by the PC machine,
but by the Malta board (MIPS). Add a new section to
keep it covered.
Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
MAINTAINERS | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe4dc51b08..c9f625fc2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
F: hw/pci-host/pam.c
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
-F: hw/isa/piix4.c
F: hw/isa/lpc_ich9.c
F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
@@ -1716,6 +1715,12 @@ F: hw/display/edid*
F: include/hw/display/edid.h
F: qemu-edid.c
+PIIX4 South Bridge (i82371AB)
+M: Hervé Poussineau <hpoussin@reactos.org>
+M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+S: Maintained
+F: hw/isa/piix4.c
+
Firmware configuration (fw_cfg)
M: Philippe Mathieu-Daudé <philmd@redhat.com>
R: Laszlo Ersek <lersek@redhat.com>
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The PIIX4 Southbridge is not used by the PC machine,
but by the Malta board (MIPS). Add a new section to
keep it covered.
Suggested-by: Michael S. Tsirkin <mst@redhat.com>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
MAINTAINERS | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index fe4dc51b08..c9f625fc2e 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
F: hw/pci-host/pam.c
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
-F: hw/isa/piix4.c
F: hw/isa/lpc_ich9.c
F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
@@ -1716,6 +1715,12 @@ F: hw/display/edid*
F: include/hw/display/edid.h
F: qemu-edid.c
+PIIX4 South Bridge (i82371AB)
+M: Hervé Poussineau <hpoussin@reactos.org>
+M: Philippe Mathieu-Daudé <f4bug@amsat.org>
+S: Maintained
+F: hw/isa/piix4.c
+
Firmware configuration (fw_cfg)
M: Philippe Mathieu-Daudé <philmd@redhat.com>
R: Laszlo Ersek <lersek@redhat.com>
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 02/20] piix4: Add the Reset Control Register
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased, updated includes]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 46 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 890d999abf..d0b18e0586 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -2,6 +2,7 @@
* QEMU PIIX4 PCI Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -28,11 +29,17 @@
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
PCIDevice *piix4_dev;
typedef struct PIIX4State {
PCIDevice dev;
+
+ /* Reset Control Register */
+ MemoryRegion rcr_mem;
+ uint8_t rcr;
} PIIX4State;
#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
@@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
}
};
+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int len)
+{
+ PIIX4State *s = opaque;
+
+ if (val & 4) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ }
+
+ s->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+{
+ PIIX4State *s = opaque;
+
+ return s->rcr;
+}
+
+static const MemoryRegionOps piix4_rcr_ops = {
+ .read = piix4_rcr_read,
+ .write = piix4_rcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
static void piix4_realize(PCIDevice *dev, Error **errp)
{
- PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+ PIIX4State *s = PIIX4_PCI_DEVICE(dev);
- if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
+ if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp)) {
return;
}
- piix4_dev = &d->dev;
+
+ memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+ "reset-control", 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
+ &s->rcr_mem, 1);
+
+ piix4_dev = dev;
}
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 02/20] piix4: Add the Reset Control Register
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased, updated includes]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 46 insertions(+), 3 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 890d999abf..d0b18e0586 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -2,6 +2,7 @@
* QEMU PIIX4 PCI Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
@@ -28,11 +29,17 @@
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
PCIDevice *piix4_dev;
typedef struct PIIX4State {
PCIDevice dev;
+
+ /* Reset Control Register */
+ MemoryRegion rcr_mem;
+ uint8_t rcr;
} PIIX4State;
#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
@@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
}
};
+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
+ unsigned int len)
+{
+ PIIX4State *s = opaque;
+
+ if (val & 4) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ }
+
+ s->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)
+{
+ PIIX4State *s = opaque;
+
+ return s->rcr;
+}
+
+static const MemoryRegionOps piix4_rcr_ops = {
+ .read = piix4_rcr_read,
+ .write = piix4_rcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
+};
+
static void piix4_realize(PCIDevice *dev, Error **errp)
{
- PIIX4State *d = PIIX4_PCI_DEVICE(dev);
+ PIIX4State *s = PIIX4_PCI_DEVICE(dev);
- if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
+ if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp)) {
return;
}
- piix4_dev = &d->dev;
+
+ memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
+ "reset-control", 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
+ &s->rcr_mem, 1);
+
+ piix4_dev = dev;
}
int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
--
2.21.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
Remove i8259 instanciated in malta board, to not have it twice.
We can also remove the now unused piix4_init() function.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
hw/mips/mips_malta.c | 32 +++++++++++++-------------------
include/hw/i386/pc.h | 1 -
3 files changed, 45 insertions(+), 31 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index d0b18e0586..9c37c85ae2 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
@@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
typedef struct PIIX4State {
PCIDevice dev;
+ qemu_irq cpu_intr;
+ qemu_irq *isa;
/* Reset Control Register */
MemoryRegion rcr_mem;
@@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
}
};
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+ PIIX4State *s = opaque;
+ qemu_set_irq(s->cpu_intr, level);
+}
+
+static void piix4_set_i8259_irq(void *opaque, int irq, int level)
+{
+ PIIX4State *s = opaque;
+ qemu_set_irq(s->isa[irq], level);
+}
+
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+ ISABus *isa_bus;
+ qemu_irq *i8259_out_irq;
- if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
- pci_address_space_io(dev), errp)) {
+ isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
+ pci_address_space_io(dev), errp);
+ if (!isa_bus) {
return;
}
+ qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
+ "isa", ISA_NUM_IRQS);
+ qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
+ "intr", 1);
+
memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
"reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
&s->rcr_mem, 1);
+ /* initialize i8259 pic */
+ i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+ s->isa = i8259_init(isa_bus, *i8259_out_irq);
+
+ /* initialize ISA irqs */
+ isa_bus_irqs(isa_bus, s->isa);
+
piix4_dev = dev;
}
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
- PCIDevice *d;
-
- d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
- return d->devfn;
-}
-
static void piix4_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..7d25ab6c23 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -97,7 +97,7 @@ typedef struct {
SysBusDevice parent_obj;
MIPSCPSState cps;
- qemu_irq *i8259;
+ qemu_irq i8259[16];
} MaltaState;
static ISADevice *pit;
@@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
int64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
- qemu_irq *isa_irq;
qemu_irq cbus_irq, i8259_irq;
+ PCIDevice *pci;
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
@@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
/* Board ID = 0x420 (Malta Board with CoreLV) */
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
- /*
- * We have a circular dependency problem: pci_bus depends on isa_irq,
- * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
- * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
- * qemu_irq_proxy() adds an extra bit of indirection, allowing us
- * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
- */
- isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
/* Northbridge */
- pci_bus = gt64120_register(isa_irq);
+ pci_bus = gt64120_register(s->i8259);
/* Southbridge */
ide_drive_get(hd, ARRAY_SIZE(hd));
- piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, "PIIX4");
+ dev = DEVICE(pci);
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ piix4_devfn = pci->devfn;
- /*
- * Interrupt controller
- * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
- */
- s->i8259 = i8259_init(isa_bus, i8259_irq);
+ /* Interrupt controller */
+ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+ for (int i = 0; i < ISA_NUM_IRQS; i++) {
+ s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+ }
- isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 37bfd95113..374f3e8835 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
Remove i8259 instanciated in malta board, to not have it twice.
We can also remove the now unused piix4_init() function.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
hw/mips/mips_malta.c | 32 +++++++++++++-------------------
include/hw/i386/pc.h | 1 -
3 files changed, 45 insertions(+), 31 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index d0b18e0586..9c37c85ae2 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
@@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
typedef struct PIIX4State {
PCIDevice dev;
+ qemu_irq cpu_intr;
+ qemu_irq *isa;
/* Reset Control Register */
MemoryRegion rcr_mem;
@@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
}
};
+static void piix4_request_i8259_irq(void *opaque, int irq, int level)
+{
+ PIIX4State *s = opaque;
+ qemu_set_irq(s->cpu_intr, level);
+}
+
+static void piix4_set_i8259_irq(void *opaque, int irq, int level)
+{
+ PIIX4State *s = opaque;
+ qemu_set_irq(s->isa[irq], level);
+}
+
static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
unsigned int len)
{
@@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
static void piix4_realize(PCIDevice *dev, Error **errp)
{
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
+ ISABus *isa_bus;
+ qemu_irq *i8259_out_irq;
- if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
- pci_address_space_io(dev), errp)) {
+ isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
+ pci_address_space_io(dev), errp);
+ if (!isa_bus) {
return;
}
+ qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
+ "isa", ISA_NUM_IRQS);
+ qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
+ "intr", 1);
+
memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
"reset-control", 1);
memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
&s->rcr_mem, 1);
+ /* initialize i8259 pic */
+ i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
+ s->isa = i8259_init(isa_bus, *i8259_out_irq);
+
+ /* initialize ISA irqs */
+ isa_bus_irqs(isa_bus, s->isa);
+
piix4_dev = dev;
}
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
- PCIDevice *d;
-
- d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
- return d->devfn;
-}
-
static void piix4_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..7d25ab6c23 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -97,7 +97,7 @@ typedef struct {
SysBusDevice parent_obj;
MIPSCPSState cps;
- qemu_irq *i8259;
+ qemu_irq i8259[16];
} MaltaState;
static ISADevice *pit;
@@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
int64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
- qemu_irq *isa_irq;
qemu_irq cbus_irq, i8259_irq;
+ PCIDevice *pci;
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
@@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
/* Board ID = 0x420 (Malta Board with CoreLV) */
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
- /*
- * We have a circular dependency problem: pci_bus depends on isa_irq,
- * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
- * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
- * qemu_irq_proxy() adds an extra bit of indirection, allowing us
- * to resolve the isa_irq -> i8259 dependency after i8259 is initialized.
- */
- isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
/* Northbridge */
- pci_bus = gt64120_register(isa_irq);
+ pci_bus = gt64120_register(s->i8259);
/* Southbridge */
ide_drive_get(hd, ARRAY_SIZE(hd));
- piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, "PIIX4");
+ dev = DEVICE(pci);
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ piix4_devfn = pci->devfn;
- /*
- * Interrupt controller
- * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
- */
- s->i8259 = i8259_init(isa_bus, i8259_irq);
+ /* Interrupt controller */
+ qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
+ for (int i = 0; i < ISA_NUM_IRQS; i++) {
+ s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
+ }
- isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 37bfd95113..374f3e8835 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCIBus *find_i440fx(void);
/* piix4.c */
extern PCIDevice *piix4_dev;
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()"
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Stefano Stabellini, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This function isn't used anymore.
This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/irq.c | 14 --------------
include/hw/irq.h | 5 -----
2 files changed, 19 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 7cc0295d0e..fb3045b912 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
return qemu_allocate_irq(qemu_splitirq, s, 0);
}
-static void proxy_irq_handler(void *opaque, int n, int level)
-{
- qemu_irq **target = opaque;
-
- if (*target) {
- qemu_set_irq((*target)[n], level);
- }
-}
-
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
-{
- return qemu_allocate_irqs(proxy_irq_handler, target, n);
-}
-
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
{
int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index fe527f6f51..24ba0ece11 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
*/
qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
- * may be set later.
- */
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-
/* For internal use in qtest. Similar to qemu_irq_split, but operating
on an existing vector of qemu_irq. */
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()"
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Thomas Huth, Stefano Stabellini, Marcel Apfelbaum,
Michael S. Tsirkin, Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
This function isn't used anymore.
This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
hw/core/irq.c | 14 --------------
include/hw/irq.h | 5 -----
2 files changed, 19 deletions(-)
diff --git a/hw/core/irq.c b/hw/core/irq.c
index 7cc0295d0e..fb3045b912 100644
--- a/hw/core/irq.c
+++ b/hw/core/irq.c
@@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
return qemu_allocate_irq(qemu_splitirq, s, 0);
}
-static void proxy_irq_handler(void *opaque, int n, int level)
-{
- qemu_irq **target = opaque;
-
- if (*target) {
- qemu_set_irq((*target)[n], level);
- }
-}
-
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
-{
- return qemu_allocate_irqs(proxy_irq_handler, target, n);
-}
-
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n)
{
int i;
diff --git a/include/hw/irq.h b/include/hw/irq.h
index fe527f6f51..24ba0ece11 100644
--- a/include/hw/irq.h
+++ b/include/hw/irq.h
@@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
*/
qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
-/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
- * may be set later.
- */
-qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
-
/* For internal use in qtest. Similar to qemu_irq_split, but operating
on an existing vector of qemu_irq. */
void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
--
2.21.0
_______________________________________________
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Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 1 -
hw/mips/mips_malta.c | 2 +-
include/hw/isa/isa.h | 2 ++
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9c37c85ae2..ac9383a658 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,6 @@ typedef struct PIIX4State {
uint8_t rcr;
} PIIX4State;
-#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
#define PIIX4_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 7d25ab6c23..e499b7a6bb 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
ide_drive_get(hd, ARRAY_SIZE(hd));
pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
- true, "PIIX4");
+ true, TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(pci);
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
piix4_devfn = pci->devfn;
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 018ada4f6f..79f703fd6c 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}
+#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
+
#endif
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 1 -
hw/mips/mips_malta.c | 2 +-
include/hw/isa/isa.h | 2 ++
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 9c37c85ae2..ac9383a658 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -45,7 +45,6 @@ typedef struct PIIX4State {
uint8_t rcr;
} PIIX4State;
-#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
#define PIIX4_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 7d25ab6c23..e499b7a6bb 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
ide_drive_get(hd, ARRAY_SIZE(hd));
pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
- true, "PIIX4");
+ true, TYPE_PIIX4_PCI_DEVICE);
dev = DEVICE(pci);
isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
piix4_devfn = pci->devfn;
diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
index 018ada4f6f..79f703fd6c 100644
--- a/include/hw/isa/isa.h
+++ b/include/hw/isa/isa.h
@@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
}
+#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
+
#endif
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Remove i8257 instantiated in malta board, to not have it twice.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 4 ++++
hw/mips/mips_malta.c | 2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index ac9383a658..0b24d8323c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -29,6 +29,7 @@
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
+#include "hw/dma/i8257.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
+ /* DMA */
+ i8257_dma_init(isa_bus, 0);
+
piix4_dev = dev;
}
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index e499b7a6bb..df247177ca 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,7 +28,6 @@
#include "cpu.h"
#include "hw/i386/pc.h"
#include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
#include "net/net.h"
#include "hw/boards.h"
@@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
- i8257_dma_init(isa_bus, 0);
mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Remove i8257 instantiated in malta board, to not have it twice.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
[PMD: rebased]
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 4 ++++
hw/mips/mips_malta.c | 2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index ac9383a658..0b24d8323c 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -29,6 +29,7 @@
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
+#include "hw/dma/i8257.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
+ /* DMA */
+ i8257_dma_init(isa_bus, 0);
+
piix4_dev = dev;
}
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index e499b7a6bb..df247177ca 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,7 +28,6 @@
#include "cpu.h"
#include "hw/i386/pc.h"
#include "hw/isa/superio.h"
-#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
#include "net/net.h"
#include "hw/boards.h"
@@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
- i8257_dma_init(isa_bus, 0);
mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 07/20] piix4: Add a i8254 PIT Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Remove i8254 instanciated in malta board, to not have it twice.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: Fixed typo (thuth)
---
hw/isa/piix4.c | 4 ++++
hw/mips/mips_malta.c | 4 ----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0b24d8323c..dda8bc3f90 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -30,6 +30,7 @@
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/dma/i8257.h"
+#include "hw/timer/i8254.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -168,6 +169,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
+ /* initialize pit */
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
/* DMA */
i8257_dma_init(isa_bus, 0);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index df247177ca..16d7a0e785 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -45,7 +45,6 @@
#include "hw/loader.h"
#include "elf.h"
#include "hw/timer/mc146818rtc.h"
-#include "hw/timer/i8254.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
@@ -99,8 +98,6 @@ typedef struct {
qemu_irq i8259[16];
} MaltaState;
-static ISADevice *pit;
-
static struct _loaderparams {
int ram_size, ram_low_size;
const char *kernel_filename;
@@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
- pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 07/20] piix4: Add a i8254 PIT Controller as specified in datasheet
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Hervé Poussineau <hpoussin@reactos.org>
Remove i8254 instanciated in malta board, to not have it twice.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-10-hpoussin@reactos.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: Fixed typo (thuth)
---
hw/isa/piix4.c | 4 ++++
hw/mips/mips_malta.c | 4 ----
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 0b24d8323c..dda8bc3f90 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -30,6 +30,7 @@
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/dma/i8257.h"
+#include "hw/timer/i8254.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -168,6 +169,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* initialize ISA irqs */
isa_bus_irqs(isa_bus, s->isa);
+ /* initialize pit */
+ i8254_pit_init(isa_bus, 0x40, 0, NULL);
+
/* DMA */
i8257_dma_init(isa_bus, 0);
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index df247177ca..16d7a0e785 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -45,7 +45,6 @@
#include "hw/loader.h"
#include "elf.h"
#include "hw/timer/mc146818rtc.h"
-#include "hw/timer/i8254.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
@@ -99,8 +98,6 @@ typedef struct {
qemu_irq i8259[16];
} MaltaState;
-static ISADevice *pit;
-
static struct _loaderparams {
int ram_size, ram_low_size;
const char *kernel_filename;
@@ -1428,7 +1425,6 @@ void mips_malta_init(MachineState *machine)
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
- pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 08/20] piix4: Add a MC146818 RTC Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Remove mc146818rtc instanciated in malta board, to not have it twice.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
[PMD: rebased, set RTC base_year to 2000]
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 3 ++-
hw/acpi/piix4.c | 2 +-
hw/i386/acpi-build.c | 3 +--
hw/i386/pc_piix.c | 1 +
hw/isa/piix4.c | 22 ++++++++++++++++++++++
hw/mips/mips_malta.c | 4 +---
include/hw/acpi/piix4.h | 6 ------
include/hw/i386/pc.h | 6 ------
include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
9 files changed, 48 insertions(+), 19 deletions(-)
delete mode 100644 include/hw/acpi/piix4.h
create mode 100644 include/hw/southbridge/piix.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c9f625fc2e..556f58bd8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
F: hw/acpi/ich9.c
F: include/hw/acpi/ich9.h
-F: include/hw/acpi/piix4.h
+F: include/hw/southbridge/piix.h
F: hw/misc/sga.c
F: hw/isa/apm.c
F: include/hw/isa/apm.h
@@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
S: Maintained
F: hw/isa/piix4.c
+F: include/hw/southbridge/piix.h
Firmware configuration (fw_cfg)
M: Philippe Mathieu-Daudé <philmd@redhat.com>
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 4e079b39bd..2efd1605b8 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/isa/apm.h"
#include "hw/i2c/pm_smbus.h"
@@ -32,7 +33,6 @@
#include "qapi/error.h"
#include "qemu/range.h"
#include "exec/address-spaces.h"
-#include "hw/acpi/piix4.h"
#include "hw/acpi/pcihp.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/cpu.h"
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1d077a7cb7..56c427f772 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -34,7 +34,6 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu.h"
-#include "hw/acpi/piix4.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/isa/isa.h"
@@ -52,7 +51,7 @@
#include "sysemu/reset.h"
/* Supported chipsets: */
-#include "hw/acpi/piix4.h"
+#include "hw/southbridge/piix.h"
#include "hw/acpi/pcihp.h"
#include "hw/i386/ich9.h"
#include "hw/pci/pci_bus.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6824b72124..431965d921 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
#include "hw/loader.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
+#include "hw/southbridge/piix.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/pci/pci.h"
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index dda8bc3f90..b35b8a5f71 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
@@ -31,6 +32,7 @@
#include "hw/sysbus.h"
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
+#include "hw/timer/mc146818rtc.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -42,6 +44,7 @@ typedef struct PIIX4State {
qemu_irq cpu_intr;
qemu_irq *isa;
+ RTCState rtc;
/* Reset Control Register */
MemoryRegion rcr_mem;
uint8_t rcr;
@@ -145,6 +148,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
ISABus *isa_bus;
qemu_irq *i8259_out_irq;
+ Error *err = NULL;
isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp);
@@ -175,9 +179,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* DMA */
i8257_dma_init(isa_bus, 0);
+ /* RTC */
+ qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
+ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+ object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+
piix4_dev = dev;
}
+static void piix4_init(Object *obj)
+{
+ PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+ object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
+}
+
static void piix4_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -202,6 +223,7 @@ static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIX4State),
+ .instance_init = piix4_init,
.class_init = piix4_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 16d7a0e785..528c34a1c3 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -26,7 +26,7 @@
#include "qemu/units.h"
#include "qemu-common.h"
#include "cpu.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/isa/superio.h"
#include "hw/char/serial.h"
#include "net/net.h"
@@ -44,7 +44,6 @@
#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
-#include "hw/timer/mc146818rtc.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
@@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
- mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
deleted file mode 100644
index 028bb53e3d..0000000000
--- a/include/hw/acpi/piix4.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef HW_ACPI_PIIX4_H
-#define HW_ACPI_PIIX4_H
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 374f3e8835..cf922fd162 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -248,12 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
#define PORT92_A20_LINE "a20"
-/* acpi_piix.c */
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- int smm_enabled, DeviceState **piix4_pm);
-
/* hpet.c */
extern int no_hpet;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
new file mode 100644
index 0000000000..b8ce26fec4
--- /dev/null
+++ b/include/hw/southbridge/piix.h
@@ -0,0 +1,20 @@
+/*
+ * QEMU PIIX South Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_SOUTHBRIDGE_PIIX_H
+#define HW_SOUTHBRIDGE_PIIX_H
+
+#define TYPE_PIIX4_PM "PIIX4_PM"
+
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq, qemu_irq smi_irq,
+ int smm_enabled, DeviceState **piix4_pm);
+
+#endif
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 08/20] piix4: Add a MC146818 RTC Controller as specified in datasheet
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Remove mc146818rtc instanciated in malta board, to not have it twice.
Acked-by: Michael S. Tsirkin <mst@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
Message-Id: <20171216090228.28505-13-hpoussin@reactos.org>
[PMD: rebased, set RTC base_year to 2000]
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 3 ++-
hw/acpi/piix4.c | 2 +-
hw/i386/acpi-build.c | 3 +--
hw/i386/pc_piix.c | 1 +
hw/isa/piix4.c | 22 ++++++++++++++++++++++
hw/mips/mips_malta.c | 4 +---
include/hw/acpi/piix4.h | 6 ------
include/hw/i386/pc.h | 6 ------
include/hw/southbridge/piix.h | 20 ++++++++++++++++++++
9 files changed, 48 insertions(+), 19 deletions(-)
delete mode 100644 include/hw/acpi/piix4.h
create mode 100644 include/hw/southbridge/piix.h
diff --git a/MAINTAINERS b/MAINTAINERS
index c9f625fc2e..556f58bd8c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1235,7 +1235,7 @@ F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
F: hw/acpi/ich9.c
F: include/hw/acpi/ich9.h
-F: include/hw/acpi/piix4.h
+F: include/hw/southbridge/piix.h
F: hw/misc/sga.c
F: hw/isa/apm.c
F: include/hw/isa/apm.h
@@ -1720,6 +1720,7 @@ M: Hervé Poussineau <hpoussin@reactos.org>
M: Philippe Mathieu-Daudé <f4bug@amsat.org>
S: Maintained
F: hw/isa/piix4.c
+F: include/hw/southbridge/piix.h
Firmware configuration (fw_cfg)
M: Philippe Mathieu-Daudé <philmd@redhat.com>
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 4e079b39bd..2efd1605b8 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -21,6 +21,7 @@
#include "qemu/osdep.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/isa/apm.h"
#include "hw/i2c/pm_smbus.h"
@@ -32,7 +33,6 @@
#include "qapi/error.h"
#include "qemu/range.h"
#include "exec/address-spaces.h"
-#include "hw/acpi/piix4.h"
#include "hw/acpi/pcihp.h"
#include "hw/acpi/cpu_hotplug.h"
#include "hw/acpi/cpu.h"
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 1d077a7cb7..56c427f772 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -34,7 +34,6 @@
#include "hw/acpi/acpi-defs.h"
#include "hw/acpi/acpi.h"
#include "hw/acpi/cpu.h"
-#include "hw/acpi/piix4.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/acpi/bios-linker-loader.h"
#include "hw/isa/isa.h"
@@ -52,7 +51,7 @@
#include "sysemu/reset.h"
/* Supported chipsets: */
-#include "hw/acpi/piix4.h"
+#include "hw/southbridge/piix.h"
#include "hw/acpi/pcihp.h"
#include "hw/i386/ich9.h"
#include "hw/pci/pci_bus.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 6824b72124..431965d921 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
#include "hw/loader.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
+#include "hw/southbridge/piix.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
#include "hw/pci/pci.h"
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index dda8bc3f90..b35b8a5f71 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
@@ -31,6 +32,7 @@
#include "hw/sysbus.h"
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
+#include "hw/timer/mc146818rtc.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -42,6 +44,7 @@ typedef struct PIIX4State {
qemu_irq cpu_intr;
qemu_irq *isa;
+ RTCState rtc;
/* Reset Control Register */
MemoryRegion rcr_mem;
uint8_t rcr;
@@ -145,6 +148,7 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
PIIX4State *s = PIIX4_PCI_DEVICE(dev);
ISABus *isa_bus;
qemu_irq *i8259_out_irq;
+ Error *err = NULL;
isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
pci_address_space_io(dev), errp);
@@ -175,9 +179,26 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
/* DMA */
i8257_dma_init(isa_bus, 0);
+ /* RTC */
+ qdev_set_parent_bus(DEVICE(&s->rtc), BUS(isa_bus));
+ qdev_prop_set_int32(DEVICE(&s->rtc), "base_year", 2000);
+ object_property_set_bool(OBJECT(&s->rtc), true, "realized", &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
+ isa_init_irq(ISA_DEVICE(&s->rtc), &s->rtc.irq, RTC_ISA_IRQ);
+
piix4_dev = dev;
}
+static void piix4_init(Object *obj)
+{
+ PIIX4State *s = PIIX4_PCI_DEVICE(obj);
+
+ object_initialize(&s->rtc, sizeof(s->rtc), TYPE_MC146818_RTC);
+}
+
static void piix4_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -202,6 +223,7 @@ static const TypeInfo piix4_info = {
.name = TYPE_PIIX4_PCI_DEVICE,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(PIIX4State),
+ .instance_init = piix4_init,
.class_init = piix4_class_init,
.interfaces = (InterfaceInfo[]) {
{ INTERFACE_CONVENTIONAL_PCI_DEVICE },
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 16d7a0e785..528c34a1c3 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -26,7 +26,7 @@
#include "qemu/units.h"
#include "qemu-common.h"
#include "cpu.h"
-#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/isa/superio.h"
#include "hw/char/serial.h"
#include "net/net.h"
@@ -44,7 +44,6 @@
#include "hw/irq.h"
#include "hw/loader.h"
#include "elf.h"
-#include "hw/timer/mc146818rtc.h"
#include "exec/address-spaces.h"
#include "hw/sysbus.h" /* SysBusDevice */
#include "qemu/host-utils.h"
@@ -1425,7 +1424,6 @@ void mips_malta_init(MachineState *machine)
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
- mc146818_rtc_init(isa_bus, 2000, NULL);
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
diff --git a/include/hw/acpi/piix4.h b/include/hw/acpi/piix4.h
deleted file mode 100644
index 028bb53e3d..0000000000
--- a/include/hw/acpi/piix4.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef HW_ACPI_PIIX4_H
-#define HW_ACPI_PIIX4_H
-
-#define TYPE_PIIX4_PM "PIIX4_PM"
-
-#endif
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 374f3e8835..cf922fd162 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -248,12 +248,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
#define PORT92_A20_LINE "a20"
-/* acpi_piix.c */
-
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
- qemu_irq sci_irq, qemu_irq smi_irq,
- int smm_enabled, DeviceState **piix4_pm);
-
/* hpet.c */
extern int no_hpet;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
new file mode 100644
index 0000000000..b8ce26fec4
--- /dev/null
+++ b/include/hw/southbridge/piix.h
@@ -0,0 +1,20 @@
+/*
+ * QEMU PIIX South Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_SOUTHBRIDGE_PIIX_H
+#define HW_SOUTHBRIDGE_PIIX_H
+
+#define TYPE_PIIX4_PM "PIIX4_PM"
+
+I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+ qemu_irq sci_irq, qemu_irq smi_irq,
+ int smm_enabled, DeviceState **piix4_pm);
+
+#endif
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
In the next commit we'll refactor the PIIX4 code out of
mips_malta_init(). As a preliminary step, add the 'ide_drives'
variable and create the drive array dynamically.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/mips/mips_malta.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 528c34a1c3..774bb810f6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
- DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+ DriveInfo **hd;
int fl_idx = 0;
int be;
@@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
pci_bus = gt64120_register(s->i8259);
/* Southbridge */
- ide_drive_get(hd, ARRAY_SIZE(hd));
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
true, TYPE_PIIX4_PCI_DEVICE);
@@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
}
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+ g_free(hd);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
In the next commit we'll refactor the PIIX4 code out of
mips_malta_init(). As a preliminary step, add the 'ide_drives'
variable and create the drive array dynamically.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/mips/mips_malta.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 528c34a1c3..774bb810f6 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
- DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
+ const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
+ DriveInfo **hd;
int fl_idx = 0;
int be;
@@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
pci_bus = gt64120_register(s->i8259);
/* Southbridge */
- ide_drive_get(hd, ARRAY_SIZE(hd));
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
true, TYPE_PIIX4_PCI_DEVICE);
@@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
}
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
+ g_free(hd);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
isa_get_irq(NULL, 9), NULL, 0, NULL);
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 10/20] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
The Malta board instantiate a PIIX4 chipset doing various
calls. Refactor all those related calls into a single
function: piix4_create().
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 774bb810f6..0d4312840b 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
}
}
+static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+ I2CBus **smbus, size_t ide_buses)
+{
+ const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+ DriveInfo **hd;
+ PCIDevice *pci;
+ DeviceState *dev;
+
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, TYPE_PIIX4_PCI_DEVICE);
+ dev = DEVICE(pci);
+ if (isa_bus) {
+ *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ }
+
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
+ pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+ g_free(hd);
+ pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+ if (smbus) {
+ *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+ isa_get_irq(NULL, 9), NULL, 0, NULL);
+ }
+
+ return dev;
+}
+
static
void mips_malta_init(MachineState *machine)
{
@@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq cbus_irq, i8259_irq;
- PCIDevice *pci;
- int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
- const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
- DriveInfo **hd;
int fl_idx = 0;
int be;
@@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
pci_bus = gt64120_register(s->i8259);
/* Southbridge */
- hd = g_new(DriveInfo *, ide_drives);
- ide_drive_get(hd, ide_drives);
-
- pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
- true, TYPE_PIIX4_PCI_DEVICE);
- dev = DEVICE(pci);
- isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
- piix4_devfn = pci->devfn;
+ dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
@@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
}
- pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
- g_free(hd);
- pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
- smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
- isa_get_irq(NULL, 9), NULL, 0, NULL);
-
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 10/20] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
The Malta board instantiate a PIIX4 chipset doing various
calls. Refactor all those related calls into a single
function: piix4_create().
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/mips/mips_malta.c | 47 +++++++++++++++++++++++++++-----------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 774bb810f6..0d4312840b 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,6 +1210,34 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
}
}
+static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+ I2CBus **smbus, size_t ide_buses)
+{
+ const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+ DriveInfo **hd;
+ PCIDevice *pci;
+ DeviceState *dev;
+
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, TYPE_PIIX4_PCI_DEVICE);
+ dev = DEVICE(pci);
+ if (isa_bus) {
+ *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ }
+
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
+ pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+ g_free(hd);
+ pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+ if (smbus) {
+ *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+ isa_get_irq(NULL, 9), NULL, 0, NULL);
+ }
+
+ return dev;
+}
+
static
void mips_malta_init(MachineState *machine)
{
@@ -1231,12 +1259,8 @@ void mips_malta_init(MachineState *machine)
PCIBus *pci_bus;
ISABus *isa_bus;
qemu_irq cbus_irq, i8259_irq;
- PCIDevice *pci;
- int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
- const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
- DriveInfo **hd;
int fl_idx = 0;
int be;
@@ -1407,14 +1431,7 @@ void mips_malta_init(MachineState *machine)
pci_bus = gt64120_register(s->i8259);
/* Southbridge */
- hd = g_new(DriveInfo *, ide_drives);
- ide_drive_get(hd, ide_drives);
-
- pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
- true, TYPE_PIIX4_PCI_DEVICE);
- dev = DEVICE(pci);
- isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
- piix4_devfn = pci->devfn;
+ dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
@@ -1422,12 +1439,6 @@ void mips_malta_init(MachineState *machine)
s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
}
- pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
- g_free(hd);
- pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
- smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
- isa_get_irq(NULL, 9), NULL, 0, NULL);
-
/* generate SPD EEPROM data */
generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
generate_eeprom_serial(&smbus_eeprom_buf[6 * 256]);
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 11/20] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Now that we properly refactored the piix4_create() function, let's
move it to hw/isa/piix4.c where it belongs, so it can be reused
on other places.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 30 ++++++++++++++++++++++++++++++
hw/mips/gt64xxx_pci.c | 1 +
hw/mips/mips_malta.c | 28 ----------------------------
include/hw/i386/pc.h | 2 --
include/hw/southbridge/piix.h | 6 ++++++
5 files changed, 37 insertions(+), 30 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index b35b8a5f71..f4644b63cc 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -27,12 +27,14 @@
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
#include "hw/timer/mc146818rtc.h"
+#include "hw/ide.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -237,3 +239,31 @@ static void piix4_register_types(void)
}
type_init(piix4_register_types)
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+ I2CBus **smbus, size_t ide_buses)
+{
+ size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+ DriveInfo **hd;
+ PCIDevice *pci;
+ DeviceState *dev;
+
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, TYPE_PIIX4_PCI_DEVICE);
+ dev = DEVICE(pci);
+ if (isa_bus) {
+ *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ }
+
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
+ pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+ g_free(hd);
+ pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+ if (smbus) {
+ *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+ isa_get_irq(NULL, 9), NULL, 0, NULL);
+ }
+
+ return dev;
+}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index f325bd6c1c..c277398c0d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -28,6 +28,7 @@
#include "hw/mips/mips.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
#include "migration/vmstate.h"
#include "hw/i386/pc.h"
#include "hw/irq.h"
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 0d4312840b..477a4725c0 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
}
}
-static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
- I2CBus **smbus, size_t ide_buses)
-{
- const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
- DriveInfo **hd;
- PCIDevice *pci;
- DeviceState *dev;
-
- pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
- true, TYPE_PIIX4_PCI_DEVICE);
- dev = DEVICE(pci);
- if (isa_bus) {
- *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
- }
-
- hd = g_new(DriveInfo *, ide_drives);
- ide_drive_get(hd, ide_drives);
- pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
- g_free(hd);
- pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
- if (smbus) {
- *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
- isa_get_irq(NULL, 9), NULL, 0, NULL);
- }
-
- return dev;
-}
-
static
void mips_malta_init(MachineState *machine)
{
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index cf922fd162..848078bacc 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -278,8 +278,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
MemoryRegion *ram_memory);
PCIBus *find_i440fx(void);
-/* piix4.c */
-extern PCIDevice *piix4_dev;
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b8ce26fec4..add352456b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -2,6 +2,7 @@
* QEMU PIIX South Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+extern PCIDevice *piix4_dev;
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+ I2CBus **smbus, size_t ide_buses);
+
#endif
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 11/20] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Now that we properly refactored the piix4_create() function, let's
move it to hw/isa/piix4.c where it belongs, so it can be reused
on other places.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/isa/piix4.c | 30 ++++++++++++++++++++++++++++++
hw/mips/gt64xxx_pci.c | 1 +
hw/mips/mips_malta.c | 28 ----------------------------
include/hw/i386/pc.h | 2 --
include/hw/southbridge/piix.h | 6 ++++++
5 files changed, 37 insertions(+), 30 deletions(-)
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index b35b8a5f71..f4644b63cc 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -27,12 +27,14 @@
#include "qapi/error.h"
#include "hw/irq.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "hw/dma/i8257.h"
#include "hw/timer/i8254.h"
#include "hw/timer/mc146818rtc.h"
+#include "hw/ide.h"
#include "migration/vmstate.h"
#include "sysemu/reset.h"
#include "sysemu/runstate.h"
@@ -237,3 +239,31 @@ static void piix4_register_types(void)
}
type_init(piix4_register_types)
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+ I2CBus **smbus, size_t ide_buses)
+{
+ size_t ide_drives = ide_buses * MAX_IDE_DEVS;
+ DriveInfo **hd;
+ PCIDevice *pci;
+ DeviceState *dev;
+
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, TYPE_PIIX4_PCI_DEVICE);
+ dev = DEVICE(pci);
+ if (isa_bus) {
+ *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ }
+
+ hd = g_new(DriveInfo *, ide_drives);
+ ide_drive_get(hd, ide_drives);
+ pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
+ g_free(hd);
+ pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
+ if (smbus) {
+ *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
+ isa_get_irq(NULL, 9), NULL, 0, NULL);
+ }
+
+ return dev;
+}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index f325bd6c1c..c277398c0d 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -28,6 +28,7 @@
#include "hw/mips/mips.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
#include "migration/vmstate.h"
#include "hw/i386/pc.h"
#include "hw/irq.h"
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 0d4312840b..477a4725c0 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -1210,34 +1210,6 @@ static void mips_create_cpu(MachineState *ms, MaltaState *s,
}
}
-static DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
- I2CBus **smbus, size_t ide_buses)
-{
- const size_t ide_drives = ide_buses * MAX_IDE_DEVS;
- DriveInfo **hd;
- PCIDevice *pci;
- DeviceState *dev;
-
- pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
- true, TYPE_PIIX4_PCI_DEVICE);
- dev = DEVICE(pci);
- if (isa_bus) {
- *isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
- }
-
- hd = g_new(DriveInfo *, ide_drives);
- ide_drive_get(hd, ide_drives);
- pci_piix4_ide_init(pci_bus, hd, pci->devfn + 1);
- g_free(hd);
- pci_create_simple(pci_bus, pci->devfn + 2, "piix4-usb-uhci");
- if (smbus) {
- *smbus = piix4_pm_init(pci_bus, pci->devfn + 3, 0x1100,
- isa_get_irq(NULL, 9), NULL, 0, NULL);
- }
-
- return dev;
-}
-
static
void mips_malta_init(MachineState *machine)
{
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index cf922fd162..848078bacc 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -278,8 +278,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
MemoryRegion *ram_memory);
PCIBus *find_i440fx(void);
-/* piix4.c */
-extern PCIDevice *piix4_dev;
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index b8ce26fec4..add352456b 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -2,6 +2,7 @@
* QEMU PIIX South Bridge Emulation
*
* Copyright (c) 2006 Fabrice Bellard
+ * Copyright (c) 2018 Hervé Poussineau
*
* This work is licensed under the terms of the GNU GPL, version 2 or later.
* See the COPYING file in the top-level directory.
@@ -17,4 +18,9 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+extern PCIDevice *piix4_dev;
+
+DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
+ I2CBus **smbus, size_t ide_buses);
+
#endif
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 12/20] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefano Stabellini, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
These devices implemented their load_state_old() handler 10 years
ago, previous to QEMU v0.12.
Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
we can drop this code.
Note: the mips_r4k machine started to use the i8254 device just
after QEMU v0.5.0, but the MIPS machine types are not versioned,
so there is no migration compatibility issue removing this handler.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/acpi/piix4.c | 40 ---------------------------------
hw/intc/apic_common.c | 49 -----------------------------------------
hw/pci-host/piix.c | 25 ---------------------
hw/timer/i8254_common.c | 40 ---------------------------------
4 files changed, 154 deletions(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 2efd1605b8..93aec2dd2c 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -41,7 +41,6 @@
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/acpi_dev_interface.h"
#include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "hw/core/cpu.h"
#include "trace.h"
@@ -204,43 +203,6 @@ static const VMStateDescription vmstate_pci_status = {
}
};
-static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- PIIX4PMState *s = opaque;
- int ret, i;
- uint16_t temp;
-
- ret = pci_device_load(PCI_DEVICE(s), f);
- if (ret < 0) {
- return ret;
- }
- qemu_get_be16s(f, &s->ar.pm1.evt.sts);
- qemu_get_be16s(f, &s->ar.pm1.evt.en);
- qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
-
- ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
- if (ret) {
- return ret;
- }
-
- timer_get(f, s->ar.tmr.timer);
- qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
-
- qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
- for (i = 0; i < 3; i++) {
- qemu_get_be16s(f, &temp);
- }
-
- qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
- for (i = 0; i < 3; i++) {
- qemu_get_be16s(f, &temp);
- }
-
- ret = vmstate_load_state(f, &vmstate_pci_status,
- &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
- return ret;
-}
-
static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
{
PIIX4PMState *s = opaque;
@@ -312,8 +274,6 @@ static const VMStateDescription vmstate_acpi = {
.name = "piix4_pm",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 1,
- .load_state_old = acpi_load_old,
.post_load = vmstate_acpi_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index aafd8e0e33..375cb6abe9 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -31,7 +31,6 @@
#include "sysemu/kvm.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
static int apic_irq_delivered;
@@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
apic_init_reset(dev);
}
-/* This function is only used for old state version 1 and 2 */
-static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- APICCommonState *s = opaque;
- APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
- int i;
-
- if (version_id > 2) {
- return -EINVAL;
- }
-
- /* XXX: what if the base changes? (registered memory regions) */
- qemu_get_be32s(f, &s->apicbase);
- qemu_get_8s(f, &s->id);
- qemu_get_8s(f, &s->arb_id);
- qemu_get_8s(f, &s->tpr);
- qemu_get_be32s(f, &s->spurious_vec);
- qemu_get_8s(f, &s->log_dest);
- qemu_get_8s(f, &s->dest_mode);
- for (i = 0; i < 8; i++) {
- qemu_get_be32s(f, &s->isr[i]);
- qemu_get_be32s(f, &s->tmr[i]);
- qemu_get_be32s(f, &s->irr[i]);
- }
- for (i = 0; i < APIC_LVT_NB; i++) {
- qemu_get_be32s(f, &s->lvt[i]);
- }
- qemu_get_be32s(f, &s->esr);
- qemu_get_be32s(f, &s->icr[0]);
- qemu_get_be32s(f, &s->icr[1]);
- qemu_get_be32s(f, &s->divide_conf);
- s->count_shift = qemu_get_be32(f);
- qemu_get_be32s(f, &s->initial_count);
- s->initial_count_load_time = qemu_get_be64(f);
- s->next_time = qemu_get_be64(f);
-
- if (version_id >= 2) {
- s->timer_expiry = qemu_get_be64(f);
- }
-
- if (info->post_load) {
- info->post_load(s);
- }
- return 0;
-}
-
static const VMStateDescription vmstate_apic_common;
static void apic_common_realize(DeviceState *dev, Error **errp)
@@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
.name = "apic",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 1,
- .load_state_old = apic_load_old,
.pre_load = apic_pre_load,
.pre_save = apic_dispatch_pre_save,
.post_load = apic_dispatch_post_load,
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 135c645535..2f4cbcbfe9 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -33,7 +33,6 @@
#include "qapi/error.h"
#include "qemu/range.h"
#include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "hw/pci-host/pam.h"
#include "sysemu/reset.h"
@@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
}
}
-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
-{
- PCII440FXState *d = opaque;
- PCIDevice *pd = PCI_DEVICE(d);
- int ret, i;
- uint8_t smm_enabled;
-
- ret = pci_device_load(pd, f);
- if (ret < 0)
- return ret;
- i440fx_update_memory_mappings(d);
- qemu_get_8s(f, &smm_enabled);
-
- if (version_id == 2) {
- for (i = 0; i < PIIX_NUM_PIRQS; i++) {
- qemu_get_be32(f); /* dummy load for compatibility */
- }
- }
-
- return 0;
-}
-
static int i440fx_post_load(void *opaque, int version_id)
{
PCII440FXState *d = opaque;
@@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
.name = "I440FX",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 1,
- .load_state_old = i440fx_load_old,
.post_load = i440fx_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 57bf10cc94..050875b497 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -29,7 +29,6 @@
#include "qemu/timer.h"
#include "hw/timer/i8254.h"
#include "hw/timer/i8254_internal.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
/* val must be 0 or 1 */
@@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
}
};
-static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- PITCommonState *pit = opaque;
- PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
- PITChannelState *s;
- int i;
-
- if (version_id != 1) {
- return -EINVAL;
- }
-
- for (i = 0; i < 3; i++) {
- s = &pit->channels[i];
- s->count = qemu_get_be32(f);
- qemu_get_be16s(f, &s->latched_count);
- qemu_get_8s(f, &s->count_latched);
- qemu_get_8s(f, &s->status_latched);
- qemu_get_8s(f, &s->status);
- qemu_get_8s(f, &s->read_state);
- qemu_get_8s(f, &s->write_state);
- qemu_get_8s(f, &s->write_latch);
- qemu_get_8s(f, &s->rw_mode);
- qemu_get_8s(f, &s->mode);
- qemu_get_8s(f, &s->bcd);
- qemu_get_8s(f, &s->gate);
- s->count_load_time = qemu_get_be64(f);
- s->irq_disabled = 0;
- if (i == 0) {
- s->next_transition_time = qemu_get_be64(f);
- }
- }
- if (c->post_load) {
- c->post_load(pit);
- }
- return 0;
-}
-
static int pit_dispatch_pre_save(void *opaque)
{
PITCommonState *s = opaque;
@@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
.name = "i8254",
.version_id = 3,
.minimum_version_id = 2,
- .minimum_version_id_old = 1,
- .load_state_old = pit_load_old,
.pre_save = pit_dispatch_pre_save,
.post_load = pit_dispatch_post_load,
.fields = (VMStateField[]) {
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 12/20] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Peter Maydell, Stefano Stabellini, Marcel Apfelbaum,
Michael S. Tsirkin, Paul Durrant, Paolo Bonzini,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, xen-devel, Aleksandar Rikalo, Richard Henderson,
Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
These devices implemented their load_state_old() handler 10 years
ago, previous to QEMU v0.12.
Since commit cc425b5ddf removed the pc-0.10 and pc-0.11 machines,
we can drop this code.
Note: the mips_r4k machine started to use the i8254 device just
after QEMU v0.5.0, but the MIPS machine types are not versioned,
so there is no migration compatibility issue removing this handler.
Suggested-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/acpi/piix4.c | 40 ---------------------------------
hw/intc/apic_common.c | 49 -----------------------------------------
hw/pci-host/piix.c | 25 ---------------------
hw/timer/i8254_common.c | 40 ---------------------------------
4 files changed, 154 deletions(-)
diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 2efd1605b8..93aec2dd2c 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -41,7 +41,6 @@
#include "hw/acpi/memory_hotplug.h"
#include "hw/acpi/acpi_dev_interface.h"
#include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "hw/core/cpu.h"
#include "trace.h"
@@ -204,43 +203,6 @@ static const VMStateDescription vmstate_pci_status = {
}
};
-static int acpi_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- PIIX4PMState *s = opaque;
- int ret, i;
- uint16_t temp;
-
- ret = pci_device_load(PCI_DEVICE(s), f);
- if (ret < 0) {
- return ret;
- }
- qemu_get_be16s(f, &s->ar.pm1.evt.sts);
- qemu_get_be16s(f, &s->ar.pm1.evt.en);
- qemu_get_be16s(f, &s->ar.pm1.cnt.cnt);
-
- ret = vmstate_load_state(f, &vmstate_apm, &s->apm, 1);
- if (ret) {
- return ret;
- }
-
- timer_get(f, s->ar.tmr.timer);
- qemu_get_sbe64s(f, &s->ar.tmr.overflow_time);
-
- qemu_get_be16s(f, (uint16_t *)s->ar.gpe.sts);
- for (i = 0; i < 3; i++) {
- qemu_get_be16s(f, &temp);
- }
-
- qemu_get_be16s(f, (uint16_t *)s->ar.gpe.en);
- for (i = 0; i < 3; i++) {
- qemu_get_be16s(f, &temp);
- }
-
- ret = vmstate_load_state(f, &vmstate_pci_status,
- &s->acpi_pci_hotplug.acpi_pcihp_pci_status[ACPI_PCIHP_BSEL_DEFAULT], 1);
- return ret;
-}
-
static bool vmstate_test_use_acpi_pci_hotplug(void *opaque, int version_id)
{
PIIX4PMState *s = opaque;
@@ -312,8 +274,6 @@ static const VMStateDescription vmstate_acpi = {
.name = "piix4_pm",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 1,
- .load_state_old = acpi_load_old,
.post_load = vmstate_acpi_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PIIX4PMState),
diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c
index aafd8e0e33..375cb6abe9 100644
--- a/hw/intc/apic_common.c
+++ b/hw/intc/apic_common.c
@@ -31,7 +31,6 @@
#include "sysemu/kvm.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
static int apic_irq_delivered;
@@ -262,52 +261,6 @@ static void apic_reset_common(DeviceState *dev)
apic_init_reset(dev);
}
-/* This function is only used for old state version 1 and 2 */
-static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- APICCommonState *s = opaque;
- APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
- int i;
-
- if (version_id > 2) {
- return -EINVAL;
- }
-
- /* XXX: what if the base changes? (registered memory regions) */
- qemu_get_be32s(f, &s->apicbase);
- qemu_get_8s(f, &s->id);
- qemu_get_8s(f, &s->arb_id);
- qemu_get_8s(f, &s->tpr);
- qemu_get_be32s(f, &s->spurious_vec);
- qemu_get_8s(f, &s->log_dest);
- qemu_get_8s(f, &s->dest_mode);
- for (i = 0; i < 8; i++) {
- qemu_get_be32s(f, &s->isr[i]);
- qemu_get_be32s(f, &s->tmr[i]);
- qemu_get_be32s(f, &s->irr[i]);
- }
- for (i = 0; i < APIC_LVT_NB; i++) {
- qemu_get_be32s(f, &s->lvt[i]);
- }
- qemu_get_be32s(f, &s->esr);
- qemu_get_be32s(f, &s->icr[0]);
- qemu_get_be32s(f, &s->icr[1]);
- qemu_get_be32s(f, &s->divide_conf);
- s->count_shift = qemu_get_be32(f);
- qemu_get_be32s(f, &s->initial_count);
- s->initial_count_load_time = qemu_get_be64(f);
- s->next_time = qemu_get_be64(f);
-
- if (version_id >= 2) {
- s->timer_expiry = qemu_get_be64(f);
- }
-
- if (info->post_load) {
- info->post_load(s);
- }
- return 0;
-}
-
static const VMStateDescription vmstate_apic_common;
static void apic_common_realize(DeviceState *dev, Error **errp)
@@ -408,8 +361,6 @@ static const VMStateDescription vmstate_apic_common = {
.name = "apic",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 1,
- .load_state_old = apic_load_old,
.pre_load = apic_pre_load,
.pre_save = apic_dispatch_pre_save,
.post_load = apic_dispatch_post_load,
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 135c645535..2f4cbcbfe9 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -33,7 +33,6 @@
#include "qapi/error.h"
#include "qemu/range.h"
#include "hw/xen/xen.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
#include "hw/pci-host/pam.h"
#include "sysemu/reset.h"
@@ -174,28 +173,6 @@ static void i440fx_write_config(PCIDevice *dev,
}
}
-static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
-{
- PCII440FXState *d = opaque;
- PCIDevice *pd = PCI_DEVICE(d);
- int ret, i;
- uint8_t smm_enabled;
-
- ret = pci_device_load(pd, f);
- if (ret < 0)
- return ret;
- i440fx_update_memory_mappings(d);
- qemu_get_8s(f, &smm_enabled);
-
- if (version_id == 2) {
- for (i = 0; i < PIIX_NUM_PIRQS; i++) {
- qemu_get_be32(f); /* dummy load for compatibility */
- }
- }
-
- return 0;
-}
-
static int i440fx_post_load(void *opaque, int version_id)
{
PCII440FXState *d = opaque;
@@ -208,8 +185,6 @@ static const VMStateDescription vmstate_i440fx = {
.name = "I440FX",
.version_id = 3,
.minimum_version_id = 3,
- .minimum_version_id_old = 1,
- .load_state_old = i440fx_load_old,
.post_load = i440fx_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c
index 57bf10cc94..050875b497 100644
--- a/hw/timer/i8254_common.c
+++ b/hw/timer/i8254_common.c
@@ -29,7 +29,6 @@
#include "qemu/timer.h"
#include "hw/timer/i8254.h"
#include "hw/timer/i8254_internal.h"
-#include "migration/qemu-file-types.h"
#include "migration/vmstate.h"
/* val must be 0 or 1 */
@@ -202,43 +201,6 @@ static const VMStateDescription vmstate_pit_channel = {
}
};
-static int pit_load_old(QEMUFile *f, void *opaque, int version_id)
-{
- PITCommonState *pit = opaque;
- PITCommonClass *c = PIT_COMMON_GET_CLASS(pit);
- PITChannelState *s;
- int i;
-
- if (version_id != 1) {
- return -EINVAL;
- }
-
- for (i = 0; i < 3; i++) {
- s = &pit->channels[i];
- s->count = qemu_get_be32(f);
- qemu_get_be16s(f, &s->latched_count);
- qemu_get_8s(f, &s->count_latched);
- qemu_get_8s(f, &s->status_latched);
- qemu_get_8s(f, &s->status);
- qemu_get_8s(f, &s->read_state);
- qemu_get_8s(f, &s->write_state);
- qemu_get_8s(f, &s->write_latch);
- qemu_get_8s(f, &s->rw_mode);
- qemu_get_8s(f, &s->mode);
- qemu_get_8s(f, &s->bcd);
- qemu_get_8s(f, &s->gate);
- s->count_load_time = qemu_get_be64(f);
- s->irq_disabled = 0;
- if (i == 0) {
- s->next_transition_time = qemu_get_be64(f);
- }
- }
- if (c->post_load) {
- c->post_load(pit);
- }
- return 0;
-}
-
static int pit_dispatch_pre_save(void *opaque)
{
PITCommonState *s = opaque;
@@ -266,8 +228,6 @@ static const VMStateDescription vmstate_pit_common = {
.name = "i8254",
.version_id = 3,
.minimum_version_id = 2,
- .minimum_version_id_old = 1,
- .load_state_old = pit_load_old,
.pre_save = pit_dispatch_pre_save,
.post_load = pit_dispatch_post_load,
.fields = (VMStateField[]) {
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 13/20] hw/pci-host/piix: Extract piix3_create()
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
Extract the PIIX3 creation code from the i440fx_init() function.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 2f4cbcbfe9..3292703de7 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
}
+static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+ PIIX3State *piix3;
+ PCIDevice *pci_dev;
+
+ /*
+ * Xen supports additional interrupt routes from the PCI devices to
+ * the IOAPIC: the four pins of each PCI device on the bus are also
+ * connected to the IOAPIC directly.
+ * These additional routes can be discovered through ACPI.
+ */
+ if (xen_enabled()) {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_XEN_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+ piix3, XEN_PIIX_NUM_PIRQS);
+ } else {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+ piix3, PIIX_NUM_PIRQS);
+ pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+ }
+ *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+ return piix3;
+}
+
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
int *piix3_devfn,
@@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PAM_EXPAN_SIZE);
}
- /* Xen supports additional interrupt routes from the PCI devices to
- * the IOAPIC: the four pins of each PCI device on the bus are also
- * connected to the IOAPIC directly.
- * These additional routes can be discovered through ACPI. */
- if (xen_enabled()) {
- PCIDevice *pci_dev = pci_create_simple_multifunction(b,
- -1, true, TYPE_PIIX3_XEN_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
- piix3, XEN_PIIX_NUM_PIRQS);
- } else {
- PCIDevice *pci_dev = pci_create_simple_multifunction(b,
- -1, true, TYPE_PIIX3_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
- PIIX_NUM_PIRQS);
- pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
- }
+ piix3 = piix3_create(b, isa_bus);
piix3->pic = pic;
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
*piix3_devfn = piix3->dev.devfn;
ram_size = ram_size / 8 / 1024 / 1024;
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 13/20] hw/pci-host/piix: Extract piix3_create()
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
Extract the PIIX3 creation code from the i440fx_init() function.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++------------------
1 file changed, 31 insertions(+), 20 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 2f4cbcbfe9..3292703de7 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
}
+static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+ PIIX3State *piix3;
+ PCIDevice *pci_dev;
+
+ /*
+ * Xen supports additional interrupt routes from the PCI devices to
+ * the IOAPIC: the four pins of each PCI device on the bus are also
+ * connected to the IOAPIC directly.
+ * These additional routes can be discovered through ACPI.
+ */
+ if (xen_enabled()) {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_XEN_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+ piix3, XEN_PIIX_NUM_PIRQS);
+ } else {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+ piix3, PIIX_NUM_PIRQS);
+ pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+ }
+ *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+ return piix3;
+}
+
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
int *piix3_devfn,
@@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PAM_EXPAN_SIZE);
}
- /* Xen supports additional interrupt routes from the PCI devices to
- * the IOAPIC: the four pins of each PCI device on the bus are also
- * connected to the IOAPIC directly.
- * These additional routes can be discovered through ACPI. */
- if (xen_enabled()) {
- PCIDevice *pci_dev = pci_create_simple_multifunction(b,
- -1, true, TYPE_PIIX3_XEN_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
- piix3, XEN_PIIX_NUM_PIRQS);
- } else {
- PCIDevice *pci_dev = pci_create_simple_multifunction(b,
- -1, true, TYPE_PIIX3_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
- PIIX_NUM_PIRQS);
- pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
- }
+ piix3 = piix3_create(b, isa_bus);
piix3->pic = pic;
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
*piix3_devfn = piix3->dev.devfn;
ram_size = ram_size / 8 / 1024 / 1024;
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 14/20] hw/pci-host/piix: Move RCR_IOPORT register definition
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h", and prepend the PIIX prefix.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: prepend PIIX prefix (Aleksandar)
---
hw/i386/acpi-build.c | 2 +-
hw/pci-host/piix.c | 7 ++++---
include/hw/i386/pc.h | 6 ------
include/hw/southbridge/piix.h | 6 ++++++
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 56c427f772..478ca29874 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
/* The above need not be conditional on machine type because the reset port
* happens to be the same on PIIX (pc) and ICH9 (q35). */
- QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
+ QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
/* Fill in optional s3/s4 related properties */
o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3292703de7..6548d9a4b5 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
@@ -87,7 +88,7 @@ typedef struct PIIX3State {
/* Reset Control Register contents */
uint8_t rcr;
- /* IO memory region for Reset Control Register (RCR_IOPORT) */
+ /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
} PIIX3State;
@@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
"piix3-reset-control", 1);
- memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
- &d->rcr_mem, 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev),
+ PIIX_RCR_IOPORT, &d->rcr_mem, 1);
qemu_register_reset(piix3_reset, d);
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 848078bacc..2628de8b72 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -260,12 +260,6 @@ typedef struct PCII440FXState PCII440FXState;
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define RCR_IOPORT 0xcf9
-
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state, int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic,
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index add352456b..e49d4a6bbe 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define PIIX_RCR_IOPORT 0xcf9
+
extern PCIDevice *piix4_dev;
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 14/20] hw/pci-host/piix: Move RCR_IOPORT register definition
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The RCR_IOPORT register belongs to the PIIX chipset.
Move the definition to "piix.h", and prepend the PIIX prefix.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
v2: prepend PIIX prefix (Aleksandar)
---
hw/i386/acpi-build.c | 2 +-
hw/pci-host/piix.c | 7 ++++---
include/hw/i386/pc.h | 6 ------
include/hw/southbridge/piix.h | 6 ++++++
4 files changed, 11 insertions(+), 10 deletions(-)
diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c
index 56c427f772..478ca29874 100644
--- a/hw/i386/acpi-build.c
+++ b/hw/i386/acpi-build.c
@@ -209,7 +209,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm)
/* The above need not be conditional on machine type because the reset port
* happens to be the same on PIIX (pc) and ICH9 (q35). */
- QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != RCR_IOPORT);
+ QEMU_BUILD_BUG_ON(ICH9_RST_CNT_IOPORT != PIIX_RCR_IOPORT);
/* Fill in optional s3/s4 related properties */
o = object_property_get_qobject(obj, ACPI_PM_PROP_S3_DISABLED, NULL);
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 3292703de7..6548d9a4b5 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
#include "hw/sysbus.h"
@@ -87,7 +88,7 @@ typedef struct PIIX3State {
/* Reset Control Register contents */
uint8_t rcr;
- /* IO memory region for Reset Control Register (RCR_IOPORT) */
+ /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
MemoryRegion rcr_mem;
} PIIX3State;
@@ -695,8 +696,8 @@ static void piix3_realize(PCIDevice *dev, Error **errp)
memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
"piix3-reset-control", 1);
- memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
- &d->rcr_mem, 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev),
+ PIIX_RCR_IOPORT, &d->rcr_mem, 1);
qemu_register_reset(piix3_reset, d);
}
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 848078bacc..2628de8b72 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -260,12 +260,6 @@ typedef struct PCII440FXState PCII440FXState;
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-/*
- * Reset Control Register: PCI-accessible ISA-Compatible Register at address
- * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
- */
-#define RCR_IOPORT 0xcf9
-
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state, int *piix_devfn,
ISABus **isa_bus, qemu_irq *pic,
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index add352456b..e49d4a6bbe 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+/*
+ * Reset Control Register: PCI-accessible ISA-Compatible Register at address
+ * 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
+ */
+#define PIIX_RCR_IOPORT 0xcf9
+
extern PCIDevice *piix4_dev;
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 15/20] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.
Acked-by: Paul Durrant <paul@xen.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/xen/xen-hvm.c | 5 +++--
hw/mips/gt64xxx_pci.c | 4 ++--
hw/pci-host/piix.c | 9 ++++-----
include/hw/southbridge/piix.h | 6 ++++++
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb7f5..4ce2fb9c89 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/hw.h"
#include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
v = 0;
}
v &= 0xf;
- if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
- xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+ if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+ xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
}
}
}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix4_dev->config[0x60 + irq_num];
+ pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[0x60 + i]) {
+ if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
pic_level |= pci_irq_levels[i];
}
}
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 6548d9a4b5..390fb9ceba 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS 128ULL
-#define PIIX_PIRQC 0x60
typedef struct PIIX3State {
PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
int pic_irq;
uint64_t mask;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
int pic_irq;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQC + pin];
+ int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
pci_default_write_config(dev, address, val, len);
- if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+ if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
int pic_irq;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index e49d4a6bbe..094508b928 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 15/20] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
The IRQ Route Control registers definitions belong to the PIIX
chipset. We were only defining the 'A' register. Define the other
B, C and D registers, and use them.
Acked-by: Paul Durrant <paul@xen.org>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/xen/xen-hvm.c | 5 +++--
hw/mips/gt64xxx_pci.c | 4 ++--
hw/pci-host/piix.c | 9 ++++-----
include/hw/southbridge/piix.h | 6 ++++++
4 files changed, 15 insertions(+), 9 deletions(-)
diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c
index 6b5e5bb7f5..4ce2fb9c89 100644
--- a/hw/i386/xen/xen-hvm.c
+++ b/hw/i386/xen/xen-hvm.c
@@ -14,6 +14,7 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/i386/pc.h"
+#include "hw/southbridge/piix.h"
#include "hw/irq.h"
#include "hw/hw.h"
#include "hw/i386/apic-msidef.h"
@@ -156,8 +157,8 @@ void xen_piix_pci_write_config_client(uint32_t address, uint32_t val, int len)
v = 0;
}
v &= 0xf;
- if (((address + i) >= 0x60) && ((address + i) <= 0x63)) {
- xen_set_pci_link_route(xen_domid, address + i - 0x60, v);
+ if (((address + i) >= PIIX_PIRQCA) && ((address + i) <= PIIX_PIRQCD)) {
+ xen_set_pci_link_route(xen_domid, address + i - PIIX_PIRQCA, v);
}
}
}
diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c
index c277398c0d..5cab9c1ee1 100644
--- a/hw/mips/gt64xxx_pci.c
+++ b/hw/mips/gt64xxx_pci.c
@@ -1013,12 +1013,12 @@ static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
/* now we change the pic irq level according to the piix irq mappings */
/* XXX: optimize */
- pic_irq = piix4_dev->config[0x60 + irq_num];
+ pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
if (pic_irq < 16) {
/* The pic level is the logical OR of all the PCI irqs mapped to it. */
pic_level = 0;
for (i = 0; i < 4; i++) {
- if (pic_irq == piix4_dev->config[0x60 + i]) {
+ if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
pic_level |= pci_irq_levels[i];
}
}
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 6548d9a4b5..390fb9ceba 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -61,7 +61,6 @@ typedef struct I440FXState {
#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
#define XEN_PIIX_NUM_PIRQS 128ULL
-#define PIIX_PIRQC 0x60
typedef struct PIIX3State {
PCIDevice dev;
@@ -468,7 +467,7 @@ static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
int pic_irq;
uint64_t mask;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -482,7 +481,7 @@ static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
{
int pic_irq;
- pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
if (pic_irq >= PIIX_NUM_PIC_IRQS) {
return;
}
@@ -501,7 +500,7 @@ static void piix3_set_irq(void *opaque, int pirq, int level)
static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
{
PIIX3State *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQC + pin];
+ int irq = piix3->dev.config[PIIX_PIRQCA + pin];
PCIINTxRoute route;
if (irq < PIIX_NUM_PIC_IRQS) {
@@ -530,7 +529,7 @@ static void piix3_write_config(PCIDevice *dev,
uint32_t address, uint32_t val, int len)
{
pci_default_write_config(dev, address, val, len);
- if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
+ if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
int pic_irq;
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index e49d4a6bbe..094508b928 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -18,6 +18,12 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
qemu_irq sci_irq, qemu_irq smi_irq,
int smm_enabled, DeviceState **piix4_pm);
+/* PIRQRC[A:D]: PIRQx Route Control Registers */
+#define PIIX_PIRQCA 0x60
+#define PIIX_PIRQCB 0x61
+#define PIIX_PIRQCC 0x62
+#define PIIX_PIRQCD 0x63
+
/*
* Reset Control Register: PCI-accessible ISA-Compatible Register at address
* 0xcf9, provided by the PCI/ISA bridge (PIIX3 PCI function 0, 8086:7000).
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 16/20] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
functions. To be able to split it, we need to export some
declarations first.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 1 +
hw/acpi/pcihp.c | 2 +-
hw/i386/pc_piix.c | 1 +
hw/pci-host/piix.c | 1 +
include/hw/i386/pc.h | 22 ---------------------
include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
stubs/pci-host-piix.c | 3 ++-
7 files changed, 43 insertions(+), 24 deletions(-)
create mode 100644 include/hw/pci-host/i440fx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 556f58bd8c..adf059a164 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,6 +1228,7 @@ F: hw/i386/
F: hw/pci-host/piix.c
F: hw/pci-host/q35.c
F: hw/pci-host/pam.c
+F: include/hw/pci-host/i440fx.h
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
F: hw/isa/lpc_ich9.c
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 82d295b6e8..8413348a33 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -27,7 +27,7 @@
#include "qemu/osdep.h"
#include "hw/acpi/pcihp.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi/acpi.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 431965d921..11b8de049f 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
#include "hw/loader.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/southbridge/piix.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 390fb9ceba..95b04122fa 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 2628de8b72..833bc6737f 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -251,28 +251,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
/* hpet.c */
extern int no_hpet;
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
-
-#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-
-#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-
-PCIBus *i440fx_init(const char *host_type, const char *pci_type,
- PCII440FXState **pi440fx_state, int *piix_devfn,
- ISABus **isa_bus, qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io,
- ram_addr_t ram_size,
- ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
- MemoryRegion *pci_memory,
- MemoryRegion *ram_memory);
-
-PCIBus *find_i440fx(void);
-
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
new file mode 100644
index 0000000000..e327f9bf87
--- /dev/null
+++ b/include/hw/pci-host/i440fx.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU i440FX North Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_PCI_I440FX_H
+#define HW_PCI_I440FX_H
+
+#include "hw/hw.h"
+#include "hw/pci/pci_bus.h"
+
+typedef struct PCII440FXState PCII440FXState;
+
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+ PCII440FXState **pi440fx_state, int *piix_devfn,
+ ISABus **isa_bus, qemu_irq *pic,
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io,
+ ram_addr_t ram_size,
+ ram_addr_t below_4g_mem_size,
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion *ram_memory);
+
+PCIBus *find_i440fx(void);
+
+#endif
diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
index 6ed81b1f21..93975adbfe 100644
--- a/stubs/pci-host-piix.c
+++ b/stubs/pci-host-piix.c
@@ -1,5 +1,6 @@
#include "qemu/osdep.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
+
PCIBus *find_i440fx(void)
{
return NULL;
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 16/20] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
The hw/pci-host/piix.c contains a mix of PIIX3 and i440FX chipsets
functions. To be able to split it, we need to export some
declarations first.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 1 +
hw/acpi/pcihp.c | 2 +-
hw/i386/pc_piix.c | 1 +
hw/pci-host/piix.c | 1 +
include/hw/i386/pc.h | 22 ---------------------
include/hw/pci-host/i440fx.h | 37 ++++++++++++++++++++++++++++++++++++
stubs/pci-host-piix.c | 3 ++-
7 files changed, 43 insertions(+), 24 deletions(-)
create mode 100644 include/hw/pci-host/i440fx.h
diff --git a/MAINTAINERS b/MAINTAINERS
index 556f58bd8c..adf059a164 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1228,6 +1228,7 @@ F: hw/i386/
F: hw/pci-host/piix.c
F: hw/pci-host/q35.c
F: hw/pci-host/pam.c
+F: include/hw/pci-host/i440fx.h
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
F: hw/isa/lpc_ich9.c
diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c
index 82d295b6e8..8413348a33 100644
--- a/hw/acpi/pcihp.c
+++ b/hw/acpi/pcihp.c
@@ -27,7 +27,7 @@
#include "qemu/osdep.h"
#include "hw/acpi/pcihp.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_bridge.h"
#include "hw/acpi/acpi.h"
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 431965d921..11b8de049f 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -29,6 +29,7 @@
#include "hw/loader.h"
#include "hw/i386/pc.h"
#include "hw/i386/apic.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/southbridge/piix.h"
#include "hw/display/ramfb.h"
#include "hw/firmware/smbios.h"
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 390fb9ceba..95b04122fa 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -27,6 +27,7 @@
#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
+#include "hw/pci-host/i440fx.h"
#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
#include "hw/isa/isa.h"
diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
index 2628de8b72..833bc6737f 100644
--- a/include/hw/i386/pc.h
+++ b/include/hw/i386/pc.h
@@ -251,28 +251,6 @@ int cmos_get_fd_drive_type(FloppyDriveType fd0);
/* hpet.c */
extern int no_hpet;
-/* piix_pci.c */
-struct PCII440FXState;
-typedef struct PCII440FXState PCII440FXState;
-
-#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
-#define TYPE_I440FX_PCI_DEVICE "i440FX"
-
-#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
-
-PCIBus *i440fx_init(const char *host_type, const char *pci_type,
- PCII440FXState **pi440fx_state, int *piix_devfn,
- ISABus **isa_bus, qemu_irq *pic,
- MemoryRegion *address_space_mem,
- MemoryRegion *address_space_io,
- ram_addr_t ram_size,
- ram_addr_t below_4g_mem_size,
- ram_addr_t above_4g_mem_size,
- MemoryRegion *pci_memory,
- MemoryRegion *ram_memory);
-
-PCIBus *find_i440fx(void);
-
/* pc_sysfw.c */
void pc_system_flash_create(PCMachineState *pcms);
void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory);
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
new file mode 100644
index 0000000000..e327f9bf87
--- /dev/null
+++ b/include/hw/pci-host/i440fx.h
@@ -0,0 +1,37 @@
+/*
+ * QEMU i440FX North Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2 or later.
+ * See the COPYING file in the top-level directory.
+ *
+ */
+
+#ifndef HW_PCI_I440FX_H
+#define HW_PCI_I440FX_H
+
+#include "hw/hw.h"
+#include "hw/pci/pci_bus.h"
+
+typedef struct PCII440FXState PCII440FXState;
+
+#define TYPE_I440FX_PCI_HOST_BRIDGE "i440FX-pcihost"
+#define TYPE_I440FX_PCI_DEVICE "i440FX"
+
+#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
+
+PCIBus *i440fx_init(const char *host_type, const char *pci_type,
+ PCII440FXState **pi440fx_state, int *piix_devfn,
+ ISABus **isa_bus, qemu_irq *pic,
+ MemoryRegion *address_space_mem,
+ MemoryRegion *address_space_io,
+ ram_addr_t ram_size,
+ ram_addr_t below_4g_mem_size,
+ ram_addr_t above_4g_mem_size,
+ MemoryRegion *pci_memory,
+ MemoryRegion *ram_memory);
+
+PCIBus *find_i440fx(void);
+
+#endif
diff --git a/stubs/pci-host-piix.c b/stubs/pci-host-piix.c
index 6ed81b1f21..93975adbfe 100644
--- a/stubs/pci-host-piix.c
+++ b/stubs/pci-host-piix.c
@@ -1,5 +1,6 @@
#include "qemu/osdep.h"
-#include "hw/i386/pc.h"
+#include "hw/pci-host/i440fx.h"
+
PCIBus *find_i440fx(void)
{
return NULL;
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 17/20] hw/pci-host/piix: Fix code style issues
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
We will move this code, fix its style first.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/pci-host/piix.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 95b04122fa..1544c4726b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
static void piix3_write_config_xen(PCIDevice *dev,
uint32_t address, uint32_t val, int len);
-/* return the global irq number corresponding to a given device irq
- pin. We could also use the bus number to have a more precise
- mapping. */
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 17/20] hw/pci-host/piix: Fix code style issues
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
We will move this code, fix its style first.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/pci-host/piix.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 95b04122fa..1544c4726b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -133,9 +133,10 @@ static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
static void piix3_write_config_xen(PCIDevice *dev,
uint32_t address, uint32_t val, int len);
-/* return the global irq number corresponding to a given device irq
- pin. We could also use the bus number to have a more precise
- mapping. */
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
{
int slot_addend;
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 18/20] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Move all the PIIX3 functions to a new file: hw/isa/piix3.c.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Checkpatch warning:
ERROR: spaces required around that '*' (ctx:VxV)
#312: FILE: hw/isa/piix3.c:248:
+ .subsections = (const VMStateDescription*[]) {
^
---
MAINTAINERS | 1 +
hw/i386/Kconfig | 1 +
hw/isa/Kconfig | 4 +
hw/isa/Makefile.objs | 1 +
hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++++++
hw/pci-host/Kconfig | 1 -
hw/pci-host/piix.c | 402 ----------------------------------
include/hw/southbridge/piix.h | 36 +++
8 files changed, 442 insertions(+), 403 deletions(-)
create mode 100644 hw/isa/piix3.c
diff --git a/MAINTAINERS b/MAINTAINERS
index adf059a164..4845f47d93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
F: include/hw/pci-host/i440fx.h
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
+F: hw/isa/piix3.c
F: hw/isa/lpc_ich9.c
F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d4900e..589d75e26a 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -61,6 +61,7 @@ config I440FX
select PC_ACPI
select ACPI_SMBUS
select PCI_PIIX
+ select PIIX3
select IDE_PIIX
select DIMM
select SMBIOS
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 98a289957e..8a38813cc1 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -29,6 +29,10 @@ config PC87312
select FDC
select IDE_ISA
+config PIIX3
+ bool
+ select ISA_BUS
+
config PIIX4
bool
# For historical reasons, SuperIO devices are created in the board
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index ff97485504..8e73960a75 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
common-obj-$(CONFIG_APM) += apm.o
common-obj-$(CONFIG_I82378) += i82378.o
common-obj-$(CONFIG_PC87312) += pc87312.o
+common-obj-$(CONFIG_PIIX3) += piix3.o
common-obj-$(CONFIG_PIIX4) += piix4.o
common-obj-$(CONFIG_VT82C686) += vt82c686.o
common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
new file mode 100644
index 0000000000..fd1c78879f
--- /dev/null
+++ b/hw/isa/piix3.c
@@ -0,0 +1,399 @@
+/*
+ * QEMU PIIX PCI ISA Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "hw/southbridge/piix.h"
+#include "hw/irq.h"
+#include "hw/isa/isa.h"
+#include "hw/xen/xen.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "migration/vmstate.h"
+
+#define XEN_PIIX_NUM_PIRQS 128ULL
+
+#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
+#define PIIX3_PCI_DEVICE(obj) \
+ OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
+
+#define TYPE_PIIX3_DEVICE "PIIX3"
+#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
+
+static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+{
+ qemu_set_irq(piix3->pic[pic_irq],
+ !!(piix3->pic_levels &
+ (((1ULL << PIIX_NUM_PIRQS) - 1) <<
+ (pic_irq * PIIX_NUM_PIRQS))));
+}
+
+static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+{
+ int pic_irq;
+ uint64_t mask;
+
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ return;
+ }
+
+ mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
+ piix3->pic_levels &= ~mask;
+ piix3->pic_levels |= mask * !!level;
+}
+
+static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+{
+ int pic_irq;
+
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ return;
+ }
+
+ piix3_set_irq_level_internal(piix3, pirq, level);
+
+ piix3_set_irq_pic(piix3, pic_irq);
+}
+
+static void piix3_set_irq(void *opaque, int pirq, int level)
+{
+ PIIX3State *piix3 = opaque;
+ piix3_set_irq_level(piix3, pirq, level);
+}
+
+static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
+{
+ PIIX3State *piix3 = opaque;
+ int irq = piix3->dev.config[PIIX_PIRQCA + pin];
+ PCIINTxRoute route;
+
+ if (irq < PIIX_NUM_PIC_IRQS) {
+ route.mode = PCI_INTX_ENABLED;
+ route.irq = irq;
+ } else {
+ route.mode = PCI_INTX_DISABLED;
+ route.irq = -1;
+ }
+ return route;
+}
+
+/* irq routing is changed. so rebuild bitmap */
+static void piix3_update_irq_levels(PIIX3State *piix3)
+{
+ PCIBus *bus = pci_get_bus(&piix3->dev);
+ int pirq;
+
+ piix3->pic_levels = 0;
+ for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+ piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+ }
+}
+
+static void piix3_write_config(PCIDevice *dev,
+ uint32_t address, uint32_t val, int len)
+{
+ pci_default_write_config(dev, address, val, len);
+ if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
+ PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ int pic_irq;
+
+ pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
+ piix3_update_irq_levels(piix3);
+ for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ piix3_set_irq_pic(piix3, pic_irq);
+ }
+ }
+}
+
+static void piix3_write_config_xen(PCIDevice *dev,
+ uint32_t address, uint32_t val, int len)
+{
+ xen_piix_pci_write_config_client(address, val, len);
+ piix3_write_config(dev, address, val, len);
+}
+
+static void piix3_reset(void *opaque)
+{
+ PIIX3State *d = opaque;
+ uint8_t *pci_conf = d->dev.config;
+
+ pci_conf[0x04] = 0x07; /* master, memory and I/O */
+ pci_conf[0x05] = 0x00;
+ pci_conf[0x06] = 0x00;
+ pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
+ pci_conf[0x4c] = 0x4d;
+ pci_conf[0x4e] = 0x03;
+ pci_conf[0x4f] = 0x00;
+ pci_conf[0x60] = 0x80;
+ pci_conf[0x61] = 0x80;
+ pci_conf[0x62] = 0x80;
+ pci_conf[0x63] = 0x80;
+ pci_conf[0x69] = 0x02;
+ pci_conf[0x70] = 0x80;
+ pci_conf[0x76] = 0x0c;
+ pci_conf[0x77] = 0x0c;
+ pci_conf[0x78] = 0x02;
+ pci_conf[0x79] = 0x00;
+ pci_conf[0x80] = 0x00;
+ pci_conf[0x82] = 0x00;
+ pci_conf[0xa0] = 0x08;
+ pci_conf[0xa2] = 0x00;
+ pci_conf[0xa3] = 0x00;
+ pci_conf[0xa4] = 0x00;
+ pci_conf[0xa5] = 0x00;
+ pci_conf[0xa6] = 0x00;
+ pci_conf[0xa7] = 0x00;
+ pci_conf[0xa8] = 0x0f;
+ pci_conf[0xaa] = 0x00;
+ pci_conf[0xab] = 0x00;
+ pci_conf[0xac] = 0x00;
+ pci_conf[0xae] = 0x00;
+
+ d->pic_levels = 0;
+ d->rcr = 0;
+}
+
+static int piix3_post_load(void *opaque, int version_id)
+{
+ PIIX3State *piix3 = opaque;
+ int pirq;
+
+ /*
+ * Because the i8259 has not been deserialized yet, qemu_irq_raise
+ * might bring the system to a different state than the saved one;
+ * for example, the interrupt could be masked but the i8259 would
+ * not know that yet and would trigger an interrupt in the CPU.
+ *
+ * Here, we update irq levels without raising the interrupt.
+ * Interrupt state will be deserialized separately through the i8259.
+ */
+ piix3->pic_levels = 0;
+ for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+ piix3_set_irq_level_internal(piix3, pirq,
+ pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
+ }
+ return 0;
+}
+
+static int piix3_pre_save(void *opaque)
+{
+ int i;
+ PIIX3State *piix3 = opaque;
+
+ for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
+ piix3->pci_irq_levels_vmstate[i] =
+ pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
+ }
+
+ return 0;
+}
+
+static bool piix3_rcr_needed(void *opaque)
+{
+ PIIX3State *piix3 = opaque;
+
+ return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+ .name = "PIIX3/rcr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = piix3_rcr_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(rcr, PIIX3State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_piix3 = {
+ .name = "PIIX3",
+ .version_id = 3,
+ .minimum_version_id = 2,
+ .post_load = piix3_post_load,
+ .pre_save = piix3_pre_save,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, PIIX3State),
+ VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+ PIIX_NUM_PIRQS, 3),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription*[]) {
+ &vmstate_piix3_rcr,
+ NULL
+ }
+};
+
+
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
+{
+ PIIX3State *d = opaque;
+
+ if (val & 4) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ }
+ d->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
+{
+ PIIX3State *d = opaque;
+
+ return d->rcr;
+}
+
+static const MemoryRegionOps rcr_ops = {
+ .read = rcr_read,
+ .write = rcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN
+};
+
+static void piix3_realize(PCIDevice *dev, Error **errp)
+{
+ PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+
+ if (!isa_bus_new(DEVICE(d), get_system_memory(),
+ pci_address_space_io(dev), errp)) {
+ return;
+ }
+
+ memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
+ "piix3-reset-control", 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev),
+ PIIX_RCR_IOPORT, &d->rcr_mem, 1);
+
+ qemu_register_reset(piix3_reset, d);
+}
+
+static void pci_piix3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->desc = "ISA bridge";
+ dc->vmsd = &vmstate_piix3;
+ dc->hotpluggable = false;
+ k->realize = piix3_realize;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+ k->class_id = PCI_CLASS_BRIDGE_ISA;
+ /*
+ * Reason: part of PIIX3 southbridge, needs to be wired up by
+ * pc_piix.c's pc_init1()
+ */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo piix3_pci_type_info = {
+ .name = TYPE_PIIX3_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PIIX3State),
+ .abstract = true,
+ .class_init = pci_piix3_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+static void piix3_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->config_write = piix3_write_config;
+}
+
+static const TypeInfo piix3_info = {
+ .name = TYPE_PIIX3_DEVICE,
+ .parent = TYPE_PIIX3_PCI_DEVICE,
+ .class_init = piix3_class_init,
+};
+
+static void piix3_xen_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->config_write = piix3_write_config_xen;
+};
+
+static const TypeInfo piix3_xen_info = {
+ .name = TYPE_PIIX3_XEN_DEVICE,
+ .parent = TYPE_PIIX3_PCI_DEVICE,
+ .class_init = piix3_xen_class_init,
+};
+
+static void piix3_register_types(void)
+{
+ type_register_static(&piix3_pci_type_info);
+ type_register_static(&piix3_info);
+ type_register_static(&piix3_xen_info);
+}
+
+type_init(piix3_register_types)
+
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+{
+ int slot_addend;
+ slot_addend = (pci_dev->devfn >> 3) - 1;
+ return (pci_intx + slot_addend) & 3;
+}
+
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+ PIIX3State *piix3;
+ PCIDevice *pci_dev;
+
+ /*
+ * Xen supports additional interrupt routes from the PCI devices to
+ * the IOAPIC: the four pins of each PCI device on the bus are also
+ * connected to the IOAPIC directly.
+ * These additional routes can be discovered through ACPI.
+ */
+ if (xen_enabled()) {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_XEN_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+ piix3, XEN_PIIX_NUM_PIRQS);
+ } else {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+ piix3, PIIX_NUM_PIRQS);
+ pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+ }
+ *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+ return piix3;
+}
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 1edc1a31d4..397043b289 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -32,7 +32,6 @@ config PCI_PIIX
bool
select PCI
select PAM
- select ISA_BUS
config PCI_EXPRESS_Q35
bool
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 1544c4726b..79ecd58a2b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -24,22 +24,15 @@
#include "qemu/osdep.h"
#include "hw/i386/pc.h"
-#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/i440fx.h"
#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
-#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
-#include "qemu/range.h"
-#include "hw/xen/xen.h"
#include "migration/vmstate.h"
#include "hw/pci-host/pam.h"
-#include "sysemu/reset.h"
-#include "sysemu/runstate.h"
-#include "hw/i386/ioapic.h"
#include "qapi/visitor.h"
#include "qemu/error-report.h"
@@ -59,49 +52,9 @@ typedef struct I440FXState {
uint32_t short_root_bus;
} I440FXState;
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
-#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
-#define XEN_PIIX_NUM_PIRQS 128ULL
-
-typedef struct PIIX3State {
- PCIDevice dev;
-
- /*
- * bitmap to track pic levels.
- * The pic level is the logical OR of all the PCI irqs mapped to it
- * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
- *
- * PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
- * pic_irq * PIIX_NUM_PIRQS + pirq
- */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
-#error "unable to encode pic state in 64bit in pic_levels."
-#endif
- uint64_t pic_levels;
-
- qemu_irq *pic;
-
- /* This member isn't used. Just for save/load compatibility */
- int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
-
- /* Reset Control Register contents */
- uint8_t rcr;
-
- /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
- MemoryRegion rcr_mem;
-} PIIX3State;
-
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-#define PIIX3_PCI_DEVICE(obj) \
- OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
-
#define I440FX_PCI_DEVICE(obj) \
OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
-#define TYPE_PIIX3_DEVICE "PIIX3"
-#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
-
struct PCII440FXState {
/*< private >*/
PCIDevice parent_obj;
@@ -128,22 +81,6 @@ struct PCII440FXState {
*/
#define I440FX_COREBOOT_RAM_SIZE 0x57
-static void piix3_set_irq(void *opaque, int pirq, int level);
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
-static void piix3_write_config_xen(PCIDevice *dev,
- uint32_t address, uint32_t val, int len);
-
-/*
- * Return the global irq number corresponding to a given device irq
- * pin. We could also use the bus number to have a more precise mapping.
- */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
-{
- int slot_addend;
- slot_addend = (pci_dev->devfn >> 3) - 1;
- return (pci_intx + slot_addend) & 3;
-}
-
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i;
@@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
}
-static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
-{
- PIIX3State *piix3;
- PCIDevice *pci_dev;
-
- /*
- * Xen supports additional interrupt routes from the PCI devices to
- * the IOAPIC: the four pins of each PCI device on the bus are also
- * connected to the IOAPIC directly.
- * These additional routes can be discovered through ACPI.
- */
- if (xen_enabled()) {
- pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
- TYPE_PIIX3_XEN_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
- piix3, XEN_PIIX_NUM_PIRQS);
- } else {
- pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
- TYPE_PIIX3_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
- piix3, PIIX_NUM_PIRQS);
- pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
- }
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
- return piix3;
-}
-
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
int *piix3_devfn,
@@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
return s ? s->bus : NULL;
}
-/* PIIX3 PCI to ISA bridge */
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
-{
- qemu_set_irq(piix3->pic[pic_irq],
- !!(piix3->pic_levels &
- (((1ULL << PIIX_NUM_PIRQS) - 1) <<
- (pic_irq * PIIX_NUM_PIRQS))));
-}
-
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
-{
- int pic_irq;
- uint64_t mask;
-
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
- return;
- }
-
- mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
- piix3->pic_levels &= ~mask;
- piix3->pic_levels |= mask * !!level;
-}
-
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
-{
- int pic_irq;
-
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
- return;
- }
-
- piix3_set_irq_level_internal(piix3, pirq, level);
-
- piix3_set_irq_pic(piix3, pic_irq);
-}
-
-static void piix3_set_irq(void *opaque, int pirq, int level)
-{
- PIIX3State *piix3 = opaque;
- piix3_set_irq_level(piix3, pirq, level);
-}
-
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
-{
- PIIX3State *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQCA + pin];
- PCIINTxRoute route;
-
- if (irq < PIIX_NUM_PIC_IRQS) {
- route.mode = PCI_INTX_ENABLED;
- route.irq = irq;
- } else {
- route.mode = PCI_INTX_DISABLED;
- route.irq = -1;
- }
- return route;
-}
-
-/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
-{
- PCIBus *bus = pci_get_bus(&piix3->dev);
- int pirq;
-
- piix3->pic_levels = 0;
- for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
- }
-}
-
-static void piix3_write_config(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
-{
- pci_default_write_config(dev, address, val, len);
- if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
- int pic_irq;
-
- pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
- piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
- piix3_set_irq_pic(piix3, pic_irq);
- }
- }
-}
-
-static void piix3_write_config_xen(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
-{
- xen_piix_pci_write_config_client(address, val, len);
- piix3_write_config(dev, address, val, len);
-}
-
-static void piix3_reset(void *opaque)
-{
- PIIX3State *d = opaque;
- uint8_t *pci_conf = d->dev.config;
-
- pci_conf[0x04] = 0x07; /* master, memory and I/O */
- pci_conf[0x05] = 0x00;
- pci_conf[0x06] = 0x00;
- pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
- pci_conf[0x4c] = 0x4d;
- pci_conf[0x4e] = 0x03;
- pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x80;
- pci_conf[0x61] = 0x80;
- pci_conf[0x62] = 0x80;
- pci_conf[0x63] = 0x80;
- pci_conf[0x69] = 0x02;
- pci_conf[0x70] = 0x80;
- pci_conf[0x76] = 0x0c;
- pci_conf[0x77] = 0x0c;
- pci_conf[0x78] = 0x02;
- pci_conf[0x79] = 0x00;
- pci_conf[0x80] = 0x00;
- pci_conf[0x82] = 0x00;
- pci_conf[0xa0] = 0x08;
- pci_conf[0xa2] = 0x00;
- pci_conf[0xa3] = 0x00;
- pci_conf[0xa4] = 0x00;
- pci_conf[0xa5] = 0x00;
- pci_conf[0xa6] = 0x00;
- pci_conf[0xa7] = 0x00;
- pci_conf[0xa8] = 0x0f;
- pci_conf[0xaa] = 0x00;
- pci_conf[0xab] = 0x00;
- pci_conf[0xac] = 0x00;
- pci_conf[0xae] = 0x00;
-
- d->pic_levels = 0;
- d->rcr = 0;
-}
-
-static int piix3_post_load(void *opaque, int version_id)
-{
- PIIX3State *piix3 = opaque;
- int pirq;
-
- /* Because the i8259 has not been deserialized yet, qemu_irq_raise
- * might bring the system to a different state than the saved one;
- * for example, the interrupt could be masked but the i8259 would
- * not know that yet and would trigger an interrupt in the CPU.
- *
- * Here, we update irq levels without raising the interrupt.
- * Interrupt state will be deserialized separately through the i8259.
- */
- piix3->pic_levels = 0;
- for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level_internal(piix3, pirq,
- pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
- }
- return 0;
-}
-
-static int piix3_pre_save(void *opaque)
-{
- int i;
- PIIX3State *piix3 = opaque;
-
- for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
- piix3->pci_irq_levels_vmstate[i] =
- pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
- }
-
- return 0;
-}
-
-static bool piix3_rcr_needed(void *opaque)
-{
- PIIX3State *piix3 = opaque;
-
- return (piix3->rcr != 0);
-}
-
-static const VMStateDescription vmstate_piix3_rcr = {
- .name = "PIIX3/rcr",
- .version_id = 1,
- .minimum_version_id = 1,
- .needed = piix3_rcr_needed,
- .fields = (VMStateField[]) {
- VMSTATE_UINT8(rcr, PIIX3State),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static const VMStateDescription vmstate_piix3 = {
- .name = "PIIX3",
- .version_id = 3,
- .minimum_version_id = 2,
- .post_load = piix3_post_load,
- .pre_save = piix3_pre_save,
- .fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX3State),
- VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
- PIIX_NUM_PIRQS, 3),
- VMSTATE_END_OF_LIST()
- },
- .subsections = (const VMStateDescription*[]) {
- &vmstate_piix3_rcr,
- NULL
- }
-};
-
-
-static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
-{
- PIIX3State *d = opaque;
-
- if (val & 4) {
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
- return;
- }
- d->rcr = val & 2; /* keep System Reset type only */
-}
-
-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
-{
- PIIX3State *d = opaque;
-
- return d->rcr;
-}
-
-static const MemoryRegionOps rcr_ops = {
- .read = rcr_read,
- .write = rcr_write,
- .endianness = DEVICE_LITTLE_ENDIAN
-};
-
-static void piix3_realize(PCIDevice *dev, Error **errp)
-{
- PIIX3State *d = PIIX3_PCI_DEVICE(dev);
-
- if (!isa_bus_new(DEVICE(d), get_system_memory(),
- pci_address_space_io(dev), errp)) {
- return;
- }
-
- memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
- "piix3-reset-control", 1);
- memory_region_add_subregion_overlap(pci_address_space_io(dev),
- PIIX_RCR_IOPORT, &d->rcr_mem, 1);
-
- qemu_register_reset(piix3_reset, d);
-}
-
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- dc->desc = "ISA bridge";
- dc->vmsd = &vmstate_piix3;
- dc->hotpluggable = false;
- k->realize = piix3_realize;
- k->vendor_id = PCI_VENDOR_ID_INTEL;
- /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
- k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
- k->class_id = PCI_CLASS_BRIDGE_ISA;
- /*
- * Reason: part of PIIX3 southbridge, needs to be wired up by
- * pc_piix.c's pc_init1()
- */
- dc->user_creatable = false;
-}
-
-static const TypeInfo piix3_pci_type_info = {
- .name = TYPE_PIIX3_PCI_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX3State),
- .abstract = true,
- .class_init = pci_piix3_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
-static void piix3_class_init(ObjectClass *klass, void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->config_write = piix3_write_config;
-}
-
-static const TypeInfo piix3_info = {
- .name = TYPE_PIIX3_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
- .class_init = piix3_class_init,
-};
-
-static void piix3_xen_class_init(ObjectClass *klass, void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->config_write = piix3_write_config_xen;
-};
-
-static const TypeInfo piix3_xen_info = {
- .name = TYPE_PIIX3_XEN_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
- .class_init = piix3_xen_class_init,
-};
-
static void i440fx_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -922,9 +523,6 @@ static void i440fx_register_types(void)
{
type_register_static(&i440fx_info);
type_register_static(&igd_passthrough_i440fx_info);
- type_register_static(&piix3_pci_type_info);
- type_register_static(&piix3_info);
- type_register_static(&piix3_xen_info);
type_register_static(&i440fx_pcihost_info);
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 094508b928..152628c6d9 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -12,6 +12,8 @@
#ifndef HW_SOUTHBRIDGE_PIIX_H
#define HW_SOUTHBRIDGE_PIIX_H
+#include "hw/pci/pci.h"
+
#define TYPE_PIIX4_PM "PIIX4_PM"
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
*/
#define PIIX_RCR_IOPORT 0xcf9
+#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
+#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
+
+typedef struct PIIXState {
+ PCIDevice dev;
+
+ /*
+ * bitmap to track pic levels.
+ * The pic level is the logical OR of all the PCI irqs mapped to it
+ * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
+ *
+ * PIRQ is mapped to PIC pins, we track it by
+ * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * pic_irq * PIIX_NUM_PIRQS + pirq
+ */
+#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#error "unable to encode pic state in 64bit in pic_levels."
+#endif
+ uint64_t pic_levels;
+
+ qemu_irq *pic;
+
+ /* This member isn't used. Just for save/load compatibility */
+ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+ /* Reset Control Register contents */
+ uint8_t rcr;
+
+ /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
+ MemoryRegion rcr_mem;
+} PIIX3State;
+
extern PCIDevice *piix4_dev;
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
+
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
I2CBus **smbus, size_t ide_buses);
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 18/20] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
Move all the PIIX3 functions to a new file: hw/isa/piix3.c.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
Checkpatch warning:
ERROR: spaces required around that '*' (ctx:VxV)
#312: FILE: hw/isa/piix3.c:248:
+ .subsections = (const VMStateDescription*[]) {
^
---
MAINTAINERS | 1 +
hw/i386/Kconfig | 1 +
hw/isa/Kconfig | 4 +
hw/isa/Makefile.objs | 1 +
hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++++++
hw/pci-host/Kconfig | 1 -
hw/pci-host/piix.c | 402 ----------------------------------
include/hw/southbridge/piix.h | 36 +++
8 files changed, 442 insertions(+), 403 deletions(-)
create mode 100644 hw/isa/piix3.c
diff --git a/MAINTAINERS b/MAINTAINERS
index adf059a164..4845f47d93 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1231,6 +1231,7 @@ F: hw/pci-host/pam.c
F: include/hw/pci-host/i440fx.h
F: include/hw/pci-host/q35.h
F: include/hw/pci-host/pam.h
+F: hw/isa/piix3.c
F: hw/isa/lpc_ich9.c
F: hw/i2c/smbus_ich9.c
F: hw/acpi/piix4.c
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index c5c9d4900e..589d75e26a 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -61,6 +61,7 @@ config I440FX
select PC_ACPI
select ACPI_SMBUS
select PCI_PIIX
+ select PIIX3
select IDE_PIIX
select DIMM
select SMBIOS
diff --git a/hw/isa/Kconfig b/hw/isa/Kconfig
index 98a289957e..8a38813cc1 100644
--- a/hw/isa/Kconfig
+++ b/hw/isa/Kconfig
@@ -29,6 +29,10 @@ config PC87312
select FDC
select IDE_ISA
+config PIIX3
+ bool
+ select ISA_BUS
+
config PIIX4
bool
# For historical reasons, SuperIO devices are created in the board
diff --git a/hw/isa/Makefile.objs b/hw/isa/Makefile.objs
index ff97485504..8e73960a75 100644
--- a/hw/isa/Makefile.objs
+++ b/hw/isa/Makefile.objs
@@ -3,6 +3,7 @@ common-obj-$(CONFIG_ISA_SUPERIO) += isa-superio.o
common-obj-$(CONFIG_APM) += apm.o
common-obj-$(CONFIG_I82378) += i82378.o
common-obj-$(CONFIG_PC87312) += pc87312.o
+common-obj-$(CONFIG_PIIX3) += piix3.o
common-obj-$(CONFIG_PIIX4) += piix4.o
common-obj-$(CONFIG_VT82C686) += vt82c686.o
common-obj-$(CONFIG_SMC37C669) += smc37c669-superio.o
diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c
new file mode 100644
index 0000000000..fd1c78879f
--- /dev/null
+++ b/hw/isa/piix3.c
@@ -0,0 +1,399 @@
+/*
+ * QEMU PIIX PCI ISA Bridge Emulation
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a copy
+ * of this software and associated documentation files (the "Software"), to deal
+ * in the Software without restriction, including without limitation the rights
+ * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+ * copies of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
+ * THE SOFTWARE.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/range.h"
+#include "hw/southbridge/piix.h"
+#include "hw/irq.h"
+#include "hw/isa/isa.h"
+#include "hw/xen/xen.h"
+#include "sysemu/sysemu.h"
+#include "sysemu/reset.h"
+#include "sysemu/runstate.h"
+#include "migration/vmstate.h"
+
+#define XEN_PIIX_NUM_PIRQS 128ULL
+
+#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
+#define PIIX3_PCI_DEVICE(obj) \
+ OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
+
+#define TYPE_PIIX3_DEVICE "PIIX3"
+#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
+
+static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
+{
+ qemu_set_irq(piix3->pic[pic_irq],
+ !!(piix3->pic_levels &
+ (((1ULL << PIIX_NUM_PIRQS) - 1) <<
+ (pic_irq * PIIX_NUM_PIRQS))));
+}
+
+static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
+{
+ int pic_irq;
+ uint64_t mask;
+
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ return;
+ }
+
+ mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
+ piix3->pic_levels &= ~mask;
+ piix3->pic_levels |= mask * !!level;
+}
+
+static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
+{
+ int pic_irq;
+
+ pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
+ if (pic_irq >= PIIX_NUM_PIC_IRQS) {
+ return;
+ }
+
+ piix3_set_irq_level_internal(piix3, pirq, level);
+
+ piix3_set_irq_pic(piix3, pic_irq);
+}
+
+static void piix3_set_irq(void *opaque, int pirq, int level)
+{
+ PIIX3State *piix3 = opaque;
+ piix3_set_irq_level(piix3, pirq, level);
+}
+
+static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
+{
+ PIIX3State *piix3 = opaque;
+ int irq = piix3->dev.config[PIIX_PIRQCA + pin];
+ PCIINTxRoute route;
+
+ if (irq < PIIX_NUM_PIC_IRQS) {
+ route.mode = PCI_INTX_ENABLED;
+ route.irq = irq;
+ } else {
+ route.mode = PCI_INTX_DISABLED;
+ route.irq = -1;
+ }
+ return route;
+}
+
+/* irq routing is changed. so rebuild bitmap */
+static void piix3_update_irq_levels(PIIX3State *piix3)
+{
+ PCIBus *bus = pci_get_bus(&piix3->dev);
+ int pirq;
+
+ piix3->pic_levels = 0;
+ for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+ piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
+ }
+}
+
+static void piix3_write_config(PCIDevice *dev,
+ uint32_t address, uint32_t val, int len)
+{
+ pci_default_write_config(dev, address, val, len);
+ if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
+ PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
+ int pic_irq;
+
+ pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
+ piix3_update_irq_levels(piix3);
+ for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
+ piix3_set_irq_pic(piix3, pic_irq);
+ }
+ }
+}
+
+static void piix3_write_config_xen(PCIDevice *dev,
+ uint32_t address, uint32_t val, int len)
+{
+ xen_piix_pci_write_config_client(address, val, len);
+ piix3_write_config(dev, address, val, len);
+}
+
+static void piix3_reset(void *opaque)
+{
+ PIIX3State *d = opaque;
+ uint8_t *pci_conf = d->dev.config;
+
+ pci_conf[0x04] = 0x07; /* master, memory and I/O */
+ pci_conf[0x05] = 0x00;
+ pci_conf[0x06] = 0x00;
+ pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
+ pci_conf[0x4c] = 0x4d;
+ pci_conf[0x4e] = 0x03;
+ pci_conf[0x4f] = 0x00;
+ pci_conf[0x60] = 0x80;
+ pci_conf[0x61] = 0x80;
+ pci_conf[0x62] = 0x80;
+ pci_conf[0x63] = 0x80;
+ pci_conf[0x69] = 0x02;
+ pci_conf[0x70] = 0x80;
+ pci_conf[0x76] = 0x0c;
+ pci_conf[0x77] = 0x0c;
+ pci_conf[0x78] = 0x02;
+ pci_conf[0x79] = 0x00;
+ pci_conf[0x80] = 0x00;
+ pci_conf[0x82] = 0x00;
+ pci_conf[0xa0] = 0x08;
+ pci_conf[0xa2] = 0x00;
+ pci_conf[0xa3] = 0x00;
+ pci_conf[0xa4] = 0x00;
+ pci_conf[0xa5] = 0x00;
+ pci_conf[0xa6] = 0x00;
+ pci_conf[0xa7] = 0x00;
+ pci_conf[0xa8] = 0x0f;
+ pci_conf[0xaa] = 0x00;
+ pci_conf[0xab] = 0x00;
+ pci_conf[0xac] = 0x00;
+ pci_conf[0xae] = 0x00;
+
+ d->pic_levels = 0;
+ d->rcr = 0;
+}
+
+static int piix3_post_load(void *opaque, int version_id)
+{
+ PIIX3State *piix3 = opaque;
+ int pirq;
+
+ /*
+ * Because the i8259 has not been deserialized yet, qemu_irq_raise
+ * might bring the system to a different state than the saved one;
+ * for example, the interrupt could be masked but the i8259 would
+ * not know that yet and would trigger an interrupt in the CPU.
+ *
+ * Here, we update irq levels without raising the interrupt.
+ * Interrupt state will be deserialized separately through the i8259.
+ */
+ piix3->pic_levels = 0;
+ for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
+ piix3_set_irq_level_internal(piix3, pirq,
+ pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
+ }
+ return 0;
+}
+
+static int piix3_pre_save(void *opaque)
+{
+ int i;
+ PIIX3State *piix3 = opaque;
+
+ for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
+ piix3->pci_irq_levels_vmstate[i] =
+ pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
+ }
+
+ return 0;
+}
+
+static bool piix3_rcr_needed(void *opaque)
+{
+ PIIX3State *piix3 = opaque;
+
+ return (piix3->rcr != 0);
+}
+
+static const VMStateDescription vmstate_piix3_rcr = {
+ .name = "PIIX3/rcr",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = piix3_rcr_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(rcr, PIIX3State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_piix3 = {
+ .name = "PIIX3",
+ .version_id = 3,
+ .minimum_version_id = 2,
+ .post_load = piix3_post_load,
+ .pre_save = piix3_pre_save,
+ .fields = (VMStateField[]) {
+ VMSTATE_PCI_DEVICE(dev, PIIX3State),
+ VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
+ PIIX_NUM_PIRQS, 3),
+ VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription*[]) {
+ &vmstate_piix3_rcr,
+ NULL
+ }
+};
+
+
+static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
+{
+ PIIX3State *d = opaque;
+
+ if (val & 4) {
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+ return;
+ }
+ d->rcr = val & 2; /* keep System Reset type only */
+}
+
+static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
+{
+ PIIX3State *d = opaque;
+
+ return d->rcr;
+}
+
+static const MemoryRegionOps rcr_ops = {
+ .read = rcr_read,
+ .write = rcr_write,
+ .endianness = DEVICE_LITTLE_ENDIAN
+};
+
+static void piix3_realize(PCIDevice *dev, Error **errp)
+{
+ PIIX3State *d = PIIX3_PCI_DEVICE(dev);
+
+ if (!isa_bus_new(DEVICE(d), get_system_memory(),
+ pci_address_space_io(dev), errp)) {
+ return;
+ }
+
+ memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
+ "piix3-reset-control", 1);
+ memory_region_add_subregion_overlap(pci_address_space_io(dev),
+ PIIX_RCR_IOPORT, &d->rcr_mem, 1);
+
+ qemu_register_reset(piix3_reset, d);
+}
+
+static void pci_piix3_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ dc->desc = "ISA bridge";
+ dc->vmsd = &vmstate_piix3;
+ dc->hotpluggable = false;
+ k->realize = piix3_realize;
+ k->vendor_id = PCI_VENDOR_ID_INTEL;
+ /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
+ k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
+ k->class_id = PCI_CLASS_BRIDGE_ISA;
+ /*
+ * Reason: part of PIIX3 southbridge, needs to be wired up by
+ * pc_piix.c's pc_init1()
+ */
+ dc->user_creatable = false;
+}
+
+static const TypeInfo piix3_pci_type_info = {
+ .name = TYPE_PIIX3_PCI_DEVICE,
+ .parent = TYPE_PCI_DEVICE,
+ .instance_size = sizeof(PIIX3State),
+ .abstract = true,
+ .class_init = pci_piix3_class_init,
+ .interfaces = (InterfaceInfo[]) {
+ { INTERFACE_CONVENTIONAL_PCI_DEVICE },
+ { },
+ },
+};
+
+static void piix3_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->config_write = piix3_write_config;
+}
+
+static const TypeInfo piix3_info = {
+ .name = TYPE_PIIX3_DEVICE,
+ .parent = TYPE_PIIX3_PCI_DEVICE,
+ .class_init = piix3_class_init,
+};
+
+static void piix3_xen_class_init(ObjectClass *klass, void *data)
+{
+ PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+ k->config_write = piix3_write_config_xen;
+};
+
+static const TypeInfo piix3_xen_info = {
+ .name = TYPE_PIIX3_XEN_DEVICE,
+ .parent = TYPE_PIIX3_PCI_DEVICE,
+ .class_init = piix3_xen_class_init,
+};
+
+static void piix3_register_types(void)
+{
+ type_register_static(&piix3_pci_type_info);
+ type_register_static(&piix3_info);
+ type_register_static(&piix3_xen_info);
+}
+
+type_init(piix3_register_types)
+
+/*
+ * Return the global irq number corresponding to a given device irq
+ * pin. We could also use the bus number to have a more precise mapping.
+ */
+static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
+{
+ int slot_addend;
+ slot_addend = (pci_dev->devfn >> 3) - 1;
+ return (pci_intx + slot_addend) & 3;
+}
+
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
+{
+ PIIX3State *piix3;
+ PCIDevice *pci_dev;
+
+ /*
+ * Xen supports additional interrupt routes from the PCI devices to
+ * the IOAPIC: the four pins of each PCI device on the bus are also
+ * connected to the IOAPIC directly.
+ * These additional routes can be discovered through ACPI.
+ */
+ if (xen_enabled()) {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_XEN_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
+ piix3, XEN_PIIX_NUM_PIRQS);
+ } else {
+ pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
+ TYPE_PIIX3_DEVICE);
+ piix3 = PIIX3_PCI_DEVICE(pci_dev);
+ pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
+ piix3, PIIX_NUM_PIRQS);
+ pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
+ }
+ *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
+
+ return piix3;
+}
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 1edc1a31d4..397043b289 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -32,7 +32,6 @@ config PCI_PIIX
bool
select PCI
select PAM
- select ISA_BUS
config PCI_EXPRESS_Q35
bool
diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
index 1544c4726b..79ecd58a2b 100644
--- a/hw/pci-host/piix.c
+++ b/hw/pci-host/piix.c
@@ -24,22 +24,15 @@
#include "qemu/osdep.h"
#include "hw/i386/pc.h"
-#include "hw/irq.h"
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/i440fx.h"
#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
-#include "hw/isa/isa.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
-#include "qemu/range.h"
-#include "hw/xen/xen.h"
#include "migration/vmstate.h"
#include "hw/pci-host/pam.h"
-#include "sysemu/reset.h"
-#include "sysemu/runstate.h"
-#include "hw/i386/ioapic.h"
#include "qapi/visitor.h"
#include "qemu/error-report.h"
@@ -59,49 +52,9 @@ typedef struct I440FXState {
uint32_t short_root_bus;
} I440FXState;
-#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
-#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
-#define XEN_PIIX_NUM_PIRQS 128ULL
-
-typedef struct PIIX3State {
- PCIDevice dev;
-
- /*
- * bitmap to track pic levels.
- * The pic level is the logical OR of all the PCI irqs mapped to it
- * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
- *
- * PIRQ is mapped to PIC pins, we track it by
- * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
- * pic_irq * PIIX_NUM_PIRQS + pirq
- */
-#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
-#error "unable to encode pic state in 64bit in pic_levels."
-#endif
- uint64_t pic_levels;
-
- qemu_irq *pic;
-
- /* This member isn't used. Just for save/load compatibility */
- int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
-
- /* Reset Control Register contents */
- uint8_t rcr;
-
- /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
- MemoryRegion rcr_mem;
-} PIIX3State;
-
-#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
-#define PIIX3_PCI_DEVICE(obj) \
- OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
-
#define I440FX_PCI_DEVICE(obj) \
OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
-#define TYPE_PIIX3_DEVICE "PIIX3"
-#define TYPE_PIIX3_XEN_DEVICE "PIIX3-xen"
-
struct PCII440FXState {
/*< private >*/
PCIDevice parent_obj;
@@ -128,22 +81,6 @@ struct PCII440FXState {
*/
#define I440FX_COREBOOT_RAM_SIZE 0x57
-static void piix3_set_irq(void *opaque, int pirq, int level);
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
-static void piix3_write_config_xen(PCIDevice *dev,
- uint32_t address, uint32_t val, int len);
-
-/*
- * Return the global irq number corresponding to a given device irq
- * pin. We could also use the bus number to have a more precise mapping.
- */
-static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
-{
- int slot_addend;
- slot_addend = (pci_dev->devfn >> 3) - 1;
- return (pci_intx + slot_addend) & 3;
-}
-
static void i440fx_update_memory_mappings(PCII440FXState *d)
{
int i;
@@ -333,36 +270,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
}
}
-static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
-{
- PIIX3State *piix3;
- PCIDevice *pci_dev;
-
- /*
- * Xen supports additional interrupt routes from the PCI devices to
- * the IOAPIC: the four pins of each PCI device on the bus are also
- * connected to the IOAPIC directly.
- * These additional routes can be discovered through ACPI.
- */
- if (xen_enabled()) {
- pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
- TYPE_PIIX3_XEN_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq,
- piix3, XEN_PIIX_NUM_PIRQS);
- } else {
- pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
- TYPE_PIIX3_DEVICE);
- piix3 = PIIX3_PCI_DEVICE(pci_dev);
- pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
- piix3, PIIX_NUM_PIRQS);
- pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq);
- }
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
-
- return piix3;
-}
-
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
int *piix3_devfn,
@@ -455,312 +362,6 @@ PCIBus *find_i440fx(void)
return s ? s->bus : NULL;
}
-/* PIIX3 PCI to ISA bridge */
-static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
-{
- qemu_set_irq(piix3->pic[pic_irq],
- !!(piix3->pic_levels &
- (((1ULL << PIIX_NUM_PIRQS) - 1) <<
- (pic_irq * PIIX_NUM_PIRQS))));
-}
-
-static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
-{
- int pic_irq;
- uint64_t mask;
-
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
- return;
- }
-
- mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
- piix3->pic_levels &= ~mask;
- piix3->pic_levels |= mask * !!level;
-}
-
-static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
-{
- int pic_irq;
-
- pic_irq = piix3->dev.config[PIIX_PIRQCA + pirq];
- if (pic_irq >= PIIX_NUM_PIC_IRQS) {
- return;
- }
-
- piix3_set_irq_level_internal(piix3, pirq, level);
-
- piix3_set_irq_pic(piix3, pic_irq);
-}
-
-static void piix3_set_irq(void *opaque, int pirq, int level)
-{
- PIIX3State *piix3 = opaque;
- piix3_set_irq_level(piix3, pirq, level);
-}
-
-static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
-{
- PIIX3State *piix3 = opaque;
- int irq = piix3->dev.config[PIIX_PIRQCA + pin];
- PCIINTxRoute route;
-
- if (irq < PIIX_NUM_PIC_IRQS) {
- route.mode = PCI_INTX_ENABLED;
- route.irq = irq;
- } else {
- route.mode = PCI_INTX_DISABLED;
- route.irq = -1;
- }
- return route;
-}
-
-/* irq routing is changed. so rebuild bitmap */
-static void piix3_update_irq_levels(PIIX3State *piix3)
-{
- PCIBus *bus = pci_get_bus(&piix3->dev);
- int pirq;
-
- piix3->pic_levels = 0;
- for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level(piix3, pirq, pci_bus_get_irq_level(bus, pirq));
- }
-}
-
-static void piix3_write_config(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
-{
- pci_default_write_config(dev, address, val, len);
- if (ranges_overlap(address, len, PIIX_PIRQCA, 4)) {
- PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
- int pic_irq;
-
- pci_bus_fire_intx_routing_notifier(pci_get_bus(&piix3->dev));
- piix3_update_irq_levels(piix3);
- for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
- piix3_set_irq_pic(piix3, pic_irq);
- }
- }
-}
-
-static void piix3_write_config_xen(PCIDevice *dev,
- uint32_t address, uint32_t val, int len)
-{
- xen_piix_pci_write_config_client(address, val, len);
- piix3_write_config(dev, address, val, len);
-}
-
-static void piix3_reset(void *opaque)
-{
- PIIX3State *d = opaque;
- uint8_t *pci_conf = d->dev.config;
-
- pci_conf[0x04] = 0x07; /* master, memory and I/O */
- pci_conf[0x05] = 0x00;
- pci_conf[0x06] = 0x00;
- pci_conf[0x07] = 0x02; /* PCI_status_devsel_medium */
- pci_conf[0x4c] = 0x4d;
- pci_conf[0x4e] = 0x03;
- pci_conf[0x4f] = 0x00;
- pci_conf[0x60] = 0x80;
- pci_conf[0x61] = 0x80;
- pci_conf[0x62] = 0x80;
- pci_conf[0x63] = 0x80;
- pci_conf[0x69] = 0x02;
- pci_conf[0x70] = 0x80;
- pci_conf[0x76] = 0x0c;
- pci_conf[0x77] = 0x0c;
- pci_conf[0x78] = 0x02;
- pci_conf[0x79] = 0x00;
- pci_conf[0x80] = 0x00;
- pci_conf[0x82] = 0x00;
- pci_conf[0xa0] = 0x08;
- pci_conf[0xa2] = 0x00;
- pci_conf[0xa3] = 0x00;
- pci_conf[0xa4] = 0x00;
- pci_conf[0xa5] = 0x00;
- pci_conf[0xa6] = 0x00;
- pci_conf[0xa7] = 0x00;
- pci_conf[0xa8] = 0x0f;
- pci_conf[0xaa] = 0x00;
- pci_conf[0xab] = 0x00;
- pci_conf[0xac] = 0x00;
- pci_conf[0xae] = 0x00;
-
- d->pic_levels = 0;
- d->rcr = 0;
-}
-
-static int piix3_post_load(void *opaque, int version_id)
-{
- PIIX3State *piix3 = opaque;
- int pirq;
-
- /* Because the i8259 has not been deserialized yet, qemu_irq_raise
- * might bring the system to a different state than the saved one;
- * for example, the interrupt could be masked but the i8259 would
- * not know that yet and would trigger an interrupt in the CPU.
- *
- * Here, we update irq levels without raising the interrupt.
- * Interrupt state will be deserialized separately through the i8259.
- */
- piix3->pic_levels = 0;
- for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
- piix3_set_irq_level_internal(piix3, pirq,
- pci_bus_get_irq_level(pci_get_bus(&piix3->dev), pirq));
- }
- return 0;
-}
-
-static int piix3_pre_save(void *opaque)
-{
- int i;
- PIIX3State *piix3 = opaque;
-
- for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
- piix3->pci_irq_levels_vmstate[i] =
- pci_bus_get_irq_level(pci_get_bus(&piix3->dev), i);
- }
-
- return 0;
-}
-
-static bool piix3_rcr_needed(void *opaque)
-{
- PIIX3State *piix3 = opaque;
-
- return (piix3->rcr != 0);
-}
-
-static const VMStateDescription vmstate_piix3_rcr = {
- .name = "PIIX3/rcr",
- .version_id = 1,
- .minimum_version_id = 1,
- .needed = piix3_rcr_needed,
- .fields = (VMStateField[]) {
- VMSTATE_UINT8(rcr, PIIX3State),
- VMSTATE_END_OF_LIST()
- }
-};
-
-static const VMStateDescription vmstate_piix3 = {
- .name = "PIIX3",
- .version_id = 3,
- .minimum_version_id = 2,
- .post_load = piix3_post_load,
- .pre_save = piix3_pre_save,
- .fields = (VMStateField[]) {
- VMSTATE_PCI_DEVICE(dev, PIIX3State),
- VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
- PIIX_NUM_PIRQS, 3),
- VMSTATE_END_OF_LIST()
- },
- .subsections = (const VMStateDescription*[]) {
- &vmstate_piix3_rcr,
- NULL
- }
-};
-
-
-static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
-{
- PIIX3State *d = opaque;
-
- if (val & 4) {
- qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
- return;
- }
- d->rcr = val & 2; /* keep System Reset type only */
-}
-
-static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
-{
- PIIX3State *d = opaque;
-
- return d->rcr;
-}
-
-static const MemoryRegionOps rcr_ops = {
- .read = rcr_read,
- .write = rcr_write,
- .endianness = DEVICE_LITTLE_ENDIAN
-};
-
-static void piix3_realize(PCIDevice *dev, Error **errp)
-{
- PIIX3State *d = PIIX3_PCI_DEVICE(dev);
-
- if (!isa_bus_new(DEVICE(d), get_system_memory(),
- pci_address_space_io(dev), errp)) {
- return;
- }
-
- memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
- "piix3-reset-control", 1);
- memory_region_add_subregion_overlap(pci_address_space_io(dev),
- PIIX_RCR_IOPORT, &d->rcr_mem, 1);
-
- qemu_register_reset(piix3_reset, d);
-}
-
-static void pci_piix3_class_init(ObjectClass *klass, void *data)
-{
- DeviceClass *dc = DEVICE_CLASS(klass);
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- dc->desc = "ISA bridge";
- dc->vmsd = &vmstate_piix3;
- dc->hotpluggable = false;
- k->realize = piix3_realize;
- k->vendor_id = PCI_VENDOR_ID_INTEL;
- /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */
- k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
- k->class_id = PCI_CLASS_BRIDGE_ISA;
- /*
- * Reason: part of PIIX3 southbridge, needs to be wired up by
- * pc_piix.c's pc_init1()
- */
- dc->user_creatable = false;
-}
-
-static const TypeInfo piix3_pci_type_info = {
- .name = TYPE_PIIX3_PCI_DEVICE,
- .parent = TYPE_PCI_DEVICE,
- .instance_size = sizeof(PIIX3State),
- .abstract = true,
- .class_init = pci_piix3_class_init,
- .interfaces = (InterfaceInfo[]) {
- { INTERFACE_CONVENTIONAL_PCI_DEVICE },
- { },
- },
-};
-
-static void piix3_class_init(ObjectClass *klass, void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->config_write = piix3_write_config;
-}
-
-static const TypeInfo piix3_info = {
- .name = TYPE_PIIX3_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
- .class_init = piix3_class_init,
-};
-
-static void piix3_xen_class_init(ObjectClass *klass, void *data)
-{
- PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
-
- k->config_write = piix3_write_config_xen;
-};
-
-static const TypeInfo piix3_xen_info = {
- .name = TYPE_PIIX3_XEN_DEVICE,
- .parent = TYPE_PIIX3_PCI_DEVICE,
- .class_init = piix3_xen_class_init,
-};
-
static void i440fx_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -922,9 +523,6 @@ static void i440fx_register_types(void)
{
type_register_static(&i440fx_info);
type_register_static(&igd_passthrough_i440fx_info);
- type_register_static(&piix3_pci_type_info);
- type_register_static(&piix3_info);
- type_register_static(&piix3_xen_info);
type_register_static(&i440fx_pcihost_info);
}
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index 094508b928..152628c6d9 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -12,6 +12,8 @@
#ifndef HW_SOUTHBRIDGE_PIIX_H
#define HW_SOUTHBRIDGE_PIIX_H
+#include "hw/pci/pci.h"
+
#define TYPE_PIIX4_PM "PIIX4_PM"
I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
@@ -30,8 +32,42 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
*/
#define PIIX_RCR_IOPORT 0xcf9
+#define PIIX_NUM_PIC_IRQS 16 /* i8259 * 2 */
+#define PIIX_NUM_PIRQS 4ULL /* PIRQ[A-D] */
+
+typedef struct PIIXState {
+ PCIDevice dev;
+
+ /*
+ * bitmap to track pic levels.
+ * The pic level is the logical OR of all the PCI irqs mapped to it
+ * So one PIC level is tracked by PIIX_NUM_PIRQS bits.
+ *
+ * PIRQ is mapped to PIC pins, we track it by
+ * PIIX_NUM_PIRQS * PIIX_NUM_PIC_IRQS = 64 bits with
+ * pic_irq * PIIX_NUM_PIRQS + pirq
+ */
+#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
+#error "unable to encode pic state in 64bit in pic_levels."
+#endif
+ uint64_t pic_levels;
+
+ qemu_irq *pic;
+
+ /* This member isn't used. Just for save/load compatibility */
+ int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
+
+ /* Reset Control Register contents */
+ uint8_t rcr;
+
+ /* IO memory region for Reset Control Register (PIIX_RCR_IOPORT) */
+ MemoryRegion rcr_mem;
+} PIIX3State;
+
extern PCIDevice *piix4_dev;
+PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
+
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
I2CBus **smbus, size_t ide_buses);
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 19/20] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
it now only contains i440FX northbridge code.
Rename it to match the chipset modelled.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 2 +-
hw/i386/Kconfig | 2 +-
hw/pci-host/Kconfig | 2 +-
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/{piix.c => i440fx.c} | 0
5 files changed, 4 insertions(+), 4 deletions(-)
rename hw/pci-host/{piix.c => i440fx.c} (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4845f47d93..1bc9959b8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
S: Supported
F: include/hw/i386/
F: hw/i386/
-F: hw/pci-host/piix.c
+F: hw/pci-host/i440fx.c
F: hw/pci-host/q35.c
F: hw/pci-host/pam.c
F: include/hw/pci-host/i440fx.h
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 589d75e26a..cfe94aede7 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -60,7 +60,7 @@ config I440FX
select PC_PCI
select PC_ACPI
select ACPI_SMBUS
- select PCI_PIIX
+ select PCI_I440FX
select PIIX3
select IDE_PIIX
select DIMM
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 397043b289..b0aa8351c4 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -28,7 +28,7 @@ config PCI_SABRE
select PCI
bool
-config PCI_PIIX
+config PCI_I440FX
bool
select PCI
select PAM
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e022d..efd752b766 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
common-obj-$(CONFIG_PCI_SABRE) += sabre.o
common-obj-$(CONFIG_FULONG) += bonito.o
-common-obj-$(CONFIG_PCI_PIIX) += piix.o
+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
similarity index 100%
rename from hw/pci-host/piix.c
rename to hw/pci-host/i440fx.c
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 19/20] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Philippe Mathieu-Daudé,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
From: Philippe Mathieu-Daudé <f4bug@amsat.org>
We moved all the PIIX3 southbridge code out of hw/pci-host/piix.c,
it now only contains i440FX northbridge code.
Rename it to match the chipset modelled.
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
MAINTAINERS | 2 +-
hw/i386/Kconfig | 2 +-
hw/pci-host/Kconfig | 2 +-
hw/pci-host/Makefile.objs | 2 +-
hw/pci-host/{piix.c => i440fx.c} | 0
5 files changed, 4 insertions(+), 4 deletions(-)
rename hw/pci-host/{piix.c => i440fx.c} (100%)
diff --git a/MAINTAINERS b/MAINTAINERS
index 4845f47d93..1bc9959b8a 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1225,7 +1225,7 @@ M: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
S: Supported
F: include/hw/i386/
F: hw/i386/
-F: hw/pci-host/piix.c
+F: hw/pci-host/i440fx.c
F: hw/pci-host/q35.c
F: hw/pci-host/pam.c
F: include/hw/pci-host/i440fx.h
diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig
index 589d75e26a..cfe94aede7 100644
--- a/hw/i386/Kconfig
+++ b/hw/i386/Kconfig
@@ -60,7 +60,7 @@ config I440FX
select PC_PCI
select PC_ACPI
select ACPI_SMBUS
- select PCI_PIIX
+ select PCI_I440FX
select PIIX3
select IDE_PIIX
select DIMM
diff --git a/hw/pci-host/Kconfig b/hw/pci-host/Kconfig
index 397043b289..b0aa8351c4 100644
--- a/hw/pci-host/Kconfig
+++ b/hw/pci-host/Kconfig
@@ -28,7 +28,7 @@ config PCI_SABRE
select PCI
bool
-config PCI_PIIX
+config PCI_I440FX
bool
select PCI
select PAM
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs
index a9cd3e022d..efd752b766 100644
--- a/hw/pci-host/Makefile.objs
+++ b/hw/pci-host/Makefile.objs
@@ -13,7 +13,7 @@ common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o
common-obj-$(CONFIG_PCI_SABRE) += sabre.o
common-obj-$(CONFIG_FULONG) += bonito.o
-common-obj-$(CONFIG_PCI_PIIX) += piix.o
+common-obj-$(CONFIG_PCI_I440FX) += i440fx.o
common-obj-$(CONFIG_PCI_EXPRESS_Q35) += q35.o
common-obj-$(CONFIG_PCI_EXPRESS_GENERIC_BRIDGE) += gpex.o
common-obj-$(CONFIG_PCI_EXPRESS_XILINX) += xilinx-pcie.o
diff --git a/hw/pci-host/piix.c b/hw/pci-host/i440fx.c
similarity index 100%
rename from hw/pci-host/piix.c
rename to hw/pci-host/i440fx.c
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Michael S. Tsirkin, Paul Durrant,
Paolo Bonzini, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, xen-devel, Aleksandar Rikalo,
Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
The PIIX3 is not tied to the i440FX and can even be used without it.
Move its creation to the machine code (pc_piix.c).
We have now removed the last trace of southbridge code in the i440FX
northbridge.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/pc_piix.c | 8 +++++++-
hw/pci-host/i440fx.c | 8 --------
include/hw/pci-host/i440fx.h | 3 +--
3 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 11b8de049f..f6e7196a82 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -199,14 +199,20 @@ static void pc_init1(MachineState *machine,
}
if (pcmc->pci_enabled) {
+ PIIX3State *piix3;
+
pci_bus = i440fx_init(host_type,
pci_type,
- &i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
+ &i440fx_state,
system_memory, system_io, machine->ram_size,
pcms->below_4g_mem_size,
pcms->above_4g_mem_size,
pci_memory, ram_memory);
pcms->bus = pci_bus;
+
+ piix3 = piix3_create(pci_bus, &isa_bus);
+ piix3->pic = pcms->gsi;
+ piix3_devfn = piix3->dev.devfn;
} else {
pci_bus = NULL;
i440fx_state = NULL;
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 79ecd58a2b..f27131102d 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -27,7 +27,6 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/i440fx.h"
-#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
@@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
- int *piix3_devfn,
- ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
@@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCIBus *b;
PCIDevice *d;
PCIHostState *s;
- PIIX3State *piix3;
PCII440FXState *f;
unsigned i;
I440FXState *i440fx;
@@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PAM_EXPAN_SIZE);
}
- piix3 = piix3_create(b, isa_bus);
- piix3->pic = pic;
- *piix3_devfn = piix3->dev.devfn;
-
ram_size = ram_size / 8 / 1024 / 1024;
if (ram_size > 255) {
ram_size = 255;
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index e327f9bf87..f54e6466e4 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
- PCII440FXState **pi440fx_state, int *piix_devfn,
- ISABus **isa_bus, qemu_irq *pic,
+ PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
--
2.21.0
^ permalink raw reply related [flat|nested] 106+ messages in thread
* [Xen-devel] [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces
@ 2019-10-18 13:47 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-18 13:47 UTC (permalink / raw)
To: qemu-devel
Cc: Stefano Stabellini, Marcel Apfelbaum, Michael S. Tsirkin,
Paul Durrant, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Richard Henderson, Philippe Mathieu-Daudé,
Aurelien Jarno, Eduardo Habkost
The PIIX3 is not tied to the i440FX and can even be used without it.
Move its creation to the machine code (pc_piix.c).
We have now removed the last trace of southbridge code in the i440FX
northbridge.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
---
hw/i386/pc_piix.c | 8 +++++++-
hw/pci-host/i440fx.c | 8 --------
include/hw/pci-host/i440fx.h | 3 +--
3 files changed, 8 insertions(+), 11 deletions(-)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 11b8de049f..f6e7196a82 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -199,14 +199,20 @@ static void pc_init1(MachineState *machine,
}
if (pcmc->pci_enabled) {
+ PIIX3State *piix3;
+
pci_bus = i440fx_init(host_type,
pci_type,
- &i440fx_state, &piix3_devfn, &isa_bus, pcms->gsi,
+ &i440fx_state,
system_memory, system_io, machine->ram_size,
pcms->below_4g_mem_size,
pcms->above_4g_mem_size,
pci_memory, ram_memory);
pcms->bus = pci_bus;
+
+ piix3 = piix3_create(pci_bus, &isa_bus);
+ piix3->pic = pcms->gsi;
+ piix3_devfn = piix3->dev.devfn;
} else {
pci_bus = NULL;
i440fx_state = NULL;
diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
index 79ecd58a2b..f27131102d 100644
--- a/hw/pci-host/i440fx.c
+++ b/hw/pci-host/i440fx.c
@@ -27,7 +27,6 @@
#include "hw/pci/pci.h"
#include "hw/pci/pci_host.h"
#include "hw/pci-host/i440fx.h"
-#include "hw/southbridge/piix.h"
#include "hw/qdev-properties.h"
#include "hw/sysbus.h"
#include "qapi/error.h"
@@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error **errp)
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCII440FXState **pi440fx_state,
- int *piix3_devfn,
- ISABus **isa_bus, qemu_irq *pic,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
@@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PCIBus *b;
PCIDevice *d;
PCIHostState *s;
- PIIX3State *piix3;
PCII440FXState *f;
unsigned i;
I440FXState *i440fx;
@@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char *pci_type,
PAM_EXPAN_SIZE);
}
- piix3 = piix3_create(b, isa_bus);
- piix3->pic = pic;
- *piix3_devfn = piix3->dev.devfn;
-
ram_size = ram_size / 8 / 1024 / 1024;
if (ram_size > 255) {
ram_size = 255;
diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
index e327f9bf87..f54e6466e4 100644
--- a/include/hw/pci-host/i440fx.h
+++ b/include/hw/pci-host/i440fx.h
@@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
#define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
PCIBus *i440fx_init(const char *host_type, const char *pci_type,
- PCII440FXState **pi440fx_state, int *piix_devfn,
- ISABus **isa_bus, qemu_irq *pic,
+ PCII440FXState **pi440fx_state,
MemoryRegion *address_space_mem,
MemoryRegion *address_space_io,
ram_addr_t ram_size,
--
2.21.0
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-18 17:04 ` Aleksandar Markovic
-1 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-18 17:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 4207 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> The PIIX3 is not tied to the i440FX and can even be used without it.
> Move its creation to the machine code (pc_piix.c).
> We have now removed the last trace of southbridge code in the i440FX
> northbridge.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/i386/pc_piix.c | 8 +++++++-
> hw/pci-host/i440fx.c | 8 --------
> include/hw/pci-host/i440fx.h | 3 +--
> 3 files changed, 8 insertions(+), 11 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Philippe, I don't have any test equipment available at the moment, did you
do some smoke tests with new v2 of the series (like booting a Malta board,
or other relevant scenario)?
Veuillez agréer, Monsieur Philippe, l'assurance de mon parfaite
considération.
Aleksandar
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 11b8de049f..f6e7196a82 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -199,14 +199,20 @@ static void pc_init1(MachineState *machine,
> }
>
> if (pcmc->pci_enabled) {
> + PIIX3State *piix3;
> +
> pci_bus = i440fx_init(host_type,
> pci_type,
> - &i440fx_state, &piix3_devfn, &isa_bus,
> pcms->gsi,
> + &i440fx_state,
> system_memory, system_io, machine->ram_size,
> pcms->below_4g_mem_size,
> pcms->above_4g_mem_size,
> pci_memory, ram_memory);
> pcms->bus = pci_bus;
> +
> + piix3 = piix3_create(pci_bus, &isa_bus);
> + piix3->pic = pcms->gsi;
> + piix3_devfn = piix3->dev.devfn;
> } else {
> pci_bus = NULL;
> i440fx_state = NULL;
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
> index 79ecd58a2b..f27131102d 100644
> --- a/hw/pci-host/i440fx.c
> +++ b/hw/pci-host/i440fx.c
> @@ -27,7 +27,6 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_host.h"
> #include "hw/pci-host/i440fx.h"
> -#include "hw/southbridge/piix.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "qapi/error.h"
> @@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> PCII440FXState **pi440fx_state,
> - int *piix3_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> @@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PCIBus *b;
> PCIDevice *d;
> PCIHostState *s;
> - PIIX3State *piix3;
> PCII440FXState *f;
> unsigned i;
> I440FXState *i440fx;
> @@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PAM_EXPAN_SIZE);
> }
>
> - piix3 = piix3_create(b, isa_bus);
> - piix3->pic = pic;
> - *piix3_devfn = piix3->dev.devfn;
> -
> ram_size = ram_size / 8 / 1024 / 1024;
> if (ram_size > 255) {
> ram_size = 255;
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> index e327f9bf87..f54e6466e4 100644
> --- a/include/hw/pci-host/i440fx.h
> +++ b/include/hw/pci-host/i440fx.h
> @@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
> #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> - PCII440FXState **pi440fx_state, int *piix_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> + PCII440FXState **pi440fx_state,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> --
> 2.21.0
>
>
>
[-- Attachment #2: Type: text/html, Size: 6721 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces
@ 2019-10-18 17:04 ` Aleksandar Markovic
0 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-18 17:04 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 4207 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> The PIIX3 is not tied to the i440FX and can even be used without it.
> Move its creation to the machine code (pc_piix.c).
> We have now removed the last trace of southbridge code in the i440FX
> northbridge.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/i386/pc_piix.c | 8 +++++++-
> hw/pci-host/i440fx.c | 8 --------
> include/hw/pci-host/i440fx.h | 3 +--
> 3 files changed, 8 insertions(+), 11 deletions(-)
>
>
Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
Philippe, I don't have any test equipment available at the moment, did you
do some smoke tests with new v2 of the series (like booting a Malta board,
or other relevant scenario)?
Veuillez agréer, Monsieur Philippe, l'assurance de mon parfaite
considération.
Aleksandar
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 11b8de049f..f6e7196a82 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -199,14 +199,20 @@ static void pc_init1(MachineState *machine,
> }
>
> if (pcmc->pci_enabled) {
> + PIIX3State *piix3;
> +
> pci_bus = i440fx_init(host_type,
> pci_type,
> - &i440fx_state, &piix3_devfn, &isa_bus,
> pcms->gsi,
> + &i440fx_state,
> system_memory, system_io, machine->ram_size,
> pcms->below_4g_mem_size,
> pcms->above_4g_mem_size,
> pci_memory, ram_memory);
> pcms->bus = pci_bus;
> +
> + piix3 = piix3_create(pci_bus, &isa_bus);
> + piix3->pic = pcms->gsi;
> + piix3_devfn = piix3->dev.devfn;
> } else {
> pci_bus = NULL;
> i440fx_state = NULL;
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
> index 79ecd58a2b..f27131102d 100644
> --- a/hw/pci-host/i440fx.c
> +++ b/hw/pci-host/i440fx.c
> @@ -27,7 +27,6 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_host.h"
> #include "hw/pci-host/i440fx.h"
> -#include "hw/southbridge/piix.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "qapi/error.h"
> @@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> PCII440FXState **pi440fx_state,
> - int *piix3_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> @@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PCIBus *b;
> PCIDevice *d;
> PCIHostState *s;
> - PIIX3State *piix3;
> PCII440FXState *f;
> unsigned i;
> I440FXState *i440fx;
> @@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PAM_EXPAN_SIZE);
> }
>
> - piix3 = piix3_create(b, isa_bus);
> - piix3->pic = pic;
> - *piix3_devfn = piix3->dev.devfn;
> -
> ram_size = ram_size / 8 / 1024 / 1024;
> if (ram_size > 255) {
> ram_size = 255;
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> index e327f9bf87..f54e6466e4 100644
> --- a/include/hw/pci-host/i440fx.h
> +++ b/include/hw/pci-host/i440fx.h
> @@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
> #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE "igd-passthrough-i440FX"
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> - PCII440FXState **pi440fx_state, int *piix_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> + PCII440FXState **pi440fx_state,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> --
> 2.21.0
>
>
>
[-- Attachment #1.2: Type: text/html, Size: 6721 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-19 10:50 ` no-reply
-1 siblings, 0 replies; 106+ messages in thread
From: no-reply @ 2019-10-19 10:50 UTC (permalink / raw)
To: philmd
Cc: sstabellini, xen-devel, paul, mst, qemu-devel, ehabkost,
hpoussin, amarkovic, imammedo, anthony.perard, pbonzini,
aleksandar.rikalo, philmd, aurelien, rth
Patchew URL: https://patchew.org/QEMU/20191018134754.16362-1-philmd@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
Type: series
Message-id: 20191018134754.16362-1-philmd@redhat.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
1f84f10 hw/pci-host/i440fx: Remove the last PIIX3 traces
717a0a4 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
1294b7c hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
23d43d0 hw/pci-host/piix: Fix code style issues
6e0ce49 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
d1ac4b6 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
cb5243e hw/pci-host/piix: Move RCR_IOPORT register definition
d5e122f hw/pci-host/piix: Extract piix3_create()
c544fb9 hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
c3c706e hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
7fad3f2 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
dde8f42 hw/mips/mips_malta: Create IDE hard drive array dynamically
349a8de piix4: Add a MC146818 RTC Controller as specified in datasheet
2ad1333 piix4: Add a i8254 PIT Controller as specified in datasheet
041f420 piix4: Add a i8257 DMA Controller as specified in datasheet
9cf3651 piix4: Rename PIIX4 object to piix4-isa
a27841e Revert "irq: introduce qemu_irq_proxy()"
7d9534a piix4: Add a i8259 Interrupt Controller as specified in datasheet
6498930 piix4: Add the Reset Control Register
90cd7d4 MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
=== OUTPUT BEGIN ===
1/20 Checking commit 90cd7d4f5eb5 (MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets)
2/20 Checking commit 64989309a9b5 (piix4: Add the Reset Control Register)
3/20 Checking commit 7d9534a284e9 (piix4: Add a i8259 Interrupt Controller as specified in datasheet)
4/20 Checking commit a27841e2b3ca (Revert "irq: introduce qemu_irq_proxy()")
5/20 Checking commit 9cf3651f77e2 (piix4: Rename PIIX4 object to piix4-isa)
6/20 Checking commit 041f4205783d (piix4: Add a i8257 DMA Controller as specified in datasheet)
7/20 Checking commit 2ad1333a3a5f (piix4: Add a i8254 PIT Controller as specified in datasheet)
8/20 Checking commit 349a8deab686 (piix4: Add a MC146818 RTC Controller as specified in datasheet)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#194:
deleted file mode 100644
total: 0 errors, 1 warnings, 166 lines checked
Patch 8/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/20 Checking commit dde8f42302df (hw/mips/mips_malta: Create IDE hard drive array dynamically)
10/20 Checking commit 7fad3f28aa86 (hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create())
11/20 Checking commit c3c706e79403 (hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c)
12/20 Checking commit c544fb98aa67 (hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers)
13/20 Checking commit d5e122f286e4 (hw/pci-host/piix: Extract piix3_create())
14/20 Checking commit cb5243e8b4a0 (hw/pci-host/piix: Move RCR_IOPORT register definition)
15/20 Checking commit d1ac4b60c55c (hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers)
16/20 Checking commit 6e0ce49c6fb6 (hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#99:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 16/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/20 Checking commit 23d43d03d057 (hw/pci-host/piix: Fix code style issues)
18/20 Checking commit 1294b7c961d3 (hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#66:
new file mode 100644
ERROR: spaces required around that '*' (ctx:VxV)
#315: FILE: hw/isa/piix3.c:245:
+ .subsections = (const VMStateDescription*[]) {
^
total: 1 errors, 1 warnings, 937 lines checked
Patch 18/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/20 Checking commit 717a0a47f89a (hw/pci-host: Rename incorrectly named 'piix' as 'i440fx')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#70:
rename from hw/pci-host/piix.c
total: 0 errors, 1 warnings, 32 lines checked
Patch 19/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/20 Checking commit 1f84f103c9b2 (hw/pci-host/i440fx: Remove the last PIIX3 traces)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20191018134754.16362-1-philmd@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-19 10:50 ` no-reply
0 siblings, 0 replies; 106+ messages in thread
From: no-reply @ 2019-10-19 10:50 UTC (permalink / raw)
To: philmd
Cc: sstabellini, xen-devel, paul, mst, qemu-devel, ehabkost,
hpoussin, amarkovic, imammedo, anthony.perard, pbonzini,
aleksandar.rikalo, philmd, aurelien, rth
Patchew URL: https://patchew.org/QEMU/20191018134754.16362-1-philmd@redhat.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
Type: series
Message-id: 20191018134754.16362-1-philmd@redhat.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
1f84f10 hw/pci-host/i440fx: Remove the last PIIX3 traces
717a0a4 hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
1294b7c hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
23d43d0 hw/pci-host/piix: Fix code style issues
6e0ce49 hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
d1ac4b6 hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
cb5243e hw/pci-host/piix: Move RCR_IOPORT register definition
d5e122f hw/pci-host/piix: Extract piix3_create()
c544fb9 hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
c3c706e hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
7fad3f2 hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
dde8f42 hw/mips/mips_malta: Create IDE hard drive array dynamically
349a8de piix4: Add a MC146818 RTC Controller as specified in datasheet
2ad1333 piix4: Add a i8254 PIT Controller as specified in datasheet
041f420 piix4: Add a i8257 DMA Controller as specified in datasheet
9cf3651 piix4: Rename PIIX4 object to piix4-isa
a27841e Revert "irq: introduce qemu_irq_proxy()"
7d9534a piix4: Add a i8259 Interrupt Controller as specified in datasheet
6498930 piix4: Add the Reset Control Register
90cd7d4 MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
=== OUTPUT BEGIN ===
1/20 Checking commit 90cd7d4f5eb5 (MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets)
2/20 Checking commit 64989309a9b5 (piix4: Add the Reset Control Register)
3/20 Checking commit 7d9534a284e9 (piix4: Add a i8259 Interrupt Controller as specified in datasheet)
4/20 Checking commit a27841e2b3ca (Revert "irq: introduce qemu_irq_proxy()")
5/20 Checking commit 9cf3651f77e2 (piix4: Rename PIIX4 object to piix4-isa)
6/20 Checking commit 041f4205783d (piix4: Add a i8257 DMA Controller as specified in datasheet)
7/20 Checking commit 2ad1333a3a5f (piix4: Add a i8254 PIT Controller as specified in datasheet)
8/20 Checking commit 349a8deab686 (piix4: Add a MC146818 RTC Controller as specified in datasheet)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#194:
deleted file mode 100644
total: 0 errors, 1 warnings, 166 lines checked
Patch 8/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
9/20 Checking commit dde8f42302df (hw/mips/mips_malta: Create IDE hard drive array dynamically)
10/20 Checking commit 7fad3f28aa86 (hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create())
11/20 Checking commit c3c706e79403 (hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c)
12/20 Checking commit c544fb98aa67 (hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers)
13/20 Checking commit d5e122f286e4 (hw/pci-host/piix: Extract piix3_create())
14/20 Checking commit cb5243e8b4a0 (hw/pci-host/piix: Move RCR_IOPORT register definition)
15/20 Checking commit d1ac4b60c55c (hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers)
16/20 Checking commit 6e0ce49c6fb6 (hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#99:
new file mode 100644
total: 0 errors, 1 warnings, 101 lines checked
Patch 16/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
17/20 Checking commit 23d43d03d057 (hw/pci-host/piix: Fix code style issues)
18/20 Checking commit 1294b7c961d3 (hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c)
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#66:
new file mode 100644
ERROR: spaces required around that '*' (ctx:VxV)
#315: FILE: hw/isa/piix3.c:245:
+ .subsections = (const VMStateDescription*[]) {
^
total: 1 errors, 1 warnings, 937 lines checked
Patch 18/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
19/20 Checking commit 717a0a47f89a (hw/pci-host: Rename incorrectly named 'piix' as 'i440fx')
WARNING: added, moved or deleted file(s), does MAINTAINERS need updating?
#70:
rename from hw/pci-host/piix.c
total: 0 errors, 1 warnings, 32 lines checked
Patch 19/20 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
20/20 Checking commit 1f84f103c9b2 (hw/pci-host/i440fx: Remove the last PIIX3 traces)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/20191018134754.16362-1-philmd@redhat.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-19 15:15 ` Aleksandar Markovic
-1 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-19 15:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 6901 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> Changes since v1 [0]:
> - Removed patch reintroducing DO_UPCAST() use (thuth)
> - Took various patches out to reduce series (thuth)
> - Added review tags (thanks all for reviewing!)
>
>
As far as I can tell, a handful of checkpatch warnings are all false
positives.
Peter, I am fine with Philippe (or Herve for that matter) submitting this
series as a pull request (providing that some basic relevant Malta tests
are done), and, if you are fine too, I think we can proceed.
Integrating this series will make device model for Malta better (closer to
real hardware), and also help Philippe continue working on other device
cleanups.
Aleksandar
> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
> Key:
> [----] : patches are identical
> [####] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
>
> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC
> Chipsets'
> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified
> in datasheet'
> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in
> datasheet'
> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in
> datasheet'
> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in
> datasheet'
> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array
> dynamically'
> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as
> piix4_create()'
> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
> 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old
> handlers'
> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route
> Control Registers'
> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to
> hw/pci-host/i440fx.h'
> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
> hw/isa/piix3.c'
> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as
> 'i440fx''
> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
>
> Previous cover:
>
> This series is a rework of "piix4: cleanup and improvements" [1]
> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>
> Still trying to remove the strong X86/PC dependency 2 years later,
> one step at a time.
> Here we split the PIIX3 southbridge from i440FX northbridge.
> The i440FX northbridge is only used by the PC machine, while the
> PIIX southbridge is also used by the Malta MIPS machine.
>
> This is also a step forward using KConfig with the Malta board.
> Without this split, it was impossible to compile the Malta without
> pulling various X86 pieces of code.
>
> The overall design cleanup is not yet perfect, but enough to post
> as a series.
>
> Now that the PIIX3 code is extracted, the code duplication with the
> PIIX4 chipset is obvious. Not worth improving for now because it
> isn't broken.
>
> [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
> [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>
> Based-on: <20191018133547.10936-1-philmd@redhat.com>
> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
> rtc_init()
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
>
> Hervé Poussineau (5):
> piix4: Add the Reset Control Register
> piix4: Add a i8259 Interrupt Controller as specified in datasheet
> piix4: Rename PIIX4 object to piix4-isa
> piix4: Add a i8257 DMA Controller as specified in datasheet
> piix4: Add a i8254 PIT Controller as specified in datasheet
>
> Philippe Mathieu-Daudé (15):
> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
> Revert "irq: introduce qemu_irq_proxy()"
> piix4: Add a MC146818 RTC Controller as specified in datasheet
> hw/mips/mips_malta: Create IDE hard drive array dynamically
> hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
> hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
> hw/pci-host/piix: Extract piix3_create()
> hw/pci-host/piix: Move RCR_IOPORT register definition
> hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
> hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
> hw/pci-host/piix: Fix code style issues
> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
> hw/pci-host/i440fx: Remove the last PIIX3 traces
>
> MAINTAINERS | 14 +-
> hw/acpi/pcihp.c | 2 +-
> hw/acpi/piix4.c | 42 +--
> hw/core/irq.c | 14 -
> hw/i386/Kconfig | 3 +-
> hw/i386/acpi-build.c | 5 +-
> hw/i386/pc_piix.c | 10 +-
> hw/i386/xen/xen-hvm.c | 5 +-
> hw/intc/apic_common.c | 49 ----
> hw/isa/Kconfig | 4 +
> hw/isa/Makefile.objs | 1 +
> hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
> hw/isa/piix4.c | 151 ++++++++++-
> hw/mips/gt64xxx_pci.c | 5 +-
> hw/mips/mips_malta.c | 46 +---
> hw/pci-host/Kconfig | 3 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
> hw/timer/i8254_common.c | 40 ---
> include/hw/acpi/piix4.h | 6 -
> include/hw/i386/pc.h | 37 ---
> include/hw/irq.h | 5 -
> include/hw/isa/isa.h | 2 +
> include/hw/pci-host/i440fx.h | 36 +++
> include/hw/southbridge/piix.h | 74 ++++++
> stubs/pci-host-piix.c | 3 +-
> 26 files changed, 699 insertions(+), 683 deletions(-)
> create mode 100644 hw/isa/piix3.c
> rename hw/pci-host/{piix.c => i440fx.c} (58%)
> delete mode 100644 include/hw/acpi/piix4.h
> create mode 100644 include/hw/pci-host/i440fx.h
> create mode 100644 include/hw/southbridge/piix.h
>
> --
> 2.21.0
>
>
>
[-- Attachment #2: Type: text/html, Size: 8550 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-19 15:15 ` Aleksandar Markovic
0 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-19 15:15 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, Peter Maydell
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 6901 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> Changes since v1 [0]:
> - Removed patch reintroducing DO_UPCAST() use (thuth)
> - Took various patches out to reduce series (thuth)
> - Added review tags (thanks all for reviewing!)
>
>
As far as I can tell, a handful of checkpatch warnings are all false
positives.
Peter, I am fine with Philippe (or Herve for that matter) submitting this
series as a pull request (providing that some basic relevant Malta tests
are done), and, if you are fine too, I think we can proceed.
Integrating this series will make device model for Malta better (closer to
real hardware), and also help Philippe continue working on other device
cleanups.
Aleksandar
> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
> Key:
> [----] : patches are identical
> [####] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
>
> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC
> Chipsets'
> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified
> in datasheet'
> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in
> datasheet'
> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in
> datasheet'
> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in
> datasheet'
> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array
> dynamically'
> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as
> piix4_create()'
> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
> 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old
> handlers'
> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route
> Control Registers'
> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to
> hw/pci-host/i440fx.h'
> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
> hw/isa/piix3.c'
> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as
> 'i440fx''
> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
>
> Previous cover:
>
> This series is a rework of "piix4: cleanup and improvements" [1]
> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>
> Still trying to remove the strong X86/PC dependency 2 years later,
> one step at a time.
> Here we split the PIIX3 southbridge from i440FX northbridge.
> The i440FX northbridge is only used by the PC machine, while the
> PIIX southbridge is also used by the Malta MIPS machine.
>
> This is also a step forward using KConfig with the Malta board.
> Without this split, it was impossible to compile the Malta without
> pulling various X86 pieces of code.
>
> The overall design cleanup is not yet perfect, but enough to post
> as a series.
>
> Now that the PIIX3 code is extracted, the code duplication with the
> PIIX4 chipset is obvious. Not worth improving for now because it
> isn't broken.
>
> [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
> [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>
> Based-on: <20191018133547.10936-1-philmd@redhat.com>
> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
> rtc_init()
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
>
> Hervé Poussineau (5):
> piix4: Add the Reset Control Register
> piix4: Add a i8259 Interrupt Controller as specified in datasheet
> piix4: Rename PIIX4 object to piix4-isa
> piix4: Add a i8257 DMA Controller as specified in datasheet
> piix4: Add a i8254 PIT Controller as specified in datasheet
>
> Philippe Mathieu-Daudé (15):
> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
> Revert "irq: introduce qemu_irq_proxy()"
> piix4: Add a MC146818 RTC Controller as specified in datasheet
> hw/mips/mips_malta: Create IDE hard drive array dynamically
> hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
> hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
> hw/pci-host/piix: Extract piix3_create()
> hw/pci-host/piix: Move RCR_IOPORT register definition
> hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
> hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
> hw/pci-host/piix: Fix code style issues
> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
> hw/pci-host/i440fx: Remove the last PIIX3 traces
>
> MAINTAINERS | 14 +-
> hw/acpi/pcihp.c | 2 +-
> hw/acpi/piix4.c | 42 +--
> hw/core/irq.c | 14 -
> hw/i386/Kconfig | 3 +-
> hw/i386/acpi-build.c | 5 +-
> hw/i386/pc_piix.c | 10 +-
> hw/i386/xen/xen-hvm.c | 5 +-
> hw/intc/apic_common.c | 49 ----
> hw/isa/Kconfig | 4 +
> hw/isa/Makefile.objs | 1 +
> hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
> hw/isa/piix4.c | 151 ++++++++++-
> hw/mips/gt64xxx_pci.c | 5 +-
> hw/mips/mips_malta.c | 46 +---
> hw/pci-host/Kconfig | 3 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
> hw/timer/i8254_common.c | 40 ---
> include/hw/acpi/piix4.h | 6 -
> include/hw/i386/pc.h | 37 ---
> include/hw/irq.h | 5 -
> include/hw/isa/isa.h | 2 +
> include/hw/pci-host/i440fx.h | 36 +++
> include/hw/southbridge/piix.h | 74 ++++++
> stubs/pci-host-piix.c | 3 +-
> 26 files changed, 699 insertions(+), 683 deletions(-)
> create mode 100644 hw/isa/piix3.c
> rename hw/pci-host/{piix.c => i440fx.c} (58%)
> delete mode 100644 include/hw/acpi/piix4.h
> create mode 100644 include/hw/pci-host/i440fx.h
> create mode 100644 include/hw/southbridge/piix.h
>
> --
> 2.21.0
>
>
>
[-- Attachment #1.2: Type: text/html, Size: 8550 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces
2019-10-18 17:04 ` [Xen-devel] " Aleksandar Markovic
@ 2019-10-19 15:22 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-19 15:22 UTC (permalink / raw)
To: Aleksandar Markovic, Philippe Mathieu-Daudé
Cc: Stefano Stabellini, Eduardo Habkost, Michael S. Tsirkin,
Paul Durrant, qemu-devel, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Aurelien Jarno, Richard Henderson
Hi Aleksandar,
On 10/18/19 7:04 PM, Aleksandar Markovic wrote:
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>> wrote:
>
> The PIIX3 is not tied to the i440FX and can even be used without it.
> Move its creation to the machine code (pc_piix.c).
> We have now removed the last trace of southbridge code in the i440FX
> northbridge.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/i386/pc_piix.c | 8 +++++++-
> hw/pci-host/i440fx.c | 8 --------
> include/hw/pci-host/i440fx.h | 3 +--
> 3 files changed, 8 insertions(+), 11 deletions(-)
>
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
>
> Philippe, I don't have any test equipment available at the moment, did
> you do some smoke tests with new v2 of the series (like booting a Malta
> board, or other relevant scenario)?
This series pass all 32-bit Avocado tests, and if you apply
"tests/acceptance: Fix 64-bit MIPS target tests" I just sent [*],
all the tests pass.
AVOCADO_TIMEOUT_EXPECTED=1 avocado \
--show=app,ssh,console \
run \
-t arch:mipsel -t arch:mips -t arch:mips64el -t arch:mips64 \
tests/acceptance/
[*] mid.mail-archive.com/20191019151058.31733-1-f4bug@amsat.org
> Veuillez agréer, Monsieur Philippe, l'assurance de mon parfaite
> considération.
Merci ;)
> Aleksandar
>
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 11b8de049f..f6e7196a82 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -199,14 +199,20 @@ static void pc_init1(MachineState *machine,
> }
>
> if (pcmc->pci_enabled) {
> + PIIX3State *piix3;
> +
> pci_bus = i440fx_init(host_type,
> pci_type,
> - &i440fx_state, &piix3_devfn,
> &isa_bus, pcms->gsi,
> + &i440fx_state,
> system_memory, system_io,
> machine->ram_size,
> pcms->below_4g_mem_size,
> pcms->above_4g_mem_size,
> pci_memory, ram_memory);
> pcms->bus = pci_bus;
> +
> + piix3 = piix3_create(pci_bus, &isa_bus);
> + piix3->pic = pcms->gsi;
> + piix3_devfn = piix3->dev.devfn;
> } else {
> pci_bus = NULL;
> i440fx_state = NULL;
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
> index 79ecd58a2b..f27131102d 100644
> --- a/hw/pci-host/i440fx.c
> +++ b/hw/pci-host/i440fx.c
> @@ -27,7 +27,6 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_host.h"
> #include "hw/pci-host/i440fx.h"
> -#include "hw/southbridge/piix.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "qapi/error.h"
> @@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> PCII440FXState **pi440fx_state,
> - int *piix3_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> @@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *b;
> PCIDevice *d;
> PCIHostState *s;
> - PIIX3State *piix3;
> PCII440FXState *f;
> unsigned i;
> I440FXState *i440fx;
> @@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type,
> const char *pci_type,
> PAM_EXPAN_SIZE);
> }
>
> - piix3 = piix3_create(b, isa_bus);
> - piix3->pic = pic;
> - *piix3_devfn = piix3->dev.devfn;
> -
> ram_size = ram_size / 8 / 1024 / 1024;
> if (ram_size > 255) {
> ram_size = 255;
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> index e327f9bf87..f54e6466e4 100644
> --- a/include/hw/pci-host/i440fx.h
> +++ b/include/hw/pci-host/i440fx.h
> @@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
> #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
> "igd-passthrough-i440FX"
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> - PCII440FXState **pi440fx_state, int *piix_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> + PCII440FXState **pi440fx_state,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> --
> 2.21.0
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces
@ 2019-10-19 15:22 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-19 15:22 UTC (permalink / raw)
To: Aleksandar Markovic, Philippe Mathieu-Daudé
Cc: Stefano Stabellini, Eduardo Habkost, Michael S. Tsirkin,
Paul Durrant, qemu-devel, Paolo Bonzini, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard, xen-devel,
Aleksandar Rikalo, Aurelien Jarno, Richard Henderson
Hi Aleksandar,
On 10/18/19 7:04 PM, Aleksandar Markovic wrote:
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>> wrote:
>
> The PIIX3 is not tied to the i440FX and can even be used without it.
> Move its creation to the machine code (pc_piix.c).
> We have now removed the last trace of southbridge code in the i440FX
> northbridge.
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/i386/pc_piix.c | 8 +++++++-
> hw/pci-host/i440fx.c | 8 --------
> include/hw/pci-host/i440fx.h | 3 +--
> 3 files changed, 8 insertions(+), 11 deletions(-)
>
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
>
> Philippe, I don't have any test equipment available at the moment, did
> you do some smoke tests with new v2 of the series (like booting a Malta
> board, or other relevant scenario)?
This series pass all 32-bit Avocado tests, and if you apply
"tests/acceptance: Fix 64-bit MIPS target tests" I just sent [*],
all the tests pass.
AVOCADO_TIMEOUT_EXPECTED=1 avocado \
--show=app,ssh,console \
run \
-t arch:mipsel -t arch:mips -t arch:mips64el -t arch:mips64 \
tests/acceptance/
[*] mid.mail-archive.com/20191019151058.31733-1-f4bug@amsat.org
> Veuillez agréer, Monsieur Philippe, l'assurance de mon parfaite
> considération.
Merci ;)
> Aleksandar
>
> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
> index 11b8de049f..f6e7196a82 100644
> --- a/hw/i386/pc_piix.c
> +++ b/hw/i386/pc_piix.c
> @@ -199,14 +199,20 @@ static void pc_init1(MachineState *machine,
> }
>
> if (pcmc->pci_enabled) {
> + PIIX3State *piix3;
> +
> pci_bus = i440fx_init(host_type,
> pci_type,
> - &i440fx_state, &piix3_devfn,
> &isa_bus, pcms->gsi,
> + &i440fx_state,
> system_memory, system_io,
> machine->ram_size,
> pcms->below_4g_mem_size,
> pcms->above_4g_mem_size,
> pci_memory, ram_memory);
> pcms->bus = pci_bus;
> +
> + piix3 = piix3_create(pci_bus, &isa_bus);
> + piix3->pic = pcms->gsi;
> + piix3_devfn = piix3->dev.devfn;
> } else {
> pci_bus = NULL;
> i440fx_state = NULL;
> diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c
> index 79ecd58a2b..f27131102d 100644
> --- a/hw/pci-host/i440fx.c
> +++ b/hw/pci-host/i440fx.c
> @@ -27,7 +27,6 @@
> #include "hw/pci/pci.h"
> #include "hw/pci/pci_host.h"
> #include "hw/pci-host/i440fx.h"
> -#include "hw/southbridge/piix.h"
> #include "hw/qdev-properties.h"
> #include "hw/sysbus.h"
> #include "qapi/error.h"
> @@ -272,8 +271,6 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> PCII440FXState **pi440fx_state,
> - int *piix3_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> @@ -286,7 +283,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *b;
> PCIDevice *d;
> PCIHostState *s;
> - PIIX3State *piix3;
> PCII440FXState *f;
> unsigned i;
> I440FXState *i440fx;
> @@ -339,10 +335,6 @@ PCIBus *i440fx_init(const char *host_type,
> const char *pci_type,
> PAM_EXPAN_SIZE);
> }
>
> - piix3 = piix3_create(b, isa_bus);
> - piix3->pic = pic;
> - *piix3_devfn = piix3->dev.devfn;
> -
> ram_size = ram_size / 8 / 1024 / 1024;
> if (ram_size > 255) {
> ram_size = 255;
> diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h
> index e327f9bf87..f54e6466e4 100644
> --- a/include/hw/pci-host/i440fx.h
> +++ b/include/hw/pci-host/i440fx.h
> @@ -22,8 +22,7 @@ typedef struct PCII440FXState PCII440FXState;
> #define TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE
> "igd-passthrough-i440FX"
>
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> - PCII440FXState **pi440fx_state, int *piix_devfn,
> - ISABus **isa_bus, qemu_irq *pic,
> + PCII440FXState **pi440fx_state,
> MemoryRegion *address_space_mem,
> MemoryRegion *address_space_io,
> ram_addr_t ram_size,
> --
> 2.21.0
>
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 0:54 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 0:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Philippe Mathieu-Daudé,
Eduardo Habkost, Qemu Developers, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 1380 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:50写道：
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The PIIX4 Southbridge is not used by the PC machine,
> but by the Malta board (MIPS). Add a new section to
> keep it covered.
>
> Suggested-by: Michael S. Tsirkin <mst@redhat.com>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
Reviewed-by: Li Qiang <liq3ea@163.com>
> ---
> MAINTAINERS | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fe4dc51b08..c9f625fc2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
> F: hw/pci-host/pam.c
> F: include/hw/pci-host/q35.h
> F: include/hw/pci-host/pam.h
> -F: hw/isa/piix4.c
> F: hw/isa/lpc_ich9.c
> F: hw/i2c/smbus_ich9.c
> F: hw/acpi/piix4.c
> @@ -1716,6 +1715,12 @@ F: hw/display/edid*
> F: include/hw/display/edid.h
> F: qemu-edid.c
>
> +PIIX4 South Bridge (i82371AB)
> +M: Hervé Poussineau <hpoussin@reactos.org>
> +M: Philippe Mathieu-Daudé <f4bug@amsat.org>
> +S: Maintained
> +F: hw/isa/piix4.c
> +
> Firmware configuration (fw_cfg)
> M: Philippe Mathieu-Daudé <philmd@redhat.com>
> R: Laszlo Ersek <lersek@redhat.com>
> --
> 2.21.0
>
>
>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
@ 2019-10-21 0:54 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 0:54 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Philippe Mathieu-Daudé,
Eduardo Habkost, Qemu Developers, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 1380 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:50写道：
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> The PIIX4 Southbridge is not used by the PC machine,
> but by the Malta board (MIPS). Add a new section to
> keep it covered.
>
> Suggested-by: Michael S. Tsirkin <mst@redhat.com>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
Reviewed-by: Li Qiang <liq3ea@163.com>
> ---
> MAINTAINERS | 7 ++++++-
> 1 file changed, 6 insertions(+), 1 deletion(-)
>
> diff --git a/MAINTAINERS b/MAINTAINERS
> index fe4dc51b08..c9f625fc2e 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1230,7 +1230,6 @@ F: hw/pci-host/q35.c
> F: hw/pci-host/pam.c
> F: include/hw/pci-host/q35.h
> F: include/hw/pci-host/pam.h
> -F: hw/isa/piix4.c
> F: hw/isa/lpc_ich9.c
> F: hw/i2c/smbus_ich9.c
> F: hw/acpi/piix4.c
> @@ -1716,6 +1715,12 @@ F: hw/display/edid*
> F: include/hw/display/edid.h
> F: qemu-edid.c
>
> +PIIX4 South Bridge (i82371AB)
> +M: Hervé Poussineau <hpoussin@reactos.org>
> +M: Philippe Mathieu-Daudé <f4bug@amsat.org>
> +S: Maintained
> +F: hw/isa/piix4.c
> +
> Firmware configuration (fw_cfg)
> M: Philippe Mathieu-Daudé <philmd@redhat.com>
> R: Laszlo Ersek <lersek@redhat.com>
> --
> 2.21.0
>
>
>
[-- Attachment #1.2: Type: text/html, Size: 2478 bytes --]
[-- Attachment #2: Type: text/plain, Size: 157 bytes --]
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 02/20] piix4: Add the Reset Control Register
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 1:25 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 1:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 3518 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:50写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 890d999abf..d0b18e0586 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -2,6 +2,7 @@
> * QEMU PIIX4 PCI Bridge Emulation
> *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
> *
> * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> * of this software and associated documentation files (the "Software"),
> to deal
> @@ -28,11 +29,17 @@
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> #include "migration/vmstate.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
>
> PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> +
> + /* Reset Control Register */
> + MemoryRegion rcr_mem;
> + uint8_t rcr;
> } PIIX4State;
>
> #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int len)
> +{
> + PIIX4State *s = opaque;
> +
> + if (val & 4) {
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + return;
> + }
> +
> + s->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int
> len)
> +{
> + PIIX4State *s = opaque;
> +
> + return s->rcr;
> +}
> +
> +static const MemoryRegionOps piix4_rcr_ops = {
> + .read = piix4_rcr_read,
> + .write = piix4_rcr_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> - PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> + PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>
> - if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> pci_address_space_io(dev), errp)) {
> return;
> }
> - piix4_dev = &d->dev;
> +
> + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> + "reset-control", 1);
> + memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
>
Can we use 'RCR_IOPORT' instead of constant value here? Also don't see this
change
in later patches of this seirals.
Anyway
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Thanks,
Li Qiang
> + &s->rcr_mem, 1);
> +
> + piix4_dev = dev;
> }
>
> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 02/20] piix4: Add the Reset Control Register
@ 2019-10-21 1:25 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 1:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 3518 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:50写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> The RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-7-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 890d999abf..d0b18e0586 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -2,6 +2,7 @@
> * QEMU PIIX4 PCI Bridge Emulation
> *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
> *
> * Permission is hereby granted, free of charge, to any person obtaining
> a copy
> * of this software and associated documentation files (the "Software"),
> to deal
> @@ -28,11 +29,17 @@
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> #include "migration/vmstate.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
>
> PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> +
> + /* Reset Control Register */
> + MemoryRegion rcr_mem;
> + uint8_t rcr;
> } PIIX4State;
>
> #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int len)
> +{
> + PIIX4State *s = opaque;
> +
> + if (val & 4) {
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + return;
> + }
> +
> + s->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int
> len)
> +{
> + PIIX4State *s = opaque;
> +
> + return s->rcr;
> +}
> +
> +static const MemoryRegionOps piix4_rcr_ops = {
> + .read = piix4_rcr_read,
> + .write = piix4_rcr_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> - PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> + PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>
> - if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> pci_address_space_io(dev), errp)) {
> return;
> }
> - piix4_dev = &d->dev;
> +
> + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> + "reset-control", 1);
> + memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
>
Can we use 'RCR_IOPORT' instead of constant value here? Also don't see this
change
in later patches of this seirals.
Anyway
Reviewed-by: Li Qiang <liq3ea@gmail.com>
Thanks,
Li Qiang
> + &s->rcr_mem, 1);
> +
> + piix4_dev = dev;
> }
>
> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
>
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 02/20] piix4: Add the Reset Control Register
2019-10-21 1:25 ` [Xen-devel] " Li Qiang
@ 2019-10-21 8:37 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-21 8:37 UTC (permalink / raw)
To: Li Qiang
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
On 10/21/19 3:25 AM, Li Qiang wrote:
>
>
> Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>> 于
> 2019年10月18日周五 下午9:50写道：
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> The RCR I/O port (0xcf9) is used to generate a hard reset or a soft
> reset.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-7-hpoussin@reactos.org
> <mailto:20171216090228.28505-7-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased, updated includes]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 890d999abf..d0b18e0586 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -2,6 +2,7 @@
> * QEMU PIIX4 PCI Bridge Emulation
> *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
> *
> * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> * of this software and associated documentation files (the
> "Software"), to deal
> @@ -28,11 +29,17 @@
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> #include "migration/vmstate.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
>
> PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> +
> + /* Reset Control Register */
> + MemoryRegion rcr_mem;
> + uint8_t rcr;
> } PIIX4State;
>
> #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int len)
> +{
> + PIIX4State *s = opaque;
> +
> + if (val & 4) {
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + return;
> + }
> +
> + s->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned
> int len)
> +{
> + PIIX4State *s = opaque;
> +
> + return s->rcr;
> +}
> +
> +static const MemoryRegionOps piix4_rcr_ops = {
> + .read = piix4_rcr_read,
> + .write = piix4_rcr_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> - PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> + PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>
> - if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> pci_address_space_io(dev), errp)) {
> return;
> }
> - piix4_dev = &d->dev;
> +
> + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> + "reset-control", 1);
> + memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
>
>
>
> Can we use 'RCR_IOPORT' instead of constant value here? Also don't see
> this change
> in later patches of this seirals.
Good idea, I missed this one :)
> Anyway
>
> Reviewed-by: Li Qiang <liq3ea@gmail.com <mailto:liq3ea@gmail.com>>
Thanks!
>
> Thanks,
> Li Qiang
>
> + &s->rcr_mem, 1);
> +
> + piix4_dev = dev;
> }
>
> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 02/20] piix4: Add the Reset Control Register
@ 2019-10-21 8:37 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-21 8:37 UTC (permalink / raw)
To: Li Qiang
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
On 10/21/19 3:25 AM, Li Qiang wrote:
>
>
> Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>> 于
> 2019年10月18日周五 下午9:50写道：
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> The RCR I/O port (0xcf9) is used to generate a hard reset or a soft
> reset.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-7-hpoussin@reactos.org
> <mailto:20171216090228.28505-7-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased, updated includes]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 49 ++++++++++++++++++++++++++++++++++++++++++++++---
> 1 file changed, 46 insertions(+), 3 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 890d999abf..d0b18e0586 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -2,6 +2,7 @@
> * QEMU PIIX4 PCI Bridge Emulation
> *
> * Copyright (c) 2006 Fabrice Bellard
> + * Copyright (c) 2018 Hervé Poussineau
> *
> * Permission is hereby granted, free of charge, to any person
> obtaining a copy
> * of this software and associated documentation files (the
> "Software"), to deal
> @@ -28,11 +29,17 @@
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> #include "migration/vmstate.h"
> +#include "sysemu/reset.h"
> +#include "sysemu/runstate.h"
>
> PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> +
> + /* Reset Control Register */
> + MemoryRegion rcr_mem;
> + uint8_t rcr;
> } PIIX4State;
>
> #define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> @@ -87,15 +94,51 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> + unsigned int len)
> +{
> + PIIX4State *s = opaque;
> +
> + if (val & 4) {
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> + return;
> + }
> +
> + s->rcr = val & 2; /* keep System Reset type only */
> +}
> +
> +static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned
> int len)
> +{
> + PIIX4State *s = opaque;
> +
> + return s->rcr;
> +}
> +
> +static const MemoryRegionOps piix4_rcr_ops = {
> + .read = piix4_rcr_read,
> + .write = piix4_rcr_write,
> + .endianness = DEVICE_LITTLE_ENDIAN,
> + .impl = {
> + .min_access_size = 1,
> + .max_access_size = 1,
> + },
> +};
> +
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> - PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> + PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>
> - if (!isa_bus_new(DEVICE(d), pci_address_space(dev),
> + if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> pci_address_space_io(dev), errp)) {
> return;
> }
> - piix4_dev = &d->dev;
> +
> + memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> + "reset-control", 1);
> + memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
>
>
>
> Can we use 'RCR_IOPORT' instead of constant value here? Also don't see
> this change
> in later patches of this seirals.
Good idea, I missed this one :)
> Anyway
>
> Reviewed-by: Li Qiang <liq3ea@gmail.com <mailto:liq3ea@gmail.com>>
Thanks!
>
> Thanks,
> Li Qiang
>
> + &s->rcr_mem, 1);
> +
> + piix4_dev = dev;
> }
>
> int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> --
> 2.21.0
>
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 14:59 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 14:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 10998 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:52写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
>
Does the piix4 hardware has the GPIO for interrupt? Seems not.
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>
In i8259_init, we also allocate 16 input line and 1 output line.
Seems it is duplicated with the GPIO allocation in previous.
Also
Maybe here can uses
i8259(isa_bus, qemu_allocate_irq(piix4_request_i8259_irq, s, 0));
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
>
Also here s->i8259 and the piix4 isa point to the same input line. Seems
duplicated.
I have come up with a more cleaner patch as following:
Though 'i8259_init' is called in the mips_malta_init. But is uses the isa
bus from piix4 device.
And seems it's more clean.
You can test it with more tests.
Thanks,
Li Qiang
Author: Li Qiang <liq3ea@163.com>
Date: Mon Oct 21 22:41:17 2019 +0800
piix4
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index d0b18e0586..66a041040a 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
@@ -46,6 +47,7 @@ typedef struct PIIX4State {
#define PIIX4_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
+
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *d = PIIX4_PCI_DEVICE(dev);
@@ -141,14 +143,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
piix4_dev = dev;
}
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
- PCIDevice *d;
-
- d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
- return d->devfn;
-}
static void piix4_class_init(ObjectClass *klass, void *data)
{
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..420e0e9e80 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,6 +28,7 @@
#include "cpu.h"
#include "hw/i386/pc.h"
#include "hw/isa/superio.h"
+//#include "hw/isa/piix4.h"
#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
#include "net/net.h"
@@ -97,7 +98,7 @@ typedef struct {
SysBusDevice parent_obj;
MIPSCPSState cps;
- qemu_irq *i8259;
+ qemu_irq i8259[ISA_NUM_IRQS];
} MaltaState;
static ISADevice *pit;
@@ -1235,8 +1236,9 @@ void mips_malta_init(MachineState *machine)
int64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
- qemu_irq *isa_irq;
qemu_irq cbus_irq, i8259_irq;
+ qemu_irq *i8259;
+ PCIDevice *pci;
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
@@ -1407,29 +1409,24 @@ void mips_malta_init(MachineState *machine)
/* Board ID = 0x420 (Malta Board with CoreLV) */
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
- /*
- * We have a circular dependency problem: pci_bus depends on isa_irq,
- * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
- * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
- * qemu_irq_proxy() adds an extra bit of indirection, allowing us
- * to resolve the isa_irq -> i8259 dependency after i8259 is
initialized.
- */
- isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
/* Northbridge */
- pci_bus = gt64120_register(isa_irq);
+ pci_bus = gt64120_register(s->i8259);
/* Southbridge */
ide_drive_get(hd, ARRAY_SIZE(hd));
- piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, "PIIX4");
+ dev = DEVICE(pci);
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ piix4_devfn = pci->devfn;
- /*
- * Interrupt controller
- * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
- */
- s->i8259 = i8259_init(isa_bus, i8259_irq);
+ i8259 = i8259_init(isa_bus, i8259_irq);
+ for (int i = 0; i < ISA_NUM_IRQS; i++) {
+ s->i8259[i] = i8259[i];
+ }
+ g_free(i8259);
isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
>
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^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-21 14:59 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 14:59 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 10998 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:52写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
>
Does the piix4 hardware has the GPIO for interrupt? Seems not.
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>
In i8259_init, we also allocate 16 input line and 1 output line.
Seems it is duplicated with the GPIO allocation in previous.
Also
Maybe here can uses
i8259(isa_bus, qemu_allocate_irq(piix4_request_i8259_irq, s, 0));
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
>
Also here s->i8259 and the piix4 isa point to the same input line. Seems
duplicated.
I have come up with a more cleaner patch as following:
Though 'i8259_init' is called in the mips_malta_init. But is uses the isa
bus from piix4 device.
And seems it's more clean.
You can test it with more tests.
Thanks,
Li Qiang
Author: Li Qiang <liq3ea@163.com>
Date: Mon Oct 21 22:41:17 2019 +0800
piix4
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index d0b18e0586..66a041040a 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -24,6 +24,7 @@
*/
#include "qemu/osdep.h"
+#include "hw/irq.h"
#include "hw/i386/pc.h"
#include "hw/pci/pci.h"
#include "hw/isa/isa.h"
@@ -46,6 +47,7 @@ typedef struct PIIX4State {
#define PIIX4_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
+
static void piix4_isa_reset(DeviceState *dev)
{
PIIX4State *d = PIIX4_PCI_DEVICE(dev);
@@ -141,14 +143,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
piix4_dev = dev;
}
-int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
-{
- PCIDevice *d;
-
- d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
- *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
- return d->devfn;
-}
static void piix4_class_init(ObjectClass *klass, void *data)
{
diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
index 4d9c64b36a..420e0e9e80 100644
--- a/hw/mips/mips_malta.c
+++ b/hw/mips/mips_malta.c
@@ -28,6 +28,7 @@
#include "cpu.h"
#include "hw/i386/pc.h"
#include "hw/isa/superio.h"
+//#include "hw/isa/piix4.h"
#include "hw/dma/i8257.h"
#include "hw/char/serial.h"
#include "net/net.h"
@@ -97,7 +98,7 @@ typedef struct {
SysBusDevice parent_obj;
MIPSCPSState cps;
- qemu_irq *i8259;
+ qemu_irq i8259[ISA_NUM_IRQS];
} MaltaState;
static ISADevice *pit;
@@ -1235,8 +1236,9 @@ void mips_malta_init(MachineState *machine)
int64_t kernel_entry, bootloader_run_addr;
PCIBus *pci_bus;
ISABus *isa_bus;
- qemu_irq *isa_irq;
qemu_irq cbus_irq, i8259_irq;
+ qemu_irq *i8259;
+ PCIDevice *pci;
int piix4_devfn;
I2CBus *smbus;
DriveInfo *dinfo;
@@ -1407,29 +1409,24 @@ void mips_malta_init(MachineState *machine)
/* Board ID = 0x420 (Malta Board with CoreLV) */
stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
- /*
- * We have a circular dependency problem: pci_bus depends on isa_irq,
- * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
- * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
- * qemu_irq_proxy() adds an extra bit of indirection, allowing us
- * to resolve the isa_irq -> i8259 dependency after i8259 is
initialized.
- */
- isa_irq = qemu_irq_proxy(&s->i8259, 16);
-
/* Northbridge */
- pci_bus = gt64120_register(isa_irq);
+ pci_bus = gt64120_register(s->i8259);
/* Southbridge */
ide_drive_get(hd, ARRAY_SIZE(hd));
- piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
+ pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
+ true, "PIIX4");
+ dev = DEVICE(pci);
+ isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
+ piix4_devfn = pci->devfn;
- /*
- * Interrupt controller
- * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
- */
- s->i8259 = i8259_init(isa_bus, i8259_irq);
+ i8259 = i8259_init(isa_bus, i8259_irq);
+ for (int i = 0; i < ISA_NUM_IRQS; i++) {
+ s->i8259[i] = i8259[i];
+ }
+ g_free(i8259);
isa_bus_irqs(isa_bus, s->i8259);
pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
>
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_______________________________________________
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Xen-devel@lists.xenproject.org
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^ permalink raw reply related [flat|nested] 106+ messages in thread
* Re: [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()"
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 15:18 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Thomas Huth, Stefano Stabellini, xen-devel, Paul Durrant,
Michael S. Tsirkin, Qemu Developers, Eduardo Habkost,
Philippe Mathieu-Daudé,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 1932 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:50写道：
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This function isn't used anymore.
>
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
> ---
> hw/core/irq.c | 14 --------------
> include/hw/irq.h | 5 -----
> 2 files changed, 19 deletions(-)
>
> diff --git a/hw/core/irq.c b/hw/core/irq.c
> index 7cc0295d0e..fb3045b912 100644
> --- a/hw/core/irq.c
> +++ b/hw/core/irq.c
> @@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
> return qemu_allocate_irq(qemu_splitirq, s, 0);
> }
>
> -static void proxy_irq_handler(void *opaque, int n, int level)
> -{
> - qemu_irq **target = opaque;
> -
> - if (*target) {
> - qemu_set_irq((*target)[n], level);
> - }
> -}
> -
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
> -{
> - return qemu_allocate_irqs(proxy_irq_handler, target, n);
> -}
> -
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler,
> int n)
> {
> int i;
> diff --git a/include/hw/irq.h b/include/hw/irq.h
> index fe527f6f51..24ba0ece11 100644
> --- a/include/hw/irq.h
> +++ b/include/hw/irq.h
> @@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
> */
> qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
>
> -/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
> - * may be set later.
> - */
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
> -
> /* For internal use in qtest. Similar to qemu_irq_split, but operating
> on an existing vector of qemu_irq. */
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler,
> int n);
> --
> 2.21.0
>
>
>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()"
@ 2019-10-21 15:18 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:18 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Thomas Huth, Stefano Stabellini, xen-devel, Paul Durrant,
Michael S. Tsirkin, Qemu Developers, Eduardo Habkost,
Philippe Mathieu-Daudé,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
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Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:50写道：
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This function isn't used anymore.
>
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
> ---
> hw/core/irq.c | 14 --------------
> include/hw/irq.h | 5 -----
> 2 files changed, 19 deletions(-)
>
> diff --git a/hw/core/irq.c b/hw/core/irq.c
> index 7cc0295d0e..fb3045b912 100644
> --- a/hw/core/irq.c
> +++ b/hw/core/irq.c
> @@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2)
> return qemu_allocate_irq(qemu_splitirq, s, 0);
> }
>
> -static void proxy_irq_handler(void *opaque, int n, int level)
> -{
> - qemu_irq **target = opaque;
> -
> - if (*target) {
> - qemu_set_irq((*target)[n], level);
> - }
> -}
> -
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
> -{
> - return qemu_allocate_irqs(proxy_irq_handler, target, n);
> -}
> -
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler,
> int n)
> {
> int i;
> diff --git a/include/hw/irq.h b/include/hw/irq.h
> index fe527f6f51..24ba0ece11 100644
> --- a/include/hw/irq.h
> +++ b/include/hw/irq.h
> @@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
> */
> qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
>
> -/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
> - * may be set later.
> - */
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
> -
> /* For internal use in qtest. Similar to qemu_irq_split, but operating
> on an existing vector of qemu_irq. */
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler,
> int n);
> --
> 2.21.0
>
>
>
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 15:19 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Philippe Mathieu-Daudé,
Eduardo Habkost, Qemu Developers, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 2215 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:53写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
> ---
> hw/isa/piix4.c | 1 -
> hw/mips/mips_malta.c | 2 +-
> include/hw/isa/isa.h | 2 ++
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 9c37c85ae2..ac9383a658 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -45,7 +45,6 @@ typedef struct PIIX4State {
> uint8_t rcr;
> } PIIX4State;
>
> -#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> #define PIIX4_PCI_DEVICE(obj) \
> OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 7d25ab6c23..e499b7a6bb 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> - true, "PIIX4");
> + true, TYPE_PIIX4_PCI_DEVICE);
> dev = DEVICE(pci);
> isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> piix4_devfn = pci->devfn;
> diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
> index 018ada4f6f..79f703fd6c 100644
> --- a/include/hw/isa/isa.h
> +++ b/include/hw/isa/isa.h
> @@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
> return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
> }
>
> +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
> +
> #endif
> --
> 2.21.0
>
>
>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa
@ 2019-10-21 15:19 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:19 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Philippe Mathieu-Daudé,
Eduardo Habkost, Qemu Developers, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 2215 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:53写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
> ---
> hw/isa/piix4.c | 1 -
> hw/mips/mips_malta.c | 2 +-
> include/hw/isa/isa.h | 2 ++
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 9c37c85ae2..ac9383a658 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -45,7 +45,6 @@ typedef struct PIIX4State {
> uint8_t rcr;
> } PIIX4State;
>
> -#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> #define PIIX4_PCI_DEVICE(obj) \
> OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 7d25ab6c23..e499b7a6bb 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> - true, "PIIX4");
> + true, TYPE_PIIX4_PCI_DEVICE);
> dev = DEVICE(pci);
> isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> piix4_devfn = pci->devfn;
> diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
> index 018ada4f6f..79f703fd6c 100644
> --- a/include/hw/isa/isa.h
> +++ b/include/hw/isa/isa.h
> @@ -147,4 +147,6 @@ static inline ISABus *isa_bus_from_device(ISADevice *d)
> return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
> }
>
> +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
> +
> #endif
> --
> 2.21.0
>
>
>
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 15:25 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 2392 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:55写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8257 instantiated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 4 ++++
> hw/mips/mips_malta.c | 2 --
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index ac9383a658..0b24d8323c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
> #include "migration/vmstate.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
> /* initialize ISA irqs */
> isa_bus_irqs(isa_bus, s->isa);
>
> + /* DMA */
> + i8257_dma_init(isa_bus, 0);
> +
> piix4_dev = dev;
> }
>
>
Could you please explain why this is better calling 'i8257_dma_init' in
piix4 realize function
instead of calling it in mips_malta_init.
I'm still a little of which things should be done in realize and which
should be done in qom instance init function.
Thanks,
Li Qiang
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> - i8257_dma_init(isa_bus, 0);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
@ 2019-10-21 15:25 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:25 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 2392 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:55写道：
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8257 instantiated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 4 ++++
> hw/mips/mips_malta.c | 2 --
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index ac9383a658..0b24d8323c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
> #include "migration/vmstate.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
> /* initialize ISA irqs */
> isa_bus_irqs(isa_bus, s->isa);
>
> + /* DMA */
> + i8257_dma_init(isa_bus, 0);
> +
> piix4_dev = dev;
> }
>
>
Could you please explain why this is better calling 'i8257_dma_init' in
piix4 realize function
instead of calling it in mips_malta_init.
I'm still a little of which things should be done in realize and which
should be done in qom instance init function.
Thanks,
Li Qiang
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> - i8257_dma_init(isa_bus, 0);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
>
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-21 15:28 ` Li Qiang
-1 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 1840 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:53写道：
> In the next commit we'll refactor the PIIX4 code out of
> mips_malta_init(). As a preliminary step, add the 'ide_drives'
> variable and create the drive array dynamically.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
> ---
> hw/mips/mips_malta.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 528c34a1c3..774bb810f6 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> + const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
> + DriveInfo **hd;
> int fl_idx = 0;
> int be;
>
> @@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
> pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> - ide_drive_get(hd, ARRAY_SIZE(hd));
> + hd = g_new(DriveInfo *, ide_drives);
> + ide_drive_get(hd, ide_drives);
>
> pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> true, TYPE_PIIX4_PCI_DEVICE);
> @@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
> }
>
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> + g_free(hd);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> --
> 2.21.0
>
>
>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically
@ 2019-10-21 15:28 ` Li Qiang
0 siblings, 0 replies; 106+ messages in thread
From: Li Qiang @ 2019-10-21 15:28 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 1840 bytes --]
Philippe Mathieu-Daudé <philmd@redhat.com> 于2019年10月18日周五 下午9:53写道：
> In the next commit we'll refactor the PIIX4 code out of
> mips_malta_init(). As a preliminary step, add the 'ide_drives'
> variable and create the drive array dynamically.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>
Reviewed-by: Li Qiang <liq3ea@gmail.com>
> ---
> hw/mips/mips_malta.c | 7 +++++--
> 1 file changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 528c34a1c3..774bb810f6 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1235,7 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
> + const size_t ide_drives = MAX_IDE_BUS * MAX_IDE_DEVS;
> + DriveInfo **hd;
> int fl_idx = 0;
> int be;
>
> @@ -1406,7 +1407,8 @@ void mips_malta_init(MachineState *machine)
> pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> - ide_drive_get(hd, ARRAY_SIZE(hd));
> + hd = g_new(DriveInfo *, ide_drives);
> + ide_drive_get(hd, ide_drives);
>
> pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> true, TYPE_PIIX4_PCI_DEVICE);
> @@ -1421,6 +1423,7 @@ void mips_malta_init(MachineState *machine)
> }
>
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> + g_free(hd);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> --
> 2.21.0
>
>
>
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
2019-10-21 15:25 ` [Xen-devel] " Li Qiang
@ 2019-10-21 15:56 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-21 15:56 UTC (permalink / raw)
To: Li Qiang
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
On 10/21/19 5:25 PM, Li Qiang wrote:
>
>
> Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>> 于
> 2019年10月18日周五 下午9:55写道：
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> Remove i8257 instantiated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org
> <mailto:20171216090228.28505-9-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 4 ++++
> hw/mips/mips_malta.c | 2 --
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index ac9383a658..0b24d8323c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
> #include "migration/vmstate.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error
> **errp)
> /* initialize ISA irqs */
> isa_bus_irqs(isa_bus, s->isa);
>
> + /* DMA */
> + i8257_dma_init(isa_bus, 0);
> +
> piix4_dev = dev;
> }
>
>
> Could you please explain why this is better calling 'i8257_dma_init' in
> piix4 realize function
> instead of calling it in mips_malta_init.
i8257_dma_init() is a bit misnamed as it instantiate 2x i8257.
The PIIX4 integrates 2x i8237 (very similar to the i8257).
The i8237 are parts of the PIIX4 chip, and are not chips on the Malta
board PCB.
So when you instantiate a PIIX4 in QEMU, one expects them integrated,
and should not have to manually manage them outside of the southbridge
chipset.
> I'm still a little of which things should be done in realize and which
> should be done in qom instance init function.
I remember a thread started by Peter Maydell when he was working on the
MPS2 boards, but I can't find it.
Anyway this thread is more recent:
"Object instantiation vs. device realization: what to do when?"
https://www.mail-archive.com/qemu-devel@nongnu.org/msg596361.html
>
> Thanks,
> Li Qiang
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> - i8257_dma_init(isa_bus, 0);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
@ 2019-10-21 15:56 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-21 15:56 UTC (permalink / raw)
To: Li Qiang
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
On 10/21/19 5:25 PM, Li Qiang wrote:
>
>
> Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>> 于
> 2019年10月18日周五 下午9:55写道：
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> Remove i8257 instantiated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org
> <mailto:20171216090228.28505-9-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 4 ++++
> hw/mips/mips_malta.c | 2 --
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index ac9383a658..0b24d8323c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
> #include "migration/vmstate.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error
> **errp)
> /* initialize ISA irqs */
> isa_bus_irqs(isa_bus, s->isa);
>
> + /* DMA */
> + i8257_dma_init(isa_bus, 0);
> +
> piix4_dev = dev;
> }
>
>
> Could you please explain why this is better calling 'i8257_dma_init' in
> piix4 realize function
> instead of calling it in mips_malta_init.
i8257_dma_init() is a bit misnamed as it instantiate 2x i8257.
The PIIX4 integrates 2x i8237 (very similar to the i8257).
The i8237 are parts of the PIIX4 chip, and are not chips on the Malta
board PCB.
So when you instantiate a PIIX4 in QEMU, one expects them integrated,
and should not have to manually manage them outside of the southbridge
chipset.
> I'm still a little of which things should be done in realize and which
> should be done in qom instance init function.
I remember a thread started by Peter Maydell when he was working on the
MPS2 boards, but I can't find it.
Anyway this thread is more recent:
"Object instantiation vs. device realization: what to do when?"
https://www.mail-archive.com/qemu-devel@nongnu.org/msg596361.html
>
> Thanks,
> Li Qiang
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> - i8257_dma_init(isa_bus, 0);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> /* generate SPD EEPROM data */
> --
> 2.21.0
>
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 8:44 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
> ---
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int
> level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
My question is not about this patch:
The function name is "qdev_init_gpio_out_named" but support more than 1
gpio, right? in this case, the name shouldn't be something like
"qdev_init_gpios_out_named"?
> +
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
> s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
> &s->rcr_mem, 1);
Why do you use the priority 1 in this case?
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
> 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on
> isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
> depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
> have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
> us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 8:44 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:44 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
> ---
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int
> level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
My question is not about this patch:
The function name is "qdev_init_gpio_out_named" but support more than 1
gpio, right? in this case, the name shouldn't be something like
"qdev_init_gpios_out_named"?
> +
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
> s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
> &s->rcr_mem, 1);
Why do you use the priority 1 in this case?
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
> 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on
> isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
> depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
> have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
> us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 8:48 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
> ---
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int
> level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
I would like to understand why in `PIIX4State *s = opaque;` its not
necessary a cast or a object macro magic.
Something like:
PIIX4State *s = (PIIX4State*)opaque;
PIIX4State *s = PIIX4STATE(opaque);
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
> s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
> 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on
> isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
> depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
> have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
> us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 8:48 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:48 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
> ---
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int
> level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
I would like to understand why in `PIIX4State *s = opaque;` its not
necessary a cast or a object macro magic.
Something like:
PIIX4State *s = (PIIX4State*)opaque;
PIIX4State *s = PIIX4STATE(opaque);
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
> s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
> 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on
> isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
> depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
> have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
> us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()"
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 8:50 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Stefano Stabellini, xen-devel, Paul Durrant,
Michael S. Tsirkin, Philippe Mathieu-Daudé,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This function isn't used anymore.
>
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/core/irq.c | 14 --------------
> include/hw/irq.h | 5 -----
> 2 files changed, 19 deletions(-)
>
> diff --git a/hw/core/irq.c b/hw/core/irq.c
> index 7cc0295d0e..fb3045b912 100644
> --- a/hw/core/irq.c
> +++ b/hw/core/irq.c
> @@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq
> irq2)
> return qemu_allocate_irq(qemu_splitirq, s, 0);
> }
>
> -static void proxy_irq_handler(void *opaque, int n, int level)
> -{
> - qemu_irq **target = opaque;
> -
> - if (*target) {
> - qemu_set_irq((*target)[n], level);
> - }
> -}
> -
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
> -{
> - return qemu_allocate_irqs(proxy_irq_handler, target, n);
> -}
> -
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler
> handler, int n)
> {
> int i;
> diff --git a/include/hw/irq.h b/include/hw/irq.h
> index fe527f6f51..24ba0ece11 100644
> --- a/include/hw/irq.h
> +++ b/include/hw/irq.h
> @@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
> */
> qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
>
> -/* Returns a new IRQ set which connects 1:1 to another IRQ set,
> which
> - * may be set later.
> - */
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
> -
> /* For internal use in qtest. Similar to qemu_irq_split, but
> operating
> on an existing vector of qemu_irq. */
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler
> handler, int n);
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()"
@ 2019-10-22 8:50 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:50 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Thomas Huth, Stefano Stabellini, xen-devel, Paul Durrant,
Michael S. Tsirkin, Philippe Mathieu-Daudé,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Philippe Mathieu-Daudé <f4bug@amsat.org>
>
> This function isn't used anymore.
>
> This reverts commit 22ec3283efba9ba0792790da786d6776d83f2a92.
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
> hw/core/irq.c | 14 --------------
> include/hw/irq.h | 5 -----
> 2 files changed, 19 deletions(-)
>
> diff --git a/hw/core/irq.c b/hw/core/irq.c
> index 7cc0295d0e..fb3045b912 100644
> --- a/hw/core/irq.c
> +++ b/hw/core/irq.c
> @@ -120,20 +120,6 @@ qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq
> irq2)
> return qemu_allocate_irq(qemu_splitirq, s, 0);
> }
>
> -static void proxy_irq_handler(void *opaque, int n, int level)
> -{
> - qemu_irq **target = opaque;
> -
> - if (*target) {
> - qemu_set_irq((*target)[n], level);
> - }
> -}
> -
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n)
> -{
> - return qemu_allocate_irqs(proxy_irq_handler, target, n);
> -}
> -
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler
> handler, int n)
> {
> int i;
> diff --git a/include/hw/irq.h b/include/hw/irq.h
> index fe527f6f51..24ba0ece11 100644
> --- a/include/hw/irq.h
> +++ b/include/hw/irq.h
> @@ -51,11 +51,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq);
> */
> qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
>
> -/* Returns a new IRQ set which connects 1:1 to another IRQ set,
> which
> - * may be set later.
> - */
> -qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
> -
> /* For internal use in qtest. Similar to qemu_irq_split, but
> operating
> on an existing vector of qemu_irq. */
> void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler
> handler, int n);
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 8:57 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Philippe Mathieu-Daudé,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 1 -
> hw/mips/mips_malta.c | 2 +-
> include/hw/isa/isa.h | 2 ++
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 9c37c85ae2..ac9383a658 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -45,7 +45,6 @@ typedef struct PIIX4State {
> uint8_t rcr;
> } PIIX4State;
>
> -#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> #define PIIX4_PCI_DEVICE(obj) \
> OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 7d25ab6c23..e499b7a6bb 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> - true, "PIIX4");
> + true,
> TYPE_PIIX4_PCI_DEVICE);
> dev = DEVICE(pci);
> isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> piix4_devfn = pci->devfn;
> diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
> index 018ada4f6f..79f703fd6c 100644
> --- a/include/hw/isa/isa.h
> +++ b/include/hw/isa/isa.h
> @@ -147,4 +147,6 @@ static inline ISABus
> *isa_bus_from_device(ISADevice *d)
> return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
> }
>
> +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
> +
> #endif
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa
@ 2019-10-22 8:57 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 8:57 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Philippe Mathieu-Daudé,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Other piix4 parts are already named piix4-ide and piix4-usb-uhci.
>
> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-15-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 1 -
> hw/mips/mips_malta.c | 2 +-
> include/hw/isa/isa.h | 2 ++
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index 9c37c85ae2..ac9383a658 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -45,7 +45,6 @@ typedef struct PIIX4State {
> uint8_t rcr;
> } PIIX4State;
>
> -#define TYPE_PIIX4_PCI_DEVICE "PIIX4"
> #define PIIX4_PCI_DEVICE(obj) \
> OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 7d25ab6c23..e499b7a6bb 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -1414,7 +1414,7 @@ void mips_malta_init(MachineState *machine)
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> - true, "PIIX4");
> + true,
> TYPE_PIIX4_PCI_DEVICE);
> dev = DEVICE(pci);
> isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> piix4_devfn = pci->devfn;
> diff --git a/include/hw/isa/isa.h b/include/hw/isa/isa.h
> index 018ada4f6f..79f703fd6c 100644
> --- a/include/hw/isa/isa.h
> +++ b/include/hw/isa/isa.h
> @@ -147,4 +147,6 @@ static inline ISABus
> *isa_bus_from_device(ISADevice *d)
> return ISA_BUS(qdev_get_parent_bus(DEVICE(d)));
> }
>
> +#define TYPE_PIIX4_PCI_DEVICE "piix4-isa"
> +
> #endif
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 9:01 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 9:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8257 instantiated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 4 ++++
> hw/mips/mips_malta.c | 2 --
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index ac9383a658..0b24d8323c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
> #include "migration/vmstate.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error
> **errp)
> /* initialize ISA irqs */
> isa_bus_irqs(isa_bus, s->isa);
>
> + /* DMA */
> + i8257_dma_init(isa_bus, 0);
> +
> piix4_dev = dev;
> }
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> - i8257_dma_init(isa_bus, 0);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> /* generate SPD EEPROM data */
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet
@ 2019-10-22 9:01 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 9:01 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Remove i8257 instantiated in malta board, to not have it twice.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-9-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 4 ++++
> hw/mips/mips_malta.c | 2 --
> 2 files changed, 4 insertions(+), 2 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index ac9383a658..0b24d8323c 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -29,6 +29,7 @@
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> #include "hw/sysbus.h"
> +#include "hw/dma/i8257.h"
> #include "migration/vmstate.h"
> #include "sysemu/reset.h"
> #include "sysemu/runstate.h"
> @@ -167,6 +168,9 @@ static void piix4_realize(PCIDevice *dev, Error
> **errp)
> /* initialize ISA irqs */
> isa_bus_irqs(isa_bus, s->isa);
>
> + /* DMA */
> + i8257_dma_init(isa_bus, 0);
> +
> piix4_dev = dev;
> }
>
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index e499b7a6bb..df247177ca 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,7 +28,6 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> -#include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> #include "hw/boards.h"
> @@ -1430,7 +1429,6 @@ void mips_malta_init(MachineState *machine)
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> isa_get_irq(NULL, 9), NULL, 0, NULL);
> pit = i8254_pit_init(isa_bus, 0x40, 0, NULL);
> - i8257_dma_init(isa_bus, 0);
> mc146818_rtc_init(isa_bus, 2000, NULL);
>
> /* generate SPD EEPROM data */
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-22 8:48 ` [Xen-devel] " Esteban Bosse
@ 2019-10-22 9:24 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-22 9:24 UTC (permalink / raw)
To: Esteban Bosse, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
On 10/22/19 10:48 AM, Esteban Bosse wrote:
> El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
>> From: Hervé Poussineau <hpoussin@reactos.org>
>>
>> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
>> gpio out.
>> Remove i8259 instanciated in malta board, to not have it twice.
>>
>> We can also remove the now unused piix4_init() function.
>>
>> Acked-by: Michael S. Tsirkin <mst@redhat.com>
>> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
>> ---
>> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
>> include/hw/i386/pc.h | 1 -
>> 3 files changed, 45 insertions(+), 31 deletions(-)
>>
>> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>> index d0b18e0586..9c37c85ae2 100644
>> --- a/hw/isa/piix4.c
>> +++ b/hw/isa/piix4.c
>> @@ -24,6 +24,7 @@
>> */
>>
>> #include "qemu/osdep.h"
>> +#include "hw/irq.h"
>> #include "hw/i386/pc.h"
>> #include "hw/pci/pci.h"
>> #include "hw/isa/isa.h"
>> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>>
>> typedef struct PIIX4State {
>> PCIDevice dev;
>> + qemu_irq cpu_intr;
>> + qemu_irq *isa;
>>
>> /* Reset Control Register */
>> MemoryRegion rcr_mem;
>> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
>> }
>> };
>>
>> +static void piix4_request_i8259_irq(void *opaque, int irq, int
>> level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->cpu_intr, level);
>> +}
> I would like to understand why in `PIIX4State *s = opaque;` its not
> necessary a cast or a object macro magic.
> Something like:
> PIIX4State *s = (PIIX4State*)opaque;
> PIIX4State *s = PIIX4STATE(opaque);
I guess you mean:
#define PIIX4_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
IIUC the OBJECT_CHECK(STATE, OBJ, TYPE) macro verify the QEMU Object
OBJ is of the correct type TYPE, then cast it as a pointer to STATE.
This has some runtime cost.
This is useful when you deal with some child Object which is not TYPE
but inheritate TYPE from a parent, or if the object is an abstract
parent and you want to use its children TYPE implementations.
In piix4_realize(), the function piix4_request_i8259_irq() is registered
by qemu_allocate_irqs() as a handler with 's' as opaque pointer, and we
already know 's' is of type PIIX4State, so using OBJECT_CHECK() is not
necessary.
>> +
>> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->isa[irq], level);
>> +}
>> +
>> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
>> unsigned int len)
>> {
>> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
>> static void piix4_realize(PCIDevice *dev, Error **errp)
>> {
>> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>> + ISABus *isa_bus;
>> + qemu_irq *i8259_out_irq;
>>
>> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> - pci_address_space_io(dev), errp)) {
>> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> + pci_address_space_io(dev), errp);
>> + if (!isa_bus) {
>> return;
>> }
>>
>> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
>> + "isa", ISA_NUM_IRQS);
>> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
>> + "intr", 1);
>> +
>> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
>> s,
>> "reset-control", 1);
>> memory_region_add_subregion_overlap(pci_address_space_io(dev),
>> 0xcf9,
>> &s->rcr_mem, 1);
>>
>> + /* initialize i8259 pic */
>> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
>> 1);
>> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>> +
>> + /* initialize ISA irqs */
>> + isa_bus_irqs(isa_bus, s->isa);
>> +
>> piix4_dev = dev;
>> }
>>
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
>> -{
>> - PCIDevice *d;
>> -
>> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
>> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
>> - return d->devfn;
>> -}
>> -
>> static void piix4_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
>> index 4d9c64b36a..7d25ab6c23 100644
>> --- a/hw/mips/mips_malta.c
>> +++ b/hw/mips/mips_malta.c
>> @@ -97,7 +97,7 @@ typedef struct {
>> SysBusDevice parent_obj;
>>
>> MIPSCPSState cps;
>> - qemu_irq *i8259;
>> + qemu_irq i8259[16];
>> } MaltaState;
>>
>> static ISADevice *pit;
>> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
>> int64_t kernel_entry, bootloader_run_addr;
>> PCIBus *pci_bus;
>> ISABus *isa_bus;
>> - qemu_irq *isa_irq;
>> qemu_irq cbus_irq, i8259_irq;
>> + PCIDevice *pci;
>> int piix4_devfn;
>> I2CBus *smbus;
>> DriveInfo *dinfo;
>> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
>> /* Board ID = 0x420 (Malta Board with CoreLV) */
>> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>>
>> - /*
>> - * We have a circular dependency problem: pci_bus depends on
>> isa_irq,
>> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
>> depends
>> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
>> have
>> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
>> us
>> - * to resolve the isa_irq -> i8259 dependency after i8259 is
>> initialized.
>> - */
>> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
>> -
>> /* Northbridge */
>> - pci_bus = gt64120_register(isa_irq);
>> + pci_bus = gt64120_register(s->i8259);
>>
>> /* Southbridge */
>> ide_drive_get(hd, ARRAY_SIZE(hd));
>>
>> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
>> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
>> + true, "PIIX4");
>> + dev = DEVICE(pci);
>> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>> + piix4_devfn = pci->devfn;
>>
>> - /*
>> - * Interrupt controller
>> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
>> - */
>> - s->i8259 = i8259_init(isa_bus, i8259_irq);
>> + /* Interrupt controller */
>> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
>> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
>> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
>> + }
>>
>> - isa_bus_irqs(isa_bus, s->i8259);
>> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 37bfd95113..374f3e8835 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
>> char *pci_type,
>> PCIBus *find_i440fx(void);
>> /* piix4.c */
>> extern PCIDevice *piix4_dev;
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>>
>> /* pc_sysfw.c */
>> void pc_system_flash_create(PCMachineState *pcms);
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 9:24 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-22 9:24 UTC (permalink / raw)
To: Esteban Bosse, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
On 10/22/19 10:48 AM, Esteban Bosse wrote:
> El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
>> From: Hervé Poussineau <hpoussin@reactos.org>
>>
>> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
>> gpio out.
>> Remove i8259 instanciated in malta board, to not have it twice.
>>
>> We can also remove the now unused piix4_init() function.
>>
>> Acked-by: Michael S. Tsirkin <mst@redhat.com>
>> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
>> ---
>> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
>> include/hw/i386/pc.h | 1 -
>> 3 files changed, 45 insertions(+), 31 deletions(-)
>>
>> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>> index d0b18e0586..9c37c85ae2 100644
>> --- a/hw/isa/piix4.c
>> +++ b/hw/isa/piix4.c
>> @@ -24,6 +24,7 @@
>> */
>>
>> #include "qemu/osdep.h"
>> +#include "hw/irq.h"
>> #include "hw/i386/pc.h"
>> #include "hw/pci/pci.h"
>> #include "hw/isa/isa.h"
>> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>>
>> typedef struct PIIX4State {
>> PCIDevice dev;
>> + qemu_irq cpu_intr;
>> + qemu_irq *isa;
>>
>> /* Reset Control Register */
>> MemoryRegion rcr_mem;
>> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
>> }
>> };
>>
>> +static void piix4_request_i8259_irq(void *opaque, int irq, int
>> level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->cpu_intr, level);
>> +}
> I would like to understand why in `PIIX4State *s = opaque;` its not
> necessary a cast or a object macro magic.
> Something like:
> PIIX4State *s = (PIIX4State*)opaque;
> PIIX4State *s = PIIX4STATE(opaque);
I guess you mean:
#define PIIX4_PCI_DEVICE(obj) \
OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
IIUC the OBJECT_CHECK(STATE, OBJ, TYPE) macro verify the QEMU Object
OBJ is of the correct type TYPE, then cast it as a pointer to STATE.
This has some runtime cost.
This is useful when you deal with some child Object which is not TYPE
but inheritate TYPE from a parent, or if the object is an abstract
parent and you want to use its children TYPE implementations.
In piix4_realize(), the function piix4_request_i8259_irq() is registered
by qemu_allocate_irqs() as a handler with 's' as opaque pointer, and we
already know 's' is of type PIIX4State, so using OBJECT_CHECK() is not
necessary.
>> +
>> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->isa[irq], level);
>> +}
>> +
>> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
>> unsigned int len)
>> {
>> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
>> static void piix4_realize(PCIDevice *dev, Error **errp)
>> {
>> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>> + ISABus *isa_bus;
>> + qemu_irq *i8259_out_irq;
>>
>> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> - pci_address_space_io(dev), errp)) {
>> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> + pci_address_space_io(dev), errp);
>> + if (!isa_bus) {
>> return;
>> }
>>
>> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
>> + "isa", ISA_NUM_IRQS);
>> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
>> + "intr", 1);
>> +
>> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
>> s,
>> "reset-control", 1);
>> memory_region_add_subregion_overlap(pci_address_space_io(dev),
>> 0xcf9,
>> &s->rcr_mem, 1);
>>
>> + /* initialize i8259 pic */
>> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
>> 1);
>> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>> +
>> + /* initialize ISA irqs */
>> + isa_bus_irqs(isa_bus, s->isa);
>> +
>> piix4_dev = dev;
>> }
>>
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
>> -{
>> - PCIDevice *d;
>> -
>> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
>> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
>> - return d->devfn;
>> -}
>> -
>> static void piix4_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
>> index 4d9c64b36a..7d25ab6c23 100644
>> --- a/hw/mips/mips_malta.c
>> +++ b/hw/mips/mips_malta.c
>> @@ -97,7 +97,7 @@ typedef struct {
>> SysBusDevice parent_obj;
>>
>> MIPSCPSState cps;
>> - qemu_irq *i8259;
>> + qemu_irq i8259[16];
>> } MaltaState;
>>
>> static ISADevice *pit;
>> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
>> int64_t kernel_entry, bootloader_run_addr;
>> PCIBus *pci_bus;
>> ISABus *isa_bus;
>> - qemu_irq *isa_irq;
>> qemu_irq cbus_irq, i8259_irq;
>> + PCIDevice *pci;
>> int piix4_devfn;
>> I2CBus *smbus;
>> DriveInfo *dinfo;
>> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
>> /* Board ID = 0x420 (Malta Board with CoreLV) */
>> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>>
>> - /*
>> - * We have a circular dependency problem: pci_bus depends on
>> isa_irq,
>> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
>> depends
>> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
>> have
>> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
>> us
>> - * to resolve the isa_irq -> i8259 dependency after i8259 is
>> initialized.
>> - */
>> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
>> -
>> /* Northbridge */
>> - pci_bus = gt64120_register(isa_irq);
>> + pci_bus = gt64120_register(s->i8259);
>>
>> /* Southbridge */
>> ide_drive_get(hd, ARRAY_SIZE(hd));
>>
>> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
>> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
>> + true, "PIIX4");
>> + dev = DEVICE(pci);
>> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>> + piix4_devfn = pci->devfn;
>>
>> - /*
>> - * Interrupt controller
>> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
>> - */
>> - s->i8259 = i8259_init(isa_bus, i8259_irq);
>> + /* Interrupt controller */
>> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
>> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
>> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
>> + }
>>
>> - isa_bus_irqs(isa_bus, s->i8259);
>> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 37bfd95113..374f3e8835 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
>> char *pci_type,
>> PCIBus *find_i440fx(void);
>> /* piix4.c */
>> extern PCIDevice *piix4_dev;
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>>
>> /* pc_sysfw.c */
>> void pc_system_flash_create(PCMachineState *pcms);
>
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Xen-devel@lists.xenproject.org
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 13/20] hw/pci-host/piix: Extract piix3_create()
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 9:33 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 9:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> Extract the PIIX3 creation code from the i440fx_init() function.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++--------------
> ----
> 1 file changed, 31 insertions(+), 20 deletions(-)
>
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 2f4cbcbfe9..3292703de7 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
> }
> }
>
> +static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> +{
> + PIIX3State *piix3;
> + PCIDevice *pci_dev;
> +
> + /*
> + * Xen supports additional interrupt routes from the PCI devices
> to
> + * the IOAPIC: the four pins of each PCI device on the bus are
> also
> + * connected to the IOAPIC directly.
> + * These additional routes can be discovered through ACPI.
> + */
> + if (xen_enabled()) {
> + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> + TYPE_PIIX3_XEN_DEV
> ICE);
> + piix3 = PIIX3_PCI_DEVICE(pci_dev);
> + pci_bus_irqs(pci_bus, xen_piix3_set_irq,
> xen_pci_slot_get_pirq,
> + piix3, XEN_PIIX_NUM_PIRQS);
> + } else {
> + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> + TYPE_PIIX3_DEVICE)
> ;
> + piix3 = PIIX3_PCI_DEVICE(pci_dev);
> + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> + piix3, PIIX_NUM_PIRQS);
> + pci_bus_set_route_irq_fn(pci_bus,
> piix3_route_intx_pin_to_irq);
> + }
> + *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> +
> + return piix3;
> +}
> +
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> PCII440FXState **pi440fx_state,
> int *piix3_devfn,
> @@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PAM_EXPAN_SIZE);
> }
>
> - /* Xen supports additional interrupt routes from the PCI devices
> to
> - * the IOAPIC: the four pins of each PCI device on the bus are
> also
> - * connected to the IOAPIC directly.
> - * These additional routes can be discovered through ACPI. */
> - if (xen_enabled()) {
> - PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> - -1, true, TYPE_PIIX3_XEN_DEVICE);
> - piix3 = PIIX3_PCI_DEVICE(pci_dev);
> - pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> - piix3, XEN_PIIX_NUM_PIRQS);
> - } else {
> - PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> - -1, true, TYPE_PIIX3_DEVICE);
> - piix3 = PIIX3_PCI_DEVICE(pci_dev);
> - pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
> - PIIX_NUM_PIRQS);
> - pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
> - }
> + piix3 = piix3_create(b, isa_bus);
> piix3->pic = pic;
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> -
> *piix3_devfn = piix3->dev.devfn;
>
> ram_size = ram_size / 8 / 1024 / 1024;
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 13/20] hw/pci-host/piix: Extract piix3_create()
@ 2019-10-22 9:33 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 9:33 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> Extract the PIIX3 creation code from the i440fx_init() function.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/pci-host/piix.c | 51 ++++++++++++++++++++++++++++--------------
> ----
> 1 file changed, 31 insertions(+), 20 deletions(-)
>
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 2f4cbcbfe9..3292703de7 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -331,6 +331,36 @@ static void i440fx_realize(PCIDevice *dev, Error
> **errp)
> }
> }
>
> +static PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus)
> +{
> + PIIX3State *piix3;
> + PCIDevice *pci_dev;
> +
> + /*
> + * Xen supports additional interrupt routes from the PCI devices
> to
> + * the IOAPIC: the four pins of each PCI device on the bus are
> also
> + * connected to the IOAPIC directly.
> + * These additional routes can be discovered through ACPI.
> + */
> + if (xen_enabled()) {
> + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> + TYPE_PIIX3_XEN_DEV
> ICE);
> + piix3 = PIIX3_PCI_DEVICE(pci_dev);
> + pci_bus_irqs(pci_bus, xen_piix3_set_irq,
> xen_pci_slot_get_pirq,
> + piix3, XEN_PIIX_NUM_PIRQS);
> + } else {
> + pci_dev = pci_create_simple_multifunction(pci_bus, -1, true,
> + TYPE_PIIX3_DEVICE)
> ;
> + piix3 = PIIX3_PCI_DEVICE(pci_dev);
> + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq,
> + piix3, PIIX_NUM_PIRQS);
> + pci_bus_set_route_irq_fn(pci_bus,
> piix3_route_intx_pin_to_irq);
> + }
> + *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> +
> + return piix3;
> +}
> +
> PCIBus *i440fx_init(const char *host_type, const char *pci_type,
> PCII440FXState **pi440fx_state,
> int *piix3_devfn,
> @@ -400,27 +430,8 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PAM_EXPAN_SIZE);
> }
>
> - /* Xen supports additional interrupt routes from the PCI devices
> to
> - * the IOAPIC: the four pins of each PCI device on the bus are
> also
> - * connected to the IOAPIC directly.
> - * These additional routes can be discovered through ACPI. */
> - if (xen_enabled()) {
> - PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> - -1, true, TYPE_PIIX3_XEN_DEVICE);
> - piix3 = PIIX3_PCI_DEVICE(pci_dev);
> - pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
> - piix3, XEN_PIIX_NUM_PIRQS);
> - } else {
> - PCIDevice *pci_dev = pci_create_simple_multifunction(b,
> - -1, true, TYPE_PIIX3_DEVICE);
> - piix3 = PIIX3_PCI_DEVICE(pci_dev);
> - pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
> - PIIX_NUM_PIRQS);
> - pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
> - }
> + piix3 = piix3_create(b, isa_bus);
> piix3->pic = pic;
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
> -
> *piix3_devfn = piix3->dev.devfn;
>
> ram_size = ram_size / 8 / 1024 / 1024;
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-22 8:44 ` [Xen-devel] " Esteban Bosse
@ 2019-10-22 9:35 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-22 9:35 UTC (permalink / raw)
To: Esteban Bosse, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
On 10/22/19 10:44 AM, Esteban Bosse wrote:
> El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
>> From: Hervé Poussineau <hpoussin@reactos.org>
>>
>> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
>> gpio out.
>> Remove i8259 instanciated in malta board, to not have it twice.
>>
>> We can also remove the now unused piix4_init() function.
>>
>> Acked-by: Michael S. Tsirkin <mst@redhat.com>
>> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
>> ---
>> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
>> include/hw/i386/pc.h | 1 -
>> 3 files changed, 45 insertions(+), 31 deletions(-)
>>
>> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>> index d0b18e0586..9c37c85ae2 100644
>> --- a/hw/isa/piix4.c
>> +++ b/hw/isa/piix4.c
>> @@ -24,6 +24,7 @@
>> */
>>
>> #include "qemu/osdep.h"
>> +#include "hw/irq.h"
>> #include "hw/i386/pc.h"
>> #include "hw/pci/pci.h"
>> #include "hw/isa/isa.h"
>> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>>
>> typedef struct PIIX4State {
>> PCIDevice dev;
>> + qemu_irq cpu_intr;
>> + qemu_irq *isa;
>>
>> /* Reset Control Register */
>> MemoryRegion rcr_mem;
>> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
>> }
>> };
>>
>> +static void piix4_request_i8259_irq(void *opaque, int irq, int
>> level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->cpu_intr, level);
>> +}
>> +
>> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->isa[irq], level);
>> +}
>> +
>> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
>> unsigned int len)
>> {
>> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
>> static void piix4_realize(PCIDevice *dev, Error **errp)
>> {
>> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>> + ISABus *isa_bus;
>> + qemu_irq *i8259_out_irq;
>>
>> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> - pci_address_space_io(dev), errp)) {
>> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> + pci_address_space_io(dev), errp);
>> + if (!isa_bus) {
>> return;
>> }
>>
>> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
>> + "isa", ISA_NUM_IRQS);
>> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
>> + "intr", 1);
> My question is not about this patch:
>
> The function name is "qdev_init_gpio_out_named" but support more than 1
> gpio, right? in this case, the name shouldn't be something like
> "qdev_init_gpios_out_named"?
Indeed devices can have various IRQ output lines.
Note, QEMU does not intend to model full devices, but only the
part required to run a guest. If a guest doesn't use some part
of a device, QEMU will likely not model it.
For example, sometimes a device can have N output IRQ to signal
various error conditions, which are usually used by specific
firmwares in embedded devices. QEMU might not model embedded
boards using this device but we can find it in a generic machine
which runs a full operating system. So far these OS don't care
about handling these errors, so QEMU will only model the IRQ
line required to run the OS, no more. This is on purpose.
Now about the naming, I have no preference which form is better.
>> +
>> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
>> s,
>> "reset-control", 1);
>> memory_region_add_subregion_overlap(pci_address_space_io(dev),
>> 0xcf9,
>> &s->rcr_mem, 1);
> Why do you use the priority 1 in this case?
>>
>> + /* initialize i8259 pic */
>> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
>> 1);
>> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>> +
>> + /* initialize ISA irqs */
>> + isa_bus_irqs(isa_bus, s->isa);
>> +
>> piix4_dev = dev;
>> }
>>
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
>> -{
>> - PCIDevice *d;
>> -
>> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
>> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
>> - return d->devfn;
>> -}
>> -
>> static void piix4_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
>> index 4d9c64b36a..7d25ab6c23 100644
>> --- a/hw/mips/mips_malta.c
>> +++ b/hw/mips/mips_malta.c
>> @@ -97,7 +97,7 @@ typedef struct {
>> SysBusDevice parent_obj;
>>
>> MIPSCPSState cps;
>> - qemu_irq *i8259;
>> + qemu_irq i8259[16];
16 -> ISA_NUM_IRQS
>> } MaltaState;
>>
>> static ISADevice *pit;
>> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
>> int64_t kernel_entry, bootloader_run_addr;
>> PCIBus *pci_bus;
>> ISABus *isa_bus;
>> - qemu_irq *isa_irq;
>> qemu_irq cbus_irq, i8259_irq;
>> + PCIDevice *pci;
>> int piix4_devfn;
>> I2CBus *smbus;
>> DriveInfo *dinfo;
>> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
>> /* Board ID = 0x420 (Malta Board with CoreLV) */
>> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>>
>> - /*
>> - * We have a circular dependency problem: pci_bus depends on
>> isa_irq,
>> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
>> depends
>> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
>> have
>> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
>> us
>> - * to resolve the isa_irq -> i8259 dependency after i8259 is
>> initialized.
>> - */
>> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
>> -
>> /* Northbridge */
>> - pci_bus = gt64120_register(isa_irq);
>> + pci_bus = gt64120_register(s->i8259);
>>
>> /* Southbridge */
>> ide_drive_get(hd, ARRAY_SIZE(hd));
>>
>> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
>> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
>> + true, "PIIX4");
>> + dev = DEVICE(pci);
>> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>> + piix4_devfn = pci->devfn;
>>
>> - /*
>> - * Interrupt controller
>> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
>> - */
>> - s->i8259 = i8259_init(isa_bus, i8259_irq);
>> + /* Interrupt controller */
>> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
>> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
>> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
>> + }
>>
>> - isa_bus_irqs(isa_bus, s->i8259);
>> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 37bfd95113..374f3e8835 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
>> char *pci_type,
>> PCIBus *find_i440fx(void);
>> /* piix4.c */
>> extern PCIDevice *piix4_dev;
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>>
>> /* pc_sysfw.c */
>> void pc_system_flash_create(PCMachineState *pcms);
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 9:35 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-22 9:35 UTC (permalink / raw)
To: Esteban Bosse, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
On 10/22/19 10:44 AM, Esteban Bosse wrote:
> El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
>> From: Hervé Poussineau <hpoussin@reactos.org>
>>
>> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
>> gpio out.
>> Remove i8259 instanciated in malta board, to not have it twice.
>>
>> We can also remove the now unused piix4_init() function.
>>
>> Acked-by: Michael S. Tsirkin <mst@redhat.com>
>> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
>> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
>> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
>> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
>> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
>> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
>> ---
>> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++--------
>> ---
>> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
>> include/hw/i386/pc.h | 1 -
>> 3 files changed, 45 insertions(+), 31 deletions(-)
>>
>> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>> index d0b18e0586..9c37c85ae2 100644
>> --- a/hw/isa/piix4.c
>> +++ b/hw/isa/piix4.c
>> @@ -24,6 +24,7 @@
>> */
>>
>> #include "qemu/osdep.h"
>> +#include "hw/irq.h"
>> #include "hw/i386/pc.h"
>> #include "hw/pci/pci.h"
>> #include "hw/isa/isa.h"
>> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>>
>> typedef struct PIIX4State {
>> PCIDevice dev;
>> + qemu_irq cpu_intr;
>> + qemu_irq *isa;
>>
>> /* Reset Control Register */
>> MemoryRegion rcr_mem;
>> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
>> }
>> };
>>
>> +static void piix4_request_i8259_irq(void *opaque, int irq, int
>> level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->cpu_intr, level);
>> +}
>> +
>> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
>> +{
>> + PIIX4State *s = opaque;
>> + qemu_set_irq(s->isa[irq], level);
>> +}
>> +
>> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
>> unsigned int len)
>> {
>> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
>> static void piix4_realize(PCIDevice *dev, Error **errp)
>> {
>> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
>> + ISABus *isa_bus;
>> + qemu_irq *i8259_out_irq;
>>
>> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> - pci_address_space_io(dev), errp)) {
>> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
>> + pci_address_space_io(dev), errp);
>> + if (!isa_bus) {
>> return;
>> }
>>
>> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
>> + "isa", ISA_NUM_IRQS);
>> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
>> + "intr", 1);
> My question is not about this patch:
>
> The function name is "qdev_init_gpio_out_named" but support more than 1
> gpio, right? in this case, the name shouldn't be something like
> "qdev_init_gpios_out_named"?
Indeed devices can have various IRQ output lines.
Note, QEMU does not intend to model full devices, but only the
part required to run a guest. If a guest doesn't use some part
of a device, QEMU will likely not model it.
For example, sometimes a device can have N output IRQ to signal
various error conditions, which are usually used by specific
firmwares in embedded devices. QEMU might not model embedded
boards using this device but we can find it in a generic machine
which runs a full operating system. So far these OS don't care
about handling these errors, so QEMU will only model the IRQ
line required to run the OS, no more. This is on purpose.
Now about the naming, I have no preference which form is better.
>> +
>> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops,
>> s,
>> "reset-control", 1);
>> memory_region_add_subregion_overlap(pci_address_space_io(dev),
>> 0xcf9,
>> &s->rcr_mem, 1);
> Why do you use the priority 1 in this case?
>>
>> + /* initialize i8259 pic */
>> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s,
>> 1);
>> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>> +
>> + /* initialize ISA irqs */
>> + isa_bus_irqs(isa_bus, s->isa);
>> +
>> piix4_dev = dev;
>> }
>>
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
>> -{
>> - PCIDevice *d;
>> -
>> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
>> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
>> - return d->devfn;
>> -}
>> -
>> static void piix4_class_init(ObjectClass *klass, void *data)
>> {
>> DeviceClass *dc = DEVICE_CLASS(klass);
>> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
>> index 4d9c64b36a..7d25ab6c23 100644
>> --- a/hw/mips/mips_malta.c
>> +++ b/hw/mips/mips_malta.c
>> @@ -97,7 +97,7 @@ typedef struct {
>> SysBusDevice parent_obj;
>>
>> MIPSCPSState cps;
>> - qemu_irq *i8259;
>> + qemu_irq i8259[16];
16 -> ISA_NUM_IRQS
>> } MaltaState;
>>
>> static ISADevice *pit;
>> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
>> int64_t kernel_entry, bootloader_run_addr;
>> PCIBus *pci_bus;
>> ISABus *isa_bus;
>> - qemu_irq *isa_irq;
>> qemu_irq cbus_irq, i8259_irq;
>> + PCIDevice *pci;
>> int piix4_devfn;
>> I2CBus *smbus;
>> DriveInfo *dinfo;
>> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
>> /* Board ID = 0x420 (Malta Board with CoreLV) */
>> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>>
>> - /*
>> - * We have a circular dependency problem: pci_bus depends on
>> isa_irq,
>> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
>> depends
>> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we
>> have
>> - * qemu_irq_proxy() adds an extra bit of indirection, allowing
>> us
>> - * to resolve the isa_irq -> i8259 dependency after i8259 is
>> initialized.
>> - */
>> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
>> -
>> /* Northbridge */
>> - pci_bus = gt64120_register(isa_irq);
>> + pci_bus = gt64120_register(s->i8259);
>>
>> /* Southbridge */
>> ide_drive_get(hd, ARRAY_SIZE(hd));
>>
>> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
>> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
>> + true, "PIIX4");
>> + dev = DEVICE(pci);
>> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
>> + piix4_devfn = pci->devfn;
>>
>> - /*
>> - * Interrupt controller
>> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
>> - */
>> - s->i8259 = i8259_init(isa_bus, i8259_irq);
>> + /* Interrupt controller */
>> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
>> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
>> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
>> + }
>>
>> - isa_bus_irqs(isa_bus, s->i8259);
>> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
>> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
>> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
>> index 37bfd95113..374f3e8835 100644
>> --- a/include/hw/i386/pc.h
>> +++ b/include/hw/i386/pc.h
>> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
>> char *pci_type,
>> PCIBus *find_i440fx(void);
>> /* piix4.c */
>> extern PCIDevice *piix4_dev;
>> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>>
>> /* pc_sysfw.c */
>> void pc_system_flash_create(PCMachineState *pcms);
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 17/20] hw/pci-host/piix: Fix code style issues
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 9:39 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 9:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> We will move this code, fix its style first.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/pci-host/piix.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 95b04122fa..1544c4726b 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -133,9 +133,10 @@ static PCIINTxRoute
> piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
> static void piix3_write_config_xen(PCIDevice *dev,
> uint32_t address, uint32_t val, int
> len);
>
> -/* return the global irq number corresponding to a given device irq
> - pin. We could also use the bus number to have a more precise
> - mapping. */
> +/*
> + * Return the global irq number corresponding to a given device irq
> + * pin. We could also use the bus number to have a more precise
> mapping.
> + */
> static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> {
> int slot_addend;
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 17/20] hw/pci-host/piix: Fix code style issues
@ 2019-10-22 9:39 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-22 9:39 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> We will move this code, fix its style first.
>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/pci-host/piix.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> index 95b04122fa..1544c4726b 100644
> --- a/hw/pci-host/piix.c
> +++ b/hw/pci-host/piix.c
> @@ -133,9 +133,10 @@ static PCIINTxRoute
> piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
> static void piix3_write_config_xen(PCIDevice *dev,
> uint32_t address, uint32_t val, int
> len);
>
> -/* return the global irq number corresponding to a given device irq
> - pin. We could also use the bus number to have a more precise
> - mapping. */
> +/*
> + * Return the global irq number corresponding to a given device irq
> + * pin. We could also use the bus number to have a more precise
> mapping.
> + */
> static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
> {
> int slot_addend;
Reviewed-by: Esteban Bosse <estebanbosse@gmail.com>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-22 8:48 ` [Xen-devel] " Esteban Bosse
@ 2019-10-22 9:42 ` Peter Maydell
-1 siblings, 0 replies; 106+ messages in thread
From: Peter Maydell @ 2019-10-22 9:42 UTC (permalink / raw)
To: Esteban Bosse
Cc: Stefano Stabellini, Eduardo Habkost, Michael S. Tsirkin,
Paul Durrant, QEMU Developers, Paolo Bonzini,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, open list:X86, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Aurelien Jarno, Richard Henderson
On Tue, 22 Oct 2019 at 09:52, Esteban Bosse <estebanbosse@gmail.com> wrote:
>
> El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> > +static void piix4_request_i8259_irq(void *opaque, int irq, int
> > level)
> > +{
> > + PIIX4State *s = opaque;
> > + qemu_set_irq(s->cpu_intr, level);
> > +}
> I would like to understand why in `PIIX4State *s = opaque;` its not
> necessary a cast or a object macro magic.
> Something like:
> PIIX4State *s = (PIIX4State*)opaque;
> PIIX4State *s = PIIX4STATE(opaque);
The simple answer to "why don't we need a cast" is
"because the type of 'opaque' is 'void *', and in C there is
no need to explicitly cast a 'void *' as it will be implicitly
converted to the pointer type of the destination". (This is
different from C++, which does require an explicit cast for void*.)
For QOM types, QEMU conventionally uses the QOM casting
macro to convert a pointer-to-instance to
pointer-to-instance-of-parent-class and vice versa.
In some places, like this one, what we have is just a
void* representing opaque data having been passed around.
You could use the QOM cast macro here, which would add
a bit of extra type-safety, but the project doesn't have
a strong convention here on whether to do so or not, so
you'll often see the just-assignment code.
thanks
-- PMM
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 9:42 ` Peter Maydell
0 siblings, 0 replies; 106+ messages in thread
From: Peter Maydell @ 2019-10-22 9:42 UTC (permalink / raw)
To: Esteban Bosse
Cc: Stefano Stabellini, Eduardo Habkost, Michael S. Tsirkin,
Paul Durrant, QEMU Developers, Paolo Bonzini,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, open list:X86, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Aurelien Jarno, Richard Henderson
On Tue, 22 Oct 2019 at 09:52, Esteban Bosse <estebanbosse@gmail.com> wrote:
>
> El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé escribió:
> > +static void piix4_request_i8259_irq(void *opaque, int irq, int
> > level)
> > +{
> > + PIIX4State *s = opaque;
> > + qemu_set_irq(s->cpu_intr, level);
> > +}
> I would like to understand why in `PIIX4State *s = opaque;` its not
> necessary a cast or a object macro magic.
> Something like:
> PIIX4State *s = (PIIX4State*)opaque;
> PIIX4State *s = PIIX4STATE(opaque);
The simple answer to "why don't we need a cast" is
"because the type of 'opaque' is 'void *', and in C there is
no need to explicitly cast a 'void *' as it will be implicitly
converted to the pointer type of the destination". (This is
different from C++, which does require an explicit cast for void*.)
For QOM types, QEMU conventionally uses the QOM casting
macro to convert a pointer-to-instance to
pointer-to-instance-of-parent-class and vice versa.
In some places, like this one, what we have is just a
void* representing opaque data having been passed around.
You could use the QOM cast macro here, which would add
a bit of extra type-safety, but the project doesn't have
a strong convention here on whether to do so or not, so
you'll often see the just-assignment code.
thanks
-- PMM
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-22 9:53 ` Aleksandar Markovic
-1 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-22 9:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 6864 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
>
A detail: In the title:
Add a i8259 -> Add an i8259
A.
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
>
[-- Attachment #2: Type: text/html, Size: 9098 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 9:53 ` Aleksandar Markovic
0 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-22 9:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 6864 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> From: Hervé Poussineau <hpoussin@reactos.org>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4 gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
>
A detail: In the title:
Add a i8259 -> Add an i8259
A.
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev), 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const char
> *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
>
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_______________________________________________
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-22 9:53 ` [Xen-devel] " Aleksandar Markovic
@ 2019-10-22 10:09 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-22 10:09 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
On 10/22/19 11:53 AM, Aleksandar Markovic wrote:
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>> wrote:
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org
> <mailto:20171216090228.28505-8-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
>
>
> A detail: In the title:
> Add a i8259 -> Add an i8259
OK.
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-22 10:09 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-22 10:09 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
On 10/22/19 11:53 AM, Aleksandar Markovic wrote:
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>> wrote:
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org
> <mailto:20171216090228.28505-8-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
>
>
> A detail: In the title:
> Add a i8259 -> Add an i8259
OK.
_______________________________________________
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Xen-devel@lists.xenproject.org
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-22 9:42 ` [Xen-devel] " Peter Maydell
@ 2019-10-23 18:52 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-23 18:52 UTC (permalink / raw)
To: Peter Maydell
Cc: Stefano Stabellini, Eduardo Habkost, Michael S. Tsirkin,
Paul Durrant, QEMU Developers, Paolo Bonzini,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, open list:X86, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Aurelien Jarno, Richard Henderson
El mar, 22-10-2019 a las 10:42 +0100, Peter Maydell escribió:
> On Tue, 22 Oct 2019 at 09:52, Esteban Bosse <estebanbosse@gmail.com>
> wrote:
> > El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé
> > escribió:
> > > +static void piix4_request_i8259_irq(void *opaque, int irq, int
> > > level)
> > > +{
> > > + PIIX4State *s = opaque;
> > > + qemu_set_irq(s->cpu_intr, level);
> > > +}
> > I would like to understand why in `PIIX4State *s = opaque;` its not
> > necessary a cast or a object macro magic.
> > Something like:
> > PIIX4State *s = (PIIX4State*)opaque;
> > PIIX4State *s = PIIX4STATE(opaque);
>
> The simple answer to "why don't we need a cast" is
> "because the type of 'opaque' is 'void *', and in C there is
> no need to explicitly cast a 'void *' as it will be implicitly
> converted to the pointer type of the destination". (This is
> different from C++, which does require an explicit cast for void*.)
>
> For QOM types, QEMU conventionally uses the QOM casting
> macro to convert a pointer-to-instance to
> pointer-to-instance-of-parent-class and vice versa.
> In some places, like this one, what we have is just a
> void* representing opaque data having been passed around.
> You could use the QOM cast macro here, which would add
> a bit of extra type-safety, but the project doesn't have
> a strong convention here on whether to do so or not, so
> you'll often see the just-assignment code.
>
> thanks
> -- PMM
Thank you very much for your detailed explanation :).
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-23 18:52 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-23 18:52 UTC (permalink / raw)
To: Peter Maydell
Cc: Stefano Stabellini, Eduardo Habkost, Michael S. Tsirkin,
Paul Durrant, QEMU Developers, Paolo Bonzini,
Hervé Poussineau, Aleksandar Markovic, Igor Mammedov,
Anthony Perard, open list:X86, Aleksandar Rikalo,
Philippe Mathieu-Daudé,
Aurelien Jarno, Richard Henderson
El mar, 22-10-2019 a las 10:42 +0100, Peter Maydell escribió:
> On Tue, 22 Oct 2019 at 09:52, Esteban Bosse <estebanbosse@gmail.com>
> wrote:
> > El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé
> > escribió:
> > > +static void piix4_request_i8259_irq(void *opaque, int irq, int
> > > level)
> > > +{
> > > + PIIX4State *s = opaque;
> > > + qemu_set_irq(s->cpu_intr, level);
> > > +}
> > I would like to understand why in `PIIX4State *s = opaque;` its not
> > necessary a cast or a object macro magic.
> > Something like:
> > PIIX4State *s = (PIIX4State*)opaque;
> > PIIX4State *s = PIIX4STATE(opaque);
>
> The simple answer to "why don't we need a cast" is
> "because the type of 'opaque' is 'void *', and in C there is
> no need to explicitly cast a 'void *' as it will be implicitly
> converted to the pointer type of the destination". (This is
> different from C++, which does require an explicit cast for void*.)
>
> For QOM types, QEMU conventionally uses the QOM casting
> macro to convert a pointer-to-instance to
> pointer-to-instance-of-parent-class and vice versa.
> In some places, like this one, what we have is just a
> void* representing opaque data having been passed around.
> You could use the QOM cast macro here, which would add
> a bit of extra type-safety, but the project doesn't have
> a strong convention here on whether to do so or not, so
> you'll often see the just-assignment code.
>
> thanks
> -- PMM
Thank you very much for your detailed explanation :).
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-22 9:35 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-23 18:53 ` Esteban Bosse
-1 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-23 18:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El mar, 22-10-2019 a las 11:35 +0200, Philippe Mathieu-Daudé escribió:
> On 10/22/19 10:44 AM, Esteban Bosse wrote:
> > El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé
> > escribió:
> > > From: Hervé Poussineau <hpoussin@reactos.org>
> > >
> > > Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> > > gpio out.
> > > Remove i8259 instanciated in malta board, to not have it twice.
> > >
> > > We can also remove the now unused piix4_init() function.
> > >
> > > Acked-by: Michael S. Tsirkin <mst@redhat.com>
> > > Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> > > Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> > > Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> > > Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> > > [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > > ---
> > > hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----
> > > ---
> > > ---
> > > hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> > > include/hw/i386/pc.h | 1 -
> > > 3 files changed, 45 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> > > index d0b18e0586..9c37c85ae2 100644
> > > --- a/hw/isa/piix4.c
> > > +++ b/hw/isa/piix4.c
> > > @@ -24,6 +24,7 @@
> > > */
> > >
> > > #include "qemu/osdep.h"
> > > +#include "hw/irq.h"
> > > #include "hw/i386/pc.h"
> > > #include "hw/pci/pci.h"
> > > #include "hw/isa/isa.h"
> > > @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
> > >
> > > typedef struct PIIX4State {
> > > PCIDevice dev;
> > > + qemu_irq cpu_intr;
> > > + qemu_irq *isa;
> > >
> > > /* Reset Control Register */
> > > MemoryRegion rcr_mem;
> > > @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4
> > > = {
> > > }
> > > };
> > >
> > > +static void piix4_request_i8259_irq(void *opaque, int irq, int
> > > level)
> > > +{
> > > + PIIX4State *s = opaque;
> > > + qemu_set_irq(s->cpu_intr, level);
> > > +}
> > > +
> > > +static void piix4_set_i8259_irq(void *opaque, int irq, int
> > > level)
> > > +{
> > > + PIIX4State *s = opaque;
> > > + qemu_set_irq(s->isa[irq], level);
> > > +}
> > > +
> > > static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t
> > > val,
> > > unsigned int len)
> > > {
> > > @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops
> > > = {
> > > static void piix4_realize(PCIDevice *dev, Error **errp)
> > > {
> > > PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> > > + ISABus *isa_bus;
> > > + qemu_irq *i8259_out_irq;
> > >
> > > - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> > > - pci_address_space_io(dev), errp)) {
> > > + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> > > + pci_address_space_io(dev), errp);
> > > + if (!isa_bus) {
> > > return;
> > > }
> > >
> > > + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> > > + "isa", ISA_NUM_IRQS);
> > > + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> > > + "intr", 1);
> > My question is not about this patch:
> >
> > The function name is "qdev_init_gpio_out_named" but support more
> > than 1
> > gpio, right? in this case, the name shouldn't be something like
> > "qdev_init_gpios_out_named"?
>
> Indeed devices can have various IRQ output lines.
>
> Note, QEMU does not intend to model full devices, but only the
> part required to run a guest. If a guest doesn't use some part
> of a device, QEMU will likely not model it.
>
> For example, sometimes a device can have N output IRQ to signal
> various error conditions, which are usually used by specific
> firmwares in embedded devices. QEMU might not model embedded
> boards using this device but we can find it in a generic machine
> which runs a full operating system. So far these OS don't care
> about handling these errors, so QEMU will only model the IRQ
> line required to run the OS, no more. This is on purpose.
>
> Now about the naming, I have no preference which form is better.
>
> > > +
> > > memory_region_init_io(&s->rcr_mem, OBJECT(dev),
> > > &piix4_rcr_ops,
> > > s,
> > > "reset-control", 1);
> > > memory_region_add_subregion_overlap(pci_address_space_io(de
> > > v),
> > > 0xcf9,
> > > &s->rcr_mem, 1);
> > Why do you use the priority 1 in this case?
> > >
> > > + /* initialize i8259 pic */
> > > + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq,
> > > s,
> > > 1);
> > > + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> > > +
> > > + /* initialize ISA irqs */
> > > + isa_bus_irqs(isa_bus, s->isa);
> > > +
> > > piix4_dev = dev;
> > > }
> > >
> > > -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> > > -{
> > > - PCIDevice *d;
> > > -
> > > - d = pci_create_simple_multifunction(bus, devfn, true,
> > > "PIIX4");
> > > - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> > > - return d->devfn;
> > > -}
> > > -
> > > static void piix4_class_init(ObjectClass *klass, void *data)
> > > {
> > > DeviceClass *dc = DEVICE_CLASS(klass);
> > > diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> > > index 4d9c64b36a..7d25ab6c23 100644
> > > --- a/hw/mips/mips_malta.c
> > > +++ b/hw/mips/mips_malta.c
> > > @@ -97,7 +97,7 @@ typedef struct {
> > > SysBusDevice parent_obj;
> > >
> > > MIPSCPSState cps;
> > > - qemu_irq *i8259;
> > > + qemu_irq i8259[16];
>
> 16 -> ISA_NUM_IRQS
>
> > > } MaltaState;
> > >
> > > static ISADevice *pit;
> > > @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> > > int64_t kernel_entry, bootloader_run_addr;
> > > PCIBus *pci_bus;
> > > ISABus *isa_bus;
> > > - qemu_irq *isa_irq;
> > > qemu_irq cbus_irq, i8259_irq;
> > > + PCIDevice *pci;
> > > int piix4_devfn;
> > > I2CBus *smbus;
> > > DriveInfo *dinfo;
> > > @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState
> > > *machine)
> > > /* Board ID = 0x420 (Malta Board with CoreLV) */
> > > stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10,
> > > 0x00000420);
> > >
> > > - /*
> > > - * We have a circular dependency problem: pci_bus depends on
> > > isa_irq,
> > > - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
> > > depends
> > > - * on piix4, and piix4 depends on pci_bus. To stop the
> > > cycle we
> > > have
> > > - * qemu_irq_proxy() adds an extra bit of indirection,
> > > allowing
> > > us
> > > - * to resolve the isa_irq -> i8259 dependency after i8259 is
> > > initialized.
> > > - */
> > > - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> > > -
> > > /* Northbridge */
> > > - pci_bus = gt64120_register(isa_irq);
> > > + pci_bus = gt64120_register(s->i8259);
> > >
> > > /* Southbridge */
> > > ide_drive_get(hd, ARRAY_SIZE(hd));
> > >
> > > - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> > > + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10,
> > > 0),
> > > + true, "PIIX4");
> > > + dev = DEVICE(pci);
> > > + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> > > + piix4_devfn = pci->devfn;
> > >
> > > - /*
> > > - * Interrupt controller
> > > - * The 8259 is attached to the MIPS CPU INT0 pin, ie
> > > interrupt 2
> > > - */
> > > - s->i8259 = i8259_init(isa_bus, i8259_irq);
> > > + /* Interrupt controller */
> > > + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> > > + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> > > + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> > > + }
> > >
> > > - isa_bus_irqs(isa_bus, s->i8259);
> > > pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> > > pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-
> > > uhci");
> > > smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > > index 37bfd95113..374f3e8835 100644
> > > --- a/include/hw/i386/pc.h
> > > +++ b/include/hw/i386/pc.h
> > > @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type,
> > > const
> > > char *pci_type,
> > > PCIBus *find_i440fx(void);
> > > /* piix4.c */
> > > extern PCIDevice *piix4_dev;
> > > -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
> > >
> > > /* pc_sysfw.c */
> > > void pc_system_flash_create(PCMachineState *pcms);
Thank you very much for your explanation :).
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-23 18:53 ` Esteban Bosse
0 siblings, 0 replies; 106+ messages in thread
From: Esteban Bosse @ 2019-10-23 18:53 UTC (permalink / raw)
To: Philippe Mathieu-Daudé, qemu-devel
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Eduardo Habkost, Hervé Poussineau, Aleksandar Markovic,
Igor Mammedov, Anthony Perard, Paolo Bonzini, Aleksandar Rikalo,
Aurelien Jarno, Richard Henderson
El mar, 22-10-2019 a las 11:35 +0200, Philippe Mathieu-Daudé escribió:
> On 10/22/19 10:44 AM, Esteban Bosse wrote:
> > El vie, 18-10-2019 a las 15:47 +0200, Philippe Mathieu-Daudé
> > escribió:
> > > From: Hervé Poussineau <hpoussin@reactos.org>
> > >
> > > Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> > > gpio out.
> > > Remove i8259 instanciated in malta board, to not have it twice.
> > >
> > > We can also remove the now unused piix4_init() function.
> > >
> > > Acked-by: Michael S. Tsirkin <mst@redhat.com>
> > > Acked-by: Paolo Bonzini <pbonzini@redhat.com>
> > > Signed-off-by: Hervé Poussineau <hpoussin@reactos.org>
> > > Message-Id: <20171216090228.28505-8-hpoussin@reactos.org>
> > > Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> > > [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> > > Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
> > > ---
> > > hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----
> > > ---
> > > ---
> > > hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> > > include/hw/i386/pc.h | 1 -
> > > 3 files changed, 45 insertions(+), 31 deletions(-)
> > >
> > > diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> > > index d0b18e0586..9c37c85ae2 100644
> > > --- a/hw/isa/piix4.c
> > > +++ b/hw/isa/piix4.c
> > > @@ -24,6 +24,7 @@
> > > */
> > >
> > > #include "qemu/osdep.h"
> > > +#include "hw/irq.h"
> > > #include "hw/i386/pc.h"
> > > #include "hw/pci/pci.h"
> > > #include "hw/isa/isa.h"
> > > @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
> > >
> > > typedef struct PIIX4State {
> > > PCIDevice dev;
> > > + qemu_irq cpu_intr;
> > > + qemu_irq *isa;
> > >
> > > /* Reset Control Register */
> > > MemoryRegion rcr_mem;
> > > @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4
> > > = {
> > > }
> > > };
> > >
> > > +static void piix4_request_i8259_irq(void *opaque, int irq, int
> > > level)
> > > +{
> > > + PIIX4State *s = opaque;
> > > + qemu_set_irq(s->cpu_intr, level);
> > > +}
> > > +
> > > +static void piix4_set_i8259_irq(void *opaque, int irq, int
> > > level)
> > > +{
> > > + PIIX4State *s = opaque;
> > > + qemu_set_irq(s->isa[irq], level);
> > > +}
> > > +
> > > static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t
> > > val,
> > > unsigned int len)
> > > {
> > > @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops
> > > = {
> > > static void piix4_realize(PCIDevice *dev, Error **errp)
> > > {
> > > PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> > > + ISABus *isa_bus;
> > > + qemu_irq *i8259_out_irq;
> > >
> > > - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> > > - pci_address_space_io(dev), errp)) {
> > > + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> > > + pci_address_space_io(dev), errp);
> > > + if (!isa_bus) {
> > > return;
> > > }
> > >
> > > + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> > > + "isa", ISA_NUM_IRQS);
> > > + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> > > + "intr", 1);
> > My question is not about this patch:
> >
> > The function name is "qdev_init_gpio_out_named" but support more
> > than 1
> > gpio, right? in this case, the name shouldn't be something like
> > "qdev_init_gpios_out_named"?
>
> Indeed devices can have various IRQ output lines.
>
> Note, QEMU does not intend to model full devices, but only the
> part required to run a guest. If a guest doesn't use some part
> of a device, QEMU will likely not model it.
>
> For example, sometimes a device can have N output IRQ to signal
> various error conditions, which are usually used by specific
> firmwares in embedded devices. QEMU might not model embedded
> boards using this device but we can find it in a generic machine
> which runs a full operating system. So far these OS don't care
> about handling these errors, so QEMU will only model the IRQ
> line required to run the OS, no more. This is on purpose.
>
> Now about the naming, I have no preference which form is better.
>
> > > +
> > > memory_region_init_io(&s->rcr_mem, OBJECT(dev),
> > > &piix4_rcr_ops,
> > > s,
> > > "reset-control", 1);
> > > memory_region_add_subregion_overlap(pci_address_space_io(de
> > > v),
> > > 0xcf9,
> > > &s->rcr_mem, 1);
> > Why do you use the priority 1 in this case?
> > >
> > > + /* initialize i8259 pic */
> > > + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq,
> > > s,
> > > 1);
> > > + s->isa = i8259_init(isa_bus, *i8259_out_irq);
> > > +
> > > + /* initialize ISA irqs */
> > > + isa_bus_irqs(isa_bus, s->isa);
> > > +
> > > piix4_dev = dev;
> > > }
> > >
> > > -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> > > -{
> > > - PCIDevice *d;
> > > -
> > > - d = pci_create_simple_multifunction(bus, devfn, true,
> > > "PIIX4");
> > > - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> > > - return d->devfn;
> > > -}
> > > -
> > > static void piix4_class_init(ObjectClass *klass, void *data)
> > > {
> > > DeviceClass *dc = DEVICE_CLASS(klass);
> > > diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> > > index 4d9c64b36a..7d25ab6c23 100644
> > > --- a/hw/mips/mips_malta.c
> > > +++ b/hw/mips/mips_malta.c
> > > @@ -97,7 +97,7 @@ typedef struct {
> > > SysBusDevice parent_obj;
> > >
> > > MIPSCPSState cps;
> > > - qemu_irq *i8259;
> > > + qemu_irq i8259[16];
>
> 16 -> ISA_NUM_IRQS
>
> > > } MaltaState;
> > >
> > > static ISADevice *pit;
> > > @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> > > int64_t kernel_entry, bootloader_run_addr;
> > > PCIBus *pci_bus;
> > > ISABus *isa_bus;
> > > - qemu_irq *isa_irq;
> > > qemu_irq cbus_irq, i8259_irq;
> > > + PCIDevice *pci;
> > > int piix4_devfn;
> > > I2CBus *smbus;
> > > DriveInfo *dinfo;
> > > @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState
> > > *machine)
> > > /* Board ID = 0x420 (Malta Board with CoreLV) */
> > > stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10,
> > > 0x00000420);
> > >
> > > - /*
> > > - * We have a circular dependency problem: pci_bus depends on
> > > isa_irq,
> > > - * isa_irq is provided by i8259, i8259 depends on ISA, ISA
> > > depends
> > > - * on piix4, and piix4 depends on pci_bus. To stop the
> > > cycle we
> > > have
> > > - * qemu_irq_proxy() adds an extra bit of indirection,
> > > allowing
> > > us
> > > - * to resolve the isa_irq -> i8259 dependency after i8259 is
> > > initialized.
> > > - */
> > > - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> > > -
> > > /* Northbridge */
> > > - pci_bus = gt64120_register(isa_irq);
> > > + pci_bus = gt64120_register(s->i8259);
> > >
> > > /* Southbridge */
> > > ide_drive_get(hd, ARRAY_SIZE(hd));
> > >
> > > - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> > > + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10,
> > > 0),
> > > + true, "PIIX4");
> > > + dev = DEVICE(pci);
> > > + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> > > + piix4_devfn = pci->devfn;
> > >
> > > - /*
> > > - * Interrupt controller
> > > - * The 8259 is attached to the MIPS CPU INT0 pin, ie
> > > interrupt 2
> > > - */
> > > - s->i8259 = i8259_init(isa_bus, i8259_irq);
> > > + /* Interrupt controller */
> > > + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> > > + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> > > + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> > > + }
> > >
> > > - isa_bus_irqs(isa_bus, s->i8259);
> > > pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> > > pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-
> > > uhci");
> > > smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > > index 37bfd95113..374f3e8835 100644
> > > --- a/include/hw/i386/pc.h
> > > +++ b/include/hw/i386/pc.h
> > > @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type,
> > > const
> > > char *pci_type,
> > > PCIBus *find_i440fx(void);
> > > /* piix4.c */
> > > extern PCIDevice *piix4_dev;
> > > -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
> > >
> > > /* pc_sysfw.c */
> > > void pc_system_flash_create(PCMachineState *pcms);
Thank you very much for your explanation :).
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-24 19:55 ` Aleksandar Markovic
-1 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-24 19:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 6501 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> Changes since v1 [0]:
> - Removed patch reintroducing DO_UPCAST() use (thuth)
> - Took various patches out to reduce series (thuth)
> - Added review tags (thanks all for reviewing!)
>
>
Philippe,
Do you intend to submit v3? The softfreeze is close.
A.
> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
> Key:
> [----] : patches are identical
> [####] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
>
> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC
> Chipsets'
> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified
> in datasheet'
> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in
> datasheet'
> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in
> datasheet'
> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in
> datasheet'
> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array
> dynamically'
> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as
> piix4_create()'
> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
> 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old
> handlers'
> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route
> Control Registers'
> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to
> hw/pci-host/i440fx.h'
> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
> hw/isa/piix3.c'
> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as
> 'i440fx''
> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
>
> Previous cover:
>
> This series is a rework of "piix4: cleanup and improvements" [1]
> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>
> Still trying to remove the strong X86/PC dependency 2 years later,
> one step at a time.
> Here we split the PIIX3 southbridge from i440FX northbridge.
> The i440FX northbridge is only used by the PC machine, while the
> PIIX southbridge is also used by the Malta MIPS machine.
>
> This is also a step forward using KConfig with the Malta board.
> Without this split, it was impossible to compile the Malta without
> pulling various X86 pieces of code.
>
> The overall design cleanup is not yet perfect, but enough to post
> as a series.
>
> Now that the PIIX3 code is extracted, the code duplication with the
> PIIX4 chipset is obvious. Not worth improving for now because it
> isn't broken.
>
> [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
> [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>
> Based-on: <20191018133547.10936-1-philmd@redhat.com>
> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
> rtc_init()
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
>
> Hervé Poussineau (5):
> piix4: Add the Reset Control Register
> piix4: Add a i8259 Interrupt Controller as specified in datasheet
> piix4: Rename PIIX4 object to piix4-isa
> piix4: Add a i8257 DMA Controller as specified in datasheet
> piix4: Add a i8254 PIT Controller as specified in datasheet
>
> Philippe Mathieu-Daudé (15):
> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
> Revert "irq: introduce qemu_irq_proxy()"
> piix4: Add a MC146818 RTC Controller as specified in datasheet
> hw/mips/mips_malta: Create IDE hard drive array dynamically
> hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
> hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
> hw/pci-host/piix: Extract piix3_create()
> hw/pci-host/piix: Move RCR_IOPORT register definition
> hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
> hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
> hw/pci-host/piix: Fix code style issues
> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
> hw/pci-host/i440fx: Remove the last PIIX3 traces
>
> MAINTAINERS | 14 +-
> hw/acpi/pcihp.c | 2 +-
> hw/acpi/piix4.c | 42 +--
> hw/core/irq.c | 14 -
> hw/i386/Kconfig | 3 +-
> hw/i386/acpi-build.c | 5 +-
> hw/i386/pc_piix.c | 10 +-
> hw/i386/xen/xen-hvm.c | 5 +-
> hw/intc/apic_common.c | 49 ----
> hw/isa/Kconfig | 4 +
> hw/isa/Makefile.objs | 1 +
> hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
> hw/isa/piix4.c | 151 ++++++++++-
> hw/mips/gt64xxx_pci.c | 5 +-
> hw/mips/mips_malta.c | 46 +---
> hw/pci-host/Kconfig | 3 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
> hw/timer/i8254_common.c | 40 ---
> include/hw/acpi/piix4.h | 6 -
> include/hw/i386/pc.h | 37 ---
> include/hw/irq.h | 5 -
> include/hw/isa/isa.h | 2 +
> include/hw/pci-host/i440fx.h | 36 +++
> include/hw/southbridge/piix.h | 74 ++++++
> stubs/pci-host-piix.c | 3 +-
> 26 files changed, 699 insertions(+), 683 deletions(-)
> create mode 100644 hw/isa/piix3.c
> rename hw/pci-host/{piix.c => i440fx.c} (58%)
> delete mode 100644 include/hw/acpi/piix4.h
> create mode 100644 include/hw/pci-host/i440fx.h
> create mode 100644 include/hw/southbridge/piix.h
>
> --
> 2.21.0
>
>
>
[-- Attachment #2: Type: text/html, Size: 8120 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-24 19:55 ` Aleksandar Markovic
0 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-24 19:55 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 6501 bytes --]
On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> Changes since v1 [0]:
> - Removed patch reintroducing DO_UPCAST() use (thuth)
> - Took various patches out to reduce series (thuth)
> - Added review tags (thanks all for reviewing!)
>
>
Philippe,
Do you intend to submit v3? The softfreeze is close.
A.
> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
> Key:
> [----] : patches are identical
> [####] : number of functional differences between upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual differences,
> respectively
>
> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC
> Chipsets'
> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified
> in datasheet'
> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in
> datasheet'
> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in
> datasheet'
> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in
> datasheet'
> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array
> dynamically'
> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code as
> piix4_create()'
> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
> 012/20:[----] [--] 'hw/i386: Remove obsolete LoadStateHandler::load_state_old
> handlers'
> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route
> Control Registers'
> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to
> hw/pci-host/i440fx.h'
> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
> hw/isa/piix3.c'
> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as
> 'i440fx''
> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
>
> Previous cover:
>
> This series is a rework of "piix4: cleanup and improvements" [1]
> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>
> Still trying to remove the strong X86/PC dependency 2 years later,
> one step at a time.
> Here we split the PIIX3 southbridge from i440FX northbridge.
> The i440FX northbridge is only used by the PC machine, while the
> PIIX southbridge is also used by the Malta MIPS machine.
>
> This is also a step forward using KConfig with the Malta board.
> Without this split, it was impossible to compile the Malta without
> pulling various X86 pieces of code.
>
> The overall design cleanup is not yet perfect, but enough to post
> as a series.
>
> Now that the PIIX3 code is extracted, the code duplication with the
> PIIX4 chipset is obvious. Not worth improving for now because it
> isn't broken.
>
> [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
> [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>
> Based-on: <20191018133547.10936-1-philmd@redhat.com>
> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
> rtc_init()
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
>
> Hervé Poussineau (5):
> piix4: Add the Reset Control Register
> piix4: Add a i8259 Interrupt Controller as specified in datasheet
> piix4: Rename PIIX4 object to piix4-isa
> piix4: Add a i8257 DMA Controller as specified in datasheet
> piix4: Add a i8254 PIT Controller as specified in datasheet
>
> Philippe Mathieu-Daudé (15):
> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
> Revert "irq: introduce qemu_irq_proxy()"
> piix4: Add a MC146818 RTC Controller as specified in datasheet
> hw/mips/mips_malta: Create IDE hard drive array dynamically
> hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
> hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
> hw/pci-host/piix: Extract piix3_create()
> hw/pci-host/piix: Move RCR_IOPORT register definition
> hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
> hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
> hw/pci-host/piix: Fix code style issues
> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
> hw/pci-host/i440fx: Remove the last PIIX3 traces
>
> MAINTAINERS | 14 +-
> hw/acpi/pcihp.c | 2 +-
> hw/acpi/piix4.c | 42 +--
> hw/core/irq.c | 14 -
> hw/i386/Kconfig | 3 +-
> hw/i386/acpi-build.c | 5 +-
> hw/i386/pc_piix.c | 10 +-
> hw/i386/xen/xen-hvm.c | 5 +-
> hw/intc/apic_common.c | 49 ----
> hw/isa/Kconfig | 4 +
> hw/isa/Makefile.objs | 1 +
> hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
> hw/isa/piix4.c | 151 ++++++++++-
> hw/mips/gt64xxx_pci.c | 5 +-
> hw/mips/mips_malta.c | 46 +---
> hw/pci-host/Kconfig | 3 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
> hw/timer/i8254_common.c | 40 ---
> include/hw/acpi/piix4.h | 6 -
> include/hw/i386/pc.h | 37 ---
> include/hw/irq.h | 5 -
> include/hw/isa/isa.h | 2 +
> include/hw/pci-host/i440fx.h | 36 +++
> include/hw/southbridge/piix.h | 74 ++++++
> stubs/pci-host-piix.c | 3 +-
> 26 files changed, 699 insertions(+), 683 deletions(-)
> create mode 100644 hw/isa/piix3.c
> rename hw/pci-host/{piix.c => i440fx.c} (58%)
> delete mode 100644 include/hw/acpi/piix4.h
> create mode 100644 include/hw/pci-host/i440fx.h
> create mode 100644 include/hw/southbridge/piix.h
>
> --
> 2.21.0
>
>
>
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
2019-10-24 19:55 ` [Xen-devel] " Aleksandar Markovic
@ 2019-10-25 10:51 ` Aleksandar Markovic
-1 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-25 10:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 6973 bytes --]
On Thursday, October 24, 2019, Aleksandar Markovic <
aleksandar.m.mail@gmail.com> wrote:
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
> wrote:
>
>> Changes since v1 [0]:
>> - Removed patch reintroducing DO_UPCAST() use (thuth)
>> - Took various patches out to reduce series (thuth)
>> - Added review tags (thanks all for reviewing!)
>>
>>
> Philippe,
>
> Do you intend to submit v3? The softfreeze is close.
>
> A.
>
>
Philippe,
It looks you are very busy these days. Do you mind my integrating this
series in next Mips queue, in its present v2 state? (You can certainly do
further refinements later on.)
Aleksandar
>
>
>> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
>> Key:
>> [----] : patches are identical
>> [####] : number of functional differences between upstream/downstream
>> patch
>> [down] : patch is downstream-only
>> The flags [FC] indicate (F)unctional and (C)ontextual differences,
>> respectively
>>
>> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC
>> Chipsets'
>> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
>> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified
>> in datasheet'
>> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
>> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
>> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in
>> datasheet'
>> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in
>> datasheet'
>> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in
>> datasheet'
>> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array
>> dynamically'
>> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code
>> as piix4_create()'
>> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
>> 012/20:[----] [--] 'hw/i386: Remove obsolete
>> LoadStateHandler::load_state_old handlers'
>> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
>> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
>> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route
>> Control Registers'
>> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to
>> hw/pci-host/i440fx.h'
>> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
>> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
>> hw/isa/piix3.c'
>> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as
>> 'i440fx''
>> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
>>
>> Previous cover:
>>
>> This series is a rework of "piix4: cleanup and improvements" [1]
>> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>>
>> Still trying to remove the strong X86/PC dependency 2 years later,
>> one step at a time.
>> Here we split the PIIX3 southbridge from i440FX northbridge.
>> The i440FX northbridge is only used by the PC machine, while the
>> PIIX southbridge is also used by the Malta MIPS machine.
>>
>> This is also a step forward using KConfig with the Malta board.
>> Without this split, it was impossible to compile the Malta without
>> pulling various X86 pieces of code.
>>
>> The overall design cleanup is not yet perfect, but enough to post
>> as a series.
>>
>> Now that the PIIX3 code is extracted, the code duplication with the
>> PIIX4 chipset is obvious. Not worth improving for now because it
>> isn't broken.
>>
>> [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
>> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
>> [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>>
>> Based-on: <20191018133547.10936-1-philmd@redhat.com>
>> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
>> rtc_init()
>> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
>>
>> Hervé Poussineau (5):
>> piix4: Add the Reset Control Register
>> piix4: Add a i8259 Interrupt Controller as specified in datasheet
>> piix4: Rename PIIX4 object to piix4-isa
>> piix4: Add a i8257 DMA Controller as specified in datasheet
>> piix4: Add a i8254 PIT Controller as specified in datasheet
>>
>> Philippe Mathieu-Daudé (15):
>> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
>> Revert "irq: introduce qemu_irq_proxy()"
>> piix4: Add a MC146818 RTC Controller as specified in datasheet
>> hw/mips/mips_malta: Create IDE hard drive array dynamically
>> hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
>> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
>> hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
>> hw/pci-host/piix: Extract piix3_create()
>> hw/pci-host/piix: Move RCR_IOPORT register definition
>> hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
>> hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
>> hw/pci-host/piix: Fix code style issues
>> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
>> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
>> hw/pci-host/i440fx: Remove the last PIIX3 traces
>>
>> MAINTAINERS | 14 +-
>> hw/acpi/pcihp.c | 2 +-
>> hw/acpi/piix4.c | 42 +--
>> hw/core/irq.c | 14 -
>> hw/i386/Kconfig | 3 +-
>> hw/i386/acpi-build.c | 5 +-
>> hw/i386/pc_piix.c | 10 +-
>> hw/i386/xen/xen-hvm.c | 5 +-
>> hw/intc/apic_common.c | 49 ----
>> hw/isa/Kconfig | 4 +
>> hw/isa/Makefile.objs | 1 +
>> hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
>> hw/isa/piix4.c | 151 ++++++++++-
>> hw/mips/gt64xxx_pci.c | 5 +-
>> hw/mips/mips_malta.c | 46 +---
>> hw/pci-host/Kconfig | 3 +-
>> hw/pci-host/Makefile.objs | 2 +-
>> hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
>> hw/timer/i8254_common.c | 40 ---
>> include/hw/acpi/piix4.h | 6 -
>> include/hw/i386/pc.h | 37 ---
>> include/hw/irq.h | 5 -
>> include/hw/isa/isa.h | 2 +
>> include/hw/pci-host/i440fx.h | 36 +++
>> include/hw/southbridge/piix.h | 74 ++++++
>> stubs/pci-host-piix.c | 3 +-
>> 26 files changed, 699 insertions(+), 683 deletions(-)
>> create mode 100644 hw/isa/piix3.c
>> rename hw/pci-host/{piix.c => i440fx.c} (58%)
>> delete mode 100644 include/hw/acpi/piix4.h
>> create mode 100644 include/hw/pci-host/i440fx.h
>> create mode 100644 include/hw/southbridge/piix.h
>>
>> --
>> 2.21.0
>>
>>
>>
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^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-25 10:51 ` Aleksandar Markovic
0 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-25 10:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 6973 bytes --]
On Thursday, October 24, 2019, Aleksandar Markovic <
aleksandar.m.mail@gmail.com> wrote:
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
> wrote:
>
>> Changes since v1 [0]:
>> - Removed patch reintroducing DO_UPCAST() use (thuth)
>> - Took various patches out to reduce series (thuth)
>> - Added review tags (thanks all for reviewing!)
>>
>>
> Philippe,
>
> Do you intend to submit v3? The softfreeze is close.
>
> A.
>
>
Philippe,
It looks you are very busy these days. Do you mind my integrating this
series in next Mips queue, in its present v2 state? (You can certainly do
further refinements later on.)
Aleksandar
>
>
>> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
>> Key:
>> [----] : patches are identical
>> [####] : number of functional differences between upstream/downstream
>> patch
>> [down] : patch is downstream-only
>> The flags [FC] indicate (F)unctional and (C)ontextual differences,
>> respectively
>>
>> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge separate from PC
>> Chipsets'
>> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
>> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as specified
>> in datasheet'
>> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
>> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
>> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as specified in
>> datasheet'
>> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as specified in
>> datasheet'
>> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as specified in
>> datasheet'
>> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive array
>> dynamically'
>> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4 creation code
>> as piix4_create()'
>> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c'
>> 012/20:[----] [--] 'hw/i386: Remove obsolete
>> LoadStateHandler::load_state_old handlers'
>> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
>> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register definition'
>> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX IRQ Route
>> Control Registers'
>> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations to
>> hw/pci-host/i440fx.h'
>> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
>> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
>> hw/isa/piix3.c'
>> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix' as
>> 'i440fx''
>> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3 traces'
>>
>> Previous cover:
>>
>> This series is a rework of "piix4: cleanup and improvements" [1]
>> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>>
>> Still trying to remove the strong X86/PC dependency 2 years later,
>> one step at a time.
>> Here we split the PIIX3 southbridge from i440FX northbridge.
>> The i440FX northbridge is only used by the PC machine, while the
>> PIIX southbridge is also used by the Malta MIPS machine.
>>
>> This is also a step forward using KConfig with the Malta board.
>> Without this split, it was impossible to compile the Malta without
>> pulling various X86 pieces of code.
>>
>> The overall design cleanup is not yet perfect, but enough to post
>> as a series.
>>
>> Now that the PIIX3 code is extracted, the code duplication with the
>> PIIX4 chipset is obvious. Not worth improving for now because it
>> isn't broken.
>>
>> [0] https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
>> [1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
>> [2] https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>>
>> Based-on: <20191018133547.10936-1-philmd@redhat.com>
>> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead of
>> rtc_init()
>> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
>>
>> Hervé Poussineau (5):
>> piix4: Add the Reset Control Register
>> piix4: Add a i8259 Interrupt Controller as specified in datasheet
>> piix4: Rename PIIX4 object to piix4-isa
>> piix4: Add a i8257 DMA Controller as specified in datasheet
>> piix4: Add a i8254 PIT Controller as specified in datasheet
>>
>> Philippe Mathieu-Daudé (15):
>> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
>> Revert "irq: introduce qemu_irq_proxy()"
>> piix4: Add a MC146818 RTC Controller as specified in datasheet
>> hw/mips/mips_malta: Create IDE hard drive array dynamically
>> hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create()
>> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
>> hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers
>> hw/pci-host/piix: Extract piix3_create()
>> hw/pci-host/piix: Move RCR_IOPORT register definition
>> hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers
>> hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h
>> hw/pci-host/piix: Fix code style issues
>> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
>> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
>> hw/pci-host/i440fx: Remove the last PIIX3 traces
>>
>> MAINTAINERS | 14 +-
>> hw/acpi/pcihp.c | 2 +-
>> hw/acpi/piix4.c | 42 +--
>> hw/core/irq.c | 14 -
>> hw/i386/Kconfig | 3 +-
>> hw/i386/acpi-build.c | 5 +-
>> hw/i386/pc_piix.c | 10 +-
>> hw/i386/xen/xen-hvm.c | 5 +-
>> hw/intc/apic_common.c | 49 ----
>> hw/isa/Kconfig | 4 +
>> hw/isa/Makefile.objs | 1 +
>> hw/isa/piix3.c | 399 +++++++++++++++++++++++++++++
>> hw/isa/piix4.c | 151 ++++++++++-
>> hw/mips/gt64xxx_pci.c | 5 +-
>> hw/mips/mips_malta.c | 46 +---
>> hw/pci-host/Kconfig | 3 +-
>> hw/pci-host/Makefile.objs | 2 +-
>> hw/pci-host/{piix.c => i440fx.c} | 424 +------------------------------
>> hw/timer/i8254_common.c | 40 ---
>> include/hw/acpi/piix4.h | 6 -
>> include/hw/i386/pc.h | 37 ---
>> include/hw/irq.h | 5 -
>> include/hw/isa/isa.h | 2 +
>> include/hw/pci-host/i440fx.h | 36 +++
>> include/hw/southbridge/piix.h | 74 ++++++
>> stubs/pci-host-piix.c | 3 +-
>> 26 files changed, 699 insertions(+), 683 deletions(-)
>> create mode 100644 hw/isa/piix3.c
>> rename hw/pci-host/{piix.c => i440fx.c} (58%)
>> delete mode 100644 include/hw/acpi/piix4.h
>> create mode 100644 include/hw/pci-host/i440fx.h
>> create mode 100644 include/hw/southbridge/piix.h
>>
>> --
>> 2.21.0
>>
>>
>>
[-- Attachment #1.2: Type: text/html, Size: 8833 bytes --]
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_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
2019-10-21 14:59 ` [Xen-devel] " Li Qiang
@ 2019-10-26 14:29 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-26 14:29 UTC (permalink / raw)
To: Li Qiang, Hervé Poussineau, Aleksandar Markovic, Aurelien Jarno
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Richard Henderson
Hi Li,
On 10/21/19 4:59 PM, Li Qiang wrote:
> Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>> 于
> 2019年10月18日周五 下午9:52写道：
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org
> <mailto:20171216090228.28505-8-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
>
>
>
> Does the piix4 hardware has the GPIO for interrupt? Seems not.
Yes it does, you can check in the datasheet:
https://www.intel.com/Assets/PDF/datasheet/290562.pdf
Page 3 is the 'Simplified Block Diagram' you see the INTR pin.
Page 24 table "2.1.5. INTERRUPT CONTROLLER/APIC SIGNALS"
INTR: INTERRUPT. See CPU Interface Signals.
Page 26 "2.1.6. CPU INTERFACE SIGNALS"
CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that
an interrupt request is pending and needs to be serviced. It
is asynchronous with respect to SYSCLK or PCICLK and is always
an output. The interrupt controller must be programmed following
PCIRST# to ensure that INTR is at a known state.
>
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>
>
> In i8259_init, we also allocate 16 input line and 1 output line.
> Seems it is duplicated with the GPIO allocation in previous.
No, this is different, here we don't allocate the 16 i8259
INPUT lines, we allocate 1 input IRQ and pass it to the
i8259_init function which uses it as its OUTPUT line.
IOW:
* i8259
- 16 INPUT (from ISA devices)
- 1 OUTPUT (to PIIX)
* PIIX
- 1 INPUT (from i8259)
- 1 OUTPUT (to CPU, on the Malta board: CPU IRQ2)
> Also
> Maybe here can uses
> i8259(isa_bus, qemu_allocate_irq(piix4_request_i8259_irq, s, 0));
>
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on
> isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle
> we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
>
> Also here s->i8259 and the piix4 isa point to the same input line. Seems
> duplicated.
'i8259_irq' might be misnamed, it is initialized as the CPU INPUT IRQ:
mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
Then we connect the ISA PIC OUTPUT IRQ to the CPU INPUT IRQ:
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
Earlier, we created the GT64120 with an array of OUTPUT IRQs:
pci_bus = gt64120_register(s->i8259);
Here we connect the GT64120 OUTPUT IRQs from the PCI bus to
be INPUT of the ISA PIC:
for (int i = 0; i < ISA_NUM_IRQS; i++) {
s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
}
There were the previously used 'proxy-irq'. Now the circular
problem is resolved:
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
* on piix4, and piix4 depends on pci_bus. To stop the cycle we have
* qemu_irq_proxy() adds an extra bit of indirection, allowing us
* to resolve the isa_irq -> i8259 dependency after i8259 is
* initialized.
*/
Future plan is to remove the X86 dependency on the i8259 PIC,
then we'll be able to improve the GT64120 model and simplify
how IRQs are connected.
> I have come up with a more cleaner patch as following:
>
> Though 'i8259_init' is called in the mips_malta_init. But is uses the
> isa bus from piix4 device.
> And seems it's more clean.
> You can test it with more tests.
You can test with:
$ make mips{,64}{,el}-softmmu/all
$ make check-venv
$ AVOCADO_TIMEOUT_EXPECTED=1 \
tests/venv/bin/avocado \
--show=app,ssh,console \
run \
-t arch:mips \
-t arch:mipsel \
-t arch:mips64 \
-t arch:mips64el \
tests/acceptance/
Regards,
Phil.
> Author: Li Qiang <liq3ea@163.com <mailto:liq3ea@163.com>>
> Date: Mon Oct 21 22:41:17 2019 +0800
>
> piix4
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..66a041040a 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -46,6 +47,7 @@ typedef struct PIIX4State {
> #define PIIX4_PCI_DEVICE(obj) \
> OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> +
> static void piix4_isa_reset(DeviceState *dev)
> {
> PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> @@ -141,14 +143,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
>
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..420e0e9e80 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,6 +28,7 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> +//#include "hw/isa/piix4.h"
> #include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> @@ -97,7 +98,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[ISA_NUM_IRQS];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1236,9 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + qemu_irq *i8259;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,29 +1409,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
>
> + i8259 = i8259_init(isa_bus, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = i8259[i];
> + }
> + g_free(i8259);
> isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet
@ 2019-10-26 14:29 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-26 14:29 UTC (permalink / raw)
To: Li Qiang, Hervé Poussineau, Aleksandar Markovic, Aurelien Jarno
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
Qemu Developers, Eduardo Habkost, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Richard Henderson
Hi Li,
On 10/21/19 4:59 PM, Li Qiang wrote:
> Philippe Mathieu-Daudé <philmd@redhat.com <mailto:philmd@redhat.com>> 于
> 2019年10月18日周五 下午9:52写道：
>
> From: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
>
> Add ISA irqs as piix4 gpio in, and CPU interrupt request as piix4
> gpio out.
> Remove i8259 instanciated in malta board, to not have it twice.
>
> We can also remove the now unused piix4_init() function.
>
> Acked-by: Michael S. Tsirkin <mst@redhat.com <mailto:mst@redhat.com>>
> Acked-by: Paolo Bonzini <pbonzini@redhat.com
> <mailto:pbonzini@redhat.com>>
> Signed-off-by: Hervé Poussineau <hpoussin@reactos.org
> <mailto:hpoussin@reactos.org>>
> Message-Id: <20171216090228.28505-8-hpoussin@reactos.org
> <mailto:20171216090228.28505-8-hpoussin@reactos.org>>
> Reviewed-by: Aleksandar Markovic <amarkovic@wavecomp.com
> <mailto:amarkovic@wavecomp.com>>
> [PMD: rebased, updated includes, use ISA_NUM_IRQS in for loop]
> Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com
> <mailto:philmd@redhat.com>>
> ---
> hw/isa/piix4.c | 43 ++++++++++++++++++++++++++++++++-----------
> hw/mips/mips_malta.c | 32 +++++++++++++-------------------
> include/hw/i386/pc.h | 1 -
> 3 files changed, 45 insertions(+), 31 deletions(-)
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..9c37c85ae2 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -36,6 +37,8 @@ PCIDevice *piix4_dev;
>
> typedef struct PIIX4State {
> PCIDevice dev;
> + qemu_irq cpu_intr;
> + qemu_irq *isa;
>
> /* Reset Control Register */
> MemoryRegion rcr_mem;
> @@ -94,6 +97,18 @@ static const VMStateDescription vmstate_piix4 = {
> }
> };
>
> +static void piix4_request_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->cpu_intr, level);
> +}
> +
> +static void piix4_set_i8259_irq(void *opaque, int irq, int level)
> +{
> + PIIX4State *s = opaque;
> + qemu_set_irq(s->isa[irq], level);
> +}
> +
> static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,
> unsigned int len)
> {
> @@ -127,29 +142,35 @@ static const MemoryRegionOps piix4_rcr_ops = {
> static void piix4_realize(PCIDevice *dev, Error **errp)
> {
> PIIX4State *s = PIIX4_PCI_DEVICE(dev);
> + ISABus *isa_bus;
> + qemu_irq *i8259_out_irq;
>
> - if (!isa_bus_new(DEVICE(dev), pci_address_space(dev),
> - pci_address_space_io(dev), errp)) {
> + isa_bus = isa_bus_new(DEVICE(dev), pci_address_space(dev),
> + pci_address_space_io(dev), errp);
> + if (!isa_bus) {
> return;
> }
>
> + qdev_init_gpio_in_named(DEVICE(dev), piix4_set_i8259_irq,
> + "isa", ISA_NUM_IRQS);
> + qdev_init_gpio_out_named(DEVICE(dev), &s->cpu_intr,
> + "intr", 1);
> +
>
>
>
> Does the piix4 hardware has the GPIO for interrupt? Seems not.
Yes it does, you can check in the datasheet:
https://www.intel.com/Assets/PDF/datasheet/290562.pdf
Page 3 is the 'Simplified Block Diagram' you see the INTR pin.
Page 24 table "2.1.5. INTERRUPT CONTROLLER/APIC SIGNALS"
INTR: INTERRUPT. See CPU Interface Signals.
Page 26 "2.1.6. CPU INTERFACE SIGNALS"
CPU INTERRUPT. INTR is driven by PIIX4 to signal the CPU that
an interrupt request is pending and needs to be serviced. It
is asynchronous with respect to SYSCLK or PCICLK and is always
an output. The interrupt controller must be programmed following
PCIRST# to ensure that INTR is at a known state.
>
> memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,
> "reset-control", 1);
> memory_region_add_subregion_overlap(pci_address_space_io(dev),
> 0xcf9,
> &s->rcr_mem, 1);
>
> + /* initialize i8259 pic */
> + i8259_out_irq = qemu_allocate_irqs(piix4_request_i8259_irq, s, 1);
> + s->isa = i8259_init(isa_bus, *i8259_out_irq);
>
>
> In i8259_init, we also allocate 16 input line and 1 output line.
> Seems it is duplicated with the GPIO allocation in previous.
No, this is different, here we don't allocate the 16 i8259
INPUT lines, we allocate 1 input IRQ and pass it to the
i8259_init function which uses it as its OUTPUT line.
IOW:
* i8259
- 16 INPUT (from ISA devices)
- 1 OUTPUT (to PIIX)
* PIIX
- 1 INPUT (from i8259)
- 1 OUTPUT (to CPU, on the Malta board: CPU IRQ2)
> Also
> Maybe here can uses
> i8259(isa_bus, qemu_allocate_irq(piix4_request_i8259_irq, s, 0));
>
> +
> + /* initialize ISA irqs */
> + isa_bus_irqs(isa_bus, s->isa);
> +
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
> -
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> DeviceClass *dc = DEVICE_CLASS(klass);
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..7d25ab6c23 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -97,7 +97,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[16];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1235,8 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,30 +1407,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on
> isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle
> we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
> + /* Interrupt controller */
> + qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
> + }
>
>
> Also here s->i8259 and the piix4 isa point to the same input line. Seems
> duplicated.
'i8259_irq' might be misnamed, it is initialized as the CPU INPUT IRQ:
mips_create_cpu(machine, s, &cbus_irq, &i8259_irq);
Then we connect the ISA PIC OUTPUT IRQ to the CPU INPUT IRQ:
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
Earlier, we created the GT64120 with an array of OUTPUT IRQs:
pci_bus = gt64120_register(s->i8259);
Here we connect the GT64120 OUTPUT IRQs from the PCI bus to
be INPUT of the ISA PIC:
for (int i = 0; i < ISA_NUM_IRQS; i++) {
s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
}
There were the previously used 'proxy-irq'. Now the circular
problem is resolved:
/*
* We have a circular dependency problem: pci_bus depends on isa_irq,
* isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
* on piix4, and piix4 depends on pci_bus. To stop the cycle we have
* qemu_irq_proxy() adds an extra bit of indirection, allowing us
* to resolve the isa_irq -> i8259 dependency after i8259 is
* initialized.
*/
Future plan is to remove the X86 dependency on the i8259 PIC,
then we'll be able to improve the GT64120 model and simplify
how IRQs are connected.
> I have come up with a more cleaner patch as following:
>
> Though 'i8259_init' is called in the mips_malta_init. But is uses the
> isa bus from piix4 device.
> And seems it's more clean.
> You can test it with more tests.
You can test with:
$ make mips{,64}{,el}-softmmu/all
$ make check-venv
$ AVOCADO_TIMEOUT_EXPECTED=1 \
tests/venv/bin/avocado \
--show=app,ssh,console \
run \
-t arch:mips \
-t arch:mipsel \
-t arch:mips64 \
-t arch:mips64el \
tests/acceptance/
Regards,
Phil.
> Author: Li Qiang <liq3ea@163.com <mailto:liq3ea@163.com>>
> Date: Mon Oct 21 22:41:17 2019 +0800
>
> piix4
>
> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
> index d0b18e0586..66a041040a 100644
> --- a/hw/isa/piix4.c
> +++ b/hw/isa/piix4.c
> @@ -24,6 +24,7 @@
> */
>
> #include "qemu/osdep.h"
> +#include "hw/irq.h"
> #include "hw/i386/pc.h"
> #include "hw/pci/pci.h"
> #include "hw/isa/isa.h"
> @@ -46,6 +47,7 @@ typedef struct PIIX4State {
> #define PIIX4_PCI_DEVICE(obj) \
> OBJECT_CHECK(PIIX4State, (obj), TYPE_PIIX4_PCI_DEVICE)
>
> +
> static void piix4_isa_reset(DeviceState *dev)
> {
> PIIX4State *d = PIIX4_PCI_DEVICE(dev);
> @@ -141,14 +143,6 @@ static void piix4_realize(PCIDevice *dev, Error **errp)
> piix4_dev = dev;
> }
>
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn)
> -{
> - PCIDevice *d;
> -
> - d = pci_create_simple_multifunction(bus, devfn, true, "PIIX4");
> - *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
> - return d->devfn;
> -}
>
> static void piix4_class_init(ObjectClass *klass, void *data)
> {
> diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c
> index 4d9c64b36a..420e0e9e80 100644
> --- a/hw/mips/mips_malta.c
> +++ b/hw/mips/mips_malta.c
> @@ -28,6 +28,7 @@
> #include "cpu.h"
> #include "hw/i386/pc.h"
> #include "hw/isa/superio.h"
> +//#include "hw/isa/piix4.h"
> #include "hw/dma/i8257.h"
> #include "hw/char/serial.h"
> #include "net/net.h"
> @@ -97,7 +98,7 @@ typedef struct {
> SysBusDevice parent_obj;
>
> MIPSCPSState cps;
> - qemu_irq *i8259;
> + qemu_irq i8259[ISA_NUM_IRQS];
> } MaltaState;
>
> static ISADevice *pit;
> @@ -1235,8 +1236,9 @@ void mips_malta_init(MachineState *machine)
> int64_t kernel_entry, bootloader_run_addr;
> PCIBus *pci_bus;
> ISABus *isa_bus;
> - qemu_irq *isa_irq;
> qemu_irq cbus_irq, i8259_irq;
> + qemu_irq *i8259;
> + PCIDevice *pci;
> int piix4_devfn;
> I2CBus *smbus;
> DriveInfo *dinfo;
> @@ -1407,29 +1409,24 @@ void mips_malta_init(MachineState *machine)
> /* Board ID = 0x420 (Malta Board with CoreLV) */
> stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
>
> - /*
> - * We have a circular dependency problem: pci_bus depends on isa_irq,
> - * isa_irq is provided by i8259, i8259 depends on ISA, ISA depends
> - * on piix4, and piix4 depends on pci_bus. To stop the cycle we have
> - * qemu_irq_proxy() adds an extra bit of indirection, allowing us
> - * to resolve the isa_irq -> i8259 dependency after i8259 is
> initialized.
> - */
> - isa_irq = qemu_irq_proxy(&s->i8259, 16);
> -
> /* Northbridge */
> - pci_bus = gt64120_register(isa_irq);
> + pci_bus = gt64120_register(s->i8259);
>
> /* Southbridge */
> ide_drive_get(hd, ARRAY_SIZE(hd));
>
> - piix4_devfn = piix4_init(pci_bus, &isa_bus, 80);
> + pci = pci_create_simple_multifunction(pci_bus, PCI_DEVFN(10, 0),
> + true, "PIIX4");
> + dev = DEVICE(pci);
> + isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
> + piix4_devfn = pci->devfn;
>
> - /*
> - * Interrupt controller
> - * The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2
> - */
> - s->i8259 = i8259_init(isa_bus, i8259_irq);
>
> + i8259 = i8259_init(isa_bus, i8259_irq);
> + for (int i = 0; i < ISA_NUM_IRQS; i++) {
> + s->i8259[i] = i8259[i];
> + }
> + g_free(i8259);
> isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
>
> - isa_bus_irqs(isa_bus, s->i8259);
> pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1);
> pci_create_simple(pci_bus, piix4_devfn + 2, "piix4-usb-uhci");
> smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100,
> diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> index 37bfd95113..374f3e8835 100644
> --- a/include/hw/i386/pc.h
> +++ b/include/hw/i386/pc.h
> @@ -286,7 +286,6 @@ PCIBus *i440fx_init(const char *host_type, const
> char *pci_type,
> PCIBus *find_i440fx(void);
> /* piix4.c */
> extern PCIDevice *piix4_dev;
> -int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
>
> /* pc_sysfw.c */
> void pc_system_flash_create(PCMachineState *pcms);
> --
> 2.21.0
>
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
2019-10-25 10:51 ` [Xen-devel] " Aleksandar Markovic
@ 2019-10-26 14:39 ` Philippe Mathieu-Daudé
-1 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-26 14:39 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Hi Aleksandar,
On 10/25/19 12:51 PM, Aleksandar Markovic wrote:
> On Thursday, October 24, 2019, Aleksandar Markovic
> <aleksandar.m.mail@gmail.com <mailto:aleksandar.m.mail@gmail.com>> wrote:
>
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé
> <philmd@redhat.com <mailto:philmd@redhat.com>> wrote:
>
> Changes since v1 [0]:
> - Removed patch reintroducing DO_UPCAST() use (thuth)
> - Took various patches out to reduce series (thuth)
> - Added review tags (thanks all for reviewing!)
>
>
> Philippe,
>
> Do you intend to submit v3? The softfreeze is close.
>
> A.
>
>
> Philippe,
>
> It looks you are very busy these days. Do you mind my integrating this
> series in next Mips queue, in its present v2 state? (You can certainly
> do further refinements later on.)
I addressed the review comments from this version, however it can not
be merged yet ...
>
> Aleksandar
>
> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
> Key:
> [----] : patches are identical
> [####] : number of functional differences between
> upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual
> differences, respectively
>
> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge
> separate from PC Chipsets'
> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as
> specified in datasheet'
> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as
> specified in datasheet'
> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as
> specified in datasheet'
> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as
> specified in datasheet'
> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive
> array dynamically'
> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4
> creation code as piix4_create()'
> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to
> hw/isa/piix4.c'
> 012/20:[----] [--] 'hw/i386: Remove obsolete
> LoadStateHandler::load_state_old handlers'
> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register
> definition'
> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX
> IRQ Route Control Registers'
> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations
> to hw/pci-host/i440fx.h'
> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
> hw/isa/piix3.c'
> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix'
> as 'i440fx''
> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3
> traces'
>
> Previous cover:
>
> This series is a rework of "piix4: cleanup and improvements" [1]
> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>
> Still trying to remove the strong X86/PC dependency 2 years later,
> one step at a time.
> Here we split the PIIX3 southbridge from i440FX northbridge.
> The i440FX northbridge is only used by the PC machine, while the
> PIIX southbridge is also used by the Malta MIPS machine.
>
> This is also a step forward using KConfig with the Malta board.
> Without this split, it was impossible to compile the Malta without
> pulling various X86 pieces of code.
>
> The overall design cleanup is not yet perfect, but enough to post
> as a series.
>
> Now that the PIIX3 code is extracted, the code duplication with the
> PIIX4 chipset is obvious. Not worth improving for now because it
> isn't broken.
>
> [0]
> https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
> <https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html>
> [1]
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html <https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html>
> [2]
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html <https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html>
>
> Based-on: <20191018133547.10936-1-philmd@redhat.com
> <mailto:20191018133547.10936-1-philmd@redhat.com>>
> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead
> of rtc_init()
... because it depends on this series which has been queued by Paolo but
is not yet merged.
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
> <https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com>
>
> Hervé Poussineau (5):
> piix4: Add the Reset Control Register
> piix4: Add a i8259 Interrupt Controller as specified in datasheet
> piix4: Rename PIIX4 object to piix4-isa
> piix4: Add a i8257 DMA Controller as specified in datasheet
> piix4: Add a i8254 PIT Controller as specified in datasheet
>
> Philippe Mathieu-Daudé (15):
> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
> Revert "irq: introduce qemu_irq_proxy()"
> piix4: Add a MC146818 RTC Controller as specified in datasheet
> hw/mips/mips_malta: Create IDE hard drive array dynamically
> hw/mips/mips_malta: Extract the PIIX4 creation code as
> piix4_create()
> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
> hw/i386: Remove obsolete LoadStateHandler::load_state_old
> handlers
> hw/pci-host/piix: Extract piix3_create()
> hw/pci-host/piix: Move RCR_IOPORT register definition
> hw/pci-host/piix: Define and use the PIIX IRQ Route Control
> Registers
> hw/pci-host/piix: Move i440FX declarations to
> hw/pci-host/i440fx.h
> hw/pci-host/piix: Fix code style issues
> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
> hw/pci-host/i440fx: Remove the last PIIX3 traces
>
> MAINTAINERS | 14 +-
> hw/acpi/pcihp.c | 2 +-
> hw/acpi/piix4.c | 42 +--
> hw/core/irq.c | 14 -
> hw/i386/Kconfig | 3 +-
> hw/i386/acpi-build.c | 5 +-
> hw/i386/pc_piix.c | 10 +-
> hw/i386/xen/xen-hvm.c | 5 +-
> hw/intc/apic_common.c | 49 ----
> hw/isa/Kconfig | 4 +
> hw/isa/Makefile.objs | 1 +
> hw/isa/piix3.c | 399
> +++++++++++++++++++++++++++++
> hw/isa/piix4.c | 151 ++++++++++-
> hw/mips/gt64xxx_pci.c | 5 +-
> hw/mips/mips_malta.c | 46 +---
> hw/pci-host/Kconfig | 3 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{piix.c => i440fx.c} | 424
> +------------------------------
> hw/timer/i8254_common.c | 40 ---
> include/hw/acpi/piix4.h | 6 -
> include/hw/i386/pc.h | 37 ---
> include/hw/irq.h | 5 -
> include/hw/isa/isa.h | 2 +
> include/hw/pci-host/i440fx.h | 36 +++
> include/hw/southbridge/piix.h | 74 ++++++
> stubs/pci-host-piix.c | 3 +-
> 26 files changed, 699 insertions(+), 683 deletions(-)
> create mode 100644 hw/isa/piix3.c
> rename hw/pci-host/{piix.c => i440fx.c} (58%)
> delete mode 100644 include/hw/acpi/piix4.h
> create mode 100644 include/hw/pci-host/i440fx.h
> create mode 100644 include/hw/southbridge/piix.h
>
> --
> 2.21.0
>
>
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-26 14:39 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 106+ messages in thread
From: Philippe Mathieu-Daudé @ 2019-10-26 14:39 UTC (permalink / raw)
To: Aleksandar Markovic
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
Hi Aleksandar,
On 10/25/19 12:51 PM, Aleksandar Markovic wrote:
> On Thursday, October 24, 2019, Aleksandar Markovic
> <aleksandar.m.mail@gmail.com <mailto:aleksandar.m.mail@gmail.com>> wrote:
>
>
>
> On Friday, October 18, 2019, Philippe Mathieu-Daudé
> <philmd@redhat.com <mailto:philmd@redhat.com>> wrote:
>
> Changes since v1 [0]:
> - Removed patch reintroducing DO_UPCAST() use (thuth)
> - Took various patches out to reduce series (thuth)
> - Added review tags (thanks all for reviewing!)
>
>
> Philippe,
>
> Do you intend to submit v3? The softfreeze is close.
>
> A.
>
>
> Philippe,
>
> It looks you are very busy these days. Do you mind my integrating this
> series in next Mips queue, in its present v2 state? (You can certainly
> do further refinements later on.)
I addressed the review comments from this version, however it can not
be merged yet ...
>
> Aleksandar
>
> $ git backport-diff -u pc_split_i440fx_piix-v1 -r mc146818rtc_init..
> Key:
> [----] : patches are identical
> [####] : number of functional differences between
> upstream/downstream patch
> [down] : patch is downstream-only
> The flags [FC] indicate (F)unctional and (C)ontextual
> differences, respectively
>
> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge
> separate from PC Chipsets'
> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as
> specified in datasheet'
> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as
> specified in datasheet'
> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as
> specified in datasheet'
> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as
> specified in datasheet'
> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive
> array dynamically'
> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4
> creation code as piix4_create()'
> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to
> hw/isa/piix4.c'
> 012/20:[----] [--] 'hw/i386: Remove obsolete
> LoadStateHandler::load_state_old handlers'
> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register
> definition'
> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX
> IRQ Route Control Registers'
> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations
> to hw/pci-host/i440fx.h'
> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
> hw/isa/piix3.c'
> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix'
> as 'i440fx''
> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3
> traces'
>
> Previous cover:
>
> This series is a rework of "piix4: cleanup and improvements" [1]
> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>
> Still trying to remove the strong X86/PC dependency 2 years later,
> one step at a time.
> Here we split the PIIX3 southbridge from i440FX northbridge.
> The i440FX northbridge is only used by the PC machine, while the
> PIIX southbridge is also used by the Malta MIPS machine.
>
> This is also a step forward using KConfig with the Malta board.
> Without this split, it was impossible to compile the Malta without
> pulling various X86 pieces of code.
>
> The overall design cleanup is not yet perfect, but enough to post
> as a series.
>
> Now that the PIIX3 code is extracted, the code duplication with the
> PIIX4 chipset is obvious. Not worth improving for now because it
> isn't broken.
>
> [0]
> https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html
> <https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg03685.html>
> [1]
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html <https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html>
> [2]
> https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html <https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html>
>
> Based-on: <20191018133547.10936-1-philmd@redhat.com
> <mailto:20191018133547.10936-1-philmd@redhat.com>>
> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead
> of rtc_init()
... because it depends on this series which has been queued by Paolo but
is not yet merged.
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com
> <https://mid.mail-archive.com/20191018133547.10936-1-philmd@redhat.com>
>
> Hervé Poussineau (5):
> piix4: Add the Reset Control Register
> piix4: Add a i8259 Interrupt Controller as specified in datasheet
> piix4: Rename PIIX4 object to piix4-isa
> piix4: Add a i8257 DMA Controller as specified in datasheet
> piix4: Add a i8254 PIT Controller as specified in datasheet
>
> Philippe Mathieu-Daudé (15):
> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
> Revert "irq: introduce qemu_irq_proxy()"
> piix4: Add a MC146818 RTC Controller as specified in datasheet
> hw/mips/mips_malta: Create IDE hard drive array dynamically
> hw/mips/mips_malta: Extract the PIIX4 creation code as
> piix4_create()
> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
> hw/i386: Remove obsolete LoadStateHandler::load_state_old
> handlers
> hw/pci-host/piix: Extract piix3_create()
> hw/pci-host/piix: Move RCR_IOPORT register definition
> hw/pci-host/piix: Define and use the PIIX IRQ Route Control
> Registers
> hw/pci-host/piix: Move i440FX declarations to
> hw/pci-host/i440fx.h
> hw/pci-host/piix: Fix code style issues
> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
> hw/pci-host/i440fx: Remove the last PIIX3 traces
>
> MAINTAINERS | 14 +-
> hw/acpi/pcihp.c | 2 +-
> hw/acpi/piix4.c | 42 +--
> hw/core/irq.c | 14 -
> hw/i386/Kconfig | 3 +-
> hw/i386/acpi-build.c | 5 +-
> hw/i386/pc_piix.c | 10 +-
> hw/i386/xen/xen-hvm.c | 5 +-
> hw/intc/apic_common.c | 49 ----
> hw/isa/Kconfig | 4 +
> hw/isa/Makefile.objs | 1 +
> hw/isa/piix3.c | 399
> +++++++++++++++++++++++++++++
> hw/isa/piix4.c | 151 ++++++++++-
> hw/mips/gt64xxx_pci.c | 5 +-
> hw/mips/mips_malta.c | 46 +---
> hw/pci-host/Kconfig | 3 +-
> hw/pci-host/Makefile.objs | 2 +-
> hw/pci-host/{piix.c => i440fx.c} | 424
> +------------------------------
> hw/timer/i8254_common.c | 40 ---
> include/hw/acpi/piix4.h | 6 -
> include/hw/i386/pc.h | 37 ---
> include/hw/irq.h | 5 -
> include/hw/isa/isa.h | 2 +
> include/hw/pci-host/i440fx.h | 36 +++
> include/hw/southbridge/piix.h | 74 ++++++
> stubs/pci-host-piix.c | 3 +-
> 26 files changed, 699 insertions(+), 683 deletions(-)
> create mode 100644 hw/isa/piix3.c
> rename hw/pci-host/{piix.c => i440fx.c} (58%)
> delete mode 100644 include/hw/acpi/piix4.h
> create mode 100644 include/hw/pci-host/i440fx.h
> create mode 100644 include/hw/southbridge/piix.h
>
> --
> 2.21.0
>
>
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
2019-10-26 14:39 ` [Xen-devel] " Philippe Mathieu-Daudé
@ 2019-10-26 15:17 ` Aleksandar Markovic
-1 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-26 15:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1: Type: text/plain, Size: 9119 bytes --]
On Saturday, October 26, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> Hi Aleksandar,
>
> On 10/25/19 12:51 PM, Aleksandar Markovic wrote:
>
>> On Thursday, October 24, 2019, Aleksandar Markovic <
>> aleksandar.m.mail@gmail.com <mailto:aleksandar.m.mail@gmail.com>> wrote:
>>
>>
>>
>> On Friday, October 18, 2019, Philippe Mathieu-Daudé
>> <philmd@redhat.com <mailto:philmd@redhat.com>> wrote:
>>
>> Changes since v1 [0]:
>> - Removed patch reintroducing DO_UPCAST() use (thuth)
>> - Took various patches out to reduce series (thuth)
>> - Added review tags (thanks all for reviewing!)
>>
>>
>> Philippe,
>>
>> Do you intend to submit v3? The softfreeze is close.
>>
>> A.
>>
>>
>> Philippe,
>>
>> It looks you are very busy these days. Do you mind my integrating this
>> series in next Mips queue, in its present v2 state? (You can certainly do
>> further refinements later on.)
>>
>
> I addressed the review comments from this version, however it can not
> be merged yet ...
OK. Let's not rush. Let me know if I can help in any way.
A.
>
>
>> Aleksandar
>>
>> $ git backport-diff -u pc_split_i440fx_piix-v1 -r
>> mc146818rtc_init..
>> Key:
>> [----] : patches are identical
>> [####] : number of functional differences between
>> upstream/downstream patch
>> [down] : patch is downstream-only
>> The flags [FC] indicate (F)unctional and (C)ontextual
>> differences, respectively
>>
>> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge
>> separate from PC Chipsets'
>> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
>> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as
>> specified in datasheet'
>> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
>> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
>> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as
>> specified in datasheet'
>> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as
>> specified in datasheet'
>> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as
>> specified in datasheet'
>> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive
>> array dynamically'
>> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4
>> creation code as piix4_create()'
>> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to
>> hw/isa/piix4.c'
>> 012/20:[----] [--] 'hw/i386: Remove obsolete
>> LoadStateHandler::load_state_old handlers'
>> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
>> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register
>> definition'
>> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX
>> IRQ Route Control Registers'
>> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations
>> to hw/pci-host/i440fx.h'
>> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
>> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
>> hw/isa/piix3.c'
>> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix'
>> as 'i440fx''
>> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3
>> traces'
>>
>> Previous cover:
>>
>> This series is a rework of "piix4: cleanup and improvements" [1]
>> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>>
>> Still trying to remove the strong X86/PC dependency 2 years later,
>> one step at a time.
>> Here we split the PIIX3 southbridge from i440FX northbridge.
>> The i440FX northbridge is only used by the PC machine, while the
>> PIIX southbridge is also used by the Malta MIPS machine.
>>
>> This is also a step forward using KConfig with the Malta board.
>> Without this split, it was impossible to compile the Malta without
>> pulling various X86 pieces of code.
>>
>> The overall design cleanup is not yet perfect, but enough to post
>> as a series.
>>
>> Now that the PIIX3 code is extracted, the code duplication with
>> the
>> PIIX4 chipset is obvious. Not worth improving for now because it
>> isn't broken.
>>
>> [0]
>> https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg036
>> 85.html
>> <https://lists.gnu.org/archive/html/qemu-devel/2019-10/
>> msg03685.html>
>> [1]
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
>> <https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html>
>> [2]
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>> <https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html>
>>
>> Based-on: <20191018133547.10936-1-philmd@redhat.com
>> <mailto:20191018133547.10936-1-philmd@redhat.com>>
>> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead
>> of rtc_init()
>>
>
> ... because it depends on this series which has been queued by Paolo but
> is not yet merged.
>
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@r
>> edhat.com
>> <https://mid.mail-archive.com/20191018133547.10936-1-philmd@
>> redhat.com>
>>
>> Hervé Poussineau (5):
>> piix4: Add the Reset Control Register
>> piix4: Add a i8259 Interrupt Controller as specified in
>> datasheet
>> piix4: Rename PIIX4 object to piix4-isa
>> piix4: Add a i8257 DMA Controller as specified in datasheet
>> piix4: Add a i8254 PIT Controller as specified in datasheet
>>
>> Philippe Mathieu-Daudé (15):
>> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
>> Revert "irq: introduce qemu_irq_proxy()"
>> piix4: Add a MC146818 RTC Controller as specified in datasheet
>> hw/mips/mips_malta: Create IDE hard drive array dynamically
>> hw/mips/mips_malta: Extract the PIIX4 creation code as
>> piix4_create()
>> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
>> hw/i386: Remove obsolete LoadStateHandler::load_state_old
>> handlers
>> hw/pci-host/piix: Extract piix3_create()
>> hw/pci-host/piix: Move RCR_IOPORT register definition
>> hw/pci-host/piix: Define and use the PIIX IRQ Route Control
>> Registers
>> hw/pci-host/piix: Move i440FX declarations to
>> hw/pci-host/i440fx.h
>> hw/pci-host/piix: Fix code style issues
>> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
>> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
>> hw/pci-host/i440fx: Remove the last PIIX3 traces
>>
>> MAINTAINERS | 14 +-
>> hw/acpi/pcihp.c | 2 +-
>> hw/acpi/piix4.c | 42 +--
>> hw/core/irq.c | 14 -
>> hw/i386/Kconfig | 3 +-
>> hw/i386/acpi-build.c | 5 +-
>> hw/i386/pc_piix.c | 10 +-
>> hw/i386/xen/xen-hvm.c | 5 +-
>> hw/intc/apic_common.c | 49 ----
>> hw/isa/Kconfig | 4 +
>> hw/isa/Makefile.objs | 1 +
>> hw/isa/piix3.c | 399
>> +++++++++++++++++++++++++++++
>> hw/isa/piix4.c | 151 ++++++++++-
>> hw/mips/gt64xxx_pci.c | 5 +-
>> hw/mips/mips_malta.c | 46 +---
>> hw/pci-host/Kconfig | 3 +-
>> hw/pci-host/Makefile.objs | 2 +-
>> hw/pci-host/{piix.c => i440fx.c} | 424
>> +------------------------------
>> hw/timer/i8254_common.c | 40 ---
>> include/hw/acpi/piix4.h | 6 -
>> include/hw/i386/pc.h | 37 ---
>> include/hw/irq.h | 5 -
>> include/hw/isa/isa.h | 2 +
>> include/hw/pci-host/i440fx.h | 36 +++
>> include/hw/southbridge/piix.h | 74 ++++++
>> stubs/pci-host-piix.c | 3 +-
>> 26 files changed, 699 insertions(+), 683 deletions(-)
>> create mode 100644 hw/isa/piix3.c
>> rename hw/pci-host/{piix.c => i440fx.c} (58%)
>> delete mode 100644 include/hw/acpi/piix4.h
>> create mode 100644 include/hw/pci-host/i440fx.h
>> create mode 100644 include/hw/southbridge/piix.h
>>
>> -- 2.21.0
>>
>>
>>
[-- Attachment #2: Type: text/html, Size: 12496 bytes --]
^ permalink raw reply [flat|nested] 106+ messages in thread
* Re: [Xen-devel] [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge
@ 2019-10-26 15:17 ` Aleksandar Markovic
0 siblings, 0 replies; 106+ messages in thread
From: Aleksandar Markovic @ 2019-10-26 15:17 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Stefano Stabellini, xen-devel, Paul Durrant, Michael S. Tsirkin,
qemu-devel, Eduardo Habkost, Hervé Poussineau,
Aleksandar Markovic, Igor Mammedov, Anthony Perard,
Paolo Bonzini, Aleksandar Rikalo, Aurelien Jarno,
Richard Henderson
[-- Attachment #1.1: Type: text/plain, Size: 9119 bytes --]
On Saturday, October 26, 2019, Philippe Mathieu-Daudé <philmd@redhat.com>
wrote:
> Hi Aleksandar,
>
> On 10/25/19 12:51 PM, Aleksandar Markovic wrote:
>
>> On Thursday, October 24, 2019, Aleksandar Markovic <
>> aleksandar.m.mail@gmail.com <mailto:aleksandar.m.mail@gmail.com>> wrote:
>>
>>
>>
>> On Friday, October 18, 2019, Philippe Mathieu-Daudé
>> <philmd@redhat.com <mailto:philmd@redhat.com>> wrote:
>>
>> Changes since v1 [0]:
>> - Removed patch reintroducing DO_UPCAST() use (thuth)
>> - Took various patches out to reduce series (thuth)
>> - Added review tags (thanks all for reviewing!)
>>
>>
>> Philippe,
>>
>> Do you intend to submit v3? The softfreeze is close.
>>
>> A.
>>
>>
>> Philippe,
>>
>> It looks you are very busy these days. Do you mind my integrating this
>> series in next Mips queue, in its present v2 state? (You can certainly do
>> further refinements later on.)
>>
>
> I addressed the review comments from this version, however it can not
> be merged yet ...
OK. Let's not rush. Let me know if I can help in any way.
A.
>
>
>> Aleksandar
>>
>> $ git backport-diff -u pc_split_i440fx_piix-v1 -r
>> mc146818rtc_init..
>> Key:
>> [----] : patches are identical
>> [####] : number of functional differences between
>> upstream/downstream patch
>> [down] : patch is downstream-only
>> The flags [FC] indicate (F)unctional and (C)ontextual
>> differences, respectively
>>
>> 001/20:[----] [--] 'MAINTAINERS: Keep PIIX4 South Bridge
>> separate from PC Chipsets'
>> 002/20:[0011] [FC] 'piix4: add Reset Control Register'
>> 003/20:[0014] [FC] 'piix4: add a i8259 interrupt controller as
>> specified in datasheet'
>> 004/20:[----] [--] 'Revert "irq: introduce qemu_irq_proxy()"'
>> 005/20:[----] [--] 'piix4: rename PIIX4 object to piix4-isa'
>> 006/20:[----] [-C] 'piix4: add a i8257 dma controller as
>> specified in datasheet'
>> 007/20:[----] [-C] 'piix4: add a i8254 pit controller as
>> specified in datasheet'
>> 008/20:[----] [-C] 'piix4: add a mc146818rtc controller as
>> specified in datasheet'
>> 009/20:[----] [--] 'hw/mips/mips_malta: Create IDE hard drive
>> array dynamically'
>> 010/20:[----] [--] 'hw/mips/mips_malta: Extract the PIIX4
>> creation code as piix4_create()'
>> 011/20:[----] [--] 'hw/isa/piix4: Move piix4_create() to
>> hw/isa/piix4.c'
>> 012/20:[----] [--] 'hw/i386: Remove obsolete
>> LoadStateHandler::load_state_old handlers'
>> 013/20:[----] [--] 'hw/pci-host/piix: Extract piix3_create()'
>> 014/20:[0010] [FC] 'hw/pci-host/piix: Move RCR_IOPORT register
>> definition'
>> 015/20:[----] [--] 'hw/pci-host/piix: Define and use the PIIX
>> IRQ Route Control Registers'
>> 016/20:[----] [--] 'hw/pci-host/piix: Move i440FX declarations
>> to hw/pci-host/i440fx.h'
>> 017/20:[----] [--] 'hw/pci-host/piix: Fix code style issues'
>> 018/20:[0012] [FC] 'hw/pci-host/piix: Extract PIIX3 functions to
>> hw/isa/piix3.c'
>> 019/20:[----] [--] 'hw/pci-host: Rename incorrectly named 'piix'
>> as 'i440fx''
>> 020/20:[----] [-C] 'hw/pci-host/i440fx: Remove the last PIIX3
>> traces'
>>
>> Previous cover:
>>
>> This series is a rework of "piix4: cleanup and improvements" [1]
>> from Hervé, and my "remove i386/pc dependency: PIIX cleanup" [2].
>>
>> Still trying to remove the strong X86/PC dependency 2 years later,
>> one step at a time.
>> Here we split the PIIX3 southbridge from i440FX northbridge.
>> The i440FX northbridge is only used by the PC machine, while the
>> PIIX southbridge is also used by the Malta MIPS machine.
>>
>> This is also a step forward using KConfig with the Malta board.
>> Without this split, it was impossible to compile the Malta without
>> pulling various X86 pieces of code.
>>
>> The overall design cleanup is not yet perfect, but enough to post
>> as a series.
>>
>> Now that the PIIX3 code is extracted, the code duplication with
>> the
>> PIIX4 chipset is obvious. Not worth improving for now because it
>> isn't broken.
>>
>> [0]
>> https://lists.gnu.org/archive/html/qemu-devel/2019-10/msg036
>> 85.html
>> <https://lists.gnu.org/archive/html/qemu-devel/2019-10/
>> msg03685.html>
>> [1]
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html
>> <https://www.mail-archive.com/qemu-devel@nongnu.org/msg500737.html>
>> [2]
>> https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html
>> <https://www.mail-archive.com/qemu-devel@nongnu.org/msg504081.html>
>>
>> Based-on: <20191018133547.10936-1-philmd@redhat.com
>> <mailto:20191018133547.10936-1-philmd@redhat.com>>
>> mc146818rtc: Allow call object_initialize(MC146818_RTC) instead
>> of rtc_init()
>>
>
> ... because it depends on this series which has been queued by Paolo but
> is not yet merged.
>
> https://mid.mail-archive.com/20191018133547.10936-1-philmd@r
>> edhat.com
>> <https://mid.mail-archive.com/20191018133547.10936-1-philmd@
>> redhat.com>
>>
>> Hervé Poussineau (5):
>> piix4: Add the Reset Control Register
>> piix4: Add a i8259 Interrupt Controller as specified in
>> datasheet
>> piix4: Rename PIIX4 object to piix4-isa
>> piix4: Add a i8257 DMA Controller as specified in datasheet
>> piix4: Add a i8254 PIT Controller as specified in datasheet
>>
>> Philippe Mathieu-Daudé (15):
>> MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets
>> Revert "irq: introduce qemu_irq_proxy()"
>> piix4: Add a MC146818 RTC Controller as specified in datasheet
>> hw/mips/mips_malta: Create IDE hard drive array dynamically
>> hw/mips/mips_malta: Extract the PIIX4 creation code as
>> piix4_create()
>> hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c
>> hw/i386: Remove obsolete LoadStateHandler::load_state_old
>> handlers
>> hw/pci-host/piix: Extract piix3_create()
>> hw/pci-host/piix: Move RCR_IOPORT register definition
>> hw/pci-host/piix: Define and use the PIIX IRQ Route Control
>> Registers
>> hw/pci-host/piix: Move i440FX declarations to
>> hw/pci-host/i440fx.h
>> hw/pci-host/piix: Fix code style issues
>> hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c
>> hw/pci-host: Rename incorrectly named 'piix' as 'i440fx'
>> hw/pci-host/i440fx: Remove the last PIIX3 traces
>>
>> MAINTAINERS | 14 +-
>> hw/acpi/pcihp.c | 2 +-
>> hw/acpi/piix4.c | 42 +--
>> hw/core/irq.c | 14 -
>> hw/i386/Kconfig | 3 +-
>> hw/i386/acpi-build.c | 5 +-
>> hw/i386/pc_piix.c | 10 +-
>> hw/i386/xen/xen-hvm.c | 5 +-
>> hw/intc/apic_common.c | 49 ----
>> hw/isa/Kconfig | 4 +
>> hw/isa/Makefile.objs | 1 +
>> hw/isa/piix3.c | 399
>> +++++++++++++++++++++++++++++
>> hw/isa/piix4.c | 151 ++++++++++-
>> hw/mips/gt64xxx_pci.c | 5 +-
>> hw/mips/mips_malta.c | 46 +---
>> hw/pci-host/Kconfig | 3 +-
>> hw/pci-host/Makefile.objs | 2 +-
>> hw/pci-host/{piix.c => i440fx.c} | 424
>> +------------------------------
>> hw/timer/i8254_common.c | 40 ---
>> include/hw/acpi/piix4.h | 6 -
>> include/hw/i386/pc.h | 37 ---
>> include/hw/irq.h | 5 -
>> include/hw/isa/isa.h | 2 +
>> include/hw/pci-host/i440fx.h | 36 +++
>> include/hw/southbridge/piix.h | 74 ++++++
>> stubs/pci-host-piix.c | 3 +-
>> 26 files changed, 699 insertions(+), 683 deletions(-)
>> create mode 100644 hw/isa/piix3.c
>> rename hw/pci-host/{piix.c => i440fx.c} (58%)
>> delete mode 100644 include/hw/acpi/piix4.h
>> create mode 100644 include/hw/pci-host/i440fx.h
>> create mode 100644 include/hw/southbridge/piix.h
>>
>> -- 2.21.0
>>
>>
>>
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^ permalink raw reply [flat|nested] 106+ messages in thread
end of thread, other threads:[~2019-10-26 15:19 UTC | newest]
Thread overview: 106+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-10-18 13:47 [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 01/20] MAINTAINERS: Keep PIIX4 South Bridge separate from PC Chipsets Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 0:54 ` Li Qiang
2019-10-21 0:54 ` [Xen-devel] " Li Qiang
2019-10-18 13:47 ` [PATCH v2 02/20] piix4: Add the Reset Control Register Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 1:25 ` Li Qiang
2019-10-21 1:25 ` [Xen-devel] " Li Qiang
2019-10-21 8:37 ` Philippe Mathieu-Daudé
2019-10-21 8:37 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 03/20] piix4: Add a i8259 Interrupt Controller as specified in datasheet Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 14:59 ` Li Qiang
2019-10-21 14:59 ` [Xen-devel] " Li Qiang
2019-10-26 14:29 ` Philippe Mathieu-Daudé
2019-10-26 14:29 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-22 8:44 ` Esteban Bosse
2019-10-22 8:44 ` [Xen-devel] " Esteban Bosse
2019-10-22 9:35 ` Philippe Mathieu-Daudé
2019-10-22 9:35 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-23 18:53 ` Esteban Bosse
2019-10-23 18:53 ` [Xen-devel] " Esteban Bosse
2019-10-22 8:48 ` Esteban Bosse
2019-10-22 8:48 ` [Xen-devel] " Esteban Bosse
2019-10-22 9:24 ` Philippe Mathieu-Daudé
2019-10-22 9:24 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-22 9:42 ` Peter Maydell
2019-10-22 9:42 ` [Xen-devel] " Peter Maydell
2019-10-23 18:52 ` Esteban Bosse
2019-10-23 18:52 ` [Xen-devel] " Esteban Bosse
2019-10-22 9:53 ` Aleksandar Markovic
2019-10-22 9:53 ` [Xen-devel] " Aleksandar Markovic
2019-10-22 10:09 ` Philippe Mathieu-Daudé
2019-10-22 10:09 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 04/20] Revert "irq: introduce qemu_irq_proxy()" Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 15:18 ` Li Qiang
2019-10-21 15:18 ` [Xen-devel] " Li Qiang
2019-10-22 8:50 ` Esteban Bosse
2019-10-22 8:50 ` [Xen-devel] " Esteban Bosse
2019-10-18 13:47 ` [PATCH v2 05/20] piix4: Rename PIIX4 object to piix4-isa Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 15:19 ` Li Qiang
2019-10-21 15:19 ` [Xen-devel] " Li Qiang
2019-10-22 8:57 ` Esteban Bosse
2019-10-22 8:57 ` [Xen-devel] " Esteban Bosse
2019-10-18 13:47 ` [PATCH v2 06/20] piix4: Add a i8257 DMA Controller as specified in datasheet Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 15:25 ` Li Qiang
2019-10-21 15:25 ` [Xen-devel] " Li Qiang
2019-10-21 15:56 ` Philippe Mathieu-Daudé
2019-10-21 15:56 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-22 9:01 ` Esteban Bosse
2019-10-22 9:01 ` [Xen-devel] " Esteban Bosse
2019-10-18 13:47 ` [PATCH v2 07/20] piix4: Add a i8254 PIT " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 08/20] piix4: Add a MC146818 RTC " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 09/20] hw/mips/mips_malta: Create IDE hard drive array dynamically Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-21 15:28 ` Li Qiang
2019-10-21 15:28 ` [Xen-devel] " Li Qiang
2019-10-18 13:47 ` [PATCH v2 10/20] hw/mips/mips_malta: Extract the PIIX4 creation code as piix4_create() Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 11/20] hw/isa/piix4: Move piix4_create() to hw/isa/piix4.c Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 12/20] hw/i386: Remove obsolete LoadStateHandler::load_state_old handlers Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 13/20] hw/pci-host/piix: Extract piix3_create() Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-22 9:33 ` Esteban Bosse
2019-10-22 9:33 ` [Xen-devel] " Esteban Bosse
2019-10-18 13:47 ` [PATCH v2 14/20] hw/pci-host/piix: Move RCR_IOPORT register definition Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 15/20] hw/pci-host/piix: Define and use the PIIX IRQ Route Control Registers Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 16/20] hw/pci-host/piix: Move i440FX declarations to hw/pci-host/i440fx.h Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 17/20] hw/pci-host/piix: Fix code style issues Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-22 9:39 ` Esteban Bosse
2019-10-22 9:39 ` [Xen-devel] " Esteban Bosse
2019-10-18 13:47 ` [PATCH v2 18/20] hw/pci-host/piix: Extract PIIX3 functions to hw/isa/piix3.c Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 19/20] hw/pci-host: Rename incorrectly named 'piix' as 'i440fx' Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 13:47 ` [PATCH v2 20/20] hw/pci-host/i440fx: Remove the last PIIX3 traces Philippe Mathieu-Daudé
2019-10-18 13:47 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-18 17:04 ` Aleksandar Markovic
2019-10-18 17:04 ` [Xen-devel] " Aleksandar Markovic
2019-10-19 15:22 ` Philippe Mathieu-Daudé
2019-10-19 15:22 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-19 10:50 ` [PATCH v2 00/20] hw/i386/pc: Split PIIX3 southbridge from i440FX northbridge no-reply
2019-10-19 10:50 ` [Xen-devel] " no-reply
2019-10-19 15:15 ` Aleksandar Markovic
2019-10-19 15:15 ` [Xen-devel] " Aleksandar Markovic
2019-10-24 19:55 ` Aleksandar Markovic
2019-10-24 19:55 ` [Xen-devel] " Aleksandar Markovic
2019-10-25 10:51 ` Aleksandar Markovic
2019-10-25 10:51 ` [Xen-devel] " Aleksandar Markovic
2019-10-26 14:39 ` Philippe Mathieu-Daudé
2019-10-26 14:39 ` [Xen-devel] " Philippe Mathieu-Daudé
2019-10-26 15:17 ` Aleksandar Markovic
2019-10-26 15:17 ` [Xen-devel] " Aleksandar Markovic
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