* [PATCH v6 01/12] target/mips: Clean up helper.c
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 02/12] target/mips: Clean up op_helper.c Aleksandar Markovic
` (14 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Markus Armbruster, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Cc: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.c | 123 +++++++++++++++++++++++++++++++--------------------
1 file changed, 74 insertions(+), 49 deletions(-)
diff --git a/target/mips/helper.c b/target/mips/helper.c
index a2b6459..781930a 100644
--- a/target/mips/helper.c
+++ b/target/mips/helper.c
@@ -39,8 +39,8 @@ enum {
#if !defined(CONFIG_USER_ONLY)
/* no MMU emulation */
-int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type)
+int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type)
{
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
@@ -48,26 +48,28 @@ int no_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
}
/* fixed mapping MMU emulation */
-int fixed_mmu_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type)
+int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type)
{
if (address <= (int32_t)0x7FFFFFFFUL) {
- if (!(env->CP0_Status & (1 << CP0St_ERL)))
+ if (!(env->CP0_Status & (1 << CP0St_ERL))) {
*physical = address + 0x40000000UL;
- else
+ } else {
*physical = address;
- } else if (address <= (int32_t)0xBFFFFFFFUL)
+ }
+ } else if (address <= (int32_t)0xBFFFFFFFUL) {
*physical = address & 0x1FFFFFFF;
- else
+ } else {
*physical = address;
+ }
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
/* MIPS32/MIPS64 R4000-style MMU emulation */
-int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
- target_ulong address, int rw, int access_type)
+int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot,
+ target_ulong address, int rw, int access_type)
{
uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask;
int i;
@@ -99,8 +101,9 @@ int r4k_map_address (CPUMIPSState *env, hwaddr *physical, int *prot,
if (rw != MMU_DATA_STORE || (n ? tlb->D1 : tlb->D0)) {
*physical = tlb->PFN[n] | (address & (mask >> 1));
*prot = PAGE_READ;
- if (n ? tlb->D1 : tlb->D0)
+ if (n ? tlb->D1 : tlb->D0) {
*prot |= PAGE_WRITE;
+ }
if (!(n ? tlb->XI1 : tlb->XI0)) {
*prot |= PAGE_EXEC;
}
@@ -130,7 +133,7 @@ static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx)
int32_t adetlb_mask;
switch (mmu_idx) {
- case 3 /* ERL */:
+ case 3: /* ERL */
/* If EU is set, always unmapped */
if (eu) {
return 0;
@@ -204,7 +207,7 @@ static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical,
pa & ~(hwaddr)segmask);
}
-static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
+static int get_physical_address(CPUMIPSState *env, hwaddr *physical,
int *prot, target_ulong real_address,
int rw, int access_type, int mmu_idx)
{
@@ -252,14 +255,15 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
} else {
segctl = env->CP0_SegCtl2 >> 16;
}
- ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
- access_type, mmu_idx, segctl,
- 0x3FFFFFFF);
+ ret = get_segctl_physical_address(env, physical, prot,
+ real_address, rw, access_type,
+ mmu_idx, segctl, 0x3FFFFFFF);
#if defined(TARGET_MIPS64)
} else if (address < 0x4000000000000000ULL) {
/* xuseg */
if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot,
+ real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -267,7 +271,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
/* xsseg */
if ((supervisor_mode || kernel_mode) &&
SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot,
+ real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -307,7 +312,8 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
/* xkseg */
if (kernel_mode && KX &&
address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) {
- ret = env->tlb->map_address(env, physical, prot, real_address, rw, access_type);
+ ret = env->tlb->map_address(env, physical, prot,
+ real_address, rw, access_type);
} else {
ret = TLBRET_BADADDR;
}
@@ -328,8 +334,10 @@ static int get_physical_address (CPUMIPSState *env, hwaddr *physical,
access_type, mmu_idx,
env->CP0_SegCtl0 >> 16, 0x1FFFFFFF);
} else {
- /* kseg3 */
- /* XXX: debug segment is not emulated */
+ /*
+ * kseg3
+ * XXX: debug segment is not emulated
+ */
ret = get_segctl_physical_address(env, physical, prot, real_address, rw,
access_type, mmu_idx,
env->CP0_SegCtl0, 0x1FFFFFFF);
@@ -515,9 +523,9 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address,
#if defined(TARGET_MIPS64)
env->CP0_EntryHi &= env->SEGMask;
env->CP0_XContext =
- /* PTEBase */ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) |
- /* R */ (extract64(address, 62, 2) << (env->SEGBITS - 9)) |
- /* BadVPN2 */ (extract64(address, 13, env->SEGBITS - 13) << 4);
+ (env->CP0_XContext & ((~0ULL) << (env->SEGBITS - 7))) | /* PTEBase */
+ (extract64(address, 62, 2) << (env->SEGBITS - 9)) | /* R */
+ (extract64(address, 13, env->SEGBITS - 13) << 4); /* BadVPN2 */
#endif
cs->exception_index = exception;
env->error_code = error_code;
@@ -945,7 +953,8 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
}
#ifndef CONFIG_USER_ONLY
-hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw)
+hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address,
+ int rw)
{
hwaddr physical;
int prot;
@@ -1005,7 +1014,7 @@ static const char * const excp_names[EXCP_LAST + 1] = {
};
#endif
-target_ulong exception_resume_pc (CPUMIPSState *env)
+target_ulong exception_resume_pc(CPUMIPSState *env)
{
target_ulong bad_pc;
target_ulong isa_mode;
@@ -1013,8 +1022,10 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
isa_mode = !!(env->hflags & MIPS_HFLAG_M16);
bad_pc = env->active_tc.PC | isa_mode;
if (env->hflags & MIPS_HFLAG_BMASK) {
- /* If the exception was raised from a delay slot, come back to
- the jump. */
+ /*
+ * If the exception was raised from a delay slot, come back to
+ * the jump.
+ */
bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4);
}
@@ -1022,14 +1033,14 @@ target_ulong exception_resume_pc (CPUMIPSState *env)
}
#if !defined(CONFIG_USER_ONLY)
-static void set_hflags_for_handler (CPUMIPSState *env)
+static void set_hflags_for_handler(CPUMIPSState *env)
{
/* Exception handlers are entered in 32-bit mode. */
env->hflags &= ~(MIPS_HFLAG_M16);
/* ...except that microMIPS lets you choose. */
if (env->insn_flags & ASE_MICROMIPS) {
- env->hflags |= (!!(env->CP0_Config3
- & (1 << CP0C3_ISA_ON_EXC))
+ env->hflags |= (!!(env->CP0_Config3 &
+ (1 << CP0C3_ISA_ON_EXC))
<< MIPS_HFLAG_M16_SHIFT);
}
}
@@ -1096,10 +1107,12 @@ void mips_cpu_do_interrupt(CPUState *cs)
switch (cs->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
- /* Debug single step cannot be raised inside a delay slot and
- resume will always occur on the next instruction
- (but we assume the pc has always been updated during
- code translation). */
+ /*
+ * Debug single step cannot be raised inside a delay slot and
+ * resume will always occur on the next instruction
+ * (but we assume the pc has always been updated during
+ * code translation).
+ */
env->CP0_DEPC = env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16);
goto enter_debug_mode;
case EXCP_DINT:
@@ -1111,7 +1124,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
case EXCP_DBp:
env->CP0_Debug |= 1 << CP0DB_DBp;
/* Setup DExcCode - SDBBP instruction */
- env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 << CP0DB_DEC;
+ env->CP0_Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) |
+ (9 << CP0DB_DEC);
goto set_DEPC;
case EXCP_DDBS:
env->CP0_Debug |= 1 << CP0DB_DDBS;
@@ -1132,8 +1146,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
- if (!(env->CP0_Status & (1 << CP0St_EXL)))
+ if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_Cause &= ~(1U << CP0Ca_BD);
+ }
env->active_tc.PC = env->exception_base + 0x480;
set_hflags_for_handler(env);
break;
@@ -1159,8 +1174,9 @@ void mips_cpu_do_interrupt(CPUState *cs)
}
env->hflags |= MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
- if (!(env->CP0_Status & (1 << CP0St_EXL)))
+ if (!(env->CP0_Status & (1 << CP0St_EXL))) {
env->CP0_Cause &= ~(1U << CP0Ca_BD);
+ }
env->active_tc.PC = env->exception_base;
set_hflags_for_handler(env);
break;
@@ -1176,12 +1192,16 @@ void mips_cpu_do_interrupt(CPUState *cs)
uint32_t pending = (env->CP0_Cause & CP0Ca_IP_mask) >> CP0Ca_IP;
if (env->CP0_Config3 & (1 << CP0C3_VEIC)) {
- /* For VEIC mode, the external interrupt controller feeds
- * the vector through the CP0Cause IP lines. */
+ /*
+ * For VEIC mode, the external interrupt controller feeds
+ * the vector through the CP0Cause IP lines.
+ */
vector = pending;
} else {
- /* Vectored Interrupts
- * Mask with Status.IM7-IM0 to get enabled interrupts. */
+ /*
+ * Vectored Interrupts
+ * Mask with Status.IM7-IM0 to get enabled interrupts.
+ */
pending &= (env->CP0_Status >> CP0St_IM) & 0xff;
/* Find the highest-priority interrupt. */
while (pending >>= 1) {
@@ -1354,7 +1374,8 @@ void mips_cpu_do_interrupt(CPUState *cs)
env->active_tc.PC += offset;
set_hflags_for_handler(env);
- env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
+ env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) |
+ (cause << CP0Ca_EC);
break;
default:
abort();
@@ -1390,7 +1411,7 @@ bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
}
#if !defined(CONFIG_USER_ONLY)
-void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
+void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra)
{
CPUState *cs = env_cpu(env);
r4k_tlb_t *tlb;
@@ -1400,16 +1421,20 @@ void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra)
target_ulong mask;
tlb = &env->tlb->mmu.r4k.tlb[idx];
- /* The qemu TLB is flushed when the ASID changes, so no need to
- flush these entries again. */
+ /*
+ * The qemu TLB is flushed when the ASID changes, so no need to
+ * flush these entries again.
+ */
if (tlb->G == 0 && tlb->ASID != ASID) {
return;
}
if (use_extra && env->tlb->tlb_in_use < MIPS_TLB_MAX) {
- /* For tlbwr, we can shadow the discarded entry into
- a new (fake) TLB entry, as long as the guest can not
- tell that it's there. */
+ /*
+ * For tlbwr, we can shadow the discarded entry into
+ * a new (fake) TLB entry, as long as the guest can not
+ * tell that it's there.
+ */
env->tlb->mmu.r4k.tlb[env->tlb->tlb_in_use] = *tlb;
env->tlb->tlb_in_use++;
return;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 02/12] target/mips: Clean up op_helper.c
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 01/12] target/mips: Clean up helper.c Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 03/12] MAINTAINERS: Update mail address of Aleksandar Rikalo Aleksandar Markovic
` (13 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/op_helper.c | 1010 +++++++++++++++++++++++++++++++----------------
1 file changed, 663 insertions(+), 347 deletions(-)
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index 4de6465..18fcee4 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -64,8 +64,7 @@ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
static inline type do_##name(CPUMIPSState *env, target_ulong addr, \
int mem_idx, uintptr_t retaddr) \
{ \
- switch (mem_idx) \
- { \
+ switch (mem_idx) { \
case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \
case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \
default: \
@@ -92,12 +91,17 @@ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
static inline void do_##name(CPUMIPSState *env, target_ulong addr, \
type val, int mem_idx, uintptr_t retaddr) \
{ \
- switch (mem_idx) \
- { \
- case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \
- case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \
+ switch (mem_idx) { \
+ case 0: \
+ cpu_##insn##_kernel_ra(env, addr, val, retaddr); \
+ break; \
+ case 1: \
+ cpu_##insn##_super_ra(env, addr, val, retaddr); \
+ break; \
default: \
- case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \
+ case 2: \
+ cpu_##insn##_user_ra(env, addr, val, retaddr); \
+ break; \
case 3: \
cpu_##insn##_error_ra(env, addr, val, retaddr); \
break; \
@@ -114,7 +118,8 @@ HELPER_ST(sd, stq, uint64_t)
/* 64 bits arithmetic for 32 bits hosts */
static inline uint64_t get_HILO(CPUMIPSState *env)
{
- return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
+ return ((uint64_t)(env->active_tc.HI[0]) << 32) |
+ (uint32_t)env->active_tc.LO[0];
}
static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
@@ -435,9 +440,10 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
}
#if defined(TARGET_MIPS64)
-/* "half" load and stores. We must do the memory access inline,
- or fault handling won't work. */
-
+/*
+ * "half" load and stores. We must do the memory access inline,
+ * or fault handling won't work.
+ */
#ifdef TARGET_WORDS_BIGENDIAN
#define GET_LMASK64(v) ((v) & 7)
#else
@@ -535,7 +541,7 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -557,7 +563,7 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -579,7 +585,7 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -600,7 +606,7 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
target_ulong base_reglist = reglist & 0xf;
target_ulong do_r31 = reglist & 0x10;
- if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
+ if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) {
target_ulong i;
for (i = 0; i < base_reglist; i++) {
@@ -623,8 +629,10 @@ static bool mips_vpe_is_wfi(MIPSCPU *c)
CPUState *cpu = CPU(c);
CPUMIPSState *env = &c->env;
- /* If the VPE is halted but otherwise active, it means it's waiting for
- an interrupt. */
+ /*
+ * If the VPE is halted but otherwise active, it means it's waiting for
+ * an interrupt.\
+ */
return cpu->halted && mips_vpe_active(env);
}
@@ -638,9 +646,11 @@ static bool mips_vp_is_wfi(MIPSCPU *c)
static inline void mips_vpe_wake(MIPSCPU *c)
{
- /* Don't set ->halted = 0 directly, let it be done via cpu_has_work
- because there might be other conditions that state that c should
- be sleeping. */
+ /*
+ * Don't set ->halted = 0 directly, let it be done via cpu_has_work
+ * because there might be other conditions that state that c should
+ * be sleeping.
+ */
qemu_mutex_lock_iothread();
cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
qemu_mutex_unlock_iothread();
@@ -650,8 +660,10 @@ static inline void mips_vpe_sleep(MIPSCPU *cpu)
{
CPUState *cs = CPU(cpu);
- /* The VPE was shut off, really go to bed.
- Reset any old _WAKE requests. */
+ /*
+ * The VPE was shut off, really go to bed.
+ * Reset any old _WAKE requests.
+ */
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
}
@@ -684,9 +696,12 @@ static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
* This function will transform @tc into a local index within the
* returned #CPUMIPSState.
*/
-/* FIXME: This code assumes that all VPEs have the same number of TCs,
- which depends on runtime setup. Can probably be fixed by
- walking the list of CPUMIPSStates. */
+
+/*
+ * FIXME: This code assumes that all VPEs have the same number of TCs,
+ * which depends on runtime setup. Can probably be fixed by
+ * walking the list of CPUMIPSStates.
+ */
static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
{
MIPSCPU *cpu;
@@ -712,17 +727,21 @@ static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
return &cpu->env;
}
-/* The per VPE CP0_Status register shares some fields with the per TC
- CP0_TCStatus registers. These fields are wired to the same registers,
- so changes to either of them should be reflected on both registers.
-
- Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
-
- These helper call synchronizes the regs for a given cpu. */
+/*
+ * The per VPE CP0_Status register shares some fields with the per TC
+ * CP0_TCStatus registers. These fields are wired to the same registers,
+ * so changes to either of them should be reflected on both registers.
+ *
+ * Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
+ *
+ * These helper call synchronizes the regs for a given cpu.
+ */
-/* Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c. */
-/* static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
- int tc); */
+/*
+ * Called for updates to CP0_Status. Defined in "cpu.h" for gdbstub.c.
+ * static inline void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu,
+ * int tc);
+ */
/* Called for updates to CP0_TCStatus. */
static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
@@ -805,10 +824,11 @@ target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCStatus;
- else
+ } else {
return other->tcs[other_tc].CP0_TCStatus;
+ }
}
target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
@@ -821,10 +841,11 @@ target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCBind;
- else
+ } else {
return other->tcs[other_tc].CP0_TCBind;
+ }
}
target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
@@ -837,10 +858,11 @@ target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.PC;
- else
+ } else {
return other->tcs[other_tc].PC;
+ }
}
target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
@@ -853,10 +875,11 @@ target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCHalt;
- else
+ } else {
return other->tcs[other_tc].CP0_TCHalt;
+ }
}
target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
@@ -869,10 +892,11 @@ target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCContext;
- else
+ } else {
return other->tcs[other_tc].CP0_TCContext;
+ }
}
target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
@@ -885,10 +909,11 @@ target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCSchedule;
- else
+ } else {
return other->tcs[other_tc].CP0_TCSchedule;
+ }
}
target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
@@ -901,10 +926,11 @@ target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.CP0_TCScheFBack;
- else
+ } else {
return other->tcs[other_tc].CP0_TCScheFBack;
+ }
}
target_ulong helper_mfc0_count(CPUMIPSState *env)
@@ -987,8 +1013,9 @@ target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
target_ulong helper_mfc0_debug(CPUMIPSState *env)
{
target_ulong t0 = env->CP0_Debug;
- if (env->hflags & MIPS_HFLAG_DM)
+ if (env->hflags & MIPS_HFLAG_DM) {
t0 |= 1 << CP0DB_DM;
+ }
return t0;
}
@@ -999,10 +1026,11 @@ target_ulong helper_mftc0_debug(CPUMIPSState *env)
int32_t tcstatus;
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
tcstatus = other->active_tc.CP0_Debug_tcstatus;
- else
+ } else {
tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
+ }
/* XXX: Might be wrong, check with EJTAG spec. */
return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
@@ -1076,14 +1104,16 @@ void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
uint32_t mask = 0;
uint32_t newval;
- if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
(1 << CP0MVPCo_EVP);
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ }
+ if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0MVPCo_STLB);
+ }
newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
- // TODO: Enable/disable shared TLB, enable/disable VPEs.
+ /* TODO: Enable/disable shared TLB, enable/disable VPEs. */
env->mvp->CP0_MVPControl = newval;
}
@@ -1097,10 +1127,12 @@ void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
(1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
- /* Yield scheduler intercept not implemented. */
- /* Gating storage scheduler intercept not implemented. */
+ /*
+ * Yield scheduler intercept not implemented.
+ * Gating storage scheduler intercept not implemented.
+ */
- // TODO: Enable/disable TCs.
+ /* TODO: Enable/disable TCs. */
env->CP0_VPEControl = newval;
}
@@ -1143,13 +1175,14 @@ void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
uint32_t newval;
if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
- if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
+ if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA)) {
mask |= (0xff << CP0VPEC0_XTC);
+ }
mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
}
newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
- // TODO: TC exclusive handling due to ERL/EXL.
+ /* TODO: TC exclusive handling due to ERL/EXL. */
env->CP0_VPEConf0 = newval;
}
@@ -1181,7 +1214,7 @@ void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
/* UDI not implemented. */
/* CP2 not implemented. */
- // TODO: Handle FPU (CP1) binding.
+ /* TODO: Handle FPU (CP1) binding. */
env->CP0_VPEConf1 = newval;
}
@@ -1233,10 +1266,11 @@ void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCStatus = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCStatus = arg1;
+ }
sync_c0_tcstatus(other, other_tc, arg1);
}
@@ -1245,8 +1279,9 @@ void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
uint32_t mask = (1 << CP0TCBd_TBE);
uint32_t newval;
- if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
env->active_tc.CP0_TCBind = newval;
}
@@ -1258,8 +1293,9 @@ void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
uint32_t newval;
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
+ if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC)) {
mask |= (1 << CP0TCBd_CurVPE);
+ }
if (other_tc == other->current_tc) {
newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
other->active_tc.CP0_TCBind = newval;
@@ -1304,7 +1340,7 @@ void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
env->active_tc.CP0_TCHalt = arg1 & 0x1;
- // TODO: Halt TC / Restart (if allocated+active) TC.
+ /* TODO: Halt TC / Restart (if allocated+active) TC. */
if (env->active_tc.CP0_TCHalt & 1) {
mips_tc_sleep(cpu, env->current_tc);
} else {
@@ -1318,12 +1354,13 @@ void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
MIPSCPU *other_cpu = env_archcpu(other);
- // TODO: Halt TC / Restart (if allocated+active) TC.
+ /* TODO: Halt TC / Restart (if allocated+active) TC. */
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCHalt = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCHalt = arg1;
+ }
if (arg1 & 1) {
mips_tc_sleep(other_cpu, other_tc);
@@ -1342,10 +1379,11 @@ void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCContext = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCContext = arg1;
+ }
}
void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
@@ -1358,10 +1396,11 @@ void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCSchedule = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCSchedule = arg1;
+ }
}
void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
@@ -1374,10 +1413,11 @@ void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_TCScheFBack = arg1;
- else
+ } else {
other->tcs[other_tc].CP0_TCScheFBack = arg1;
+ }
}
void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
@@ -1703,9 +1743,15 @@ void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
case 3:
qemu_log(", ERL\n");
break;
- case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
- case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
- case MIPS_HFLAG_KM: qemu_log("\n"); break;
+ case MIPS_HFLAG_UM:
+ qemu_log(", UM\n");
+ break;
+ case MIPS_HFLAG_SM:
+ qemu_log(", SM\n");
+ break;
+ case MIPS_HFLAG_KM:
+ qemu_log("\n");
+ break;
default:
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
@@ -1860,21 +1906,26 @@ void helper_mtc0_maari(CPUMIPSState *env, target_ulong arg1)
{
int index = arg1 & 0x3f;
if (index == 0x3f) {
- /* Software may write all ones to INDEX to determine the
- maximum value supported. */
+ /*
+ * Software may write all ones to INDEX to determine the
+ * maximum value supported.
+ */
env->CP0_MAARI = MIPS_MAAR_MAX - 1;
} else if (index < MIPS_MAAR_MAX) {
env->CP0_MAARI = index;
}
- /* Other than the all ones, if the
- value written is not supported, then INDEX is unchanged
- from its previous value. */
+ /*
+ * Other than the all ones, if the value written is not supported,
+ * then INDEX is unchanged from its previous value.
+ */
}
void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
{
- /* Watch exceptions for instructions, data loads, data stores
- not implemented. */
+ /*
+ * Watch exceptions for instructions, data loads, data stores
+ * not implemented.
+ */
env->CP0_WatchLo[sel] = (arg1 & ~0x7);
}
@@ -1899,10 +1950,11 @@ void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
{
env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
- if (arg1 & (1 << CP0DB_DM))
+ if (arg1 & (1 << CP0DB_DM)) {
env->hflags |= MIPS_HFLAG_DM;
- else
+ } else {
env->hflags &= ~MIPS_HFLAG_DM;
+ }
}
void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
@@ -1912,10 +1964,11 @@ void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
/* XXX: Might be wrong, check with EJTAG spec. */
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.CP0_Debug_tcstatus = val;
- else
+ } else {
other->tcs[other_tc].CP0_Debug_tcstatus = val;
+ }
other->CP0_Debug = (other->CP0_Debug &
((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
(arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
@@ -1944,9 +1997,11 @@ void helper_mtc0_errctl(CPUMIPSState *env, target_ulong arg1)
void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
{
if (env->hflags & MIPS_HFLAG_ITC_CACHE) {
- /* If CACHE instruction is configured for ITC tags then make all
- CP0.TagLo bits writable. The actual write to ITC Configuration
- Tag will take care of the read-only bits. */
+ /*
+ * If CACHE instruction is configured for ITC tags then make all
+ * CP0.TagLo bits writable. The actual write to ITC Configuration
+ * Tag will take care of the read-only bits.
+ */
env->CP0_TagLo = arg1;
} else {
env->CP0_TagLo = arg1 & 0xFFFFFCF6;
@@ -1974,10 +2029,11 @@ target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.gpr[sel];
- else
+ } else {
return other->tcs[other_tc].gpr[sel];
+ }
}
target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
@@ -1985,10 +2041,11 @@ target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.LO[sel];
- else
+ } else {
return other->tcs[other_tc].LO[sel];
+ }
}
target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
@@ -1996,10 +2053,11 @@ target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.HI[sel];
- else
+ } else {
return other->tcs[other_tc].HI[sel];
+ }
}
target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
@@ -2007,10 +2065,11 @@ target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.ACX[sel];
- else
+ } else {
return other->tcs[other_tc].ACX[sel];
+ }
}
target_ulong helper_mftdsp(CPUMIPSState *env)
@@ -2018,10 +2077,11 @@ target_ulong helper_mftdsp(CPUMIPSState *env)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
return other->active_tc.DSPControl;
- else
+ } else {
return other->tcs[other_tc].DSPControl;
+ }
}
void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2029,10 +2089,11 @@ void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.gpr[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].gpr[sel] = arg1;
+ }
}
void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2040,10 +2101,11 @@ void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.LO[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].LO[sel] = arg1;
+ }
}
void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2051,10 +2113,11 @@ void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.HI[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].HI[sel] = arg1;
+ }
}
void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
@@ -2062,10 +2125,11 @@ void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.ACX[sel] = arg1;
- else
+ } else {
other->tcs[other_tc].ACX[sel] = arg1;
+ }
}
void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
@@ -2073,22 +2137,23 @@ void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
- if (other_tc == other->current_tc)
+ if (other_tc == other->current_tc) {
other->active_tc.DSPControl = arg1;
- else
+ } else {
other->tcs[other_tc].DSPControl = arg1;
+ }
}
/* MIPS MT functions */
target_ulong helper_dmt(void)
{
- // TODO
- return 0;
+ /* TODO */
+ return 0;
}
target_ulong helper_emt(void)
{
- // TODO
+ /* TODO */
return 0;
}
@@ -2130,8 +2195,10 @@ target_ulong helper_evpe(CPUMIPSState *env)
void helper_fork(target_ulong arg1, target_ulong arg2)
{
- // arg1 = rt, arg2 = rs
- // TODO: store to TC register
+ /*
+ * arg1 = rt, arg2 = rs
+ * TODO: store to TC register
+ */
}
target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
@@ -2149,11 +2216,12 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
}
}
} else if (arg1 == 0) {
- if (0 /* TODO: TC underflow */) {
+ if (0) {
+ /* TODO: TC underflow */
env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
do_raise_exception(env, EXCP_THREAD, GETPC());
} else {
- // TODO: Deallocate TC
+ /* TODO: Deallocate TC */
}
} else if (arg1 > 0) {
/* Yield qualifier inputs not implemented. */
@@ -2193,8 +2261,10 @@ target_ulong helper_evp(CPUMIPSState *env)
CPU_FOREACH(other_cs) {
MIPSCPU *other_cpu = MIPS_CPU(other_cs);
if ((&other_cpu->env != env) && !mips_vp_is_wfi(other_cpu)) {
- /* If the VP is WFI, don't disturb its sleep.
- * Otherwise, wake it up. */
+ /*
+ * If the VP is WFI, don't disturb its sleep.
+ * Otherwise, wake it up.
+ */
mips_vpe_wake(other_cpu);
}
}
@@ -2206,7 +2276,7 @@ target_ulong helper_evp(CPUMIPSState *env)
#ifndef CONFIG_USER_ONLY
/* TLB management */
-static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
+static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first)
{
/* Discard entries from env->tlb[first] onwards. */
while (env->tlb->tlb_in_use > first) {
@@ -2308,8 +2378,10 @@ void r4k_helper_tlbwi(CPUMIPSState *env)
XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1;
RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1;
- /* Discard cached TLB entries, unless tlbwi is just upgrading access
- permissions on the current entry. */
+ /*
+ * Discard cached TLB entries, unless tlbwi is just upgrading access
+ * permissions on the current entry.
+ */
if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
(!tlb->EHINV && EHINV) ||
(tlb->V0 && !V0) || (tlb->D0 && !D0) ||
@@ -2370,7 +2442,7 @@ void r4k_helper_tlbp(CPUMIPSState *env)
#endif
/* Check ASID, virtual page number & size */
if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
- r4k_mips_tlb_flush_extra (env, i);
+ r4k_mips_tlb_flush_extra(env, i);
break;
}
}
@@ -2400,8 +2472,9 @@ void r4k_helper_tlbr(CPUMIPSState *env)
tlb = &env->tlb->mmu.r4k.tlb[idx];
/* If this will change the current ASID, flush qemu's TLB. */
- if (ASID != tlb->ASID)
+ if (ASID != tlb->ASID) {
cpu_mips_tlb_flush(env);
+ }
r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
@@ -2476,10 +2549,12 @@ static void debug_pre_eret(CPUMIPSState *env)
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
- if (env->CP0_Status & (1 << CP0St_ERL))
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
- if (env->hflags & MIPS_HFLAG_DM)
+ }
+ if (env->hflags & MIPS_HFLAG_DM) {
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
+ }
qemu_log("\n");
}
}
@@ -2489,17 +2564,25 @@ static void debug_post_eret(CPUMIPSState *env)
if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
env->active_tc.PC, env->CP0_EPC);
- if (env->CP0_Status & (1 << CP0St_ERL))
+ if (env->CP0_Status & (1 << CP0St_ERL)) {
qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
- if (env->hflags & MIPS_HFLAG_DM)
+ }
+ if (env->hflags & MIPS_HFLAG_DM) {
qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
+ }
switch (cpu_mmu_index(env, false)) {
case 3:
qemu_log(", ERL\n");
break;
- case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
- case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
- case MIPS_HFLAG_KM: qemu_log("\n"); break;
+ case MIPS_HFLAG_UM:
+ qemu_log(", UM\n");
+ break;
+ case MIPS_HFLAG_SM:
+ qemu_log(", SM\n");
+ break;
+ case MIPS_HFLAG_KM:
+ qemu_log("\n");
+ break;
default:
cpu_abort(env_cpu(env), "Invalid MMU mode!\n");
break;
@@ -2609,8 +2692,9 @@ void helper_pmon(CPUMIPSState *env, int function)
function /= 2;
switch (function) {
case 2: /* TODO: char inbyte(int waitflag); */
- if (env->active_tc.gpr[4] == 0)
+ if (env->active_tc.gpr[4] == 0) {
env->active_tc.gpr[2] = -1;
+ }
/* Fall through */
case 11: /* TODO: char inbyte (void); */
env->active_tc.gpr[2] = -1;
@@ -2636,8 +2720,10 @@ void helper_wait(CPUMIPSState *env)
cs->halted = 1;
cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
- /* Last instruction in the block, PC was updated before
- - no need to recover PC and icount */
+ /*
+ * Last instruction in the block, PC was updated before
+ * - no need to recover PC and icount.
+ */
raise_exception(env, EXCP_HLT);
}
@@ -2731,13 +2817,15 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
}
break;
case 25:
- arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
+ arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) |
+ ((env->active_fpu.fcr31 >> 23) & 0x1);
break;
case 26:
arg1 = env->active_fpu.fcr31 & 0x0003f07c;
break;
case 28:
- arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
+ arg1 = (env->active_fpu.fcr31 & 0x00000f83) |
+ ((env->active_fpu.fcr31 >> 22) & 0x4);
break;
default:
arg1 = (int32_t)env->active_fpu.fcr31;
@@ -2802,19 +2890,24 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
if ((env->insn_flags & ISA_MIPS32R6) || (arg1 & 0xffffff00)) {
return;
}
- env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
- ((arg1 & 0x1) << 23);
+ env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) |
+ ((arg1 & 0xfe) << 24) |
+ ((arg1 & 0x1) << 23);
break;
case 26:
- if (arg1 & 0x007c0000)
+ if (arg1 & 0x007c0000) {
return;
- env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
+ }
+ env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) |
+ (arg1 & 0x0003f07c);
break;
case 28:
- if (arg1 & 0x007c0000)
+ if (arg1 & 0x007c0000) {
return;
- env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
- ((arg1 & 0x4) << 22);
+ }
+ env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) |
+ (arg1 & 0x00000f83) |
+ ((arg1 & 0x4) << 22);
break;
case 31:
env->active_fpu.fcr31 = (arg1 & env->active_fpu.fcr31_rw_bitmask) |
@@ -2828,8 +2921,10 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
}
restore_fp_status(env);
set_float_exception_flags(0, &env->active_fpu.fp_status);
- if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
+ if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) &
+ GET_FP_CAUSE(env->active_fpu.fcr31)) {
do_raise_exception(env, EXCP_FPE, GETPC());
+ }
}
int ieee_ex_to_mips(int xcpt)
@@ -2857,7 +2952,8 @@ int ieee_ex_to_mips(int xcpt)
static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
{
- int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
+ int tmp = ieee_ex_to_mips(get_float_exception_flags(
+ &env->active_fpu.fp_status));
SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
@@ -2872,10 +2968,12 @@ static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
}
}
-/* Float support.
- Single precition routines have a "s" suffix, double precision a
- "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
- paired single lower "pl", paired single upper "pu". */
+/*
+ * Float support.
+ * Single precition routines have a "s" suffix, double precision a
+ * "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
+ * paired single lower "pl", paired single upper "pu".
+ */
/* unary operations, modifying fp status */
uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
@@ -3056,7 +3154,8 @@ uint64_t helper_float_round_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3071,7 +3170,8 @@ uint64_t helper_float_round_l_s(CPUMIPSState *env, uint32_t fst0)
{
uint64_t dt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3086,7 +3186,8 @@ uint32_t helper_float_round_w_d(CPUMIPSState *env, uint64_t fdt0)
{
uint32_t wt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3101,7 +3202,8 @@ uint32_t helper_float_round_w_s(CPUMIPSState *env, uint32_t fst0)
{
uint32_t wt2;
- set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
+ set_float_rounding_mode(float_round_nearest_even,
+ &env->active_fpu.fp_status);
wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
restore_rounding_mode(env);
if (get_float_exception_flags(&env->active_fpu.fp_status)
@@ -3116,7 +3218,8 @@ uint64_t helper_float_trunc_l_d(CPUMIPSState *env, uint64_t fdt0)
{
uint64_t dt2;
- dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
+ dt2 = float64_to_int64_round_to_zero(fdt0,
+ &env->active_fpu.fp_status);
if (get_float_exception_flags(&env->active_fpu.fp_status)
& (float_flag_invalid | float_flag_overflow)) {
dt2 = FP_TO_INT64_OVERFLOW;
@@ -3697,7 +3800,8 @@ uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
uint32_t fst2;
uint32_t fsth2;
- fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
+ fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF,
+ &env->active_fpu.fp_status);
fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
@@ -3737,8 +3841,8 @@ uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
}
#define FLOAT_RINT(name, bits) \
-uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
- uint ## bits ## _t fs) \
+uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
+ uint ## bits ## _t fs) \
{ \
uint ## bits ## _t fdret; \
\
@@ -3763,8 +3867,8 @@ FLOAT_RINT(rint_d, 64)
#define FLOAT_CLASS_POSITIVE_ZERO 0x200
#define FLOAT_CLASS(name, bits) \
-uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
- float_status *status) \
+uint ## bits ## _t float_ ## name(uint ## bits ## _t arg, \
+ float_status *status) \
{ \
if (float ## bits ## _is_signaling_nan(arg, status)) { \
return FLOAT_CLASS_SIGNALING_NAN; \
@@ -3793,8 +3897,8 @@ uint ## bits ## _t float_ ## name (uint ## bits ## _t arg, \
} \
} \
\
-uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
- uint ## bits ## _t arg) \
+uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
+ uint ## bits ## _t arg) \
{ \
return float_ ## name(arg, &env->active_fpu.fp_status); \
}
@@ -3810,7 +3914,7 @@ uint64_t helper_float_ ## name ## _d(CPUMIPSState *env, \
{ \
uint64_t dt2; \
\
- dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status); \
+ dt2 = float64_ ## name(fdt0, fdt1, &env->active_fpu.fp_status);\
update_fcr31(env, GETPC()); \
return dt2; \
} \
@@ -3820,7 +3924,7 @@ uint32_t helper_float_ ## name ## _s(CPUMIPSState *env, \
{ \
uint32_t wt2; \
\
- wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
+ wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status);\
update_fcr31(env, GETPC()); \
return wt2; \
} \
@@ -3836,8 +3940,8 @@ uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env, \
uint32_t wt2; \
uint32_t wth2; \
\
- wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status); \
- wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status); \
+ wt2 = float32_ ## name(fst0, fst1, &env->active_fpu.fp_status); \
+ wth2 = float32_ ## name(fsth0, fsth1, &env->active_fpu.fp_status); \
update_fcr31(env, GETPC()); \
return ((uint64_t)wth2 << 32) | wt2; \
}
@@ -3852,7 +3956,8 @@ FLOAT_BINOP(div)
uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
- fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
+ fdt2 = float64_chs(float64_sub(fdt2, float64_one,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fdt2;
}
@@ -3860,7 +3965,8 @@ uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
{
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_sub(fst2, float32_one,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fst2;
}
@@ -3874,8 +3980,10 @@ uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
- fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_sub(fst2, float32_one,
+ &env->active_fpu.fp_status));
+ fsth2 = float32_chs(float32_sub(fsth2, float32_one,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -3884,7 +3992,8 @@ uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
{
fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
- fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
+ fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fdt2;
}
@@ -3893,7 +4002,8 @@ uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
{
fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return fst2;
}
@@ -3909,8 +4019,10 @@ uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
- fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
- fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
+ fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32,
+ &env->active_fpu.fp_status));
+ fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32,
+ &env->active_fpu.fp_status));
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -3924,8 +4036,8 @@ uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
uint32_t fst2;
uint32_t fsth2;
- fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
+ fst2 = float32_add(fst0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_add(fst1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
@@ -3939,16 +4051,16 @@ uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
uint32_t fst2;
uint32_t fsth2;
- fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
- fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
+ fst2 = float32_mul(fst0, fsth0, &env->active_fpu.fp_status);
+ fsth2 = float32_mul(fst1, fsth1, &env->active_fpu.fp_status);
update_fcr31(env, GETPC());
return ((uint64_t)fsth2 << 32) | fst2;
}
#define FLOAT_MINMAX(name, bits, minmaxfunc) \
-uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
- uint ## bits ## _t fs, \
- uint ## bits ## _t ft) \
+uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
+ uint ## bits ## _t fs, \
+ uint ## bits ## _t ft) \
{ \
uint ## bits ## _t fdret; \
\
@@ -4026,10 +4138,10 @@ FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
#undef FLOAT_FMA
#define FLOAT_FMADDSUB(name, bits, muladd_arg) \
-uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env, \
- uint ## bits ## _t fs, \
- uint ## bits ## _t ft, \
- uint ## bits ## _t fd) \
+uint ## bits ## _t helper_float_ ## name(CPUMIPSState *env, \
+ uint ## bits ## _t fs, \
+ uint ## bits ## _t ft, \
+ uint ## bits ## _t fd) \
{ \
uint ## bits ## _t fdret; \
\
@@ -4072,26 +4184,58 @@ void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
CLEAR_FP_COND(cc, env->active_fpu); \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered_quiet() is still called. */
-FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
-FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered() is still called. */
-FOP_COND_D(sf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
-FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(lt, float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(le, float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
-FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status) || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered_quiet() is still called.
+ */
+FOP_COND_D(f, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_D(un, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status))
+FOP_COND_D(eq, float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered() is still called.
+ */
+FOP_COND_D(sf, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_D(ngle, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status))
+FOP_COND_D(seq, float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ngl, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(lt, float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(nge, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(le, float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status))
+FOP_COND_D(ngt, float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status))
#define FOP_COND_S(op, cond) \
void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
@@ -4119,26 +4263,58 @@ void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
CLEAR_FP_COND(cc, env->active_fpu); \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered_quiet() is still called. */
-FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_COND_S(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
-FOP_COND_S(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered() is still called. */
-FOP_COND_S(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
-FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(le, float32_le(fst0, fst1, &env->active_fpu.fp_status))
-FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered_quiet() is still called.
+ */
+FOP_COND_S(f, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_S(un, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status))
+FOP_COND_S(eq, float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(olt, float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ole, float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered() is still called.
+ */
+FOP_COND_S(sf, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_S(ngle, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status))
+FOP_COND_S(seq, float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ngl, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(lt, float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(nge, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(le, float32_le(fst0, fst1,
+ &env->active_fpu.fp_status))
+FOP_COND_S(ngt, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status))
#define FOP_COND_PS(op, condl, condh) \
void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
@@ -4184,47 +4360,107 @@ void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0, \
CLEAR_FP_COND(cc + 1, env->active_fpu); \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered_quiet() is still called. */
-FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
- (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
-FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
-FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status) || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered() is still called. */
-FOP_COND_PS(sf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
- (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
-FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
-FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
- float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(lt, float32_lt(fst0, fst1, &env->active_fpu.fp_status),
- float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(le, float32_le(fst0, fst1, &env->active_fpu.fp_status),
- float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
-FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status) || float32_le(fst0, fst1, &env->active_fpu.fp_status),
- float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status) || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered_quiet() is still called.
+ */
+FOP_COND_PS(f, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status), 0),
+ (float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_PS(un, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(eq, float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_eq_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_lt_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ole, float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_le_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered_quiet(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered() is still called.
+ */
+FOP_COND_PS(sf, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status), 0),
+ (float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status), 0))
+FOP_COND_PS(ngle, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(seq, float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_eq(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ngl, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(lt, float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_lt(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(nge, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(le, float32_le(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_le(fsth0, fsth1,
+ &env->active_fpu.fp_status))
+FOP_COND_PS(ngt, float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status),
+ float32_unordered(fsth1, fsth0,
+ &env->active_fpu.fp_status)
+ || float32_le(fsth0, fsth1,
+ &env->active_fpu.fp_status))
/* R6 compare operations */
#define FOP_CONDN_D(op, cond) \
-uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
- uint64_t fdt1) \
+uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0, \
+ uint64_t fdt1) \
{ \
uint64_t c; \
c = cond; \
@@ -4236,50 +4472,90 @@ uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0, \
} \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered_quiet() is still called. */
-FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
-FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float64_unordered() is still called. */
-FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
-FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sle, (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sor, (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
-FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
- || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered_quiet() is still called.
+ */
+FOP_CONDN_D(af, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_D(un, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(eq, (float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(lt, (float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(le, (float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float64_unordered() is still called.\
+ */
+FOP_CONDN_D(saf, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_D(sun, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(seq, (float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_eq(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(slt, (float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sle, (float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(or, (float64_le_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(une, (float64_unordered_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(ne, (float64_lt_quiet(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt_quiet(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sor, (float64_le(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_le(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_D(sne, (float64_lt(fdt1, fdt0,
+ &env->active_fpu.fp_status)
+ || float64_lt(fdt0, fdt1,
+ &env->active_fpu.fp_status)))
#define FOP_CONDN_S(op, cond) \
-uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
- uint32_t fst1) \
+uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0, \
+ uint32_t fst1) \
{ \
uint64_t c; \
c = cond; \
@@ -4291,46 +4567,86 @@ uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0, \
} \
}
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered_quiet() is still called. */
-FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
-FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-/* NOTE: the comma operator will make "cond" to eval to false,
- * but float32_unordered() is still called. */
-FOP_CONDN_S(saf, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
-FOP_CONDN_S(sun, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
-FOP_CONDN_S(seq, (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(slt, (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sle, (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sor, (float32_le(fst1, fst0, &env->active_fpu.fp_status)
- || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
-FOP_CONDN_S(sne, (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
- || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered_quiet() is still called.
+ */
+FOP_CONDN_S(af, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_S(un, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(eq, (float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ueq, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(lt, (float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ult, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(le, (float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ule, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+/*
+ * NOTE: the comma operator will make "cond" to eval to false,
+ * but float32_unordered() is still called.
+ */
+FOP_CONDN_S(saf, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status), 0))
+FOP_CONDN_S(sun, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(seq, (float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_eq(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(slt, (float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sult, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sle, (float32_le(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sule, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(or, (float32_le_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(une, (float32_unordered_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(ne, (float32_lt_quiet(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt_quiet(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sor, (float32_le(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_le(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sune, (float32_unordered(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
+FOP_CONDN_S(sne, (float32_lt(fst1, fst0,
+ &env->active_fpu.fp_status)
+ || float32_lt(fst0, fst1,
+ &env->active_fpu.fp_status)))
/* MSA */
/* Data format min and max values */
@@ -4522,7 +4838,7 @@ void helper_msa_ld_d(CPUMIPSState *env, uint32_t wd,
}
#define MSA_PAGESPAN(x) \
- ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN/8 - 1) >= TARGET_PAGE_SIZE)
+ ((((x) & ~TARGET_PAGE_MASK) + MSA_WRLEN / 8 - 1) >= TARGET_PAGE_SIZE)
static inline void ensure_writable_pages(CPUMIPSState *env,
target_ulong addr,
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 03/12] MAINTAINERS: Update mail address of Aleksandar Rikalo
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 01/12] target/mips: Clean up helper.c Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 02/12] target/mips: Clean up op_helper.c Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 04/12] target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D> Aleksandar Markovic
` (12 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Aleksandar Rikalo wishes to change his primary mail address for QEMU.
Some minor line order is corrected in .mailmap to be alphabetical,
too.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
.mailmap | 5 +++--
MAINTAINERS | 18 +++++++++---------
2 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/.mailmap b/.mailmap
index 0756a0b..3816e4e 100644
--- a/.mailmap
+++ b/.mailmap
@@ -39,10 +39,11 @@ Julia Suvorova <jusual@mail.ru> Julia Suvorova via Qemu-devel <qemu-devel@nongnu
Justin Terry (VM) <juterry@microsoft.com> Justin Terry (VM) via Qemu-devel <qemu-devel@nongnu.org>
# Next, replace old addresses by a more recent one.
-Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
-James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@mips.com>
Aleksandar Markovic <amarkovic@wavecomp.com> <aleksandar.markovic@imgtec.com>
+Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com> <arikalo@wavecomp.com>
+Anthony Liguori <anthony@codemonkey.ws> Anthony Liguori <aliguori@us.ibm.com>
+James Hogan <jhogan@kernel.org> <james.hogan@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@mips.com>
Paul Burton <pburton@wavecomp.com> <paul.burton@imgtec.com>
Paul Burton <pburton@wavecomp.com> <paul@archlinuxmips.org>
diff --git a/MAINTAINERS b/MAINTAINERS
index 3ca8148..4964fbb 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -208,7 +208,7 @@ F: disas/microblaze.c
MIPS TCG CPUs
M: Aurelien Jarno <aurelien@aurel32.net>
M: Aleksandar Markovic <amarkovic@wavecomp.com>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: target/mips/
F: default-configs/*mips*
@@ -363,7 +363,7 @@ F: target/arm/kvm.c
MIPS KVM CPUs
M: James Hogan <jhogan@kernel.org>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: target/mips/kvm.c
@@ -934,7 +934,7 @@ MIPS Machines
-------------
Jazz
M: Hervé Poussineau <hpoussin@reactos.org>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/mips/mips_jazz.c
F: hw/display/jazz_led.c
@@ -942,7 +942,7 @@ F: hw/dma/rc4030.c
Malta
M: Aurelien Jarno <aurelien@aurel32.net>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/mips/mips_malta.c
F: hw/mips/gt64xxx_pci.c
@@ -950,20 +950,20 @@ F: tests/acceptance/linux_ssh_mips_malta.py
Mipssim
M: Aleksandar Markovic <amarkovic@wavecomp.com>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Odd Fixes
F: hw/mips/mips_mipssim.c
F: hw/net/mipsnet.c
R4000
M: Aurelien Jarno <aurelien@aurel32.net>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/mips/mips_r4k.c
Fulong 2E
M: Aleksandar Markovic <amarkovic@wavecomp.com>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Odd Fixes
F: hw/mips/mips_fulong2e.c
F: hw/isa/vt82c686.c
@@ -972,7 +972,7 @@ F: include/hw/isa/vt82c686.h
Boston
M: Paul Burton <pburton@wavecomp.com>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: hw/core/loader-fit.c
F: hw/mips/boston.c
@@ -2348,7 +2348,7 @@ F: disas/i386.c
MIPS TCG target
M: Aurelien Jarno <aurelien@aurel32.net>
-R: Aleksandar Rikalo <arikalo@wavecomp.com>
+R: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
S: Maintained
F: tcg/mips/
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 04/12] target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (2 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 03/12] MAINTAINERS: Update mail address of Aleksandar Rikalo Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 05/12] target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D> Aleksandar Markovic
` (11 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 11 +++-
target/mips/msa_helper.c | 163 ++++++++++++++++++++++++++++++++++++++++++-----
target/mips/translate.c | 38 +++++++++--
3 files changed, 187 insertions(+), 25 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index d615c83..cef4de6 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -877,6 +877,15 @@ DEF_HELPER_4(msa_div_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_div_u_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_div_u_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_w, void, env, i32, i32, i32)
@@ -940,8 +949,6 @@ DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_max_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_min_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index a2052ba..3eb0ab1 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1736,7 +1736,152 @@ void helper_msa_div_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Max Min group helpers here */
+static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
+ uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
+ return abs_arg1 > abs_arg2 ? arg1 : arg2;
+}
+
+void helper_msa_max_a_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_max_a_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_max_a_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_max_a_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_max_a_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_max_a_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_max_a_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_max_a_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_max_a_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_max_a_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_max_a_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_max_a_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_max_a_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_max_a_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_max_a_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_max_a_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_max_a_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_max_a_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_max_a_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_max_a_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_max_a_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_max_a_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_max_a_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_max_a_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_max_a_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_max_a_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_max_a_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_max_a_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_max_a_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_max_a_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_max_a_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_max_a_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_max_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_max_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
+ uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
+ return abs_arg1 < abs_arg2 ? arg1 : arg2;
+}
+
+void helper_msa_min_a_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_min_a_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_min_a_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_min_a_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_min_a_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_min_a_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_min_a_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_min_a_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_min_a_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_min_a_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_min_a_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_min_a_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_min_a_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_min_a_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_min_a_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_min_a_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_min_a_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_min_a_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_min_a_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_min_a_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_min_a_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_min_a_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_min_a_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_min_a_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_min_a_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_min_a_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_min_a_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_min_a_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_min_a_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_min_a_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_min_a_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_min_a_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_min_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_min_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
/*
@@ -2456,20 +2601,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_max_a_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
- uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
- return abs_arg1 > abs_arg2 ? arg1 : arg2;
-}
-
-static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
- uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
- return abs_arg1 < abs_arg2 ? arg1 : arg2;
-}
-
static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
@@ -2773,8 +2904,6 @@ MSA_BINOP_DF(max_s)
MSA_BINOP_DF(max_u)
MSA_BINOP_DF(min_s)
MSA_BINOP_DF(min_u)
-MSA_BINOP_DF(max_a)
-MSA_BINOP_DF(min_a)
MSA_BINOP_DF(add_a)
MSA_BINOP_DF(adds_a)
MSA_BINOP_DF(adds_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 5039716..8e26548 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28642,6 +28642,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MAX_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MIN_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_MOD_S_df:
switch (df) {
case DF_BYTE:
@@ -28767,15 +28799,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_ILVR_df:
gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MAX_A_df:
- gen_helper_msa_max_a_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ILVEV_df:
gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MIN_A_df:
- gen_helper_msa_min_a_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ILVOD_df:
gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 05/12] target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (3 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 04/12] target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 06/12] target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D> Aleksandar Markovic
` (10 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 20 ++-
target/mips/msa_helper.c | 320 ++++++++++++++++++++++++++++++++++++++++++-----
target/mips/translate.c | 76 +++++++++--
3 files changed, 372 insertions(+), 44 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index cef4de6..6419bb8 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -881,10 +881,26 @@ DEF_HELPER_4(msa_max_a_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_max_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_max_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_min_a_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_min_u_d, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_u_h, void, env, i32, i32, i32)
@@ -945,10 +961,6 @@ DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_max_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_max_u_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_min_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_min_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 3eb0ab1..65df15d 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1810,6 +1810,152 @@ void helper_msa_max_a_d(CPUMIPSState *env,
}
+static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return arg1 > arg2 ? arg1 : arg2;
+}
+
+void helper_msa_max_s_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_max_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_max_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_max_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_max_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_max_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_max_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_max_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_max_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_max_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_max_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_max_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_max_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_max_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_max_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_max_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_max_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_max_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_max_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_max_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_max_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_max_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_max_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_max_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_max_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_max_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_max_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_max_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_max_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_max_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_max_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_max_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_max_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_max_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_arg2 = UNSIGNED(arg2, df);
+ return u_arg1 > u_arg2 ? arg1 : arg2;
+}
+
+void helper_msa_max_u_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_max_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_max_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_max_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_max_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_max_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_max_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_max_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_max_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_max_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_max_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_max_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_max_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_max_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_max_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_max_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_max_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_max_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_max_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_max_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_max_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_max_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_max_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_max_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_max_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_max_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_max_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_max_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_max_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_max_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_max_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_max_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_max_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_max_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
static inline int64_t msa_min_a_df(uint32_t df, int64_t arg1, int64_t arg2)
{
uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
@@ -1884,6 +2030,152 @@ void helper_msa_min_a_d(CPUMIPSState *env,
}
+static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return arg1 < arg2 ? arg1 : arg2;
+}
+
+void helper_msa_min_s_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_min_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_min_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_min_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_min_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_min_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_min_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_min_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_min_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_min_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_min_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_min_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_min_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_min_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_min_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_min_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_min_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_min_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_min_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_min_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_min_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_min_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_min_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_min_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_min_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_min_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_min_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_min_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_min_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_min_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_min_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_min_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_min_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_min_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_arg2 = UNSIGNED(arg2, df);
+ return u_arg1 < u_arg2 ? arg1 : arg2;
+}
+
+void helper_msa_min_u_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_min_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_min_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_min_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_min_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_min_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_min_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_min_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_min_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_min_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_min_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_min_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_min_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_min_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_min_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_min_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_min_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_min_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_min_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_min_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_min_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_min_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_min_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_min_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_min_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_min_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_min_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_min_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_min_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_min_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_min_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_min_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_min_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_min_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Int Modulo
* ----------
@@ -2354,30 +2646,6 @@ static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
return arg1 - arg2;
}
-static inline int64_t msa_max_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return arg1 > arg2 ? arg1 : arg2;
-}
-
-static inline int64_t msa_max_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_arg2 = UNSIGNED(arg2, df);
- return u_arg1 > u_arg2 ? arg1 : arg2;
-}
-
-static inline int64_t msa_min_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return arg1 < arg2 ? arg1 : arg2;
-}
-
-static inline int64_t msa_min_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_arg2 = UNSIGNED(arg2, df);
- return u_arg1 < u_arg2 ? arg1 : arg2;
-}
-
#define MSA_BINOP_IMM_DF(helper, func) \
void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, \
uint32_t wd, uint32_t ws, int32_t u5) \
@@ -2900,10 +3168,6 @@ MSA_BINOP_DF(sra)
MSA_BINOP_DF(srl)
MSA_BINOP_DF(addv)
MSA_BINOP_DF(subv)
-MSA_BINOP_DF(max_s)
-MSA_BINOP_DF(max_u)
-MSA_BINOP_DF(min_s)
-MSA_BINOP_DF(min_u)
MSA_BINOP_DF(add_a)
MSA_BINOP_DF(adds_a)
MSA_BINOP_DF(adds_s)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8e26548..7a35c26 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28658,6 +28658,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MAX_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MAX_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_max_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_max_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_max_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_max_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_MIN_A_df:
switch (df) {
case DF_BYTE:
@@ -28674,6 +28706,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_MIN_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_MIN_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_min_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_min_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_min_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_min_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_MOD_S_df:
switch (df) {
case DF_BYTE:
@@ -28751,9 +28815,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SRL_df:
gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MAX_S_df:
- gen_helper_msa_max_s_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ADDS_S_df:
gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28769,9 +28830,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SRLR_df:
gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MAX_U_df:
- gen_helper_msa_max_u_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ADDS_U_df:
gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28781,18 +28839,12 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_PCKOD_df:
gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MIN_S_df:
- gen_helper_msa_min_s_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ASUB_S_df:
gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
break;
case OPC_ILVL_df:
gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_MIN_U_df:
- gen_helper_msa_min_u_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ASUB_U_df:
gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 06/12] target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (4 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 05/12] target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 07/12] target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D> Aleksandar Markovic
` (9 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 21 +-
target/mips/msa_helper.c | 768 +++++++++++++++++++++++++----------------------
target/mips/translate.c | 76 ++++-
3 files changed, 496 insertions(+), 369 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 6419bb8..f3df187 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -912,6 +912,23 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvod_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvl_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_ilvr_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_and_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
@@ -984,10 +1001,6 @@ DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvl_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvev_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_ilvod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 65df15d..499fcde 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2432,7 +2432,421 @@ void helper_msa_mod_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Interleave group helpers here */
+
+void helper_msa_ilvev_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[8] = pws->b[9];
+ pwd->b[9] = pwt->b[9];
+ pwd->b[10] = pws->b[11];
+ pwd->b[11] = pwt->b[11];
+ pwd->b[12] = pws->b[13];
+ pwd->b[13] = pwt->b[13];
+ pwd->b[14] = pws->b[15];
+ pwd->b[15] = pwt->b[15];
+ pwd->b[0] = pws->b[1];
+ pwd->b[1] = pwt->b[1];
+ pwd->b[2] = pws->b[3];
+ pwd->b[3] = pwt->b[3];
+ pwd->b[4] = pws->b[5];
+ pwd->b[5] = pwt->b[5];
+ pwd->b[6] = pws->b[7];
+ pwd->b[7] = pwt->b[7];
+#else
+ pwd->b[15] = pws->b[14];
+ pwd->b[14] = pwt->b[14];
+ pwd->b[13] = pws->b[12];
+ pwd->b[12] = pwt->b[12];
+ pwd->b[11] = pws->b[10];
+ pwd->b[10] = pwt->b[10];
+ pwd->b[9] = pws->b[8];
+ pwd->b[8] = pwt->b[8];
+ pwd->b[7] = pws->b[6];
+ pwd->b[6] = pwt->b[6];
+ pwd->b[5] = pws->b[4];
+ pwd->b[4] = pwt->b[4];
+ pwd->b[3] = pws->b[2];
+ pwd->b[2] = pwt->b[2];
+ pwd->b[1] = pws->b[0];
+ pwd->b[0] = pwt->b[0];
+#endif
+}
+
+void helper_msa_ilvev_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[4] = pws->h[5];
+ pwd->h[5] = pwt->h[5];
+ pwd->h[6] = pws->h[7];
+ pwd->h[7] = pwt->h[7];
+ pwd->h[0] = pws->h[1];
+ pwd->h[1] = pwt->h[1];
+ pwd->h[2] = pws->h[3];
+ pwd->h[3] = pwt->h[3];
+#else
+ pwd->h[7] = pws->h[6];
+ pwd->h[6] = pwt->h[6];
+ pwd->h[5] = pws->h[4];
+ pwd->h[4] = pwt->h[4];
+ pwd->h[3] = pws->h[2];
+ pwd->h[2] = pwt->h[2];
+ pwd->h[1] = pws->h[0];
+ pwd->h[0] = pwt->h[0];
+#endif
+}
+
+void helper_msa_ilvev_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[2] = pws->w[3];
+ pwd->w[3] = pwt->w[3];
+ pwd->w[0] = pws->w[1];
+ pwd->w[1] = pwt->w[1];
+#else
+ pwd->w[3] = pws->w[2];
+ pwd->w[2] = pwt->w[2];
+ pwd->w[1] = pws->w[0];
+ pwd->w[0] = pwt->w[0];
+#endif
+}
+
+void helper_msa_ilvev_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[1] = pws->d[0];
+ pwd->d[0] = pwt->d[0];
+}
+
+
+void helper_msa_ilvod_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[7] = pwt->b[6];
+ pwd->b[6] = pws->b[6];
+ pwd->b[5] = pwt->b[4];
+ pwd->b[4] = pws->b[4];
+ pwd->b[3] = pwt->b[2];
+ pwd->b[2] = pws->b[2];
+ pwd->b[1] = pwt->b[0];
+ pwd->b[0] = pws->b[0];
+ pwd->b[15] = pwt->b[14];
+ pwd->b[14] = pws->b[14];
+ pwd->b[13] = pwt->b[12];
+ pwd->b[12] = pws->b[12];
+ pwd->b[11] = pwt->b[10];
+ pwd->b[10] = pws->b[10];
+ pwd->b[9] = pwt->b[8];
+ pwd->b[8] = pws->b[8];
+#else
+ pwd->b[0] = pwt->b[1];
+ pwd->b[1] = pws->b[1];
+ pwd->b[2] = pwt->b[3];
+ pwd->b[3] = pws->b[3];
+ pwd->b[4] = pwt->b[5];
+ pwd->b[5] = pws->b[5];
+ pwd->b[6] = pwt->b[7];
+ pwd->b[7] = pws->b[7];
+ pwd->b[8] = pwt->b[9];
+ pwd->b[9] = pws->b[9];
+ pwd->b[10] = pwt->b[11];
+ pwd->b[11] = pws->b[11];
+ pwd->b[12] = pwt->b[13];
+ pwd->b[13] = pws->b[13];
+ pwd->b[14] = pwt->b[15];
+ pwd->b[15] = pws->b[15];
+#endif
+}
+
+void helper_msa_ilvod_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[3] = pwt->h[2];
+ pwd->h[2] = pws->h[2];
+ pwd->h[1] = pwt->h[0];
+ pwd->h[0] = pws->h[0];
+ pwd->h[7] = pwt->h[6];
+ pwd->h[6] = pws->h[6];
+ pwd->h[5] = pwt->h[4];
+ pwd->h[4] = pws->h[4];
+#else
+ pwd->h[0] = pwt->h[1];
+ pwd->h[1] = pws->h[1];
+ pwd->h[2] = pwt->h[3];
+ pwd->h[3] = pws->h[3];
+ pwd->h[4] = pwt->h[5];
+ pwd->h[5] = pws->h[5];
+ pwd->h[6] = pwt->h[7];
+ pwd->h[7] = pws->h[7];
+#endif
+}
+
+void helper_msa_ilvod_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[1] = pwt->w[0];
+ pwd->w[0] = pws->w[0];
+ pwd->w[3] = pwt->w[2];
+ pwd->w[2] = pws->w[2];
+#else
+ pwd->w[0] = pwt->w[1];
+ pwd->w[1] = pws->w[1];
+ pwd->w[2] = pwt->w[3];
+ pwd->w[3] = pws->w[3];
+#endif
+}
+
+void helper_msa_ilvod_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = pwt->d[1];
+ pwd->d[1] = pws->d[1];
+}
+
+
+void helper_msa_ilvl_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[7] = pwt->b[15];
+ pwd->b[6] = pws->b[15];
+ pwd->b[5] = pwt->b[14];
+ pwd->b[4] = pws->b[14];
+ pwd->b[3] = pwt->b[13];
+ pwd->b[2] = pws->b[13];
+ pwd->b[1] = pwt->b[12];
+ pwd->b[0] = pws->b[12];
+ pwd->b[15] = pwt->b[11];
+ pwd->b[14] = pws->b[11];
+ pwd->b[13] = pwt->b[10];
+ pwd->b[12] = pws->b[10];
+ pwd->b[11] = pwt->b[9];
+ pwd->b[10] = pws->b[9];
+ pwd->b[9] = pwt->b[8];
+ pwd->b[8] = pws->b[8];
+#else
+ pwd->b[0] = pwt->b[8];
+ pwd->b[1] = pws->b[8];
+ pwd->b[2] = pwt->b[9];
+ pwd->b[3] = pws->b[9];
+ pwd->b[4] = pwt->b[10];
+ pwd->b[5] = pws->b[10];
+ pwd->b[6] = pwt->b[11];
+ pwd->b[7] = pws->b[11];
+ pwd->b[8] = pwt->b[12];
+ pwd->b[9] = pws->b[12];
+ pwd->b[10] = pwt->b[13];
+ pwd->b[11] = pws->b[13];
+ pwd->b[12] = pwt->b[14];
+ pwd->b[13] = pws->b[14];
+ pwd->b[14] = pwt->b[15];
+ pwd->b[15] = pws->b[15];
+#endif
+}
+
+void helper_msa_ilvl_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[3] = pwt->h[7];
+ pwd->h[2] = pws->h[7];
+ pwd->h[1] = pwt->h[6];
+ pwd->h[0] = pws->h[6];
+ pwd->h[7] = pwt->h[5];
+ pwd->h[6] = pws->h[5];
+ pwd->h[5] = pwt->h[4];
+ pwd->h[4] = pws->h[4];
+#else
+ pwd->h[0] = pwt->h[4];
+ pwd->h[1] = pws->h[4];
+ pwd->h[2] = pwt->h[5];
+ pwd->h[3] = pws->h[5];
+ pwd->h[4] = pwt->h[6];
+ pwd->h[5] = pws->h[6];
+ pwd->h[6] = pwt->h[7];
+ pwd->h[7] = pws->h[7];
+#endif
+}
+
+void helper_msa_ilvl_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[1] = pwt->w[3];
+ pwd->w[0] = pws->w[3];
+ pwd->w[3] = pwt->w[2];
+ pwd->w[2] = pws->w[2];
+#else
+ pwd->w[0] = pwt->w[2];
+ pwd->w[1] = pws->w[2];
+ pwd->w[2] = pwt->w[3];
+ pwd->w[3] = pws->w[3];
+#endif
+}
+
+void helper_msa_ilvl_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = pwt->d[1];
+ pwd->d[1] = pws->d[1];
+}
+
+
+void helper_msa_ilvr_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[8] = pws->b[0];
+ pwd->b[9] = pwt->b[0];
+ pwd->b[10] = pws->b[1];
+ pwd->b[11] = pwt->b[1];
+ pwd->b[12] = pws->b[2];
+ pwd->b[13] = pwt->b[2];
+ pwd->b[14] = pws->b[3];
+ pwd->b[15] = pwt->b[3];
+ pwd->b[0] = pws->b[4];
+ pwd->b[1] = pwt->b[4];
+ pwd->b[2] = pws->b[5];
+ pwd->b[3] = pwt->b[5];
+ pwd->b[4] = pws->b[6];
+ pwd->b[5] = pwt->b[6];
+ pwd->b[6] = pws->b[7];
+ pwd->b[7] = pwt->b[7];
+#else
+ pwd->b[15] = pws->b[7];
+ pwd->b[14] = pwt->b[7];
+ pwd->b[13] = pws->b[6];
+ pwd->b[12] = pwt->b[6];
+ pwd->b[11] = pws->b[5];
+ pwd->b[10] = pwt->b[5];
+ pwd->b[9] = pws->b[4];
+ pwd->b[8] = pwt->b[4];
+ pwd->b[7] = pws->b[3];
+ pwd->b[6] = pwt->b[3];
+ pwd->b[5] = pws->b[2];
+ pwd->b[4] = pwt->b[2];
+ pwd->b[3] = pws->b[1];
+ pwd->b[2] = pwt->b[1];
+ pwd->b[1] = pws->b[0];
+ pwd->b[0] = pwt->b[0];
+#endif
+}
+
+void helper_msa_ilvr_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[4] = pws->h[0];
+ pwd->h[5] = pwt->h[0];
+ pwd->h[6] = pws->h[1];
+ pwd->h[7] = pwt->h[1];
+ pwd->h[0] = pws->h[2];
+ pwd->h[1] = pwt->h[2];
+ pwd->h[2] = pws->h[3];
+ pwd->h[3] = pwt->h[3];
+#else
+ pwd->h[7] = pws->h[3];
+ pwd->h[6] = pwt->h[3];
+ pwd->h[5] = pws->h[2];
+ pwd->h[4] = pwt->h[2];
+ pwd->h[3] = pws->h[1];
+ pwd->h[2] = pwt->h[1];
+ pwd->h[1] = pws->h[0];
+ pwd->h[0] = pwt->h[0];
+#endif
+}
+
+void helper_msa_ilvr_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[2] = pws->w[0];
+ pwd->w[3] = pwt->w[0];
+ pwd->w[0] = pws->w[1];
+ pwd->w[1] = pwt->w[1];
+#else
+ pwd->w[3] = pws->w[1];
+ pwd->w[2] = pwt->w[1];
+ pwd->w[1] = pws->w[0];
+ pwd->w[0] = pwt->w[0];
+#endif
+}
+
+void helper_msa_ilvr_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[1] = pws->d[0];
+ pwd->d[0] = pwt->d[0];
+}
/*
@@ -3522,358 +3936,6 @@ MSA_FN_DF(vshf_df)
#undef MSA_FN_DF
-void helper_msa_ilvev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- wr_t *pws = &(env->active_fpu.fpr[ws].wr);
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
-
- switch (df) {
- case DF_BYTE:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->b[8] = pws->b[9];
- pwd->b[9] = pwt->b[9];
- pwd->b[10] = pws->b[11];
- pwd->b[11] = pwt->b[11];
- pwd->b[12] = pws->b[13];
- pwd->b[13] = pwt->b[13];
- pwd->b[14] = pws->b[15];
- pwd->b[15] = pwt->b[15];
- pwd->b[0] = pws->b[1];
- pwd->b[1] = pwt->b[1];
- pwd->b[2] = pws->b[3];
- pwd->b[3] = pwt->b[3];
- pwd->b[4] = pws->b[5];
- pwd->b[5] = pwt->b[5];
- pwd->b[6] = pws->b[7];
- pwd->b[7] = pwt->b[7];
-#else
- pwd->b[15] = pws->b[14];
- pwd->b[14] = pwt->b[14];
- pwd->b[13] = pws->b[12];
- pwd->b[12] = pwt->b[12];
- pwd->b[11] = pws->b[10];
- pwd->b[10] = pwt->b[10];
- pwd->b[9] = pws->b[8];
- pwd->b[8] = pwt->b[8];
- pwd->b[7] = pws->b[6];
- pwd->b[6] = pwt->b[6];
- pwd->b[5] = pws->b[4];
- pwd->b[4] = pwt->b[4];
- pwd->b[3] = pws->b[2];
- pwd->b[2] = pwt->b[2];
- pwd->b[1] = pws->b[0];
- pwd->b[0] = pwt->b[0];
-#endif
- break;
- case DF_HALF:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->h[4] = pws->h[5];
- pwd->h[5] = pwt->h[5];
- pwd->h[6] = pws->h[7];
- pwd->h[7] = pwt->h[7];
- pwd->h[0] = pws->h[1];
- pwd->h[1] = pwt->h[1];
- pwd->h[2] = pws->h[3];
- pwd->h[3] = pwt->h[3];
-#else
- pwd->h[7] = pws->h[6];
- pwd->h[6] = pwt->h[6];
- pwd->h[5] = pws->h[4];
- pwd->h[4] = pwt->h[4];
- pwd->h[3] = pws->h[2];
- pwd->h[2] = pwt->h[2];
- pwd->h[1] = pws->h[0];
- pwd->h[0] = pwt->h[0];
-#endif
- break;
- case DF_WORD:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->w[2] = pws->w[3];
- pwd->w[3] = pwt->w[3];
- pwd->w[0] = pws->w[1];
- pwd->w[1] = pwt->w[1];
-#else
- pwd->w[3] = pws->w[2];
- pwd->w[2] = pwt->w[2];
- pwd->w[1] = pws->w[0];
- pwd->w[0] = pwt->w[0];
-#endif
- break;
- case DF_DOUBLE:
- pwd->d[1] = pws->d[0];
- pwd->d[0] = pwt->d[0];
- break;
- default:
- assert(0);
- }
-}
-
-void helper_msa_ilvod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- wr_t *pws = &(env->active_fpu.fpr[ws].wr);
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
-
- switch (df) {
- case DF_BYTE:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->b[7] = pwt->b[6];
- pwd->b[6] = pws->b[6];
- pwd->b[5] = pwt->b[4];
- pwd->b[4] = pws->b[4];
- pwd->b[3] = pwt->b[2];
- pwd->b[2] = pws->b[2];
- pwd->b[1] = pwt->b[0];
- pwd->b[0] = pws->b[0];
- pwd->b[15] = pwt->b[14];
- pwd->b[14] = pws->b[14];
- pwd->b[13] = pwt->b[12];
- pwd->b[12] = pws->b[12];
- pwd->b[11] = pwt->b[10];
- pwd->b[10] = pws->b[10];
- pwd->b[9] = pwt->b[8];
- pwd->b[8] = pws->b[8];
-#else
- pwd->b[0] = pwt->b[1];
- pwd->b[1] = pws->b[1];
- pwd->b[2] = pwt->b[3];
- pwd->b[3] = pws->b[3];
- pwd->b[4] = pwt->b[5];
- pwd->b[5] = pws->b[5];
- pwd->b[6] = pwt->b[7];
- pwd->b[7] = pws->b[7];
- pwd->b[8] = pwt->b[9];
- pwd->b[9] = pws->b[9];
- pwd->b[10] = pwt->b[11];
- pwd->b[11] = pws->b[11];
- pwd->b[12] = pwt->b[13];
- pwd->b[13] = pws->b[13];
- pwd->b[14] = pwt->b[15];
- pwd->b[15] = pws->b[15];
-#endif
- break;
- case DF_HALF:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->h[3] = pwt->h[2];
- pwd->h[2] = pws->h[2];
- pwd->h[1] = pwt->h[0];
- pwd->h[0] = pws->h[0];
- pwd->h[7] = pwt->h[6];
- pwd->h[6] = pws->h[6];
- pwd->h[5] = pwt->h[4];
- pwd->h[4] = pws->h[4];
-#else
- pwd->h[0] = pwt->h[1];
- pwd->h[1] = pws->h[1];
- pwd->h[2] = pwt->h[3];
- pwd->h[3] = pws->h[3];
- pwd->h[4] = pwt->h[5];
- pwd->h[5] = pws->h[5];
- pwd->h[6] = pwt->h[7];
- pwd->h[7] = pws->h[7];
-#endif
- break;
- case DF_WORD:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->w[1] = pwt->w[0];
- pwd->w[0] = pws->w[0];
- pwd->w[3] = pwt->w[2];
- pwd->w[2] = pws->w[2];
-#else
- pwd->w[0] = pwt->w[1];
- pwd->w[1] = pws->w[1];
- pwd->w[2] = pwt->w[3];
- pwd->w[3] = pws->w[3];
-#endif
- break;
- case DF_DOUBLE:
- pwd->d[0] = pwt->d[1];
- pwd->d[1] = pws->d[1];
- break;
- default:
- assert(0);
- }
-}
-
-void helper_msa_ilvl_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- wr_t *pws = &(env->active_fpu.fpr[ws].wr);
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
-
- switch (df) {
- case DF_BYTE:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->b[7] = pwt->b[15];
- pwd->b[6] = pws->b[15];
- pwd->b[5] = pwt->b[14];
- pwd->b[4] = pws->b[14];
- pwd->b[3] = pwt->b[13];
- pwd->b[2] = pws->b[13];
- pwd->b[1] = pwt->b[12];
- pwd->b[0] = pws->b[12];
- pwd->b[15] = pwt->b[11];
- pwd->b[14] = pws->b[11];
- pwd->b[13] = pwt->b[10];
- pwd->b[12] = pws->b[10];
- pwd->b[11] = pwt->b[9];
- pwd->b[10] = pws->b[9];
- pwd->b[9] = pwt->b[8];
- pwd->b[8] = pws->b[8];
-#else
- pwd->b[0] = pwt->b[8];
- pwd->b[1] = pws->b[8];
- pwd->b[2] = pwt->b[9];
- pwd->b[3] = pws->b[9];
- pwd->b[4] = pwt->b[10];
- pwd->b[5] = pws->b[10];
- pwd->b[6] = pwt->b[11];
- pwd->b[7] = pws->b[11];
- pwd->b[8] = pwt->b[12];
- pwd->b[9] = pws->b[12];
- pwd->b[10] = pwt->b[13];
- pwd->b[11] = pws->b[13];
- pwd->b[12] = pwt->b[14];
- pwd->b[13] = pws->b[14];
- pwd->b[14] = pwt->b[15];
- pwd->b[15] = pws->b[15];
-#endif
- break;
- case DF_HALF:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->h[3] = pwt->h[7];
- pwd->h[2] = pws->h[7];
- pwd->h[1] = pwt->h[6];
- pwd->h[0] = pws->h[6];
- pwd->h[7] = pwt->h[5];
- pwd->h[6] = pws->h[5];
- pwd->h[5] = pwt->h[4];
- pwd->h[4] = pws->h[4];
-#else
- pwd->h[0] = pwt->h[4];
- pwd->h[1] = pws->h[4];
- pwd->h[2] = pwt->h[5];
- pwd->h[3] = pws->h[5];
- pwd->h[4] = pwt->h[6];
- pwd->h[5] = pws->h[6];
- pwd->h[6] = pwt->h[7];
- pwd->h[7] = pws->h[7];
-#endif
- break;
- case DF_WORD:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->w[1] = pwt->w[3];
- pwd->w[0] = pws->w[3];
- pwd->w[3] = pwt->w[2];
- pwd->w[2] = pws->w[2];
-#else
- pwd->w[0] = pwt->w[2];
- pwd->w[1] = pws->w[2];
- pwd->w[2] = pwt->w[3];
- pwd->w[3] = pws->w[3];
-#endif
- break;
- case DF_DOUBLE:
- pwd->d[0] = pwt->d[1];
- pwd->d[1] = pws->d[1];
- break;
- default:
- assert(0);
- }
-}
-
-void helper_msa_ilvr_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- wr_t *pws = &(env->active_fpu.fpr[ws].wr);
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
-
- switch (df) {
- case DF_BYTE:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->b[8] = pws->b[0];
- pwd->b[9] = pwt->b[0];
- pwd->b[10] = pws->b[1];
- pwd->b[11] = pwt->b[1];
- pwd->b[12] = pws->b[2];
- pwd->b[13] = pwt->b[2];
- pwd->b[14] = pws->b[3];
- pwd->b[15] = pwt->b[3];
- pwd->b[0] = pws->b[4];
- pwd->b[1] = pwt->b[4];
- pwd->b[2] = pws->b[5];
- pwd->b[3] = pwt->b[5];
- pwd->b[4] = pws->b[6];
- pwd->b[5] = pwt->b[6];
- pwd->b[6] = pws->b[7];
- pwd->b[7] = pwt->b[7];
-#else
- pwd->b[15] = pws->b[7];
- pwd->b[14] = pwt->b[7];
- pwd->b[13] = pws->b[6];
- pwd->b[12] = pwt->b[6];
- pwd->b[11] = pws->b[5];
- pwd->b[10] = pwt->b[5];
- pwd->b[9] = pws->b[4];
- pwd->b[8] = pwt->b[4];
- pwd->b[7] = pws->b[3];
- pwd->b[6] = pwt->b[3];
- pwd->b[5] = pws->b[2];
- pwd->b[4] = pwt->b[2];
- pwd->b[3] = pws->b[1];
- pwd->b[2] = pwt->b[1];
- pwd->b[1] = pws->b[0];
- pwd->b[0] = pwt->b[0];
-#endif
- break;
- case DF_HALF:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->h[4] = pws->h[0];
- pwd->h[5] = pwt->h[0];
- pwd->h[6] = pws->h[1];
- pwd->h[7] = pwt->h[1];
- pwd->h[0] = pws->h[2];
- pwd->h[1] = pwt->h[2];
- pwd->h[2] = pws->h[3];
- pwd->h[3] = pwt->h[3];
-#else
- pwd->h[7] = pws->h[3];
- pwd->h[6] = pwt->h[3];
- pwd->h[5] = pws->h[2];
- pwd->h[4] = pwt->h[2];
- pwd->h[3] = pws->h[1];
- pwd->h[2] = pwt->h[1];
- pwd->h[1] = pws->h[0];
- pwd->h[0] = pwt->h[0];
-#endif
- break;
- case DF_WORD:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->w[2] = pws->w[0];
- pwd->w[3] = pwt->w[0];
- pwd->w[0] = pws->w[1];
- pwd->w[1] = pwt->w[1];
-#else
- pwd->w[3] = pws->w[1];
- pwd->w[2] = pwt->w[1];
- pwd->w[1] = pws->w[0];
- pwd->w[0] = pwt->w[0];
-#endif
- break;
- case DF_DOUBLE:
- pwd->d[1] = pws->d[0];
- pwd->d[0] = pwt->d[0];
- break;
- default:
- assert(0);
- }
-}
-
void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t wt)
{
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7a35c26..ea8b8f4 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28770,6 +28770,70 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_ILVEV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvev_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvev_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvev_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvev_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVOD_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvod_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvod_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvod_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvod_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvl_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvl_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvl_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvl_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ILVR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_ilvr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_ilvr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_ilvr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_ilvr_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_SLL_df:
gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28842,21 +28906,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_ASUB_S_df:
gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ILVL_df:
- gen_helper_msa_ilvl_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ASUB_U_df:
gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ILVR_df:
- gen_helper_msa_ilvr_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_ILVEV_df:
- gen_helper_msa_ilvev_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_ILVOD_df:
- gen_helper_msa_ilvod_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_DOTP_S_df:
case OPC_DOTP_U_df:
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 07/12] target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (5 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 06/12] target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 08/12] target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D> Aleksandar Markovic
` (8 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 30 +++-
target/mips/msa_helper.c | 426 +++++++++++++++++++++++++++++++++++++++++------
target/mips/translate.c | 95 +++++++++--
3 files changed, 482 insertions(+), 69 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index f3df187..ce01e97 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -822,6 +822,31 @@ DEF_HELPER_4(msa_bset_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bset_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_bset_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_add_a_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_a_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_a_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_adds_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_adds_u_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_addv_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
@@ -976,12 +1001,7 @@ DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_addv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_add_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_adds_a_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_adds_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_adds_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 499fcde..c31f46c 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -805,7 +805,383 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt)
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Add group helpers here */
+
+static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
+ uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
+ return abs_arg1 + abs_arg2;
+}
+
+void helper_msa_add_a_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_add_a_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_add_a_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_add_a_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_add_a_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_add_a_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_add_a_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_add_a_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_add_a_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_add_a_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_add_a_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_add_a_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_add_a_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_add_a_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_add_a_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_add_a_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_add_a_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_add_a_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_add_a_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_add_a_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_add_a_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_add_a_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_add_a_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_add_a_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_add_a_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_add_a_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_add_a_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_add_a_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_add_a_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_add_a_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_add_a_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_add_a_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_add_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_add_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t max_int = (uint64_t)DF_MAX_INT(df);
+ uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
+ uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
+ if (abs_arg1 > max_int || abs_arg2 > max_int) {
+ return (int64_t)max_int;
+ } else {
+ return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
+ }
+}
+
+void helper_msa_adds_a_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_adds_a_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_adds_a_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_adds_a_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_adds_a_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_adds_a_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_adds_a_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_adds_a_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_adds_a_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_adds_a_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_adds_a_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_adds_a_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_adds_a_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_adds_a_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_adds_a_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_adds_a_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_adds_a_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_adds_a_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_adds_a_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_adds_a_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_adds_a_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_adds_a_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_adds_a_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_adds_a_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_adds_a_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_adds_a_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_adds_a_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_adds_a_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_adds_a_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_adds_a_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_adds_a_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_adds_a_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_adds_a_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_adds_a_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int64_t max_int = DF_MAX_INT(df);
+ int64_t min_int = DF_MIN_INT(df);
+ if (arg1 < 0) {
+ return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
+ } else {
+ return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
+ }
+}
+
+void helper_msa_adds_s_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_adds_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_adds_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_adds_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_adds_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_adds_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_adds_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_adds_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_adds_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_adds_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_adds_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_adds_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_adds_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_adds_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_adds_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_adds_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_adds_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_adds_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_adds_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_adds_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_adds_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_adds_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_adds_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_adds_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_adds_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_adds_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_adds_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_adds_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_adds_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_adds_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_adds_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_adds_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_adds_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_adds_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
+{
+ uint64_t max_uint = DF_MAX_UINT(df);
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_arg2 = UNSIGNED(arg2, df);
+ return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
+}
+
+void helper_msa_adds_u_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_adds_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_adds_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_adds_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_adds_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_adds_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_adds_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_adds_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_adds_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_adds_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_adds_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_adds_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_adds_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_adds_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_adds_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_adds_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_adds_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_adds_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_adds_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_adds_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_adds_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_adds_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_adds_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_adds_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_adds_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_adds_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_adds_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_adds_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_adds_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_adds_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_adds_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_adds_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_adds_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_adds_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return arg1 + arg2;
+}
+
+void helper_msa_addv_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_addv_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_addv_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_addv_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_addv_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_addv_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_addv_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_addv_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_addv_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_addv_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_addv_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_addv_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_addv_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_addv_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_addv_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_addv_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_addv_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_addv_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_addv_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_addv_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_addv_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_addv_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_addv_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_addv_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_addv_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_addv_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_addv_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_addv_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_addv_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_addv_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_addv_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_addv_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_addv_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_addv_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
/*
@@ -3050,11 +3426,6 @@ void helper_msa_shf_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
msa_move_v(pwd, pwx);
}
-static inline int64_t msa_addv_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return arg1 + arg2;
-}
-
static inline int64_t msa_subv_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 - arg2;
@@ -3283,44 +3654,6 @@ MSA_TEROP_IMMU_DF(binsli, binsl)
MSA_TEROP_IMMU_DF(binsri, binsr)
#undef MSA_TEROP_IMMU_DF
-static inline int64_t msa_add_a_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
- uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
- return abs_arg1 + abs_arg2;
-}
-
-static inline int64_t msa_adds_a_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t max_int = (uint64_t)DF_MAX_INT(df);
- uint64_t abs_arg1 = arg1 >= 0 ? arg1 : -arg1;
- uint64_t abs_arg2 = arg2 >= 0 ? arg2 : -arg2;
- if (abs_arg1 > max_int || abs_arg2 > max_int) {
- return (int64_t)max_int;
- } else {
- return (abs_arg1 < max_int - abs_arg2) ? abs_arg1 + abs_arg2 : max_int;
- }
-}
-
-static inline int64_t msa_adds_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int64_t max_int = DF_MAX_INT(df);
- int64_t min_int = DF_MIN_INT(df);
- if (arg1 < 0) {
- return (min_int - arg1 < arg2) ? arg1 + arg2 : min_int;
- } else {
- return (arg2 < max_int - arg1) ? arg1 + arg2 : max_int;
- }
-}
-
-static inline uint64_t msa_adds_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
-{
- uint64_t max_uint = DF_MAX_UINT(df);
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_arg2 = UNSIGNED(arg2, df);
- return (u_arg1 < max_uint - u_arg2) ? u_arg1 + u_arg2 : max_uint;
-}
-
static inline int64_t msa_subs_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t max_int = DF_MAX_INT(df);
@@ -3580,12 +3913,7 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
MSA_BINOP_DF(sll)
MSA_BINOP_DF(sra)
MSA_BINOP_DF(srl)
-MSA_BINOP_DF(addv)
MSA_BINOP_DF(subv)
-MSA_BINOP_DF(add_a)
-MSA_BINOP_DF(adds_a)
-MSA_BINOP_DF(adds_s)
-MSA_BINOP_DF(adds_u)
MSA_BINOP_DF(subs_s)
MSA_BINOP_DF(subs_u)
MSA_BINOP_DF(subsus_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ea8b8f4..14f9891 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28466,6 +28466,86 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_ADD_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_add_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_add_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_add_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_add_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDS_A_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_adds_a_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_adds_a_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_adds_a_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_adds_a_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDS_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_adds_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_adds_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_adds_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_adds_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDS_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_adds_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_adds_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_adds_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_adds_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ADDV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_addv_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_addv_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_addv_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_addv_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_AVE_S_df:
switch (df) {
case DF_BYTE:
@@ -28837,12 +28917,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SLL_df:
gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ADDV_df:
- gen_helper_msa_addv_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_ADD_A_df:
- gen_helper_msa_add_a_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBS_S_df:
gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28861,9 +28935,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SUBV_df:
gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ADDS_A_df:
- gen_helper_msa_adds_a_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBS_U_df:
gen_helper_msa_subs_u_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28879,9 +28950,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SRL_df:
gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ADDS_S_df:
- gen_helper_msa_adds_s_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUS_U_df:
gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28894,9 +28962,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SRLR_df:
gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ADDS_U_df:
- gen_helper_msa_adds_u_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 08/12] target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (6 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 07/12] target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 09/12] target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D> Aleksandar Markovic
` (7 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 10 +++-
target/mips/msa_helper.c | 131 ++++++++++++++++++++++++++++++++++++++---------
target/mips/translate.c | 32 +++++++++---
3 files changed, 141 insertions(+), 32 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index ce01e97..f25ba90 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -847,6 +847,14 @@ DEF_HELPER_4(msa_addv_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_addv_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_addv_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hadd_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hadd_u_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ave_s_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ave_s_w, void, env, i32, i32, i32)
@@ -1024,8 +1032,6 @@ DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_hadd_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_hadd_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index c31f46c..f5d3737 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -1184,6 +1184,113 @@ void helper_msa_addv_d(CPUMIPSState *env,
}
+#define SIGNED_EVEN(a, df) \
+ ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
+
+#define UNSIGNED_EVEN(a, df) \
+ ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
+
+#define SIGNED_ODD(a, df) \
+ ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
+
+#define UNSIGNED_ODD(a, df) \
+ ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
+
+
+static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
+}
+
+void helper_msa_hadd_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_hadd_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_hadd_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_hadd_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_hadd_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_hadd_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_hadd_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_hadd_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_hadd_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_hadd_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_hadd_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_hadd_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_hadd_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_hadd_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_hadd_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_hadd_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_hadd_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
+}
+
+void helper_msa_hadd_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_hadd_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_hadd_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_hadd_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_hadd_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_hadd_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_hadd_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_hadd_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_hadd_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_hadd_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_hadd_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_hadd_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_hadd_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_hadd_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_hadd_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_hadd_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_hadd_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/*
* Int Average
* -----------
@@ -3727,18 +3834,6 @@ static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
return arg1 * arg2;
}
-#define SIGNED_EVEN(a, df) \
- ((((int64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
-
-#define UNSIGNED_EVEN(a, df) \
- ((((uint64_t)(a)) << (64 - DF_BITS(df) / 2)) >> (64 - DF_BITS(df) / 2))
-
-#define SIGNED_ODD(a, df) \
- ((((int64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
-
-#define UNSIGNED_ODD(a, df) \
- ((((uint64_t)(a)) << (64 - DF_BITS(df))) >> (64 - DF_BITS(df) / 2))
-
#define SIGNED_EXTRACT(e, o, a, df) \
do { \
e = SIGNED_EVEN(a, df); \
@@ -3815,16 +3910,6 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd,
}
}
-static inline int64_t msa_hadd_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return SIGNED_ODD(arg1, df) + SIGNED_EVEN(arg2, df);
-}
-
-static inline int64_t msa_hadd_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return UNSIGNED_ODD(arg1, df) + UNSIGNED_EVEN(arg2, df);
-}
-
static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
@@ -3925,8 +4010,6 @@ MSA_BINOP_DF(dotp_s)
MSA_BINOP_DF(dotp_u)
MSA_BINOP_DF(srar)
MSA_BINOP_DF(srlr)
-MSA_BINOP_DF(hadd_s)
-MSA_BINOP_DF(hadd_u)
MSA_BINOP_DF(hsub_s)
MSA_BINOP_DF(hsub_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 14f9891..9e8e973 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28990,6 +28990,32 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
switch (MASK_MSA_3R(ctx->opcode)) {
+ case OPC_HADD_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hadd_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hadd_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hadd_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_HADD_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hadd_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hadd_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hadd_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_DOTP_S_df:
gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -29005,15 +29031,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_DPSUB_S_df:
gen_helper_msa_dpsub_s_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_HADD_S_df:
- gen_helper_msa_hadd_s_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_DPSUB_U_df:
gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_HADD_U_df:
- gen_helper_msa_hadd_u_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_HSUB_S_df:
gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 09/12] target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (7 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 08/12] target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 10/12] target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D> Aleksandar Markovic
` (6 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 30 +++-
target/mips/msa_helper.c | 424 +++++++++++++++++++++++++++++++++++++++++------
target/mips/translate.c | 91 ++++++++--
3 files changed, 479 insertions(+), 66 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index f25ba90..f779404 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -967,6 +967,31 @@ DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sll_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_sra_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_sra_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srar_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srar_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srl_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srl_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_srlr_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_srlr_d, void, env, i32, i32, i32)
+
DEF_HELPER_3(msa_move_v, void, env, i32, i32)
DEF_HELPER_4(msa_andi_b, void, env, i32, i32, i32)
@@ -1004,9 +1029,6 @@ DEF_HELPER_5(msa_sat_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srari_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_srlri_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_sll_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_sra_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsl_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_binsr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subv_df, void, env, i32, i32, i32, i32)
@@ -1030,8 +1052,6 @@ DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srar_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_srlr_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index f5d3737..38ff1da 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3461,7 +3461,382 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Shift group helpers here */
+
+static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ return arg1 << b_arg2;
+}
+
+void helper_msa_sll_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_sll_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_sll_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_sll_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_sll_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_sll_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_sll_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_sll_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_sll_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_sll_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_sll_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_sll_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_sll_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_sll_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_sll_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_sll_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_sll_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_sll_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_sll_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_sll_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_sll_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_sll_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_sll_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_sll_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_sll_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_sll_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_sll_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_sll_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_sll_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_sll_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_sll_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_sll_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_sll_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_sll_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ return arg1 >> b_arg2;
+}
+
+void helper_msa_sra_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_sra_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_sra_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_sra_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_sra_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_sra_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_sra_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_sra_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_sra_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_sra_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_sra_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_sra_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_sra_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_sra_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_sra_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_sra_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_sra_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_sra_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_sra_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_sra_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_sra_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_sra_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_sra_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_sra_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_sra_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_sra_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_sra_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_sra_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_sra_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_sra_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_sra_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_sra_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_sra_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_sra_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ if (b_arg2 == 0) {
+ return arg1;
+ } else {
+ int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
+ return (arg1 >> b_arg2) + r_bit;
+ }
+}
+
+void helper_msa_srar_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_srar_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_srar_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_srar_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_srar_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_srar_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_srar_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_srar_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_srar_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_srar_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_srar_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_srar_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_srar_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_srar_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_srar_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_srar_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_srar_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_srar_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_srar_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_srar_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_srar_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_srar_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_srar_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_srar_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_srar_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_srar_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_srar_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_srar_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_srar_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_srar_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_srar_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_srar_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_srar_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_srar_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ return u_arg1 >> b_arg2;
+}
+
+void helper_msa_srl_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_srl_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_srl_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_srl_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_srl_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_srl_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_srl_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_srl_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_srl_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_srl_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_srl_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_srl_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_srl_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_srl_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_srl_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_srl_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_srl_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_srl_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_srl_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_srl_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_srl_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_srl_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_srl_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_srl_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_srl_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_srl_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_srl_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_srl_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_srl_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_srl_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_srl_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_srl_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_srl_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_srl_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ int32_t b_arg2 = BIT_POSITION(arg2, df);
+ if (b_arg2 == 0) {
+ return u_arg1;
+ } else {
+ uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
+ return (u_arg1 >> b_arg2) + r_bit;
+ }
+}
+
+void helper_msa_srlr_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_srlr_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_srlr_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_srlr_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_srlr_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_srlr_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_srlr_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_srlr_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_srlr_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_srlr_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_srlr_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_srlr_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_srlr_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_srlr_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_srlr_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_srlr_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_srlr_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_srlr_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_srlr_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_srlr_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_srlr_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_srlr_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_srlr_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_srlr_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_srlr_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_srlr_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_srlr_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_srlr_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_srlr_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_srlr_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_srlr_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_srlr_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_srlr_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_srlr_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
#define MSA_FN_IMM8(FUNC, DEST, OPERATION) \
@@ -3617,25 +3992,6 @@ void helper_msa_ldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
}
}
-static inline int64_t msa_sll_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- return arg1 << b_arg2;
-}
-
-static inline int64_t msa_sra_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- return arg1 >> b_arg2;
-}
-
-static inline int64_t msa_srl_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- return u_arg1 >> b_arg2;
-}
-
static inline int64_t msa_sat_s_df(uint32_t df, int64_t arg, uint32_t m)
{
return arg < M_MIN_INT(m + 1) ? M_MIN_INT(m + 1) :
@@ -3650,29 +4006,6 @@ static inline int64_t msa_sat_u_df(uint32_t df, int64_t arg, uint32_t m)
M_MAX_UINT(m + 1);
}
-static inline int64_t msa_srar_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- if (b_arg2 == 0) {
- return arg1;
- } else {
- int64_t r_bit = (arg1 >> (b_arg2 - 1)) & 1;
- return (arg1 >> b_arg2) + r_bit;
- }
-}
-
-static inline int64_t msa_srlr_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- int32_t b_arg2 = BIT_POSITION(arg2, df);
- if (b_arg2 == 0) {
- return u_arg1;
- } else {
- uint64_t r_bit = (u_arg1 >> (b_arg2 - 1)) & 1;
- return (u_arg1 >> b_arg2) + r_bit;
- }
-}
-
#define MSA_BINOP_IMMU_DF(helper, func) \
void helper_msa_ ## helper ## _df(CPUMIPSState *env, uint32_t df, uint32_t wd, \
uint32_t ws, uint32_t u5) \
@@ -3995,9 +4328,6 @@ void helper_msa_ ## func ## _df(CPUMIPSState *env, uint32_t df, \
} \
}
-MSA_BINOP_DF(sll)
-MSA_BINOP_DF(sra)
-MSA_BINOP_DF(srl)
MSA_BINOP_DF(subv)
MSA_BINOP_DF(subs_s)
MSA_BINOP_DF(subs_u)
@@ -4008,8 +4338,6 @@ MSA_BINOP_DF(asub_u)
MSA_BINOP_DF(mulv)
MSA_BINOP_DF(dotp_s)
MSA_BINOP_DF(dotp_u)
-MSA_BINOP_DF(srar)
-MSA_BINOP_DF(srlr)
MSA_BINOP_DF(hsub_s)
MSA_BINOP_DF(hsub_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 9e8e973..7cdf68d 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28915,7 +28915,84 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
}
break;
case OPC_SLL_df:
- gen_helper_msa_sll_df(cpu_env, tdf, twd, tws, twt);
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_sll_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_sll_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_sll_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_sll_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRA_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_sra_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_sra_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_sra_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_sra_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRAR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_srar_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_srar_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_srar_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_srar_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRL_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_srl_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_srl_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_srl_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_srl_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_SRLR_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_srlr_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_srlr_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_srlr_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_srlr_d(cpu_env, twd, tws, twt);
+ break;
+ }
break;
case OPC_SUBS_S_df:
gen_helper_msa_subs_s_df(cpu_env, tdf, twd, tws, twt);
@@ -28929,9 +29006,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_VSHF_df:
gen_helper_msa_vshf_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_SRA_df:
- gen_helper_msa_sra_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBV_df:
gen_helper_msa_subv_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28944,12 +29018,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SPLAT_df:
gen_helper_msa_splat_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_SRAR_df:
- gen_helper_msa_srar_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_SRL_df:
- gen_helper_msa_srl_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUS_U_df:
gen_helper_msa_subsus_u_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -28959,9 +29027,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_PCKEV_df:
gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_SRLR_df:
- gen_helper_msa_srlr_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 10/12] target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (8 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 09/12] target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 11/12] target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D> Aleksandar Markovic
` (5 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Reviewed-by: Aleksandar Rikalo <aleksandar.rikalo@rt-rk.com>
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 11 +-
target/mips/msa_helper.c | 386 +++++++++++++++++++++++++----------------------
target/mips/translate.c | 38 ++++-
3 files changed, 249 insertions(+), 186 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index f779404..7bb13d5 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -967,6 +967,15 @@ DEF_HELPER_4(msa_nor_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_or_v, void, env, i32, i32, i32)
DEF_HELPER_4(msa_xor_v, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckev_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_pckod_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_sll_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sll_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_sll_w, void, env, i32, i32, i32)
@@ -1049,8 +1058,6 @@ DEF_HELPER_5(msa_dpsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_pckev_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_pckod_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 38ff1da..2400632 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -3430,7 +3430,214 @@ void helper_msa_move_v(CPUMIPSState *env, uint32_t wd, uint32_t ws)
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Pack group helpers here */
+
+void helper_msa_pckev_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[8] = pws->b[9];
+ pwd->b[10] = pws->b[13];
+ pwd->b[12] = pws->b[1];
+ pwd->b[14] = pws->b[5];
+ pwd->b[0] = pwt->b[9];
+ pwd->b[2] = pwt->b[13];
+ pwd->b[4] = pwt->b[1];
+ pwd->b[6] = pwt->b[5];
+ pwd->b[9] = pws->b[11];
+ pwd->b[13] = pws->b[3];
+ pwd->b[1] = pwt->b[11];
+ pwd->b[5] = pwt->b[3];
+ pwd->b[11] = pws->b[15];
+ pwd->b[3] = pwt->b[15];
+ pwd->b[15] = pws->b[7];
+ pwd->b[7] = pwt->b[7];
+#else
+ pwd->b[15] = pws->b[14];
+ pwd->b[13] = pws->b[10];
+ pwd->b[11] = pws->b[6];
+ pwd->b[9] = pws->b[2];
+ pwd->b[7] = pwt->b[14];
+ pwd->b[5] = pwt->b[10];
+ pwd->b[3] = pwt->b[6];
+ pwd->b[1] = pwt->b[2];
+ pwd->b[14] = pws->b[12];
+ pwd->b[10] = pws->b[4];
+ pwd->b[6] = pwt->b[12];
+ pwd->b[2] = pwt->b[4];
+ pwd->b[12] = pws->b[8];
+ pwd->b[4] = pwt->b[8];
+ pwd->b[8] = pws->b[0];
+ pwd->b[0] = pwt->b[0];
+#endif
+}
+
+void helper_msa_pckev_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[4] = pws->h[5];
+ pwd->h[6] = pws->h[1];
+ pwd->h[0] = pwt->h[5];
+ pwd->h[2] = pwt->h[1];
+ pwd->h[5] = pws->h[7];
+ pwd->h[1] = pwt->h[7];
+ pwd->h[7] = pws->h[3];
+ pwd->h[3] = pwt->h[3];
+#else
+ pwd->h[7] = pws->h[6];
+ pwd->h[5] = pws->h[2];
+ pwd->h[3] = pwt->h[6];
+ pwd->h[1] = pwt->h[2];
+ pwd->h[6] = pws->h[4];
+ pwd->h[2] = pwt->h[4];
+ pwd->h[4] = pws->h[0];
+ pwd->h[0] = pwt->h[0];
+#endif
+}
+
+void helper_msa_pckev_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[2] = pws->w[3];
+ pwd->w[0] = pwt->w[3];
+ pwd->w[3] = pws->w[1];
+ pwd->w[1] = pwt->w[1];
+#else
+ pwd->w[3] = pws->w[2];
+ pwd->w[1] = pwt->w[2];
+ pwd->w[2] = pws->w[0];
+ pwd->w[0] = pwt->w[0];
+#endif
+}
+
+void helper_msa_pckev_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[1] = pws->d[0];
+ pwd->d[0] = pwt->d[0];
+}
+
+
+void helper_msa_pckod_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->b[7] = pwt->b[6];
+ pwd->b[5] = pwt->b[2];
+ pwd->b[3] = pwt->b[14];
+ pwd->b[1] = pwt->b[10];
+ pwd->b[15] = pws->b[6];
+ pwd->b[13] = pws->b[2];
+ pwd->b[11] = pws->b[14];
+ pwd->b[9] = pws->b[10];
+ pwd->b[6] = pwt->b[4];
+ pwd->b[2] = pwt->b[12];
+ pwd->b[14] = pws->b[4];
+ pwd->b[10] = pws->b[12];
+ pwd->b[4] = pwt->b[0];
+ pwd->b[12] = pws->b[0];
+ pwd->b[0] = pwt->b[8];
+ pwd->b[8] = pws->b[8];
+#else
+ pwd->b[0] = pwt->b[1];
+ pwd->b[2] = pwt->b[5];
+ pwd->b[4] = pwt->b[9];
+ pwd->b[6] = pwt->b[13];
+ pwd->b[8] = pws->b[1];
+ pwd->b[10] = pws->b[5];
+ pwd->b[12] = pws->b[9];
+ pwd->b[14] = pws->b[13];
+ pwd->b[1] = pwt->b[3];
+ pwd->b[5] = pwt->b[11];
+ pwd->b[9] = pws->b[3];
+ pwd->b[13] = pws->b[11];
+ pwd->b[3] = pwt->b[7];
+ pwd->b[11] = pws->b[7];
+ pwd->b[7] = pwt->b[15];
+ pwd->b[15] = pws->b[15];
+#endif
+
+}
+
+void helper_msa_pckod_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->h[3] = pwt->h[2];
+ pwd->h[1] = pwt->h[6];
+ pwd->h[7] = pws->h[2];
+ pwd->h[5] = pws->h[6];
+ pwd->h[2] = pwt->h[0];
+ pwd->h[6] = pws->h[0];
+ pwd->h[0] = pwt->h[4];
+ pwd->h[4] = pws->h[4];
+#else
+ pwd->h[0] = pwt->h[1];
+ pwd->h[2] = pwt->h[5];
+ pwd->h[4] = pws->h[1];
+ pwd->h[6] = pws->h[5];
+ pwd->h[1] = pwt->h[3];
+ pwd->h[5] = pws->h[3];
+ pwd->h[3] = pwt->h[7];
+ pwd->h[7] = pws->h[7];
+#endif
+}
+
+void helper_msa_pckod_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+#if defined(HOST_WORDS_BIGENDIAN)
+ pwd->w[1] = pwt->w[0];
+ pwd->w[3] = pws->w[0];
+ pwd->w[0] = pwt->w[2];
+ pwd->w[2] = pws->w[2];
+#else
+ pwd->w[0] = pwt->w[1];
+ pwd->w[2] = pws->w[1];
+ pwd->w[1] = pwt->w[3];
+ pwd->w[3] = pws->w[3];
+#endif
+}
+
+void helper_msa_pckod_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = pwt->d[1];
+ pwd->d[1] = pws->d[1];
+}
/*
@@ -4675,183 +4882,6 @@ MSA_FN_DF(vshf_df)
#undef MSA_FN_DF
-void helper_msa_pckev_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- wr_t *pws = &(env->active_fpu.fpr[ws].wr);
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
-
- switch (df) {
- case DF_BYTE:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->b[8] = pws->b[9];
- pwd->b[10] = pws->b[13];
- pwd->b[12] = pws->b[1];
- pwd->b[14] = pws->b[5];
- pwd->b[0] = pwt->b[9];
- pwd->b[2] = pwt->b[13];
- pwd->b[4] = pwt->b[1];
- pwd->b[6] = pwt->b[5];
- pwd->b[9] = pws->b[11];
- pwd->b[13] = pws->b[3];
- pwd->b[1] = pwt->b[11];
- pwd->b[5] = pwt->b[3];
- pwd->b[11] = pws->b[15];
- pwd->b[3] = pwt->b[15];
- pwd->b[15] = pws->b[7];
- pwd->b[7] = pwt->b[7];
-#else
- pwd->b[15] = pws->b[14];
- pwd->b[13] = pws->b[10];
- pwd->b[11] = pws->b[6];
- pwd->b[9] = pws->b[2];
- pwd->b[7] = pwt->b[14];
- pwd->b[5] = pwt->b[10];
- pwd->b[3] = pwt->b[6];
- pwd->b[1] = pwt->b[2];
- pwd->b[14] = pws->b[12];
- pwd->b[10] = pws->b[4];
- pwd->b[6] = pwt->b[12];
- pwd->b[2] = pwt->b[4];
- pwd->b[12] = pws->b[8];
- pwd->b[4] = pwt->b[8];
- pwd->b[8] = pws->b[0];
- pwd->b[0] = pwt->b[0];
-#endif
- break;
- case DF_HALF:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->h[4] = pws->h[5];
- pwd->h[6] = pws->h[1];
- pwd->h[0] = pwt->h[5];
- pwd->h[2] = pwt->h[1];
- pwd->h[5] = pws->h[7];
- pwd->h[1] = pwt->h[7];
- pwd->h[7] = pws->h[3];
- pwd->h[3] = pwt->h[3];
-#else
- pwd->h[7] = pws->h[6];
- pwd->h[5] = pws->h[2];
- pwd->h[3] = pwt->h[6];
- pwd->h[1] = pwt->h[2];
- pwd->h[6] = pws->h[4];
- pwd->h[2] = pwt->h[4];
- pwd->h[4] = pws->h[0];
- pwd->h[0] = pwt->h[0];
-#endif
- break;
- case DF_WORD:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->w[2] = pws->w[3];
- pwd->w[0] = pwt->w[3];
- pwd->w[3] = pws->w[1];
- pwd->w[1] = pwt->w[1];
-#else
- pwd->w[3] = pws->w[2];
- pwd->w[1] = pwt->w[2];
- pwd->w[2] = pws->w[0];
- pwd->w[0] = pwt->w[0];
-#endif
- break;
- case DF_DOUBLE:
- pwd->d[1] = pws->d[0];
- pwd->d[0] = pwt->d[0];
- break;
- default:
- assert(0);
- }
-}
-
-void helper_msa_pckod_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
- uint32_t ws, uint32_t wt)
-{
- wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
- wr_t *pws = &(env->active_fpu.fpr[ws].wr);
- wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
-
- switch (df) {
- case DF_BYTE:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->b[7] = pwt->b[6];
- pwd->b[5] = pwt->b[2];
- pwd->b[3] = pwt->b[14];
- pwd->b[1] = pwt->b[10];
- pwd->b[15] = pws->b[6];
- pwd->b[13] = pws->b[2];
- pwd->b[11] = pws->b[14];
- pwd->b[9] = pws->b[10];
- pwd->b[6] = pwt->b[4];
- pwd->b[2] = pwt->b[12];
- pwd->b[14] = pws->b[4];
- pwd->b[10] = pws->b[12];
- pwd->b[4] = pwt->b[0];
- pwd->b[12] = pws->b[0];
- pwd->b[0] = pwt->b[8];
- pwd->b[8] = pws->b[8];
-#else
- pwd->b[0] = pwt->b[1];
- pwd->b[2] = pwt->b[5];
- pwd->b[4] = pwt->b[9];
- pwd->b[6] = pwt->b[13];
- pwd->b[8] = pws->b[1];
- pwd->b[10] = pws->b[5];
- pwd->b[12] = pws->b[9];
- pwd->b[14] = pws->b[13];
- pwd->b[1] = pwt->b[3];
- pwd->b[5] = pwt->b[11];
- pwd->b[9] = pws->b[3];
- pwd->b[13] = pws->b[11];
- pwd->b[3] = pwt->b[7];
- pwd->b[11] = pws->b[7];
- pwd->b[7] = pwt->b[15];
- pwd->b[15] = pws->b[15];
-#endif
- break;
- case DF_HALF:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->h[3] = pwt->h[2];
- pwd->h[1] = pwt->h[6];
- pwd->h[7] = pws->h[2];
- pwd->h[5] = pws->h[6];
- pwd->h[2] = pwt->h[0];
- pwd->h[6] = pws->h[0];
- pwd->h[0] = pwt->h[4];
- pwd->h[4] = pws->h[4];
-#else
- pwd->h[0] = pwt->h[1];
- pwd->h[2] = pwt->h[5];
- pwd->h[4] = pws->h[1];
- pwd->h[6] = pws->h[5];
- pwd->h[1] = pwt->h[3];
- pwd->h[5] = pws->h[3];
- pwd->h[3] = pwt->h[7];
- pwd->h[7] = pws->h[7];
-#endif
- break;
- case DF_WORD:
-#if defined(HOST_WORDS_BIGENDIAN)
- pwd->w[1] = pwt->w[0];
- pwd->w[3] = pws->w[0];
- pwd->w[0] = pwt->w[2];
- pwd->w[2] = pws->w[2];
-#else
- pwd->w[0] = pwt->w[1];
- pwd->w[2] = pws->w[1];
- pwd->w[1] = pwt->w[3];
- pwd->w[3] = pws->w[3];
-#endif
- break;
- case DF_DOUBLE:
- pwd->d[0] = pwt->d[1];
- pwd->d[1] = pws->d[1];
- break;
- default:
- assert(0);
- }
-}
-
-
void helper_msa_sldi_df(CPUMIPSState *env, uint32_t df, uint32_t wd,
uint32_t ws, uint32_t n)
{
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 7cdf68d..a57e0da 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28914,6 +28914,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_PCKEV_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_pckev_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_pckev_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_pckev_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_pckev_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_PCKOD_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_pckod_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_pckod_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_pckod_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_pckod_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_SLL_df:
switch (df) {
case DF_BYTE:
@@ -29024,15 +29056,9 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_MSUBV_df:
gen_helper_msa_msubv_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_PCKEV_df:
- gen_helper_msa_pckev_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_PCKOD_df:
- gen_helper_msa_pckod_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_ASUB_S_df:
gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
break;
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 11/12] target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (9 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 10/12] target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-21 19:11 ` [PATCH v6 12/12] target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D> Aleksandar Markovic
` (4 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 10 ++++-
target/mips/msa_helper.c | 108 +++++++++++++++++++++++++++++++++++++++++------
target/mips/translate.c | 32 +++++++++++---
3 files changed, 129 insertions(+), 21 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index 7bb13d5..d7c4bbf 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -945,6 +945,14 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_hsub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_hsub_u_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_ilvev_b, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_ilvev_w, void, env, i32, i32, i32)
@@ -1059,8 +1067,6 @@ DEF_HELPER_5(msa_dpsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sld_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splat_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_vshf_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_hsub_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_hsub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_sldi_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_splati_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index 2400632..ae9e8e0 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2888,7 +2888,101 @@ void helper_msa_mod_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
-/* TODO: insert Int Subtract group helpers here */
+/* TODO: insert the rest of Int Subtract group helpers here */
+
+
+static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
+}
+
+void helper_msa_hsub_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_hsub_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_hsub_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_hsub_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_hsub_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_hsub_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_hsub_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_hsub_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_hsub_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_hsub_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_hsub_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_hsub_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_hsub_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_hsub_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_hsub_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_hsub_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_hsub_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
+}
+
+void helper_msa_hsub_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_hsub_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_hsub_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_hsub_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_hsub_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_hsub_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_hsub_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_hsub_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_hsub_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_hsub_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_hsub_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_hsub_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_hsub_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_hsub_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_hsub_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_hsub_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_hsub_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
/*
@@ -4450,16 +4544,6 @@ static inline void msa_sld_df(uint32_t df, wr_t *pwd,
}
}
-static inline int64_t msa_hsub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return SIGNED_ODD(arg1, df) - SIGNED_EVEN(arg2, df);
-}
-
-static inline int64_t msa_hsub_u_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- return UNSIGNED_ODD(arg1, df) - UNSIGNED_EVEN(arg2, df);
-}
-
static inline int64_t msa_mul_q_df(uint32_t df, int64_t arg1, int64_t arg2)
{
int64_t q_min = DF_MIN_INT(df);
@@ -4545,8 +4629,6 @@ MSA_BINOP_DF(asub_u)
MSA_BINOP_DF(mulv)
MSA_BINOP_DF(dotp_s)
MSA_BINOP_DF(dotp_u)
-MSA_BINOP_DF(hsub_s)
-MSA_BINOP_DF(hsub_u)
MSA_BINOP_DF(mul_q)
MSA_BINOP_DF(mulr_q)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a57e0da..4c68c5b 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -29107,6 +29107,32 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_HSUB_S_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hsub_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hsub_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hsub_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_HSUB_U_df:
+ switch (df) {
+ case DF_HALF:
+ gen_helper_msa_hsub_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_hsub_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_hsub_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_DOTP_S_df:
gen_helper_msa_dotp_s_df(cpu_env, tdf, twd, tws, twt);
break;
@@ -29125,12 +29151,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_DPSUB_U_df:
gen_helper_msa_dpsub_u_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_HSUB_S_df:
- gen_helper_msa_hsub_s_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_HSUB_U_df:
- gen_helper_msa_hsub_u_df(cpu_env, tdf, twd, tws, twt);
- break;
}
break;
default:
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* [PATCH v6 12/12] target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (10 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 11/12] target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D> Aleksandar Markovic
@ 2019-10-21 19:11 ` Aleksandar Markovic
2019-10-22 5:18 ` [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 no-reply
` (3 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: Aleksandar Markovic @ 2019-10-21 19:11 UTC (permalink / raw)
To: qemu-devel; +Cc: aleksandar.rikalo, Aleksandar Markovic
From: Aleksandar Markovic <amarkovic@wavecomp.com>
Achieves clearer code and slightly better performance.
Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
---
target/mips/helper.h | 12 +++-
target/mips/msa_helper.c | 169 ++++++++++++++++++++++++++++++++++++++++++-----
target/mips/translate.c | 38 +++++++++--
3 files changed, 193 insertions(+), 26 deletions(-)
diff --git a/target/mips/helper.h b/target/mips/helper.h
index d7c4bbf..7b8ad74 100644
--- a/target/mips/helper.h
+++ b/target/mips/helper.h
@@ -945,6 +945,16 @@ DEF_HELPER_4(msa_mod_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_mod_s_d, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_s_d, void, env, i32, i32, i32)
+
+DEF_HELPER_4(msa_asub_u_b, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_h, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_w, void, env, i32, i32, i32)
+DEF_HELPER_4(msa_asub_u_d, void, env, i32, i32, i32)
+
DEF_HELPER_4(msa_hsub_s_h, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_s_w, void, env, i32, i32, i32)
DEF_HELPER_4(msa_hsub_s_d, void, env, i32, i32, i32)
@@ -1053,8 +1063,6 @@ DEF_HELPER_5(msa_subs_s_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subs_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsus_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_subsuu_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_asub_s_df, void, env, i32, i32, i32, i32)
-DEF_HELPER_5(msa_asub_u_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_mulv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_maddv_df, void, env, i32, i32, i32, i32)
DEF_HELPER_5(msa_msubv_df, void, env, i32, i32, i32, i32)
diff --git a/target/mips/msa_helper.c b/target/mips/msa_helper.c
index ae9e8e0..0e39016 100644
--- a/target/mips/msa_helper.c
+++ b/target/mips/msa_helper.c
@@ -2888,6 +2888,157 @@ void helper_msa_mod_u_d(CPUMIPSState *env,
* +---------------+----------------------------------------------------------+
*/
+
+static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
+{
+ /* signed compare */
+ return (arg1 < arg2) ?
+ (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
+}
+
+void helper_msa_asub_s_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_asub_s_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_asub_s_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_asub_s_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_asub_s_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_asub_s_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_asub_s_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_asub_s_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_asub_s_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_asub_s_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_asub_s_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_asub_s_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_asub_s_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_asub_s_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_asub_s_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_asub_s_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_asub_s_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_asub_s_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_asub_s_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_asub_s_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_asub_s_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_asub_s_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_asub_s_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_asub_s_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_asub_s_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_asub_s_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_asub_s_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_asub_s_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_asub_s_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_asub_s_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_asub_s_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_asub_s_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_asub_s_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_asub_s_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
+static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
+{
+ uint64_t u_arg1 = UNSIGNED(arg1, df);
+ uint64_t u_arg2 = UNSIGNED(arg2, df);
+ /* unsigned compare */
+ return (u_arg1 < u_arg2) ?
+ (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
+}
+
+void helper_msa_asub_u_b(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->b[0] = msa_asub_u_df(DF_BYTE, pws->b[0], pwt->b[0]);
+ pwd->b[1] = msa_asub_u_df(DF_BYTE, pws->b[1], pwt->b[1]);
+ pwd->b[2] = msa_asub_u_df(DF_BYTE, pws->b[2], pwt->b[2]);
+ pwd->b[3] = msa_asub_u_df(DF_BYTE, pws->b[3], pwt->b[3]);
+ pwd->b[4] = msa_asub_u_df(DF_BYTE, pws->b[4], pwt->b[4]);
+ pwd->b[5] = msa_asub_u_df(DF_BYTE, pws->b[5], pwt->b[5]);
+ pwd->b[6] = msa_asub_u_df(DF_BYTE, pws->b[6], pwt->b[6]);
+ pwd->b[7] = msa_asub_u_df(DF_BYTE, pws->b[7], pwt->b[7]);
+ pwd->b[8] = msa_asub_u_df(DF_BYTE, pws->b[8], pwt->b[8]);
+ pwd->b[9] = msa_asub_u_df(DF_BYTE, pws->b[9], pwt->b[9]);
+ pwd->b[10] = msa_asub_u_df(DF_BYTE, pws->b[10], pwt->b[10]);
+ pwd->b[11] = msa_asub_u_df(DF_BYTE, pws->b[11], pwt->b[11]);
+ pwd->b[12] = msa_asub_u_df(DF_BYTE, pws->b[12], pwt->b[12]);
+ pwd->b[13] = msa_asub_u_df(DF_BYTE, pws->b[13], pwt->b[13]);
+ pwd->b[14] = msa_asub_u_df(DF_BYTE, pws->b[14], pwt->b[14]);
+ pwd->b[15] = msa_asub_u_df(DF_BYTE, pws->b[15], pwt->b[15]);
+}
+
+void helper_msa_asub_u_h(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->h[0] = msa_asub_u_df(DF_HALF, pws->h[0], pwt->h[0]);
+ pwd->h[1] = msa_asub_u_df(DF_HALF, pws->h[1], pwt->h[1]);
+ pwd->h[2] = msa_asub_u_df(DF_HALF, pws->h[2], pwt->h[2]);
+ pwd->h[3] = msa_asub_u_df(DF_HALF, pws->h[3], pwt->h[3]);
+ pwd->h[4] = msa_asub_u_df(DF_HALF, pws->h[4], pwt->h[4]);
+ pwd->h[5] = msa_asub_u_df(DF_HALF, pws->h[5], pwt->h[5]);
+ pwd->h[6] = msa_asub_u_df(DF_HALF, pws->h[6], pwt->h[6]);
+ pwd->h[7] = msa_asub_u_df(DF_HALF, pws->h[7], pwt->h[7]);
+}
+
+void helper_msa_asub_u_w(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->w[0] = msa_asub_u_df(DF_WORD, pws->w[0], pwt->w[0]);
+ pwd->w[1] = msa_asub_u_df(DF_WORD, pws->w[1], pwt->w[1]);
+ pwd->w[2] = msa_asub_u_df(DF_WORD, pws->w[2], pwt->w[2]);
+ pwd->w[3] = msa_asub_u_df(DF_WORD, pws->w[3], pwt->w[3]);
+}
+
+void helper_msa_asub_u_d(CPUMIPSState *env,
+ uint32_t wd, uint32_t ws, uint32_t wt)
+{
+ wr_t *pwd = &(env->active_fpu.fpr[wd].wr);
+ wr_t *pws = &(env->active_fpu.fpr[ws].wr);
+ wr_t *pwt = &(env->active_fpu.fpr[wt].wr);
+
+ pwd->d[0] = msa_asub_u_df(DF_DOUBLE, pws->d[0], pwt->d[0]);
+ pwd->d[1] = msa_asub_u_df(DF_DOUBLE, pws->d[1], pwt->d[1]);
+}
+
+
/* TODO: insert the rest of Int Subtract group helpers here */
@@ -4447,22 +4598,6 @@ static inline int64_t msa_subsuu_s_df(uint32_t df, int64_t arg1, int64_t arg2)
}
}
-static inline int64_t msa_asub_s_df(uint32_t df, int64_t arg1, int64_t arg2)
-{
- /* signed compare */
- return (arg1 < arg2) ?
- (uint64_t)(arg2 - arg1) : (uint64_t)(arg1 - arg2);
-}
-
-static inline uint64_t msa_asub_u_df(uint32_t df, uint64_t arg1, uint64_t arg2)
-{
- uint64_t u_arg1 = UNSIGNED(arg1, df);
- uint64_t u_arg2 = UNSIGNED(arg2, df);
- /* unsigned compare */
- return (u_arg1 < u_arg2) ?
- (uint64_t)(u_arg2 - u_arg1) : (uint64_t)(u_arg1 - u_arg2);
-}
-
static inline int64_t msa_mulv_df(uint32_t df, int64_t arg1, int64_t arg2)
{
return arg1 * arg2;
@@ -4624,8 +4759,6 @@ MSA_BINOP_DF(subs_s)
MSA_BINOP_DF(subs_u)
MSA_BINOP_DF(subsus_u)
MSA_BINOP_DF(subsuu_s)
-MSA_BINOP_DF(asub_s)
-MSA_BINOP_DF(asub_u)
MSA_BINOP_DF(mulv)
MSA_BINOP_DF(dotp_s)
MSA_BINOP_DF(dotp_u)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 4c68c5b..20c69d2 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -28850,6 +28850,38 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
break;
}
break;
+ case OPC_ASUB_S_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_asub_s_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_asub_s_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_asub_s_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_asub_s_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
+ case OPC_ASUB_U_df:
+ switch (df) {
+ case DF_BYTE:
+ gen_helper_msa_asub_u_b(cpu_env, twd, tws, twt);
+ break;
+ case DF_HALF:
+ gen_helper_msa_asub_u_h(cpu_env, twd, tws, twt);
+ break;
+ case DF_WORD:
+ gen_helper_msa_asub_u_w(cpu_env, twd, tws, twt);
+ break;
+ case DF_DOUBLE:
+ gen_helper_msa_asub_u_d(cpu_env, twd, tws, twt);
+ break;
+ }
+ break;
case OPC_ILVEV_df:
switch (df) {
case DF_BYTE:
@@ -29059,12 +29091,6 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx)
case OPC_SUBSUU_S_df:
gen_helper_msa_subsuu_s_df(cpu_env, tdf, twd, tws, twt);
break;
- case OPC_ASUB_S_df:
- gen_helper_msa_asub_s_df(cpu_env, tdf, twd, tws, twt);
- break;
- case OPC_ASUB_U_df:
- gen_helper_msa_asub_u_df(cpu_env, tdf, twd, tws, twt);
- break;
case OPC_DOTP_S_df:
case OPC_DOTP_U_df:
--
2.7.4
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (11 preceding siblings ...)
2019-10-21 19:11 ` [PATCH v6 12/12] target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D> Aleksandar Markovic
@ 2019-10-22 5:18 ` no-reply
2019-10-22 10:27 ` no-reply
` (2 subsequent siblings)
15 siblings, 0 replies; 17+ messages in thread
From: no-reply @ 2019-10-22 5:18 UTC (permalink / raw)
To: aleksandar.markovic; +Cc: aleksandar.rikalo, qemu-devel, amarkovic
Patchew URL: https://patchew.org/QEMU/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
Type: series
Message-id: 1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
Switched to a new branch 'test'
67bb877 target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
e2de4dc target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
5a7dfbf target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
48614e3 target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
b71fd4f target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
0ab1f37 target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
f6c7c8a target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
6e09061 target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
abc5063 target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
4c9a2be MAINTAINERS: Update mail address of Aleksandar Rikalo
b1f1de4 target/mips: Clean up op_helper.c
18f4171 target/mips: Clean up helper.c
=== OUTPUT BEGIN ===
1/12 Checking commit 18f417113620 (target/mips: Clean up helper.c)
2/12 Checking commit b1f1de430f2e (target/mips: Clean up op_helper.c)
ERROR: spaces required around that '*' (ctx:WxV)
#1059: FILE: target/mips/op_helper.c:3871:
+ float_status *status) \
^
total: 1 errors, 0 warnings, 1681 lines checked
Patch 2/12 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/12 Checking commit 4c9a2bed5479 (MAINTAINERS: Update mail address of Aleksandar Rikalo)
4/12 Checking commit abc5063443d3 (target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>)
5/12 Checking commit 6e09061f3d43 (target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>)
6/12 Checking commit f6c7c8ad441b (target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>)
7/12 Checking commit 0ab1f37b65bf (target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>)
8/12 Checking commit b71fd4fe41cc (target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>)
9/12 Checking commit 48614e367297 (target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>)
10/12 Checking commit 5a7dfbf52558 (target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>)
11/12 Checking commit e2de4dc7eb94 (target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>)
12/12 Checking commit 67bb8777638a (target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (12 preceding siblings ...)
2019-10-22 5:18 ` [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 no-reply
@ 2019-10-22 10:27 ` no-reply
2019-10-22 16:05 ` no-reply
2019-10-23 8:35 ` no-reply
15 siblings, 0 replies; 17+ messages in thread
From: no-reply @ 2019-10-22 10:27 UTC (permalink / raw)
To: aleksandar.markovic; +Cc: aleksandar.rikalo, qemu-devel, amarkovic
Patchew URL: https://patchew.org/QEMU/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
Type: series
Message-id: 1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
4a47a90 target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
80b4880 target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
045f415 target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
861d76a target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
39d4345 target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
a86a459 target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
5714c4f target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
17d744e target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
bd4d22e target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
e271939 MAINTAINERS: Update mail address of Aleksandar Rikalo
9938bd3 target/mips: Clean up op_helper.c
fc20b79 target/mips: Clean up helper.c
=== OUTPUT BEGIN ===
1/12 Checking commit fc20b79dea40 (target/mips: Clean up helper.c)
2/12 Checking commit 9938bd3b2fb2 (target/mips: Clean up op_helper.c)
ERROR: spaces required around that '*' (ctx:WxV)
#1059: FILE: target/mips/op_helper.c:3871:
+ float_status *status) \
^
total: 1 errors, 0 warnings, 1681 lines checked
Patch 2/12 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/12 Checking commit e2719394e1b4 (MAINTAINERS: Update mail address of Aleksandar Rikalo)
4/12 Checking commit bd4d22e72ce9 (target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>)
5/12 Checking commit 17d744ed246a (target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>)
6/12 Checking commit 5714c4f6f3ae (target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>)
7/12 Checking commit a86a45905bb5 (target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>)
8/12 Checking commit 39d4345977ca (target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>)
9/12 Checking commit 861d76a00b7b (target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>)
10/12 Checking commit 045f415cf74c (target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>)
11/12 Checking commit 80b488087528 (target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>)
12/12 Checking commit 4a47a90d1e70 (target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (13 preceding siblings ...)
2019-10-22 10:27 ` no-reply
@ 2019-10-22 16:05 ` no-reply
2019-10-23 8:35 ` no-reply
15 siblings, 0 replies; 17+ messages in thread
From: no-reply @ 2019-10-22 16:05 UTC (permalink / raw)
To: aleksandar.markovic; +Cc: aleksandar.rikalo, qemu-devel, amarkovic
Patchew URL: https://patchew.org/QEMU/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
Type: series
Message-id: 1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Switched to a new branch 'test'
36112c6 target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
c385d15 target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
1cb06f9 target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
c163234 target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
e291f35 target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
6e9e5a5 target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
d6312d1 target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
8825acf target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
fc46b54 target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
217fbe2 MAINTAINERS: Update mail address of Aleksandar Rikalo
5e0227b target/mips: Clean up op_helper.c
a8fa795 target/mips: Clean up helper.c
=== OUTPUT BEGIN ===
1/12 Checking commit a8fa7957997d (target/mips: Clean up helper.c)
2/12 Checking commit 5e0227b2346c (target/mips: Clean up op_helper.c)
ERROR: spaces required around that '*' (ctx:WxV)
#1059: FILE: target/mips/op_helper.c:3871:
+ float_status *status) \
^
total: 1 errors, 0 warnings, 1681 lines checked
Patch 2/12 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/12 Checking commit 217fbe216ae8 (MAINTAINERS: Update mail address of Aleksandar Rikalo)
4/12 Checking commit fc46b54fe0a0 (target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>)
5/12 Checking commit 8825acf5951f (target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>)
6/12 Checking commit d6312d1d6fe6 (target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>)
7/12 Checking commit 6e9e5a5404a5 (target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>)
8/12 Checking commit e291f3532f5d (target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>)
9/12 Checking commit c16323490f9c (target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>)
10/12 Checking commit 1cb06f9ae607 (target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>)
11/12 Checking commit c385d15ca204 (target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>)
12/12 Checking commit 36112c61daf9 (target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
2019-10-21 19:11 [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
` (14 preceding siblings ...)
2019-10-22 16:05 ` no-reply
@ 2019-10-23 8:35 ` no-reply
15 siblings, 0 replies; 17+ messages in thread
From: no-reply @ 2019-10-23 8:35 UTC (permalink / raw)
To: aleksandar.markovic; +Cc: aleksandar.rikalo, qemu-devel, amarkovic
Patchew URL: https://patchew.org/QEMU/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/
Hi,
This series seems to have some coding style problems. See output below for
more information:
Subject: [PATCH v6 00/12] target/mips: Misc cleanups for September/October 2019
Type: series
Message-id: 1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com
=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
- [tag update] patchew/20191018092136.26581-1-eric.auger@redhat.com -> patchew/20191018092136.26581-1-eric.auger@redhat.com
* [new tag] patchew/20191023082431.30780-1-pbonzini@redhat.com -> patchew/20191023082431.30780-1-pbonzini@redhat.com
- [tag update] patchew/cover.1570208781.git.maozhongyi@cmss.chinamobile.com -> patchew/cover.1570208781.git.maozhongyi@cmss.chinamobile.com
Switched to a new branch 'test'
d09fef5 target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>
30a6202 target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>
308fc7a target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>
32248b0 target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>
dad828f target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>
f1c8a56 target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>
f5f90bf target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>
ce348ae target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>
704c174 target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>
4fcd018 MAINTAINERS: Update mail address of Aleksandar Rikalo
7311d0a target/mips: Clean up op_helper.c
c464bc9 target/mips: Clean up helper.c
=== OUTPUT BEGIN ===
1/12 Checking commit c464bc9194b7 (target/mips: Clean up helper.c)
2/12 Checking commit 7311d0a646ea (target/mips: Clean up op_helper.c)
ERROR: spaces required around that '*' (ctx:WxV)
#1059: FILE: target/mips/op_helper.c:3871:
+ float_status *status) \
^
total: 1 errors, 0 warnings, 1681 lines checked
Patch 2/12 has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/12 Checking commit 4fcd018cf015 (MAINTAINERS: Update mail address of Aleksandar Rikalo)
4/12 Checking commit 704c174cc449 (target/mips: msa: Split helpers for <MAX|MIN>_A.<B|H|W|D>)
5/12 Checking commit ce348ae7e85b (target/mips: msa: Split helpers for <MAX|MIN>_<S|U>.<B|H|W|D>)
6/12 Checking commit f5f90bf94e05 (target/mips: msa: Split helpers for ILV<EV|OD|L|R>.<B|H|W|D>)
7/12 Checking commit f1c8a567a523 (target/mips: msa: Split helpers for ADD<_A|S_A|S_S|S_U|V>.<B|H|W|D>)
8/12 Checking commit dad828f28cc7 (target/mips: msa: Split helpers for HADD_<S|U>.<H|W|D>)
9/12 Checking commit 32248b0e5194 (target/mips: msa: Split helpers for S<LL|RA|RAR|RL|RLR>.<B|H|W|D>)
10/12 Checking commit 308fc7adf033 (target/mips: msa: Split helpers for PCK<EV|OD>.<B|H|W|D>)
11/12 Checking commit 30a62025b560 (target/mips: msa: Split helpers for HSUB_<S|U>.<H|W|D>)
12/12 Checking commit d09fef515e58 (target/mips: msa: Split helpers for ASUB_<S|U>.<B|H|W|D>)
=== OUTPUT END ===
Test command exited with code: 1
The full log is available at
http://patchew.org/logs/1571685097-15175-1-git-send-email-aleksandar.markovic@rt-rk.com/testing.checkpatch/?type=message.
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