All of lore.kernel.org
 help / color / mirror / Atom feed
From: Chris Wilson <chris@chris-wilson.co.uk>
To: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915/selftests: Add coverage of mocs registers
Date: Thu, 24 Oct 2019 08:13:29 +0100	[thread overview]
Message-ID: <157190120947.18724.9509951564701317530@skylake-alporthouse-com> (raw)
In-Reply-To: <20191023210340.GP3257@intel.com>

Quoting Kumar Valsan, Prathap (2019-10-23 22:03:40)
> On Tue, Oct 22, 2019 at 12:57:05PM +0100, Chris Wilson wrote:
> > Probe the mocs registers for new contexts and across GPU resets. Similar
> > to intel_workarounds, we have tables of what register values we expect
> > to see, so verify that user contexts are affected by them. In the
> > future, we should add tests similar to intel_sseu to cover dynamic
> > reconfigurations.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> 
> s/for_each_engine/for_each_uabi_engine ?

No, we are inside the gt compartment, so we only operate within our
little enclosure. Think parallelism...
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk>
To: "Kumar Valsan, Prathap" <prathap.kumar.valsan@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915/selftests: Add coverage of mocs registers
Date: Thu, 24 Oct 2019 08:13:29 +0100	[thread overview]
Message-ID: <157190120947.18724.9509951564701317530@skylake-alporthouse-com> (raw)
Message-ID: <20191024071329.Jzl8dfSNl_2A36kY23VJSiphWrf-v3BrvQft3nGRKwA@z> (raw)
In-Reply-To: <20191023210340.GP3257@intel.com>

Quoting Kumar Valsan, Prathap (2019-10-23 22:03:40)
> On Tue, Oct 22, 2019 at 12:57:05PM +0100, Chris Wilson wrote:
> > Probe the mocs registers for new contexts and across GPU resets. Similar
> > to intel_workarounds, we have tables of what register values we expect
> > to see, so verify that user contexts are affected by them. In the
> > future, we should add tests similar to intel_sseu to cover dynamic
> > reconfigurations.
> > 
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Prathap Kumar Valsan <prathap.kumar.valsan@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> 
> s/for_each_engine/for_each_uabi_engine ?

No, we are inside the gt compartment, so we only operate within our
little enclosure. Think parallelism...
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2019-10-24  7:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-22 11:51 [PATCH 1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others Chris Wilson
2019-10-22 11:51 ` [PATCH 2/4] drm/i915/gt: Tidy up debug-warns for the mocs control table Chris Wilson
2019-10-22 11:51 ` [PATCH 3/4] drm/i915/gt: Refactor mocs loops into single control macro Chris Wilson
2019-10-22 11:51 ` [PATCH 4/4] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
2019-10-22 11:57   ` [PATCH] " Chris Wilson
2019-10-23 21:03     ` Kumar Valsan, Prathap
2019-10-23 21:03       ` [Intel-gfx] " Kumar Valsan, Prathap
2019-10-24  7:13       ` Chris Wilson [this message]
2019-10-24  7:13         ` Chris Wilson
2019-10-24 17:01         ` Kumar Valsan, Prathap
2019-10-24 17:01           ` [Intel-gfx] " Kumar Valsan, Prathap
2019-10-22 19:28 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/gt: Set unused mocs entry to follow PTE on tgl as on all others (rev2) Patchwork
2019-10-22 19:55 ` ✓ Fi.CI.BAT: success " Patchwork
2019-10-23 11:00 ` ✓ Fi.CI.IGT: " Patchwork
2019-10-23 11:00   ` [Intel-gfx] " Patchwork
  -- strict thread matches above, loose matches on Subject: below --
2019-10-18 12:06 [PATCH] drm/i915/selftests: Add coverage of mocs registers Chris Wilson
2019-10-18 14:09 ` Kumar Valsan, Prathap
2019-10-17  8:01 Chris Wilson
2019-10-17  9:27 ` Chris Wilson

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=157190120947.18724.9509951564701317530@skylake-alporthouse-com \
    --to=chris@chris-wilson.co.uk \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=prathap.kumar.valsan@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.