* [PATCH 0/2] Add support for 2nd generation AMD EPYC processors
@ 2019-11-05 21:17 Moger, Babu
2019-11-05 21:17 ` [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model Moger, Babu
2019-11-05 21:17 ` [PATCH 2/2] i386: Add 2nd Generation AMD EPYC processors Moger, Babu
0 siblings, 2 replies; 6+ messages in thread
From: Moger, Babu @ 2019-11-05 21:17 UTC (permalink / raw)
To: mst, marcel.apfelbaum, pbonzini, rth, ehabkost; +Cc: qemu-devel
The following series adds the support for 2nd generation AMD EPYC Processors
on qemu guests. The model display name for will be EPYC-Rome.
Also fixes few missed cpu feature bits in 1st generation EPYC models.
The Reference documents are available at
https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
https://www.amd.com/system/files/TechDocs/24594.pdf
---
Babu Moger (2):
i386: Add missing cpu feature bits in EPYC model
i386: Add 2nd Generation AMD EPYC processors
hw/i386/pc.c | 8 +++-
target/i386/cpu.c | 113 ++++++++++++++++++++++++++++++++++++++++++++++++++---
target/i386/cpu.h | 2 +
3 files changed, 115 insertions(+), 8 deletions(-)
--
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model
2019-11-05 21:17 [PATCH 0/2] Add support for 2nd generation AMD EPYC processors Moger, Babu
@ 2019-11-05 21:17 ` Moger, Babu
2019-11-05 21:43 ` Eduardo Habkost
2019-11-05 21:17 ` [PATCH 2/2] i386: Add 2nd Generation AMD EPYC processors Moger, Babu
1 sibling, 1 reply; 6+ messages in thread
From: Moger, Babu @ 2019-11-05 21:17 UTC (permalink / raw)
To: mst, marcel.apfelbaum, pbonzini, rth, ehabkost; +Cc: qemu-devel
Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
to use extended performance counter support. It enables six
programmable counters instead of 4 counters.
clzero : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
pointers.
ibpb : Indirect Branch Prediction Barrie.
xsaves : XSAVES, XRSTORS and IA32_XSS supported.
Depends on:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
52297436199d ("kvm: svm: Update svm_xsaves_supported")
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
hw/i386/pc.c | 8 +++++++-
target/i386/cpu.c | 11 +++++------
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 51b72439b4..a72fe1db31 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -105,7 +105,13 @@ struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
/* Physical Address of PVH entry point read from kernel ELF NOTE */
static size_t pvh_start_addr;
-GlobalProperty pc_compat_4_1[] = {};
+GlobalProperty pc_compat_4_1[] = {
+ { "EPYC" "-" TYPE_X86_CPU, "perfctr-core", "off" },
+ { "EPYC" "-" TYPE_X86_CPU, "clzero", "off" },
+ { "EPYC" "-" TYPE_X86_CPU, "xsaveerptr", "off" },
+ { "EPYC" "-" TYPE_X86_CPU, "ibpb", "off" },
+ { "EPYC" "-" TYPE_X86_CPU, "xsaves", "off" },
+};
const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
GlobalProperty pc_compat_4_0[] = {};
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 07cf562d89..71233e6310 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3110,19 +3110,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
- CPUID_EXT3_TOPOEXT,
+ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
+ .features[FEAT_8000_0008_EBX] =
+ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
+ CPUID_8000_0008_EBX_IBPB,
.features[FEAT_7_0_EBX] =
CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
CPUID_7_0_EBX_SHA_NI,
- /* Missing: XSAVES (not supported by some Linux versions,
- * including v4.1 to v4.12).
- * KVM doesn't yet expose any XSAVES state save component.
- */
.features[FEAT_XSAVE] =
CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
- CPUID_XSAVE_XGETBV1,
+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
.features[FEAT_6_EAX] =
CPUID_6_EAX_ARAT,
.features[FEAT_SVM] =
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] i386: Add 2nd Generation AMD EPYC processors
2019-11-05 21:17 [PATCH 0/2] Add support for 2nd generation AMD EPYC processors Moger, Babu
2019-11-05 21:17 ` [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model Moger, Babu
@ 2019-11-05 21:17 ` Moger, Babu
1 sibling, 0 replies; 6+ messages in thread
From: Moger, Babu @ 2019-11-05 21:17 UTC (permalink / raw)
To: mst, marcel.apfelbaum, pbonzini, rth, ehabkost; +Cc: qemu-devel
Adds the support for 2nd Gen AMD EPYC Processors. The model display
name will be EPYC-Rome.
Adds the following new feature bits on top of the feature bits from the
first generation EPYC models.
perfctr-core : core performance counter extensions support. Enables the VM to
use extended performance counter support. It enables six
programmable counters instead of four counters.
clzero : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
pointers.
wbnoinvd : Write back and do not invalidate cache
ibpb : Indirect Branch Prediction Barrier
amd-stibp : Single Thread Indirect Branch Predictor
clwb : Cache Line Write Back and Retain
xsaves : XSAVES, XRSTORS and IA32_XSS support
rdpid : Read Processor ID instruction support
umip : User-Mode Instruction Prevention support
The Reference documents are available at
https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
https://www.amd.com/system/files/TechDocs/24594.pdf
Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
6d61e3c32248 ("kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID")
52297436199d ("kvm: svm: Update svm_xsaves_supported")
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
target/i386/cpu.c | 102 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
target/i386/cpu.h | 2 +
2 files changed, 103 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 71233e6310..846662c879 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1133,7 +1133,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
"clzero", NULL, "xsaveerptr", NULL,
NULL, NULL, NULL, NULL,
NULL, "wbnoinvd", NULL, NULL,
- "ibpb", NULL, NULL, NULL,
+ "ibpb", NULL, NULL, "amd-stibp",
NULL, NULL, NULL, NULL,
NULL, NULL, NULL, NULL,
"amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
@@ -1796,6 +1796,56 @@ static CPUCaches epyc_cache_info = {
},
};
+static CPUCaches epyc_rome_cache_info = {
+ .l1d_cache = &(CPUCacheInfo) {
+ .type = DATA_CACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .l1i_cache = &(CPUCacheInfo) {
+ .type = INSTRUCTION_CACHE,
+ .level = 1,
+ .size = 32 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 64,
+ .lines_per_tag = 1,
+ .self_init = 1,
+ .no_invd_sharing = true,
+ },
+ .l2_cache = &(CPUCacheInfo) {
+ .type = UNIFIED_CACHE,
+ .level = 2,
+ .size = 512 * KiB,
+ .line_size = 64,
+ .associativity = 8,
+ .partitions = 1,
+ .sets = 1024,
+ .lines_per_tag = 1,
+ },
+ .l3_cache = &(CPUCacheInfo) {
+ .type = UNIFIED_CACHE,
+ .level = 3,
+ .size = 16 * MiB,
+ .line_size = 64,
+ .associativity = 16,
+ .partitions = 1,
+ .sets = 16384,
+ .lines_per_tag = 1,
+ .self_init = true,
+ .inclusive = true,
+ .complex_indexing = true,
+ },
+};
+
static X86CPUDefinition builtin_x86_defs[] = {
{
.name = "qemu64",
@@ -3194,6 +3244,56 @@ static X86CPUDefinition builtin_x86_defs[] = {
.model_id = "Hygon Dhyana Processor",
.cache_info = &epyc_cache_info,
},
+ {
+ .name = "EPYC-Rome",
+ .level = 0xd,
+ .vendor = CPUID_VENDOR_AMD,
+ .family = 23,
+ .model = 49,
+ .stepping = 0,
+ .features[FEAT_1_EDX] =
+ CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+ CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+ CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+ CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+ CPUID_VME | CPUID_FP87,
+ .features[FEAT_1_ECX] =
+ CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+ CPUID_EXT_XSAVE | CPUID_EXT_AES | CPUID_EXT_POPCNT |
+ CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+ CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+ CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+ .features[FEAT_8000_0001_EDX] =
+ CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+ CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+ CPUID_EXT2_SYSCALL,
+ .features[FEAT_8000_0001_ECX] =
+ CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+ CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+ CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+ CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
+ .features[FEAT_8000_0008_EBX] =
+ CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
+ CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
+ CPUID_8000_0008_EBX_STIBP,
+ .features[FEAT_7_0_EBX] =
+ CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+ CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
+ CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+ CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
+ .features[FEAT_7_0_ECX] =
+ CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
+ .features[FEAT_XSAVE] =
+ CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+ CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
+ .features[FEAT_6_EAX] =
+ CPUID_6_EAX_ARAT,
+ .features[FEAT_SVM] =
+ CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
+ .xlevel = 0x8000001E,
+ .model_id = "AMD EPYC-Rome Processor",
+ .cache_info = &epyc_rome_cache_info,
+ },
};
/* KVM-specific features that are automatically added/removed
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index af57fda8e5..24cdca5d3f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -781,6 +781,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_8000_0008_EBX_WBNOINVD (1U << 9)
/* Indirect Branch Prediction Barrier */
#define CPUID_8000_0008_EBX_IBPB (1U << 12)
+/* Single Thread Indirect Branch Predictors */
+#define CPUID_8000_0008_EBX_STIBP (1U << 15)
#define CPUID_XSAVE_XSAVEOPT (1U << 0)
#define CPUID_XSAVE_XSAVEC (1U << 1)
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model
2019-11-05 21:17 ` [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model Moger, Babu
@ 2019-11-05 21:43 ` Eduardo Habkost
2019-11-06 0:16 ` Moger, Babu
0 siblings, 1 reply; 6+ messages in thread
From: Eduardo Habkost @ 2019-11-05 21:43 UTC (permalink / raw)
To: Moger, Babu; +Cc: pbonzini, rth, qemu-devel, mst
On Tue, Nov 05, 2019 at 09:17:30PM +0000, Moger, Babu wrote:
> Adds the following missing CPUID bits:
> perfctr-core : core performance counter extensions support. Enables the VM
> to use extended performance counter support. It enables six
> programmable counters instead of 4 counters.
> clzero : instruction zeroes out the 64 byte cache line specified in RAX.
> xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
> pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
> pointers.
> ibpb : Indirect Branch Prediction Barrie.
> xsaves : XSAVES, XRSTORS and IA32_XSS supported.
>
> Depends on:
> 40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
> 504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
> 52297436199d ("kvm: svm: Update svm_xsaves_supported")
>
> Signed-off-by: Babu Moger <babu.moger@amd.com>
> ---
> hw/i386/pc.c | 8 +++++++-
> target/i386/cpu.c | 11 +++++------
> 2 files changed, 12 insertions(+), 7 deletions(-)
>
> diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> index 51b72439b4..a72fe1db31 100644
> --- a/hw/i386/pc.c
> +++ b/hw/i386/pc.c
> @@ -105,7 +105,13 @@ struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
> /* Physical Address of PVH entry point read from kernel ELF NOTE */
> static size_t pvh_start_addr;
>
> -GlobalProperty pc_compat_4_1[] = {};
> +GlobalProperty pc_compat_4_1[] = {
> + { "EPYC" "-" TYPE_X86_CPU, "perfctr-core", "off" },
> + { "EPYC" "-" TYPE_X86_CPU, "clzero", "off" },
> + { "EPYC" "-" TYPE_X86_CPU, "xsaveerptr", "off" },
> + { "EPYC" "-" TYPE_X86_CPU, "ibpb", "off" },
> + { "EPYC" "-" TYPE_X86_CPU, "xsaves", "off" },
> +};
machine-type-based CPU compatibility was now replaced by
versioned CPU models. Please use the X86CPUDefinition.versions
field to add a new version of EPYC instead.
> const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
>
> GlobalProperty pc_compat_4_0[] = {};
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 07cf562d89..71233e6310 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3110,19 +3110,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
> CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
> CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
> CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
> - CPUID_EXT3_TOPOEXT,
> + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
> + .features[FEAT_8000_0008_EBX] =
> + CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
> + CPUID_8000_0008_EBX_IBPB,
> .features[FEAT_7_0_EBX] =
> CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
> CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
> CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
> CPUID_7_0_EBX_SHA_NI,
> - /* Missing: XSAVES (not supported by some Linux versions,
> - * including v4.1 to v4.12).
> - * KVM doesn't yet expose any XSAVES state save component.
> - */
> .features[FEAT_XSAVE] =
> CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> - CPUID_XSAVE_XGETBV1,
> + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
> .features[FEAT_6_EAX] =
> CPUID_6_EAX_ARAT,
> .features[FEAT_SVM] =
>
--
Eduardo
^ permalink raw reply [flat|nested] 6+ messages in thread
* RE: [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model
2019-11-05 21:43 ` Eduardo Habkost
@ 2019-11-06 0:16 ` Moger, Babu
2019-11-06 0:32 ` Eduardo Habkost
0 siblings, 1 reply; 6+ messages in thread
From: Moger, Babu @ 2019-11-06 0:16 UTC (permalink / raw)
To: Eduardo Habkost; +Cc: pbonzini, rth, qemu-devel, mst
> -----Original Message-----
> From: Eduardo Habkost <ehabkost@redhat.com>
> Sent: Tuesday, November 5, 2019 3:43 PM
> To: Moger, Babu <Babu.Moger@amd.com>
> Cc: mst@redhat.com; marcel.apfelbaum@gmail.com; pbonzini@redhat.com;
> rth@twiddle.net; qemu-devel@nongnu.org
> Subject: Re: [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model
>
> On Tue, Nov 05, 2019 at 09:17:30PM +0000, Moger, Babu wrote:
> > Adds the following missing CPUID bits:
> > perfctr-core : core performance counter extensions support. Enables the VM
> > to use extended performance counter support. It enables six
> > programmable counters instead of 4 counters.
> > clzero : instruction zeroes out the 64 byte cache line specified in RAX.
> > xsaveerptr : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
> > pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
> > pointers.
> > ibpb : Indirect Branch Prediction Barrie.
> > xsaves : XSAVES, XRSTORS and IA32_XSS supported.
> >
> > Depends on:
> > 40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
> > 504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
> > 52297436199d ("kvm: svm: Update svm_xsaves_supported")
> >
> > Signed-off-by: Babu Moger <babu.moger@amd.com>
> > ---
> > hw/i386/pc.c | 8 +++++++-
> > target/i386/cpu.c | 11 +++++------
> > 2 files changed, 12 insertions(+), 7 deletions(-)
> >
> > diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> > index 51b72439b4..a72fe1db31 100644
> > --- a/hw/i386/pc.c
> > +++ b/hw/i386/pc.c
> > @@ -105,7 +105,13 @@ struct hpet_fw_config hpet_cfg = {.count =
> UINT8_MAX};
> > /* Physical Address of PVH entry point read from kernel ELF NOTE */
> > static size_t pvh_start_addr;
> >
> > -GlobalProperty pc_compat_4_1[] = {};
> > +GlobalProperty pc_compat_4_1[] = {
> > + { "EPYC" "-" TYPE_X86_CPU, "perfctr-core", "off" },
> > + { "EPYC" "-" TYPE_X86_CPU, "clzero", "off" },
> > + { "EPYC" "-" TYPE_X86_CPU, "xsaveerptr", "off" },
> > + { "EPYC" "-" TYPE_X86_CPU, "ibpb", "off" },
> > + { "EPYC" "-" TYPE_X86_CPU, "xsaves", "off" },
> > +};
>
> machine-type-based CPU compatibility was now replaced by
> versioned CPU models. Please use the X86CPUDefinition.versions
> field to add a new version of EPYC instead.
Ok. Did you mean like this commit below?
fd63c6d1a5f77d68 ("i386: Add Cascadelake-Server-v2 CPU model")
>
> > const size_t pc_compat_4_1_len = G_N_ELEMENTS(pc_compat_4_1);
> >
> > GlobalProperty pc_compat_4_0[] = {};
> > diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> > index 07cf562d89..71233e6310 100644
> > --- a/target/i386/cpu.c
> > +++ b/target/i386/cpu.c
> > @@ -3110,19 +3110,18 @@ static X86CPUDefinition builtin_x86_defs[] = {
> > CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
> > CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM
> |
> > CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
> > - CPUID_EXT3_TOPOEXT,
> > + CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
> > + .features[FEAT_8000_0008_EBX] =
> > + CPUID_8000_0008_EBX_CLZERO |
> CPUID_8000_0008_EBX_XSAVEERPTR |
> > + CPUID_8000_0008_EBX_IBPB,
> > .features[FEAT_7_0_EBX] =
> > CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
> CPUID_7_0_EBX_AVX2 |
> > CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 |
> CPUID_7_0_EBX_RDSEED |
> > CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP |
> CPUID_7_0_EBX_CLFLUSHOPT |
> > CPUID_7_0_EBX_SHA_NI,
> > - /* Missing: XSAVES (not supported by some Linux versions,
> > - * including v4.1 to v4.12).
> > - * KVM doesn't yet expose any XSAVES state save component.
> > - */
> > .features[FEAT_XSAVE] =
> > CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
> > - CPUID_XSAVE_XGETBV1,
> > + CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
> > .features[FEAT_6_EAX] =
> > CPUID_6_EAX_ARAT,
> > .features[FEAT_SVM] =
> >
>
> --
> Eduardo
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model
2019-11-06 0:16 ` Moger, Babu
@ 2019-11-06 0:32 ` Eduardo Habkost
0 siblings, 0 replies; 6+ messages in thread
From: Eduardo Habkost @ 2019-11-06 0:32 UTC (permalink / raw)
To: Moger, Babu; +Cc: pbonzini, rth, qemu-devel, mst
On Wed, Nov 06, 2019 at 12:16:53AM +0000, Moger, Babu wrote:
[...]
> > > diff --git a/hw/i386/pc.c b/hw/i386/pc.c
> > > index 51b72439b4..a72fe1db31 100644
> > > --- a/hw/i386/pc.c
> > > +++ b/hw/i386/pc.c
> > > @@ -105,7 +105,13 @@ struct hpet_fw_config hpet_cfg = {.count =
> > UINT8_MAX};
> > > /* Physical Address of PVH entry point read from kernel ELF NOTE */
> > > static size_t pvh_start_addr;
> > >
> > > -GlobalProperty pc_compat_4_1[] = {};
> > > +GlobalProperty pc_compat_4_1[] = {
> > > + { "EPYC" "-" TYPE_X86_CPU, "perfctr-core", "off" },
> > > + { "EPYC" "-" TYPE_X86_CPU, "clzero", "off" },
> > > + { "EPYC" "-" TYPE_X86_CPU, "xsaveerptr", "off" },
> > > + { "EPYC" "-" TYPE_X86_CPU, "ibpb", "off" },
> > > + { "EPYC" "-" TYPE_X86_CPU, "xsaves", "off" },
> > > +};
> >
> > machine-type-based CPU compatibility was now replaced by
> > versioned CPU models. Please use the X86CPUDefinition.versions
> > field to add a new version of EPYC instead.
>
> Ok. Did you mean like this commit below?
> fd63c6d1a5f77d68 ("i386: Add Cascadelake-Server-v2 CPU model")
Correct. Thanks!
--
Eduardo
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-11-06 0:33 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-05 21:17 [PATCH 0/2] Add support for 2nd generation AMD EPYC processors Moger, Babu
2019-11-05 21:17 ` [PATCH 1/2] i386: Add missing cpu feature bits in EPYC model Moger, Babu
2019-11-05 21:43 ` Eduardo Habkost
2019-11-06 0:16 ` Moger, Babu
2019-11-06 0:32 ` Eduardo Habkost
2019-11-05 21:17 ` [PATCH 2/2] i386: Add 2nd Generation AMD EPYC processors Moger, Babu
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