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From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org,
	Masami Hiramatsu <masami.hiramatsu@linaro.org>,
	Jassi Brar <jaswinder.singh@linaro.org>,
	Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Subject: [PATCH 1/2] PCI: uniphier: Set mode register to host mode
Date: Thu,  7 Nov 2019 13:58:14 +0900	[thread overview]
Message-ID: <1573102695-7018-1-git-send-email-hayashi.kunihiko@socionext.com> (raw)

In order to avoid effect of the initial mode depending on SoCs,
this patch sets the mode register to host(RC) mode.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/pci/controller/dwc/pcie-uniphier.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
index 3f30ee4..8fd7bad 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -33,6 +33,10 @@
 #define PCL_PIPEMON			0x0044
 #define PCL_PCLK_ALIVE			BIT(15)
 
+#define PCL_MODE			0x8000
+#define PCL_MODE_REGEN			BIT(8)
+#define PCL_MODE_REGVAL			BIT(0)
+
 #define PCL_APP_READY_CTRL		0x8008
 #define PCL_APP_LTSSM_ENABLE		BIT(0)
 
@@ -85,6 +89,12 @@ static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
 {
 	u32 val;
 
+	/* set RC MODE */
+	val = readl(priv->base + PCL_MODE);
+	val |= PCL_MODE_REGEN;
+	val &= ~PCL_MODE_REGVAL;
+	writel(val, priv->base + PCL_MODE);
+
 	/* use auxiliary power detection */
 	val = readl(priv->base + PCL_APP_PM0);
 	val |= PCL_SYS_AUX_PWR_DET;
-- 
2.7.4


WARNING: multiple messages have this Message-ID (diff)
From: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>
Cc: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>,
	Masami Hiramatsu <masami.hiramatsu@linaro.org>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	Jassi Brar <jaswinder.singh@linaro.org>,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 1/2] PCI: uniphier: Set mode register to host mode
Date: Thu,  7 Nov 2019 13:58:14 +0900	[thread overview]
Message-ID: <1573102695-7018-1-git-send-email-hayashi.kunihiko@socionext.com> (raw)

In order to avoid effect of the initial mode depending on SoCs,
this patch sets the mode register to host(RC) mode.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
---
 drivers/pci/controller/dwc/pcie-uniphier.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c
index 3f30ee4..8fd7bad 100644
--- a/drivers/pci/controller/dwc/pcie-uniphier.c
+++ b/drivers/pci/controller/dwc/pcie-uniphier.c
@@ -33,6 +33,10 @@
 #define PCL_PIPEMON			0x0044
 #define PCL_PCLK_ALIVE			BIT(15)
 
+#define PCL_MODE			0x8000
+#define PCL_MODE_REGEN			BIT(8)
+#define PCL_MODE_REGVAL			BIT(0)
+
 #define PCL_APP_READY_CTRL		0x8008
 #define PCL_APP_LTSSM_ENABLE		BIT(0)
 
@@ -85,6 +89,12 @@ static void uniphier_pcie_init_rc(struct uniphier_pcie_priv *priv)
 {
 	u32 val;
 
+	/* set RC MODE */
+	val = readl(priv->base + PCL_MODE);
+	val |= PCL_MODE_REGEN;
+	val &= ~PCL_MODE_REGVAL;
+	writel(val, priv->base + PCL_MODE);
+
 	/* use auxiliary power detection */
 	val = readl(priv->base + PCL_APP_PM0);
 	val |= PCL_SYS_AUX_PWR_DET;
-- 
2.7.4


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             reply	other threads:[~2019-11-07  4:59 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-11-07  4:58 Kunihiko Hayashi [this message]
2019-11-07  4:58 ` [PATCH 1/2] PCI: uniphier: Set mode register to host mode Kunihiko Hayashi
2019-11-07  4:58 ` [PATCH 2/2] PCI: uniphier: Add checking whether PERST# is deasserted Kunihiko Hayashi
2019-11-07  4:58   ` Kunihiko Hayashi
2019-11-07 10:02   ` Andrew Murray
2019-11-07 10:02     ` Andrew Murray
2019-11-07 11:52     ` Kunihiko Hayashi
2019-11-07 11:52       ` Kunihiko Hayashi
2019-11-07 12:46       ` Andrew Murray
2019-11-07 12:46         ` Andrew Murray
2019-11-08  7:30         ` Kunihiko Hayashi
2019-11-08  7:30           ` Kunihiko Hayashi
2019-11-08  9:59           ` Andrew Murray
2019-11-08  9:59             ` Andrew Murray
2019-11-21 16:47           ` Lorenzo Pieralisi
2019-11-21 16:47             ` Lorenzo Pieralisi
2019-11-22 11:53             ` Kunihiko Hayashi
2019-11-22 11:53               ` Kunihiko Hayashi
2019-12-04 10:05               ` Kunihiko Hayashi
2019-12-04 10:05                 ` Kunihiko Hayashi
2019-12-06  6:58                 ` Kishon Vijay Abraham I
2019-12-06  6:58                   ` Kishon Vijay Abraham I
2019-12-06  8:58                   ` Kunihiko Hayashi
2019-12-06  8:58                     ` Kunihiko Hayashi
2019-12-06  9:01                     ` Kishon Vijay Abraham I
2019-12-06  9:01                       ` Kishon Vijay Abraham I
2019-12-09  2:35                       ` Kunihiko Hayashi
2019-12-09  2:35                         ` Kunihiko Hayashi
2019-11-07  9:52 ` [PATCH 1/2] PCI: uniphier: Set mode register to host mode Andrew Murray
2019-11-07  9:52   ` Andrew Murray
2019-11-21 16:49 ` Lorenzo Pieralisi
2019-11-21 16:49   ` Lorenzo Pieralisi

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