From: Chris Wilson <chris@chris-wilson.co.uk>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH] drm/i915: Leave the aliasing-ppgtt size alone
Date: Thu, 07 Nov 2019 08:35:34 +0000 [thread overview]
Message-ID: <157311573445.26738.6578769117298044224@skylake-alporthouse-com> (raw)
In-Reply-To: <877e4cnl1s.fsf@gaia.fi.intel.com>
Quoting Mika Kuoppala (2019-11-07 08:32:47)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > The hidden aliasing-ppgtt's size is never revealed, as we only inspect
> > the front GTT when engaged. However, we were "fixing" the hidden ppgtt
> > to match, with the net result that we ended up leaking the unused
> > portion (on Braswell were we preallocated the entire range).
>
> On here I think that the comment is a bit misleading. We preallocate
> the pdps upfront, the va_ranges that the aliasing init does matches
> in size.
>
> As there is two types of 'preallocation' at play in here,
> the commit message should be amended to explicitly state that the top
> pdps leak.
You knew what I meant :-p
Easiest way would to be use gen8_preallocate_top_level_pdp() instead.
-Chris
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Intel-gfx@lists.freedesktop.org
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WARNING: multiple messages have this Message-ID (diff)
From: Chris Wilson <chris@chris-wilson.co.uk>
To: Mika Kuoppala <mika.kuoppala@linux.intel.com>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH] drm/i915: Leave the aliasing-ppgtt size alone
Date: Thu, 07 Nov 2019 08:35:34 +0000 [thread overview]
Message-ID: <157311573445.26738.6578769117298044224@skylake-alporthouse-com> (raw)
Message-ID: <20191107083534.9P0ue9XfI9MqwvPR4us97AAn72PB_F5D_UaA8CoPHtk@z> (raw)
In-Reply-To: <877e4cnl1s.fsf@gaia.fi.intel.com>
Quoting Mika Kuoppala (2019-11-07 08:32:47)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > The hidden aliasing-ppgtt's size is never revealed, as we only inspect
> > the front GTT when engaged. However, we were "fixing" the hidden ppgtt
> > to match, with the net result that we ended up leaking the unused
> > portion (on Braswell were we preallocated the entire range).
>
> On here I think that the comment is a bit misleading. We preallocate
> the pdps upfront, the va_ranges that the aliasing init does matches
> in size.
>
> As there is two types of 'preallocation' at play in here,
> the commit message should be amended to explicitly state that the top
> pdps leak.
You knew what I meant :-p
Easiest way would to be use gen8_preallocate_top_level_pdp() instead.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
next prev parent reply other threads:[~2019-11-07 8:35 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-06 22:12 [PATCH] drm/i915: Leave the aliasing-ppgtt size alone Chris Wilson
2019-11-06 22:12 ` [Intel-gfx] " Chris Wilson
2019-11-07 0:25 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-11-07 0:25 ` [Intel-gfx] " Patchwork
2019-11-07 8:32 ` [PATCH] " Mika Kuoppala
2019-11-07 8:32 ` [Intel-gfx] " Mika Kuoppala
2019-11-07 8:35 ` Chris Wilson [this message]
2019-11-07 8:35 ` Chris Wilson
2019-11-08 2:47 ` ✓ Fi.CI.IGT: success for " Patchwork
2019-11-08 2:47 ` [Intel-gfx] " Patchwork
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