[PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors

[PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors

[Moger, Babu]

The following series adds the support for 2nd generation AMD EPYC Processors
on qemu guests. The model display name for 2nd generation will be EPYC-Rome.

Also fixes few missed cpu feature bits in 1st generation EPYC models.

The Reference documents are available at
https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
https://www.amd.com/system/files/TechDocs/24594.pdf

---
v2: Used the versioned CPU models instead of machine-type-based CPU
    compatibility (commented by Eduardo).

Babu Moger (2):
      i386: Add missing cpu feature bits in EPYC model
      i386: Add 2nd Generation AMD EPYC processors


 target/i386/cpu.c |  119 +++++++++++++++++++++++++++++++++++++++++++++++++++--
 target/i386/cpu.h |    2 +
 2 files changed, 116 insertions(+), 5 deletions(-)

--

[PATCH v2 1/2] i386: Add missing cpu feature bits in EPYC model

[Moger, Babu]

Adds the following missing CPUID bits:
perfctr-core : core performance counter extensions support. Enables the VM
               to use extended performance counter support. It enables six
               programmable counters instead of 4 counters.
clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
               pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
               pointers.
ibpb         : Indirect Branch Prediction Barrie.
xsaves       : XSAVES, XRSTORS and IA32_XSS supported.

Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
52297436199d ("kvm: svm: Update svm_xsaves_supported")

These new features will be added in EPYC-v3. The -cpu help output after the change.
x86 EPYC-v1               AMD EPYC Processor
x86 EPYC-v2               AMD EPYC Processor (with IBPB)
x86 EPYC-v3               AMD EPYC Processor

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c |   17 +++++++++++++----
 1 file changed, 13 insertions(+), 4 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 07cf562d89..6b7b0f8a4b 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3116,10 +3116,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
             CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
             CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
             CPUID_7_0_EBX_SHA_NI,
-        /* Missing: XSAVES (not supported by some Linux versions,
-         * including v4.1 to v4.12).
-         * KVM doesn't yet expose any XSAVES state save component.
-         */
         .features[FEAT_XSAVE] =
             CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
             CPUID_XSAVE_XGETBV1,
@@ -3142,6 +3138,19 @@ static X86CPUDefinition builtin_x86_defs[] = {
                     { /* end of list */ }
                 }
             },
+            {
+                .version = 3,
+                .props = (PropValue[]) {
+                    { "ibpb", "on" },
+                    { "perfctr-core", "on" },
+                    { "clzero", "on" },
+                    { "xsaveerptr", "on" },
+                    { "xsaves", "on" },
+                    { "model-id",
+                      "AMD EPYC Processor" },
+                    { /* end of list */ }
+                }
+            },
             { /* end of list */ }
         }
     },

[PATCH v2 2/2] i386: Add 2nd Generation AMD EPYC processors

[Moger, Babu]

Adds the support for 2nd Gen AMD EPYC Processors. The model display
name will be EPYC-Rome.

Adds the following new feature bits on top of the feature bits from the
first generation EPYC models.
perfctr-core : core performance counter extensions support. Enables the VM to
               use extended performance counter support. It enables six
               programmable counters instead of four counters.
clzero       : instruction zeroes out the 64 byte cache line specified in RAX.
xsaveerptr   : XSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save error
               pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
               pointers.
wbnoinvd     : Write back and do not invalidate cache
ibpb         : Indirect Branch Prediction Barrier
amd-stibp    : Single Thread Indirect Branch Predictor
clwb         : Cache Line Write Back and Retain
xsaves       : XSAVES, XRSTORS and IA32_XSS support
rdpid        : Read Processor ID instruction support
umip         : User-Mode Instruction Prevention support

The  Reference documents are available at
https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
https://www.amd.com/system/files/TechDocs/24594.pdf

Depends on following kernel commits:
40bc47b08b6e ("kvm: x86: Enumerate support for CLZERO instruction")
504ce1954fba ("KVM: x86: Expose XSAVEERPTR to the guest")
6d61e3c32248 ("kvm: x86: Expose RDPID in KVM_GET_SUPPORTED_CPUID")
52297436199d ("kvm: svm: Update svm_xsaves_supported")

Signed-off-by: Babu Moger <babu.moger@amd.com>
---
 target/i386/cpu.c |  102 ++++++++++++++++++++++++++++++++++++++++++++++++++++-
 target/i386/cpu.h |    2 +
 2 files changed, 103 insertions(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6b7b0f8a4b..70afc3fb30 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -1133,7 +1133,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
             "clzero", NULL, "xsaveerptr", NULL,
             NULL, NULL, NULL, NULL,
             NULL, "wbnoinvd", NULL, NULL,
-            "ibpb", NULL, NULL, NULL,
+            "ibpb", NULL, NULL, "amd-stibp",
             NULL, NULL, NULL, NULL,
             NULL, NULL, NULL, NULL,
             "amd-ssbd", "virt-ssbd", "amd-no-ssb", NULL,
@@ -1796,6 +1796,56 @@ static CPUCaches epyc_cache_info = {
     },
 };
 
+static CPUCaches epyc_rome_cache_info = {
+    .l1d_cache = &(CPUCacheInfo) {
+        .type = DATA_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l1i_cache = &(CPUCacheInfo) {
+        .type = INSTRUCTION_CACHE,
+        .level = 1,
+        .size = 32 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 64,
+        .lines_per_tag = 1,
+        .self_init = 1,
+        .no_invd_sharing = true,
+    },
+    .l2_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 2,
+        .size = 512 * KiB,
+        .line_size = 64,
+        .associativity = 8,
+        .partitions = 1,
+        .sets = 1024,
+        .lines_per_tag = 1,
+    },
+    .l3_cache = &(CPUCacheInfo) {
+        .type = UNIFIED_CACHE,
+        .level = 3,
+        .size = 16 * MiB,
+        .line_size = 64,
+        .associativity = 16,
+        .partitions = 1,
+        .sets = 16384,
+        .lines_per_tag = 1,
+        .self_init = true,
+        .inclusive = true,
+        .complex_indexing = true,
+    },
+};
+
 static X86CPUDefinition builtin_x86_defs[] = {
     {
         .name = "qemu64",
@@ -3204,6 +3254,56 @@ static X86CPUDefinition builtin_x86_defs[] = {
         .model_id = "Hygon Dhyana Processor",
         .cache_info = &epyc_cache_info,
     },
+    {
+        .name = "EPYC-Rome",
+        .level = 0xd,
+        .vendor = CPUID_VENDOR_AMD,
+        .family = 23,
+        .model = 49,
+        .stepping = 0,
+        .features[FEAT_1_EDX] =
+            CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH |
+            CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | CPUID_PGE |
+            CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 | CPUID_MCE |
+            CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE | CPUID_DE |
+            CPUID_VME | CPUID_FP87,
+        .features[FEAT_1_ECX] =
+            CPUID_EXT_RDRAND | CPUID_EXT_F16C | CPUID_EXT_AVX |
+            CPUID_EXT_XSAVE | CPUID_EXT_AES |  CPUID_EXT_POPCNT |
+            CPUID_EXT_MOVBE | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
+            CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 |
+            CPUID_EXT_MONITOR | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
+        .features[FEAT_8000_0001_EDX] =
+            CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB |
+            CPUID_EXT2_FFXSR | CPUID_EXT2_MMXEXT | CPUID_EXT2_NX |
+            CPUID_EXT2_SYSCALL,
+        .features[FEAT_8000_0001_ECX] =
+            CPUID_EXT3_OSVW | CPUID_EXT3_3DNOWPREFETCH |
+            CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM |
+            CPUID_EXT3_CR8LEG | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM |
+            CPUID_EXT3_TOPOEXT | CPUID_EXT3_PERFCORE,
+        .features[FEAT_8000_0008_EBX] =
+            CPUID_8000_0008_EBX_CLZERO | CPUID_8000_0008_EBX_XSAVEERPTR |
+            CPUID_8000_0008_EBX_WBNOINVD | CPUID_8000_0008_EBX_IBPB |
+            CPUID_8000_0008_EBX_STIBP,
+        .features[FEAT_7_0_EBX] =
+            CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_AVX2 |
+            CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_RDSEED |
+            CPUID_7_0_EBX_ADX | CPUID_7_0_EBX_SMAP | CPUID_7_0_EBX_CLFLUSHOPT |
+            CPUID_7_0_EBX_SHA_NI | CPUID_7_0_EBX_CLWB,
+        .features[FEAT_7_0_ECX] =
+            CPUID_7_0_ECX_UMIP | CPUID_7_0_ECX_RDPID,
+        .features[FEAT_XSAVE] =
+            CPUID_XSAVE_XSAVEOPT | CPUID_XSAVE_XSAVEC |
+            CPUID_XSAVE_XGETBV1 | CPUID_XSAVE_XSAVES,
+        .features[FEAT_6_EAX] =
+            CPUID_6_EAX_ARAT,
+        .features[FEAT_SVM] =
+            CPUID_SVM_NPT | CPUID_SVM_NRIPSAVE,
+        .xlevel = 0x8000001E,
+        .model_id = "AMD EPYC-Rome Processor",
+        .cache_info = &epyc_rome_cache_info,
+    },
 };
 
 /* KVM-specific features that are automatically added/removed
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index af57fda8e5..24cdca5d3f 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -781,6 +781,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
 #define CPUID_8000_0008_EBX_WBNOINVD    (1U << 9)
 /* Indirect Branch Prediction Barrier */
 #define CPUID_8000_0008_EBX_IBPB        (1U << 12)
+/* Single Thread Indirect Branch Predictors */
+#define CPUID_8000_0008_EBX_STIBP       (1U << 15)
 
 #define CPUID_XSAVE_XSAVEOPT   (1U << 0)
 #define CPUID_XSAVE_XSAVEC     (1U << 1)

Re: [PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors

[Liang Yan]

Kindly Ping.
Just wondering if there are any plans for it.

Best,
Liang


On 11/7/19 1:00 PM, Moger, Babu wrote:
> The following series adds the support for 2nd generation AMD EPYC Processors
> on qemu guests. The model display name for 2nd generation will be EPYC-Rome.
> 
> Also fixes few missed cpu feature bits in 1st generation EPYC models.
> 
> The Reference documents are available at
> https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
> https://www.amd.com/system/files/TechDocs/24594.pdf
> 
> ---
> v2: Used the versioned CPU models instead of machine-type-based CPU
>     compatibility (commented by Eduardo).
> 
> Babu Moger (2):
>       i386: Add missing cpu feature bits in EPYC model
>       i386: Add 2nd Generation AMD EPYC processors
> 
> 
>  target/i386/cpu.c |  119 +++++++++++++++++++++++++++++++++++++++++++++++++++--
>  target/i386/cpu.h |    2 +
>  2 files changed, 116 insertions(+), 5 deletions(-)
> 
> --
> 

Re: [PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors

[Babu Moger]

On 1/7/20 12:47 PM, Liang Yan wrote:
> Kindly Ping.
> Just wondering if there are any plans for it.

Yes. Waiting for the feedback or acceptance. Probably delay is due to
December holidays. Hopefully all are back now.

> 
> Best,
> Liang
> 
> 
> On 11/7/19 1:00 PM, Moger, Babu wrote:
>> The following series adds the support for 2nd generation AMD EPYC Processors
>> on qemu guests. The model display name for 2nd generation will be EPYC-Rome.
>>
>> Also fixes few missed cpu feature bits in 1st generation EPYC models.
>>
>> The Reference documents are available at
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fdeveloper.amd.com%2Fwp-content%2Fresources%2F55803_0.54-PUB.pdf&data=02%7C01%7CBabu.Moger%40amd.com%7C139e73eeb64b47cd381e08d793a3db70%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637140204317280432&sdata=Mmdaa9miW4aiuDcCAaMfI8zOOYSC7oTFmZurr7tIc%2BE%3D&reserved=0
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.amd.com%2Fsystem%2Ffiles%2FTechDocs%2F24594.pdf&data=02%7C01%7CBabu.Moger%40amd.com%7C139e73eeb64b47cd381e08d793a3db70%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637140204317280432&sdata=52%2BseLs2VpNsBMblsC4BI7S0Kz5D%2FoOoqUMNd48NHK0%3D&reserved=0
>>
>> ---
>> v2: Used the versioned CPU models instead of machine-type-based CPU
>>     compatibility (commented by Eduardo).
>>
>> Babu Moger (2):
>>       i386: Add missing cpu feature bits in EPYC model
>>       i386: Add 2nd Generation AMD EPYC processors
>>
>>
>>  target/i386/cpu.c |  119 +++++++++++++++++++++++++++++++++++++++++++++++++++--
>>  target/i386/cpu.h |    2 +
>>  2 files changed, 116 insertions(+), 5 deletions(-)
>>
>> --
>>

Re: [PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors

[Babu Moger]

Its been a while. Pinging again.  Please review.

On 11/7/19 12:00 PM, Moger, Babu wrote:
> The following series adds the support for 2nd generation AMD EPYC Processors
> on qemu guests. The model display name for 2nd generation will be EPYC-Rome.
> 
> Also fixes few missed cpu feature bits in 1st generation EPYC models.
> 
> The Reference documents are available at
> https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
> https://www.amd.com/system/files/TechDocs/24594.pdf
> 
> ---
> v2: Used the versioned CPU models instead of machine-type-based CPU
>     compatibility (commented by Eduardo).
> 
> Babu Moger (2):
>       i386: Add missing cpu feature bits in EPYC model
>       i386: Add 2nd Generation AMD EPYC processors
> 
> 
>  target/i386/cpu.c |  119 +++++++++++++++++++++++++++++++++++++++++++++++++++--
>  target/i386/cpu.h |    2 +
>  2 files changed, 116 insertions(+), 5 deletions(-)
> 
> --
> 

Re: [PATCH v2 0/2] Add support for 2nd generation AMD EPYC processors

[Eduardo Habkost]

On Thu, Nov 07, 2019 at 06:00:51PM +0000, Moger, Babu wrote:
> The following series adds the support for 2nd generation AMD EPYC Processors
> on qemu guests. The model display name for 2nd generation will be EPYC-Rome.
> 
> Also fixes few missed cpu feature bits in 1st generation EPYC models.
> 
> The Reference documents are available at
> https://developer.amd.com/wp-content/resources/55803_0.54-PUB.pdf
> https://www.amd.com/system/files/TechDocs/24594.pdf

Queued, thanks and sorry for taking so long to handle this.

-- 
Eduardo