* [PATCH 1/2] clk: imx: sccg: use relaxed io api
@ 2019-11-13 10:02 ` Peng Fan
0 siblings, 0 replies; 4+ messages in thread
From: Peng Fan @ 2019-11-13 10:02 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, Abel Vesa
Cc: kernel, dl-linux-imx, Aisheng Dong, linux-clk, linux-arm-kernel,
linux-kernel, Leonard Crestez, Alice Guo, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
It is ok to use relaxed api here, no need to use stronger readl/writel
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-sccg-pll.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 2cf874813458..e03f8acb1e82 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -106,8 +106,9 @@ static int clk_sccg_pll_wait_lock(struct clk_sccg_pll *pll)
/* don't wait for lock if all plls are bypassed */
if (!(val & SSCG_PLL_BYPASS2_MASK))
- return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
- 0, PLL_SCCG_LOCK_TIMEOUT);
+ return readl_relaxed_poll_timeout(pll->base, val,
+ val & PLL_LOCK_MASK,
+ 0, PLL_SCCG_LOCK_TIMEOUT);
return 0;
}
@@ -349,7 +350,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
temp64 = parent_rate;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK) {
temp64 = parent_rate;
} else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -372,10 +373,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
u32 val;
/* set bypass here too since the parent might be the same */
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
val = readl_relaxed(pll->base + PLL_CFG2);
val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -396,7 +397,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
u32 val;
u8 ret = pll->parent;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK)
ret = pll->bypass2;
else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -409,10 +410,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
u32 val;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
return clk_sccg_pll_wait_lock(pll);
}
--
2.16.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 1/2] clk: imx: sccg: use relaxed io api
@ 2019-11-13 10:02 ` Peng Fan
0 siblings, 0 replies; 4+ messages in thread
From: Peng Fan @ 2019-11-13 10:02 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, Abel Vesa
Cc: Aisheng Dong, Peng Fan, Alice Guo, linux-kernel, dl-linux-imx,
kernel, Leonard Crestez, linux-clk, linux-arm-kernel
From: Peng Fan <peng.fan@nxp.com>
It is ok to use relaxed api here, no need to use stronger readl/writel
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-sccg-pll.c | 17 +++++++++--------
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 2cf874813458..e03f8acb1e82 100644
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -106,8 +106,9 @@ static int clk_sccg_pll_wait_lock(struct clk_sccg_pll *pll)
/* don't wait for lock if all plls are bypassed */
if (!(val & SSCG_PLL_BYPASS2_MASK))
- return readl_poll_timeout(pll->base, val, val & PLL_LOCK_MASK,
- 0, PLL_SCCG_LOCK_TIMEOUT);
+ return readl_relaxed_poll_timeout(pll->base, val,
+ val & PLL_LOCK_MASK,
+ 0, PLL_SCCG_LOCK_TIMEOUT);
return 0;
}
@@ -349,7 +350,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
temp64 = parent_rate;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK) {
temp64 = parent_rate;
} else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -372,10 +373,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
u32 val;
/* set bypass here too since the parent might be the same */
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
val = readl_relaxed(pll->base + PLL_CFG2);
val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -396,7 +397,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
u32 val;
u8 ret = pll->parent;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
if (val & SSCG_PLL_BYPASS2_MASK)
ret = pll->bypass2;
else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -409,10 +410,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
u32 val;
- val = readl(pll->base + PLL_CFG0);
+ val = readl_relaxed(pll->base + PLL_CFG0);
val &= ~SSCG_PLL_BYPASS_MASK;
val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
- writel(val, pll->base + PLL_CFG0);
+ writel_relaxed(val, pll->base + PLL_CFG0);
return clk_sccg_pll_wait_lock(pll);
}
--
2.16.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: imx: composite-8m: use relaxed io api
2019-11-13 10:02 ` Peng Fan
@ 2019-11-13 10:02 ` Peng Fan
-1 siblings, 0 replies; 4+ messages in thread
From: Peng Fan @ 2019-11-13 10:02 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, Abel Vesa
Cc: kernel, dl-linux-imx, Aisheng Dong, linux-clk, linux-arm-kernel,
linux-kernel, Leonard Crestez, Alice Guo, Peng Fan
From: Peng Fan <peng.fan@nxp.com>
It is ok to use relaxed api here, no need to use stronger readl/writel
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-composite-8m.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 20f7c91c03d2..513dc57483d0 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -31,14 +31,14 @@ static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
unsigned int prediv_value;
unsigned int div_value;
- prediv_value = readl(divider->reg) >> divider->shift;
+ prediv_value = readl_relaxed(divider->reg) >> divider->shift;
prediv_value &= clk_div_mask(divider->width);
prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
NULL, divider->flags,
divider->width);
- div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value = readl_relaxed(divider->reg) >> PCG_DIV_SHIFT;
div_value &= clk_div_mask(PCG_DIV_WIDTH);
return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
@@ -104,13 +104,13 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
spin_lock_irqsave(divider->lock, flags);
- val = readl(divider->reg);
+ val = readl_relaxed(divider->reg);
val &= ~((clk_div_mask(divider->width) << divider->shift) |
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
val |= (u32)(prediv_value - 1) << divider->shift;
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
- writel(val, divider->reg);
+ writel_relaxed(val, divider->reg);
spin_unlock_irqrestore(divider->lock, flags);
--
2.16.4
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH 2/2] clk: imx: composite-8m: use relaxed io api
@ 2019-11-13 10:02 ` Peng Fan
0 siblings, 0 replies; 4+ messages in thread
From: Peng Fan @ 2019-11-13 10:02 UTC (permalink / raw)
To: sboyd, shawnguo, s.hauer, festevam, Abel Vesa
Cc: Aisheng Dong, Peng Fan, Alice Guo, linux-kernel, dl-linux-imx,
kernel, Leonard Crestez, linux-clk, linux-arm-kernel
From: Peng Fan <peng.fan@nxp.com>
It is ok to use relaxed api here, no need to use stronger readl/writel
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---
drivers/clk/imx/clk-composite-8m.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/clk/imx/clk-composite-8m.c b/drivers/clk/imx/clk-composite-8m.c
index 20f7c91c03d2..513dc57483d0 100644
--- a/drivers/clk/imx/clk-composite-8m.c
+++ b/drivers/clk/imx/clk-composite-8m.c
@@ -31,14 +31,14 @@ static unsigned long imx8m_clk_composite_divider_recalc_rate(struct clk_hw *hw,
unsigned int prediv_value;
unsigned int div_value;
- prediv_value = readl(divider->reg) >> divider->shift;
+ prediv_value = readl_relaxed(divider->reg) >> divider->shift;
prediv_value &= clk_div_mask(divider->width);
prediv_rate = divider_recalc_rate(hw, parent_rate, prediv_value,
NULL, divider->flags,
divider->width);
- div_value = readl(divider->reg) >> PCG_DIV_SHIFT;
+ div_value = readl_relaxed(divider->reg) >> PCG_DIV_SHIFT;
div_value &= clk_div_mask(PCG_DIV_WIDTH);
return divider_recalc_rate(hw, prediv_rate, div_value, NULL,
@@ -104,13 +104,13 @@ static int imx8m_clk_composite_divider_set_rate(struct clk_hw *hw,
spin_lock_irqsave(divider->lock, flags);
- val = readl(divider->reg);
+ val = readl_relaxed(divider->reg);
val &= ~((clk_div_mask(divider->width) << divider->shift) |
(clk_div_mask(PCG_DIV_WIDTH) << PCG_DIV_SHIFT));
val |= (u32)(prediv_value - 1) << divider->shift;
val |= (u32)(div_value - 1) << PCG_DIV_SHIFT;
- writel(val, divider->reg);
+ writel_relaxed(val, divider->reg);
spin_unlock_irqrestore(divider->lock, flags);
--
2.16.4
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 4+ messages in thread
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2019-11-13 10:02 [PATCH 1/2] clk: imx: sccg: use relaxed io api Peng Fan
2019-11-13 10:02 ` Peng Fan
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2019-11-13 10:02 ` Peng Fan
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