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* [PATCH v12 0/2] Refactor Gen11+ SAGV support
@ 2019-11-15 14:53 ` Stanislav Lisovskiy
  0 siblings, 0 replies; 23+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-15 14:53 UTC (permalink / raw)
  To: intel-gfx

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

Stanislav Lisovskiy (2):
  drm/i915: Refactor intel_can_enable_sagv
  drm/i915: Restrict qgv points which don't have enough bandwidth.

 drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c       | 134 +++++-
 drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  | 103 ++++-
 .../drm/i915/display/intel_display_types.h    |  18 +
 drivers/gpu/drm/i915/i915_drv.h               |  13 +-
 drivers/gpu/drm/i915/i915_reg.h               |   5 +
 drivers/gpu/drm/i915/intel_pm.c               | 418 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   1 +
 drivers/gpu/drm/i915/intel_sideband.c         |  27 +-
 10 files changed, 650 insertions(+), 73 deletions(-)

-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v12 0/2] Refactor Gen11+ SAGV support
@ 2019-11-15 14:53 ` Stanislav Lisovskiy
  0 siblings, 0 replies; 23+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-15 14:53 UTC (permalink / raw)
  To: intel-gfx

For Gen11+ platforms BSpec suggests disabling specific
QGV points separately, depending on bandwidth limitations
and current display configuration. Thus it required adding
a new PCode request for disabling QGV points and some
refactoring of already existing SAGV code.
Also had to refactor intel_can_enable_sagv function,
as current seems to be outdated and using skl specific
workarounds, also not following BSpec for Gen11+.

Stanislav Lisovskiy (2):
  drm/i915: Refactor intel_can_enable_sagv
  drm/i915: Restrict qgv points which don't have enough bandwidth.

 drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c       | 134 +++++-
 drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  | 103 ++++-
 .../drm/i915/display/intel_display_types.h    |  18 +
 drivers/gpu/drm/i915/i915_drv.h               |  13 +-
 drivers/gpu/drm/i915/i915_reg.h               |   5 +
 drivers/gpu/drm/i915/intel_pm.c               | 418 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   1 +
 drivers/gpu/drm/i915/intel_sideband.c         |  27 +-
 10 files changed, 650 insertions(+), 73 deletions(-)

-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-15 14:54   ` Stanislav Lisovskiy
  0 siblings, 0 replies; 23+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-15 14:54 UTC (permalink / raw)
  To: intel-gfx

Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.

v2:
    - Rework watermark calculation algorithm to
      attempt to calculate Level 0 watermark
      with added sagv block time latency and
      check if it fits in DBuf in order to
      determine if SAGV can be enabled already
      at this stage, just as BSpec 49325 states.
      if that fails rollback to usual Level 0
      latency and disable SAGV.
    - Remove unneeded tabs(James Ausmus)

v3: Rebased the patch

v4: - Added back interlaced check for Gen12 and
      added separate function for TGL SAGV check
      (thanks to James Ausmus for spotting)
    - Removed unneeded gen check
    - Extracted Gen12 SAGV decision making code
      to a separate function from skl_compute_wm

v5: - Added SAGV global state to dev_priv, because
      we need to track all pipes, not only those
      in atomic state. Each pipe has now correspondent
      bit mask reflecting, whether it can tolerate
      SAGV or not(thanks to Ville Syrjala for suggestions).
    - Now using active flag instead of enable in crc
      usage check.

v6: - Fixed rebase conflicts

v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
      calls when copying level 0 water marks for enabled SAGV, to
      fix this now simply using that field right away, without copying,
      for that introduced a new wm_level accessor which decides which
      wm_level to return based on SAGV state.

v8: - Protect crtc_sagv_mask same way as we do for other global state
      changes: i.e check if changes are needed, then grab all crtc locks
      to serialize the changes.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
 .../drm/i915/display/intel_display_types.h    |  15 +
 drivers/gpu/drm/i915/i915_drv.h               |   6 +
 drivers/gpu/drm/i915/intel_pm.c               | 418 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   1 +
 5 files changed, 409 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adf50c4b38ad..7f31e33d0b16 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13401,7 +13401,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
@@ -13453,7 +13456,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
@@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 							      new_crtc_state);
 	}
 
+	dev_priv->crtc_sagv_mask = state->crtc_sagv_mask;
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		intel_post_plane_update(old_crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..6a300cac883f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,20 @@ struct intel_atomic_state {
 	 */
 	u8 active_pipe_changes;
 
+	/*
+	 * Contains a mask which reflects whether correspondent pipe
+	 * can tolerate SAGV or not, so that we can make a decision
+	 * at atomic_commit_tail stage, whether we enable it or not
+	 * based on global state in dev_priv.
+	 */
+	u32 crtc_sagv_mask;
+
+	/*
+	 * Used to determine if the mask has been already calculated
+	 * for this state, to avoid unnecessary calculations.
+	 */
+	bool crtc_sagv_mask_set;
+
 	u8 active_pipes;
 	/* minimum acceptable cdclk for each pipe */
 	int min_cdclk[I915_MAX_PIPES];
@@ -670,6 +684,7 @@ struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
+	struct skl_wm_level sagv_wm0;
 	bool is_planar;
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1779f600fcfb..0ac9d7b006ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1171,6 +1171,12 @@ struct drm_i915_private {
 
 	u32 sagv_block_time_us;
 
+	/*
+	 * Contains a bit mask, whether correspondent
+	 * pipe allows SAGV or not.
+	 */
+	u32 crtc_sagv_mask;
+
 	struct {
 		/*
 		 * Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 05ba9e1bd247..c914bd1862ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
 }
 
-static bool
+bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	/* HACK! */
-	if (IS_GEN(dev_priv, 12))
-		return false;
-
 	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
 		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
@@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static void skl_set_sagv_mask(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 	enum pipe pipe;
 	int level, latency;
 
+	if (state->crtc_sagv_mask_set)
+		return;
+
 	if (!intel_has_sagv(dev_priv))
-		return false;
+		return;
 
 	/*
 	 * If there are no active CRTCs, no additional checks need be performed
 	 */
 	if (hweight8(state->active_pipes) == 0)
-		return true;
+		return;
 
 	/*
 	 * SKL+ workaround: bspec recommends we disable SAGV when we have
 	 * more then one pipe enabled
 	 */
 	if (hweight8(state->active_pipes) > 1)
-		return false;
+		return;
 
 	/* Since we're now guaranteed to only have one active CRTC... */
 	pipe = ffs(state->active_pipes) - 1;
 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 	crtc_state = to_intel_crtc_state(crtc->base.state);
+	state->crtc_sagv_mask &= ~BIT(crtc->pipe);
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		return false;
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+		state->crtc_sagv_mask_set = true;
+		return;
+	}
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
 		struct skl_plane_wm *wm =
@@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 		 * incur memory latencies higher than sagv_block_time_us we
 		 * can't enable SAGV.
 		 */
-		if (latency < dev_priv->sagv_block_time_us)
+		if (latency < dev_priv->sagv_block_time_us) {
+			state->crtc_sagv_mask_set = true;
+			return;
+		}
+	}
+
+	state->crtc_sagv_mask |= BIT(crtc->pipe);
+	state->crtc_sagv_mask_set = true;
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_set_sagv_mask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	int level, latency;
+	int i;
+	int plane_id;
+
+	if (state->crtc_sagv_mask_set)
+		return;
+
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * If there are no active CRTCs, no additional checks need be performed
+	 */
+	if (hweight8(state->active_pipes) == 0)
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc,
+					     new_crtc_state, i) {
+		unsigned int flags = crtc->base.state->adjusted_mode.flags;
+		bool can_sagv;
+
+		if (flags & DRM_MODE_FLAG_INTERLACE)
+			continue;
+
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		can_sagv = true;
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			struct skl_plane_wm *wm =
+				&new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+			/* Skip this plane if it's not enabled */
+			if (!wm->wm[0].plane_en)
+				continue;
+
+			/* Find the highest enabled wm level for this plane */
+			for (level = ilk_wm_max_level(dev_priv);
+			     !wm->wm[level].plane_en; --level) {
+			}
+
+			latency = dev_priv->wm.skl_latency[level];
+
+			/*
+			 * If any of the planes on this pipe don't enable
+			 * wm levels that incur memory latencies higher than
+			 * sagv_block_time_us we can't enable SAGV.
+			 */
+			if (latency < dev_priv->sagv_block_time_us) {
+				can_sagv = false;
+				break;
+			}
+		}
+		if (can_sagv)
+			state->crtc_sagv_mask |= BIT(crtc->pipe);
+		else
+			state->crtc_sagv_mask &= ~BIT(crtc->pipe);
+	}
+	state->crtc_sagv_mask_set = true;
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret, i;
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+
+	/*
+	 * Make sure we always pick global state first,
+	 * there shouldn't be any issue as we hold only locks
+	 * to correspondent crtcs in state, however once
+	 * we detect that we need to change SAGV mask
+	 * in global state, we will grab all the crtc locks
+	 * in order to get this serialized, thus other
+	 * racing commits having other crtc locks, will have
+	 * to start over again, as stated by Wound-Wait
+	 * algorithm.
+	 */
+	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_set_sagv_mask(state);
+	else if (INTEL_GEN(dev_priv) == 11)
+		icl_set_sagv_mask(state);
+	else
+		skl_set_sagv_mask(state);
+
+	/*
+	 * For SAGV we need to account all the pipes,
+	 * not only the ones which are in state currently.
+	 * Grab all locks if we detect that we are actually
+	 * going to do something.
+	 */
+	if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) {
+		ret = intel_atomic_serialize_global_state(state);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return false;
+		}
+	}
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		u32 mask = BIT(crtc->pipe);
+		bool state_sagv_masked = (mask & state->crtc_sagv_mask) == 0;
+
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		if (state_sagv_masked)
 			return false;
 	}
 
@@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 				 int color_plane);
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
+				 u32 latency,
 				 const struct skl_wm_params *wp,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */);
@@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 	WARN_ON(ret);
 
 	for (level = 0; level <= max_level; level++) {
-		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+		u32 latency = dev_priv->wm.skl_latency[level];
+
+		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
 		if (wm.min_ddb_alloc == U16_MAX)
 			break;
 
@@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	return total_data_rate;
 }
 
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+			    struct skl_ddb_allocation *ddb /* out */)
+{
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+	u16 alloc_size;
+	u16 total[I915_MAX_PLANES] = {};
+	u64 total_data_rate;
+	enum plane_id plane_id;
+	int num_active;
+	u64 plane_data_rate[I915_MAX_PLANES] = {};
+	u32 blocks;
+
+	/*
+	 * No need to check gen here, we call this only for gen12
+	 */
+	total_data_rate =
+		icl_get_total_relative_data_rate(crtc_state,
+						 plane_data_rate);
+
+	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+					   total_data_rate,
+					   ddb, alloc, &num_active);
+	alloc_size = skl_ddb_entry_size(alloc);
+	if (alloc_size == 0)
+		return -ENOSPC;
+
+	/* Allocate fixed number of blocks for cursor. */
+	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+	alloc_size -= total[PLANE_CURSOR];
+	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+		alloc->end - total[PLANE_CURSOR];
+	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+
+	/*
+	 * Do check if we can fit L0 + sagv_block_time and
+	 * disable SAGV if we can't.
+	 */
+	blocks = 0;
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		const struct skl_plane_wm *wm =
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+
+		if (plane_id == PLANE_CURSOR) {
+			if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
+				    total[PLANE_CURSOR])) {
+				blocks = U32_MAX;
+				break;
+			}
+			continue;
+		}
+
+		blocks += wm->sagv_wm0.min_ddb_alloc;
+		if (blocks > alloc_size)
+			return -ENOSPC;
+	}
+	return 0;
+}
+
+const struct skl_wm_level *
+skl_plane_wm_level(struct intel_plane *plane,
+		const struct intel_crtc_state *crtc_state,
+		int level,
+		bool yuv)
+{
+	struct drm_atomic_state *state = crtc_state->uapi.state;
+	enum plane_id plane_id = plane->id;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+
+	/*
+	 * Looks ridicilous but need to check if state is not
+	 * NULL here as it might be as some cursor plane manipulations
+	 * seem to happen when no atomic state is actually present,
+	 * despite crtc_state is allocated. Removing state check
+	 * from here will result in kernel panic on boot.
+	 * However we now need to check whether should be use SAGV
+	 * wm levels here.
+	 */
+	if (state) {
+		struct intel_atomic_state *intel_state =
+			to_intel_atomic_state(state);
+		if (intel_can_enable_sagv(intel_state) && !level)
+			return &wm->sagv_wm0;
+	}
+
+	return yuv ? &wm->uv_wm[level] : &wm->wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		      struct skl_ddb_allocation *ddb /* out */)
@@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	u16 uv_total[I915_MAX_PLANES] = {};
 	u64 total_data_rate;
 	enum plane_id plane_id;
+	struct intel_plane *plane;
+	const struct skl_wm_level *wm_level;
+	const struct skl_wm_level *wm_uv_level;
 	int num_active;
 	u64 plane_data_rate[I915_MAX_PLANES] = {};
 	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
@@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	 */
 	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
 		blocks = 0;
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-			const struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
+		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+			plane_id = plane->id;
+			wm_level = skl_plane_wm_level(plane, crtc_state,
+						      level, false);
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+							 level, true);
 
 			if (plane_id == PLANE_CURSOR) {
-				if (WARN_ON(wm->wm[level].min_ddb_alloc >
+				if (WARN_ON(wm_level->min_ddb_alloc >
 					    total[PLANE_CURSOR])) {
 					blocks = U32_MAX;
 					break;
@@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 				continue;
 			}
 
-			blocks += wm->wm[level].min_ddb_alloc;
-			blocks += wm->uv_wm[level].min_ddb_alloc;
+			blocks += wm_level->min_ddb_alloc;
+			blocks += wm_uv_level->min_ddb_alloc;
 		}
 
 		if (blocks <= alloc_size) {
@@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	 * watermark level, plus an extra share of the leftover blocks
 	 * proportional to its relative data rate.
 	 */
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-		const struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane_id];
+	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
 		u64 rate;
 		u16 extra;
 
+		plane_id = plane->id;
+		wm_level = skl_plane_wm_level(plane, crtc_state,
+					      level, false);
+		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						 level, true);
+
 		if (plane_id == PLANE_CURSOR)
 			continue;
 
@@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+		total[plane_id] = wm_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 
@@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+		uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 	}
@@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	 * that aren't actually possible.
 	 */
 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
 			struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
+				&crtc_state->wm.skl.optimal.planes[plane->id];
+
+			wm_level = skl_plane_wm_level(plane, crtc_state,
+						      level, false);
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						      level, true);
 
 			/*
 			 * We only disable the watermarks for each plane if
@@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 			 *  planes must be enabled before the level will be used."
 			 * So this is actually safe to do.
 			 */
-			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
-			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
-				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+			if (wm_level->min_ddb_alloc > total[plane->id] ||
+			    wm_uv_level->min_ddb_alloc > uv_total[plane->id])
+				memset(&wm->wm[level], 0,
+				       sizeof(struct skl_wm_level));
 
 			/*
 			 * Wa_1408961008:icl, ehl
@@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 			 */
 			if (IS_GEN(dev_priv, 11) &&
 			    level == 1 && wm->wm[0].plane_en) {
-				wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
-				wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
-				wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+				wm_level = skl_plane_wm_level(plane, crtc_state,
+							      0, false);
+				wm->wm[level].plane_res_b =
+					wm_level->plane_res_b;
+				wm->wm[level].plane_res_l =
+					wm_level->plane_res_l;
+				wm->wm[level].ignore_lines =
+					wm_level->ignore_lines;
 			}
 		}
 	}
@@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
 
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
+				 u32 latency,
 				 const struct skl_wm_params *wp,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	u32 latency = dev_priv->wm.skl_latency[level];
 	uint_fixed_16_16_t method1, method2;
 	uint_fixed_16_16_t selected_result;
 	u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 static void
 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_wm_level *levels)
+		      struct skl_plane_wm *plane_wm,
+		      bool yuv)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
+	/*
+	 * Check which kind of plane is it and based on that calculate
+	 * correspondent WM levels.
+	 */
+	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
 	struct skl_wm_level *result_prev = &levels[0];
 
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
+		u32 latency = dev_priv->wm.skl_latency[level];
 
-		skl_compute_plane_wm(crtc_state, level, wm_params,
-				     result_prev, result);
+		skl_compute_plane_wm(crtc_state, level, latency,
+				     wm_params, result_prev, result);
 
 		result_prev = result;
 	}
+	/*
+	 * For Gen12 if it is an L0 we need to also
+	 * consider sagv_block_time when calculating
+	 * L0 watermark - we will need that when making
+	 * a decision whether enable SAGV or not.
+	 * For older gens we agreed to copy L0 value for
+	 * compatibility.
+	 */
+	if ((INTEL_GEN(dev_priv) >= 12)) {
+		u32 latency = dev_priv->wm.skl_latency[0];
+
+		latency += dev_priv->sagv_block_time_us;
+		skl_compute_plane_wm(crtc_state, 0, latency,
+		     wm_params, &levels[0],
+		    &plane_wm->sagv_wm0);
+	} else
+		memcpy(&plane_wm->sagv_wm0, &levels[0],
+			sizeof(struct skl_wm_level));
 }
 
 static u32
@@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
 	skl_compute_transition_wm(crtc_state, &wm_params, wm);
 
 	return 0;
@@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
 
 	return 0;
 }
@@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 	const struct skl_ddb_entry *ddb_uv =
 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+	const struct skl_wm_level *wm_level;
 
 	for (level = 0; level <= max_level; level++) {
+		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
@@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.optimal.planes[plane_id];
 	const struct skl_ddb_entry *ddb =
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+	const struct skl_wm_level *wm_level;
 
 	for (level = 0; level <= max_level; level++) {
+		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
@@ -5451,18 +5729,73 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 	return 0;
 }
 
+static void tgl_set_sagv_mask(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc_state *old_crtc_state;
+	struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+	int ret;
+	int i;
+	struct intel_plane *plane;
+
+	if (state->crtc_sagv_mask_set)
+		return;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		int pipe_bit = BIT(crtc->pipe);
+		bool skip = true;
+
+		/*
+		 * If we had set this mast already once for this state,
+		 * no need to waste CPU cycles for doing this again.
+		 */
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
+
+			if (!skl_plane_wm_equals(dev_priv,
+				&old_crtc_state->wm.skl.optimal.planes[plane_id],
+				&new_crtc_state->wm.skl.optimal.planes[plane_id])) {
+				skip = false;
+				break;
+			}
+		}
+
+		/*
+		 * Check if wm levels are actually the same as for previous
+		 * state, which means we can just skip doing this long check
+		 * and just  copy correspondent bit from previous state.
+		 */
+		if (skip)
+			continue;
+
+		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+		if (!ret)
+			state->crtc_sagv_mask |= pipe_bit;
+		else
+			state->crtc_sagv_mask &= ~pipe_bit;
+	}
+	state->crtc_sagv_mask_set = true;
+}
+
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
 	struct intel_crtc *crtc;
 	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc_state *old_crtc_state;
-	struct skl_ddb_values *results = &state->wm_results;
 	int ret, i;
+	struct skl_ddb_values *results = &state->wm_results;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 
 	/* Clear all dirty flags */
 	results->dirty_pipes = 0;
 
+	/* If we exit before check is done */
+	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
+
 	ret = skl_ddb_add_affected_pipes(state);
 	if (ret)
 		return ret;
@@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
+			if (level == 0)
+				memcpy(&wm->sagv_wm0, &wm->wm[level],
+					sizeof(struct skl_wm_level));
 		}
 
 		if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..53275860731a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-15 14:54   ` Stanislav Lisovskiy
  0 siblings, 0 replies; 23+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-15 14:54 UTC (permalink / raw)
  To: intel-gfx

Currently intel_can_enable_sagv function contains
a mix of workarounds for different platforms
some of them are not valid for gens >= 11 already,
so lets split it into separate functions.

v2:
    - Rework watermark calculation algorithm to
      attempt to calculate Level 0 watermark
      with added sagv block time latency and
      check if it fits in DBuf in order to
      determine if SAGV can be enabled already
      at this stage, just as BSpec 49325 states.
      if that fails rollback to usual Level 0
      latency and disable SAGV.
    - Remove unneeded tabs(James Ausmus)

v3: Rebased the patch

v4: - Added back interlaced check for Gen12 and
      added separate function for TGL SAGV check
      (thanks to James Ausmus for spotting)
    - Removed unneeded gen check
    - Extracted Gen12 SAGV decision making code
      to a separate function from skl_compute_wm

v5: - Added SAGV global state to dev_priv, because
      we need to track all pipes, not only those
      in atomic state. Each pipe has now correspondent
      bit mask reflecting, whether it can tolerate
      SAGV or not(thanks to Ville Syrjala for suggestions).
    - Now using active flag instead of enable in crc
      usage check.

v6: - Fixed rebase conflicts

v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
      calls when copying level 0 water marks for enabled SAGV, to
      fix this now simply using that field right away, without copying,
      for that introduced a new wm_level accessor which decides which
      wm_level to return based on SAGV state.

v8: - Protect crtc_sagv_mask same way as we do for other global state
      changes: i.e check if changes are needed, then grab all crtc locks
      to serialize the changes.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
 .../drm/i915/display/intel_display_types.h    |  15 +
 drivers/gpu/drm/i915/i915_drv.h               |   6 +
 drivers/gpu/drm/i915/intel_pm.c               | 418 ++++++++++++++++--
 drivers/gpu/drm/i915/intel_pm.h               |   1 +
 5 files changed, 409 insertions(+), 43 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index adf50c4b38ad..7f31e33d0b16 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13401,7 +13401,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
@@ -13453,7 +13456,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
 		/* Watermarks */
 		for (level = 0; level <= max_level; level++) {
 			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
-						&sw_plane_wm->wm[level]))
+						&sw_plane_wm->wm[level]) ||
+			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
+						&sw_plane_wm->sagv_wm0) &&
+			   (level == 0)))
 				continue;
 
 			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
@@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 							      new_crtc_state);
 	}
 
+	dev_priv->crtc_sagv_mask = state->crtc_sagv_mask;
+
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
 		intel_post_plane_update(old_crtc_state);
 
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 83ea04149b77..6a300cac883f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -490,6 +490,20 @@ struct intel_atomic_state {
 	 */
 	u8 active_pipe_changes;
 
+	/*
+	 * Contains a mask which reflects whether correspondent pipe
+	 * can tolerate SAGV or not, so that we can make a decision
+	 * at atomic_commit_tail stage, whether we enable it or not
+	 * based on global state in dev_priv.
+	 */
+	u32 crtc_sagv_mask;
+
+	/*
+	 * Used to determine if the mask has been already calculated
+	 * for this state, to avoid unnecessary calculations.
+	 */
+	bool crtc_sagv_mask_set;
+
 	u8 active_pipes;
 	/* minimum acceptable cdclk for each pipe */
 	int min_cdclk[I915_MAX_PIPES];
@@ -670,6 +684,7 @@ struct skl_plane_wm {
 	struct skl_wm_level wm[8];
 	struct skl_wm_level uv_wm[8];
 	struct skl_wm_level trans_wm;
+	struct skl_wm_level sagv_wm0;
 	bool is_planar;
 };
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 1779f600fcfb..0ac9d7b006ca 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1171,6 +1171,12 @@ struct drm_i915_private {
 
 	u32 sagv_block_time_us;
 
+	/*
+	 * Contains a bit mask, whether correspondent
+	 * pipe allows SAGV or not.
+	 */
+	u32 crtc_sagv_mask;
+
 	struct {
 		/*
 		 * Raw watermark latency values:
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 05ba9e1bd247..c914bd1862ba 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
 	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
 }
 
-static bool
+bool
 intel_has_sagv(struct drm_i915_private *dev_priv)
 {
-	/* HACK! */
-	if (IS_GEN(dev_priv, 12))
-		return false;
-
 	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
 		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
 }
@@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
 	return 0;
 }
 
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+static void skl_set_sagv_mask(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
 	struct drm_i915_private *dev_priv = to_i915(dev);
@@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 	enum pipe pipe;
 	int level, latency;
 
+	if (state->crtc_sagv_mask_set)
+		return;
+
 	if (!intel_has_sagv(dev_priv))
-		return false;
+		return;
 
 	/*
 	 * If there are no active CRTCs, no additional checks need be performed
 	 */
 	if (hweight8(state->active_pipes) == 0)
-		return true;
+		return;
 
 	/*
 	 * SKL+ workaround: bspec recommends we disable SAGV when we have
 	 * more then one pipe enabled
 	 */
 	if (hweight8(state->active_pipes) > 1)
-		return false;
+		return;
 
 	/* Since we're now guaranteed to only have one active CRTC... */
 	pipe = ffs(state->active_pipes) - 1;
 	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
 	crtc_state = to_intel_crtc_state(crtc->base.state);
+	state->crtc_sagv_mask &= ~BIT(crtc->pipe);
 
-	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
-		return false;
+	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
+		state->crtc_sagv_mask_set = true;
+		return;
+	}
 
 	for_each_intel_plane_on_crtc(dev, crtc, plane) {
 		struct skl_plane_wm *wm =
@@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
 		 * incur memory latencies higher than sagv_block_time_us we
 		 * can't enable SAGV.
 		 */
-		if (latency < dev_priv->sagv_block_time_us)
+		if (latency < dev_priv->sagv_block_time_us) {
+			state->crtc_sagv_mask_set = true;
+			return;
+		}
+	}
+
+	state->crtc_sagv_mask |= BIT(crtc->pipe);
+	state->crtc_sagv_mask_set = true;
+}
+
+static void tgl_set_sagv_mask(struct intel_atomic_state *state);
+
+static void icl_set_sagv_mask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	int level, latency;
+	int i;
+	int plane_id;
+
+	if (state->crtc_sagv_mask_set)
+		return;
+
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * If there are no active CRTCs, no additional checks need be performed
+	 */
+	if (hweight8(state->active_pipes) == 0)
+		return;
+
+	for_each_new_intel_crtc_in_state(state, crtc,
+					     new_crtc_state, i) {
+		unsigned int flags = crtc->base.state->adjusted_mode.flags;
+		bool can_sagv;
+
+		if (flags & DRM_MODE_FLAG_INTERLACE)
+			continue;
+
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		can_sagv = true;
+		for_each_plane_id_on_crtc(crtc, plane_id) {
+			struct skl_plane_wm *wm =
+				&new_crtc_state->wm.skl.optimal.planes[plane_id];
+
+			/* Skip this plane if it's not enabled */
+			if (!wm->wm[0].plane_en)
+				continue;
+
+			/* Find the highest enabled wm level for this plane */
+			for (level = ilk_wm_max_level(dev_priv);
+			     !wm->wm[level].plane_en; --level) {
+			}
+
+			latency = dev_priv->wm.skl_latency[level];
+
+			/*
+			 * If any of the planes on this pipe don't enable
+			 * wm levels that incur memory latencies higher than
+			 * sagv_block_time_us we can't enable SAGV.
+			 */
+			if (latency < dev_priv->sagv_block_time_us) {
+				can_sagv = false;
+				break;
+			}
+		}
+		if (can_sagv)
+			state->crtc_sagv_mask |= BIT(crtc->pipe);
+		else
+			state->crtc_sagv_mask &= ~BIT(crtc->pipe);
+	}
+	state->crtc_sagv_mask_set = true;
+}
+
+bool intel_can_enable_sagv(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret, i;
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+
+	/*
+	 * Make sure we always pick global state first,
+	 * there shouldn't be any issue as we hold only locks
+	 * to correspondent crtcs in state, however once
+	 * we detect that we need to change SAGV mask
+	 * in global state, we will grab all the crtc locks
+	 * in order to get this serialized, thus other
+	 * racing commits having other crtc locks, will have
+	 * to start over again, as stated by Wound-Wait
+	 * algorithm.
+	 */
+	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
+
+	if (INTEL_GEN(dev_priv) >= 12)
+		tgl_set_sagv_mask(state);
+	else if (INTEL_GEN(dev_priv) == 11)
+		icl_set_sagv_mask(state);
+	else
+		skl_set_sagv_mask(state);
+
+	/*
+	 * For SAGV we need to account all the pipes,
+	 * not only the ones which are in state currently.
+	 * Grab all locks if we detect that we are actually
+	 * going to do something.
+	 */
+	if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) {
+		ret = intel_atomic_serialize_global_state(state);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return false;
+		}
+	}
+
+	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+		u32 mask = BIT(crtc->pipe);
+		bool state_sagv_masked = (mask & state->crtc_sagv_mask) == 0;
+
+		if (!new_crtc_state->hw.active)
+			continue;
+
+		if (state_sagv_masked)
 			return false;
 	}
 
@@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
 				 int color_plane);
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
+				 u32 latency,
 				 const struct skl_wm_params *wp,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */);
@@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
 	WARN_ON(ret);
 
 	for (level = 0; level <= max_level; level++) {
-		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
+		u32 latency = dev_priv->wm.skl_latency[level];
+
+		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
+
 		if (wm.min_ddb_alloc == U16_MAX)
 			break;
 
@@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
 	return total_data_rate;
 }
 
+static int
+tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
+			    struct skl_ddb_allocation *ddb /* out */)
+{
+	struct drm_crtc *crtc = crtc_state->uapi.crtc;
+	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
+	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
+	u16 alloc_size;
+	u16 total[I915_MAX_PLANES] = {};
+	u64 total_data_rate;
+	enum plane_id plane_id;
+	int num_active;
+	u64 plane_data_rate[I915_MAX_PLANES] = {};
+	u32 blocks;
+
+	/*
+	 * No need to check gen here, we call this only for gen12
+	 */
+	total_data_rate =
+		icl_get_total_relative_data_rate(crtc_state,
+						 plane_data_rate);
+
+	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
+					   total_data_rate,
+					   ddb, alloc, &num_active);
+	alloc_size = skl_ddb_entry_size(alloc);
+	if (alloc_size == 0)
+		return -ENOSPC;
+
+	/* Allocate fixed number of blocks for cursor. */
+	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
+	alloc_size -= total[PLANE_CURSOR];
+	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
+		alloc->end - total[PLANE_CURSOR];
+	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
+
+	/*
+	 * Do check if we can fit L0 + sagv_block_time and
+	 * disable SAGV if we can't.
+	 */
+	blocks = 0;
+	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		const struct skl_plane_wm *wm =
+			&crtc_state->wm.skl.optimal.planes[plane_id];
+
+		if (plane_id == PLANE_CURSOR) {
+			if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
+				    total[PLANE_CURSOR])) {
+				blocks = U32_MAX;
+				break;
+			}
+			continue;
+		}
+
+		blocks += wm->sagv_wm0.min_ddb_alloc;
+		if (blocks > alloc_size)
+			return -ENOSPC;
+	}
+	return 0;
+}
+
+const struct skl_wm_level *
+skl_plane_wm_level(struct intel_plane *plane,
+		const struct intel_crtc_state *crtc_state,
+		int level,
+		bool yuv)
+{
+	struct drm_atomic_state *state = crtc_state->uapi.state;
+	enum plane_id plane_id = plane->id;
+	const struct skl_plane_wm *wm =
+		&crtc_state->wm.skl.optimal.planes[plane_id];
+
+	/*
+	 * Looks ridicilous but need to check if state is not
+	 * NULL here as it might be as some cursor plane manipulations
+	 * seem to happen when no atomic state is actually present,
+	 * despite crtc_state is allocated. Removing state check
+	 * from here will result in kernel panic on boot.
+	 * However we now need to check whether should be use SAGV
+	 * wm levels here.
+	 */
+	if (state) {
+		struct intel_atomic_state *intel_state =
+			to_intel_atomic_state(state);
+		if (intel_can_enable_sagv(intel_state) && !level)
+			return &wm->sagv_wm0;
+	}
+
+	return yuv ? &wm->uv_wm[level] : &wm->wm[level];
+}
+
 static int
 skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		      struct skl_ddb_allocation *ddb /* out */)
@@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	u16 uv_total[I915_MAX_PLANES] = {};
 	u64 total_data_rate;
 	enum plane_id plane_id;
+	struct intel_plane *plane;
+	const struct skl_wm_level *wm_level;
+	const struct skl_wm_level *wm_uv_level;
 	int num_active;
 	u64 plane_data_rate[I915_MAX_PLANES] = {};
 	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
@@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	 */
 	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
 		blocks = 0;
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-			const struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
+		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
+			plane_id = plane->id;
+			wm_level = skl_plane_wm_level(plane, crtc_state,
+						      level, false);
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+							 level, true);
 
 			if (plane_id == PLANE_CURSOR) {
-				if (WARN_ON(wm->wm[level].min_ddb_alloc >
+				if (WARN_ON(wm_level->min_ddb_alloc >
 					    total[PLANE_CURSOR])) {
 					blocks = U32_MAX;
 					break;
@@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 				continue;
 			}
 
-			blocks += wm->wm[level].min_ddb_alloc;
-			blocks += wm->uv_wm[level].min_ddb_alloc;
+			blocks += wm_level->min_ddb_alloc;
+			blocks += wm_uv_level->min_ddb_alloc;
 		}
 
 		if (blocks <= alloc_size) {
@@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	 * watermark level, plus an extra share of the leftover blocks
 	 * proportional to its relative data rate.
 	 */
-	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
-		const struct skl_plane_wm *wm =
-			&crtc_state->wm.skl.optimal.planes[plane_id];
+	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
 		u64 rate;
 		u16 extra;
 
+		plane_id = plane->id;
+		wm_level = skl_plane_wm_level(plane, crtc_state,
+					      level, false);
+		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						 level, true);
+
 		if (plane_id == PLANE_CURSOR)
 			continue;
 
@@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+		total[plane_id] = wm_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 
@@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 		extra = min_t(u16, alloc_size,
 			      DIV64_U64_ROUND_UP(alloc_size * rate,
 						 total_data_rate));
-		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+		uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
 		alloc_size -= extra;
 		total_data_rate -= rate;
 	}
@@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 	 * that aren't actually possible.
 	 */
 	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
-		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
+		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
 			struct skl_plane_wm *wm =
-				&crtc_state->wm.skl.optimal.planes[plane_id];
+				&crtc_state->wm.skl.optimal.planes[plane->id];
+
+			wm_level = skl_plane_wm_level(plane, crtc_state,
+						      level, false);
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						      level, true);
 
 			/*
 			 * We only disable the watermarks for each plane if
@@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 			 *  planes must be enabled before the level will be used."
 			 * So this is actually safe to do.
 			 */
-			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
-			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
-				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+			if (wm_level->min_ddb_alloc > total[plane->id] ||
+			    wm_uv_level->min_ddb_alloc > uv_total[plane->id])
+				memset(&wm->wm[level], 0,
+				       sizeof(struct skl_wm_level));
 
 			/*
 			 * Wa_1408961008:icl, ehl
@@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
 			 */
 			if (IS_GEN(dev_priv, 11) &&
 			    level == 1 && wm->wm[0].plane_en) {
-				wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
-				wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
-				wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+				wm_level = skl_plane_wm_level(plane, crtc_state,
+							      0, false);
+				wm->wm[level].plane_res_b =
+					wm_level->plane_res_b;
+				wm->wm[level].plane_res_l =
+					wm_level->plane_res_l;
+				wm->wm[level].ignore_lines =
+					wm_level->ignore_lines;
 			}
 		}
 	}
@@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
 
 static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 				 int level,
+				 u32 latency,
 				 const struct skl_wm_params *wp,
 				 const struct skl_wm_level *result_prev,
 				 struct skl_wm_level *result /* out */)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
-	u32 latency = dev_priv->wm.skl_latency[level];
 	uint_fixed_16_16_t method1, method2;
 	uint_fixed_16_16_t selected_result;
 	u32 res_blocks, res_lines, min_ddb_alloc = 0;
@@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
 static void
 skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
 		      const struct skl_wm_params *wm_params,
-		      struct skl_wm_level *levels)
+		      struct skl_plane_wm *plane_wm,
+		      bool yuv)
 {
 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 	int level, max_level = ilk_wm_max_level(dev_priv);
+	/*
+	 * Check which kind of plane is it and based on that calculate
+	 * correspondent WM levels.
+	 */
+	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
 	struct skl_wm_level *result_prev = &levels[0];
 
 	for (level = 0; level <= max_level; level++) {
 		struct skl_wm_level *result = &levels[level];
+		u32 latency = dev_priv->wm.skl_latency[level];
 
-		skl_compute_plane_wm(crtc_state, level, wm_params,
-				     result_prev, result);
+		skl_compute_plane_wm(crtc_state, level, latency,
+				     wm_params, result_prev, result);
 
 		result_prev = result;
 	}
+	/*
+	 * For Gen12 if it is an L0 we need to also
+	 * consider sagv_block_time when calculating
+	 * L0 watermark - we will need that when making
+	 * a decision whether enable SAGV or not.
+	 * For older gens we agreed to copy L0 value for
+	 * compatibility.
+	 */
+	if ((INTEL_GEN(dev_priv) >= 12)) {
+		u32 latency = dev_priv->wm.skl_latency[0];
+
+		latency += dev_priv->sagv_block_time_us;
+		skl_compute_plane_wm(crtc_state, 0, latency,
+		     wm_params, &levels[0],
+		    &plane_wm->sagv_wm0);
+	} else
+		memcpy(&plane_wm->sagv_wm0, &levels[0],
+			sizeof(struct skl_wm_level));
 }
 
 static u32
@@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
 	skl_compute_transition_wm(crtc_state, &wm_params, wm);
 
 	return 0;
@@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
 	if (ret)
 		return ret;
 
-	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
 
 	return 0;
 }
@@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
 	const struct skl_ddb_entry *ddb_uv =
 		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
+	const struct skl_wm_level *wm_level;
 
 	for (level = 0; level <= max_level; level++) {
+		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
 		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
 			   &wm->trans_wm);
@@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
 		&crtc_state->wm.skl.optimal.planes[plane_id];
 	const struct skl_ddb_entry *ddb =
 		&crtc_state->wm.skl.plane_ddb_y[plane_id];
+	const struct skl_wm_level *wm_level;
 
 	for (level = 0; level <= max_level; level++) {
+		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
+
 		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
-				   &wm->wm[level]);
+				   wm_level);
 	}
 	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
 
@@ -5451,18 +5729,73 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
 	return 0;
 }
 
+static void tgl_set_sagv_mask(struct intel_atomic_state *state)
+{
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+	struct intel_crtc *crtc;
+	struct intel_crtc_state *new_crtc_state;
+	struct intel_crtc_state *old_crtc_state;
+	struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+	int ret;
+	int i;
+	struct intel_plane *plane;
+
+	if (state->crtc_sagv_mask_set)
+		return;
+
+	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
+					    new_crtc_state, i) {
+		int pipe_bit = BIT(crtc->pipe);
+		bool skip = true;
+
+		/*
+		 * If we had set this mast already once for this state,
+		 * no need to waste CPU cycles for doing this again.
+		 */
+		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
+			enum plane_id plane_id = plane->id;
+
+			if (!skl_plane_wm_equals(dev_priv,
+				&old_crtc_state->wm.skl.optimal.planes[plane_id],
+				&new_crtc_state->wm.skl.optimal.planes[plane_id])) {
+				skip = false;
+				break;
+			}
+		}
+
+		/*
+		 * Check if wm levels are actually the same as for previous
+		 * state, which means we can just skip doing this long check
+		 * and just  copy correspondent bit from previous state.
+		 */
+		if (skip)
+			continue;
+
+		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
+		if (!ret)
+			state->crtc_sagv_mask |= pipe_bit;
+		else
+			state->crtc_sagv_mask &= ~pipe_bit;
+	}
+	state->crtc_sagv_mask_set = true;
+}
+
 static int
 skl_compute_wm(struct intel_atomic_state *state)
 {
 	struct intel_crtc *crtc;
 	struct intel_crtc_state *new_crtc_state;
 	struct intel_crtc_state *old_crtc_state;
-	struct skl_ddb_values *results = &state->wm_results;
 	int ret, i;
+	struct skl_ddb_values *results = &state->wm_results;
+	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 
 	/* Clear all dirty flags */
 	results->dirty_pipes = 0;
 
+	/* If we exit before check is done */
+	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
+
 	ret = skl_ddb_add_affected_pipes(state);
 	if (ret)
 		return ret;
@@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 				val = I915_READ(CUR_WM(pipe, level));
 
 			skl_wm_level_from_reg_val(val, &wm->wm[level]);
+			if (level == 0)
+				memcpy(&wm->sagv_wm0, &wm->wm[level],
+					sizeof(struct skl_wm_level));
 		}
 
 		if (plane_id != PLANE_CURSOR)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..53275860731a 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
 void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
 void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
 bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_has_sagv(struct drm_i915_private *dev_priv);
 int intel_enable_sagv(struct drm_i915_private *dev_priv);
 int intel_disable_sagv(struct drm_i915_private *dev_priv);
 bool skl_wm_level_equals(const struct skl_wm_level *l1,
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-15 14:54   ` Stanislav Lisovskiy
  0 siblings, 0 replies; 23+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-15 14:54 UTC (permalink / raw)
  To: intel-gfx

According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
    values.

v3: Forbid simultaneous legacy SAGV PCode requests and
    restricting qgv points. Put the actual restriction
    to commit function, added serialization(thanks to Ville)
    to prevent commit being applied out of order in case of
    nonblocking and/or nomodeset commits.

v4:
    - Minor code refactoring, fixed few typos(thanks to James Ausmus)
    - Change the naming of qgv point
      masking/unmasking functions(James Ausmus).
    - Simplify the masking/unmasking operation itself,
      as we don't need to mask only single point per request(James Ausmus)
    - Reject and stick to highest bandwidth point if SAGV
      can't be enabled(BSpec)

v5:
    - Add new mailbox reply codes, which seems to happen during boot
      time for TGL and indicate that QGV setting is not yet available.

v6:
    - Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
    - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
      can be disabled by BIOS, which is completely legal. So don't
      make CI panic. Instead if we detect that there is only 1 QGV
      point accessible just analyze if we can fit the required bandwidth
      requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
      simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
       without modeset, which caused copying of non-calculated cdclk
       to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
     - Remove unneeded intel_qgv_info qi struct from bw check and zero
       out the needed one(Matthew Roper)
     - Changed QGV error message to have more clear meaning(Matthew Roper)
     - Use state->modeset_set instead of any_ms(Matthew Roper)
     - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
     - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
     - Moved unrelated changes to other patch(using latency as parameter
       for plane wm calculation, moved to SAGV refactoring patch)

Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c       | 134 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  91 +++++++++++-
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_reg.h               |   5 +
 drivers/gpu/drm/i915/intel_sideband.c         |  27 +++-
 8 files changed, 241 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 7b49623419ba..41a2a89c9bdb 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
 void intel_atomic_state_clear(struct drm_atomic_state *state);
 
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
 struct intel_crtc_state *
 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 			    struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 3f6e29f61323..809fc1bf99c5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
 #include "intel_bw.h"
 #include "intel_display_types.h"
 #include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
 
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
@@ -15,7 +18,7 @@ struct intel_qgv_point {
 };
 
 struct intel_qgv_info {
-	struct intel_qgv_point points[3];
+	struct intel_qgv_point points[NUM_SAGV_POINTS];
 	u8 num_points;
 	u8 num_channels;
 	u8 t_bl;
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask)
+{
+	int ret;
+
+	/* bspec says to keep retrying for at least 1 ms */
+	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+				points_mask,
+				GEN11_PCODE_POINTS_RESTRICTED_MASK,
+				GEN11_PCODE_POINTS_RESTRICTED,
+				1);
+
+	if (ret < 0) {
+		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 			      struct intel_qgv_info *qi)
 {
@@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
 }
 
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
-					int num_planes)
-{
-	if (INTEL_GEN(dev_priv) >= 11)
-		/*
-		 * FIXME with SAGV disabled maybe we can assume
-		 * point 1 will always be used? Seems to match
-		 * the behaviour observed in the wild.
-		 */
-		return min3(icl_max_bw(dev_priv, num_planes, 0),
-			    icl_max_bw(dev_priv, num_planes, 1),
-			    icl_max_bw(dev_priv, num_planes, 2));
-	else
-		return UINT_MAX;
-}
-
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
 {
 	/*
@@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	unsigned int data_rate, max_data_rate;
 	unsigned int num_active_planes;
 	struct intel_crtc *crtc;
-	int i;
+	int i, ret;
+	u32 allowed_points = 0;
+	unsigned int max_bw_point = 0, max_bw = 0;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	u32 mask = (1 << num_qgv_points) - 1;
 
 	/* FIXME earlier gens need some checks too */
 	if (INTEL_GEN(dev_priv) < 11)
@@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	data_rate = intel_bw_data_rate(dev_priv, bw_state);
 	num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
 
-	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
 	data_rate = DIV_ROUND_UP(data_rate, 1000);
 
-	if (data_rate > max_data_rate) {
-		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
-			      data_rate, max_data_rate, num_active_planes);
+	for (i = 0; i < num_qgv_points; i++) {
+		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+		if (max_data_rate >= data_rate)
+			allowed_points |= BIT(i);
+		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+			      i, max_data_rate, data_rate);
+	}
+
+	/*
+	 * BSpec states that we always should have at least one allowed point
+	 * left, so if we couldn't - simply reject the configuration for obvious
+	 * reasons.
+	 */
+	if (allowed_points == 0) {
+		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+			      " bandwidth for display configuration.\n");
 		return -EINVAL;
 	}
 
+	/*
+	 * In case if SAGV is disabled in BIOS, we always get 1
+	 * SAGV point, but we can't send PCode commands to restrict it
+	 * as it will fail and pointless anyway.
+	 */
+	if (num_qgv_points == 1)
+		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+	else
+		dev_priv->sagv_status = I915_SAGV_ENABLED;
+
+	/*
+	 * Leave only single point with highest bandwidth, if
+	 * we can't enable SAGV according to BSpec.
+	 */
+	if (!intel_can_enable_sagv(state)) {
+
+		/*
+		 * This is a border line condition when we have 0 planes
+		 * and SAGV not enabled means that we should keep QGV with
+		 * highest bandwidth, however algorithm returns wrong result
+		 * for 0 planes and 0 data rate, so just stick to last config
+		 * then. Otherwise use the QGV point with highest BW according
+		 * to BSpec.
+		 */
+		if (!data_rate && !num_active_planes) {
+			DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
+			allowed_points = (~dev_priv->qgv_points_mask) & mask;
+		} else {
+			allowed_points = 1 << max_bw_point;
+			DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+				      max_bw_point);
+		}
+	}
+	/*
+	 * We store the ones which need to be masked as that is what PCode
+	 * actually accepts as a parameter.
+	 */
+	state->qgv_points_mask = (~allowed_points) & mask;
+
+	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+		      state, state->qgv_points_mask);
+
+	/*
+	 * If the actual mask had changed we need to make sure that
+	 * the commits are serialized(in case this is a nomodeset, nonblocking)
+	 */
+	if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
+		ret = intel_atomic_serialize_global_state(state);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 9db10af012f4..66bf9bc10b73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7f31e33d0b16..fd35d0b0699c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14755,6 +14755,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
 	intel_atomic_helper_free_state(i915);
 }
 
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret;
+	u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	unsigned int mask = (1 << num_qgv_points) - 1;
+
+	/*
+	 * As we don't know initial hardware state during initial commit
+	 * we should not do anything, until we actually figure out,
+	 * what are the qgv points to mask.
+	 */
+	if (!new_mask)
+		return;
+
+	WARN_ON(new_mask == mask);
+
+	/*
+	 * Just return if we can't control SAGV or don't have it.
+	 */
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+			      ret);
+	else
+		dev_priv->qgv_points_mask = new_mask;
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret;
+	u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
+
+	/*
+	 * As we don't know initial hardware state during initial commit
+	 * we should not do anything, until we actually figure out,
+	 * what are the qgv points to mask.
+	 */
+	if (!new_mask)
+		return;
+
+	/*
+	 * Just return if we can't control SAGV or don't have it.
+	 */
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+			      ret);
+	else
+		dev_priv->qgv_points_mask = new_mask;
+}
+
 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
@@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		}
 	}
 
+	if ((INTEL_GEN(dev_priv) >= 11))
+		intel_qgv_points_mask(state);
+
 	intel_commit_modeset_disables(state);
 
 	/* FIXME: Eventually get rid of our crtc->config pointer */
@@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 * SKL workaround: bspec recommends we disable the SAGV when we
 		 * have more then one pipe enabled
 		 */
-		if (!intel_can_enable_sagv(state))
-			intel_disable_sagv(dev_priv);
+		if (INTEL_GEN(dev_priv) < 11)
+			if (!intel_can_enable_sagv(state))
+				intel_disable_sagv(dev_priv);
 
 		intel_modeset_verify_disabled(dev_priv, state);
 	}
@@ -14883,8 +14961,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset)
 		intel_verify_planes(state);
 
-	if (state->modeset && intel_can_enable_sagv(state))
-		intel_enable_sagv(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11) {
+		if (state->modeset && intel_can_enable_sagv(state))
+			intel_enable_sagv(dev_priv);
+	} else
+		intel_qgv_points_unmask(state);
 
 	drm_atomic_helper_commit_hw_done(&state->base);
 
@@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	intel_shared_dpll_swap_state(state);
 	intel_atomic_track_fbs(state);
 
-	if (state->global_state_changed) {
+	if (state->global_state_changed && state->modeset) {
 		assert_global_state_locked(dev_priv);
 
 		memcpy(dev_priv->min_cdclk, state->min_cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6a300cac883f..3535857dfed2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -534,6 +534,9 @@ struct intel_atomic_state {
 	struct i915_sw_fence commit_ready;
 
 	struct llist_node freed;
+
+	/* Gen11+ only */
+	u32 qgv_points_mask;
 };
 
 struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ac9d7b006ca..54657b68010a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -850,6 +850,9 @@ enum intel_pipe_crc_source {
 	INTEL_PIPE_CRC_SOURCE_MAX,
 };
 
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
 #define INTEL_PIPE_CRC_ENTRIES_NR	128
 struct intel_pipe_crc {
 	spinlock_t lock;
@@ -1238,11 +1241,13 @@ struct drm_i915_private {
 	} dram_info;
 
 	struct intel_bw_info {
-		unsigned int deratedbw[3]; /* for each QGV point */
+		unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
 		u8 num_qgv_points;
 		u8 num_planes;
 	} max_bw[6];
 
+	u32 qgv_points_mask;
+
 	struct drm_private_obj bw_obj;
 
 	struct intel_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a4e5a4ae3885..2ea83ff681b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8981,6 +8981,8 @@ enum {
 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
 #define     GEN7_PCODE_TIMEOUT			0x2
 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
+#define     GEN11_PCODE_MAIL_BOX_LOCKED		0x6
+#define     GEN11_PCODE_REJECTED		0x11
 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define   GEN6_PCODE_READ_RC6VIDS		0x5
@@ -9002,6 +9004,7 @@ enum {
 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
 #define   GEN6_PCODE_READ_D_COMP		0x10
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
@@ -9014,6 +9017,8 @@ enum {
 #define     GEN9_SAGV_IS_DISABLED		0x1
 #define     GEN9_SAGV_ENABLE			0x3
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define GEN11_PCODE_POINTS_RESTRICTED		0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..ff9dbed094d8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
 	}
 }
 
+static inline int gen11_check_mailbox_status(u32 mbox)
+{
+	switch (mbox & GEN6_PCODE_ERROR_MASK) {
+	case GEN6_PCODE_SUCCESS:
+		return 0;
+	case GEN6_PCODE_ILLEGAL_CMD:
+		return -ENXIO;
+	case GEN7_PCODE_TIMEOUT:
+		return -ETIMEDOUT;
+	case GEN7_PCODE_ILLEGAL_DATA:
+		return -EINVAL;
+	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+		return -EOVERFLOW;
+	case GEN11_PCODE_MAIL_BOX_LOCKED:
+		return -EAGAIN;
+	case GEN11_PCODE_REJECTED:
+		return -EACCES;
+	default:
+		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+		return 0;
+	}
+}
+
 static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
 				  u32 mbox, u32 *val, u32 *val1,
 				  int fast_timeout_us,
@@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
 	if (is_read && val1)
 		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
 
-	if (INTEL_GEN(i915) > 6)
+	if (INTEL_GEN(i915) >= 11)
+		return gen11_check_mailbox_status(mbox);
+	else if (INTEL_GEN(i915) > 6)
 		return gen7_check_mailbox_status(mbox);
 	else
 		return gen6_check_mailbox_status(mbox);
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* [Intel-gfx] [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-15 14:54   ` Stanislav Lisovskiy
  0 siblings, 0 replies; 23+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-15 14:54 UTC (permalink / raw)
  To: intel-gfx

According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
    values.

v3: Forbid simultaneous legacy SAGV PCode requests and
    restricting qgv points. Put the actual restriction
    to commit function, added serialization(thanks to Ville)
    to prevent commit being applied out of order in case of
    nonblocking and/or nomodeset commits.

v4:
    - Minor code refactoring, fixed few typos(thanks to James Ausmus)
    - Change the naming of qgv point
      masking/unmasking functions(James Ausmus).
    - Simplify the masking/unmasking operation itself,
      as we don't need to mask only single point per request(James Ausmus)
    - Reject and stick to highest bandwidth point if SAGV
      can't be enabled(BSpec)

v5:
    - Add new mailbox reply codes, which seems to happen during boot
      time for TGL and indicate that QGV setting is not yet available.

v6:
    - Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
    - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
      can be disabled by BIOS, which is completely legal. So don't
      make CI panic. Instead if we detect that there is only 1 QGV
      point accessible just analyze if we can fit the required bandwidth
      requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
      simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
       without modeset, which caused copying of non-calculated cdclk
       to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
     - Remove unneeded intel_qgv_info qi struct from bw check and zero
       out the needed one(Matthew Roper)
     - Changed QGV error message to have more clear meaning(Matthew Roper)
     - Use state->modeset_set instead of any_ms(Matthew Roper)
     - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
     - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
     - Moved unrelated changes to other patch(using latency as parameter
       for plane wm calculation, moved to SAGV refactoring patch)

Reviewed-by: James Ausmus <james.ausmus@intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
 drivers/gpu/drm/i915/display/intel_bw.c       | 134 +++++++++++++++---
 drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
 drivers/gpu/drm/i915/display/intel_display.c  |  91 +++++++++++-
 .../drm/i915/display/intel_display_types.h    |   3 +
 drivers/gpu/drm/i915/i915_drv.h               |   7 +-
 drivers/gpu/drm/i915/i915_reg.h               |   5 +
 drivers/gpu/drm/i915/intel_sideband.c         |  27 +++-
 8 files changed, 241 insertions(+), 30 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index 7b49623419ba..41a2a89c9bdb 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
 struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
 void intel_atomic_state_clear(struct drm_atomic_state *state);
 
+int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
+
 struct intel_crtc_state *
 intel_atomic_get_crtc_state(struct drm_atomic_state *state,
 			    struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 3f6e29f61323..809fc1bf99c5 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
 #include "intel_bw.h"
 #include "intel_display_types.h"
 #include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
 
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
@@ -15,7 +18,7 @@ struct intel_qgv_point {
 };
 
 struct intel_qgv_info {
-	struct intel_qgv_point points[3];
+	struct intel_qgv_point points[NUM_SAGV_POINTS];
 	u8 num_points;
 	u8 num_channels;
 	u8 t_bl;
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
 	return 0;
 }
 
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask)
+{
+	int ret;
+
+	/* bspec says to keep retrying for at least 1 ms */
+	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+				points_mask,
+				GEN11_PCODE_POINTS_RESTRICTED_MASK,
+				GEN11_PCODE_POINTS_RESTRICTED,
+				1);
+
+	if (ret < 0) {
+		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 			      struct intel_qgv_info *qi)
 {
@@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 		icl_get_bw_info(dev_priv, &icl_sa_info);
 }
 
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
-					int num_planes)
-{
-	if (INTEL_GEN(dev_priv) >= 11)
-		/*
-		 * FIXME with SAGV disabled maybe we can assume
-		 * point 1 will always be used? Seems to match
-		 * the behaviour observed in the wild.
-		 */
-		return min3(icl_max_bw(dev_priv, num_planes, 0),
-			    icl_max_bw(dev_priv, num_planes, 1),
-			    icl_max_bw(dev_priv, num_planes, 2));
-	else
-		return UINT_MAX;
-}
-
 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
 {
 	/*
@@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	unsigned int data_rate, max_data_rate;
 	unsigned int num_active_planes;
 	struct intel_crtc *crtc;
-	int i;
+	int i, ret;
+	u32 allowed_points = 0;
+	unsigned int max_bw_point = 0, max_bw = 0;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	u32 mask = (1 << num_qgv_points) - 1;
 
 	/* FIXME earlier gens need some checks too */
 	if (INTEL_GEN(dev_priv) < 11)
@@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
 	data_rate = intel_bw_data_rate(dev_priv, bw_state);
 	num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
 
-	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
-
 	data_rate = DIV_ROUND_UP(data_rate, 1000);
 
-	if (data_rate > max_data_rate) {
-		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
-			      data_rate, max_data_rate, num_active_planes);
+	for (i = 0; i < num_qgv_points; i++) {
+		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+		/*
+		 * We need to know which qgv point gives us
+		 * maximum bandwidth in order to disable SAGV
+		 * if we find that we exceed SAGV block time
+		 * with watermarks. By that moment we already
+		 * have those, as it is calculated earlier in
+		 * intel_atomic_check,
+		 */
+		if (max_data_rate > max_bw) {
+			max_bw_point = i;
+			max_bw = max_data_rate;
+		}
+		if (max_data_rate >= data_rate)
+			allowed_points |= BIT(i);
+		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+			      i, max_data_rate, data_rate);
+	}
+
+	/*
+	 * BSpec states that we always should have at least one allowed point
+	 * left, so if we couldn't - simply reject the configuration for obvious
+	 * reasons.
+	 */
+	if (allowed_points == 0) {
+		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+			      " bandwidth for display configuration.\n");
 		return -EINVAL;
 	}
 
+	/*
+	 * In case if SAGV is disabled in BIOS, we always get 1
+	 * SAGV point, but we can't send PCode commands to restrict it
+	 * as it will fail and pointless anyway.
+	 */
+	if (num_qgv_points == 1)
+		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+	else
+		dev_priv->sagv_status = I915_SAGV_ENABLED;
+
+	/*
+	 * Leave only single point with highest bandwidth, if
+	 * we can't enable SAGV according to BSpec.
+	 */
+	if (!intel_can_enable_sagv(state)) {
+
+		/*
+		 * This is a border line condition when we have 0 planes
+		 * and SAGV not enabled means that we should keep QGV with
+		 * highest bandwidth, however algorithm returns wrong result
+		 * for 0 planes and 0 data rate, so just stick to last config
+		 * then. Otherwise use the QGV point with highest BW according
+		 * to BSpec.
+		 */
+		if (!data_rate && !num_active_planes) {
+			DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
+			allowed_points = (~dev_priv->qgv_points_mask) & mask;
+		} else {
+			allowed_points = 1 << max_bw_point;
+			DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+				      max_bw_point);
+		}
+	}
+	/*
+	 * We store the ones which need to be masked as that is what PCode
+	 * actually accepts as a parameter.
+	 */
+	state->qgv_points_mask = (~allowed_points) & mask;
+
+	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
+		      state, state->qgv_points_mask);
+
+	/*
+	 * If the actual mask had changed we need to make sure that
+	 * the commits are serialized(in case this is a nomodeset, nonblocking)
+	 */
+	if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
+		ret = intel_atomic_serialize_global_state(state);
+		if (ret) {
+			DRM_DEBUG_KMS("Could not serialize global state\n");
+			return ret;
+		}
+	}
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 9db10af012f4..66bf9bc10b73 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
 int intel_bw_atomic_check(struct intel_atomic_state *state);
 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 			  const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+				  u32 points_mask);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 7f31e33d0b16..fd35d0b0699c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14755,6 +14755,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
 	intel_atomic_helper_free_state(i915);
 }
 
+static void intel_qgv_points_mask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret;
+	u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
+	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+	unsigned int mask = (1 << num_qgv_points) - 1;
+
+	/*
+	 * As we don't know initial hardware state during initial commit
+	 * we should not do anything, until we actually figure out,
+	 * what are the qgv points to mask.
+	 */
+	if (!new_mask)
+		return;
+
+	WARN_ON(new_mask == mask);
+
+	/*
+	 * Just return if we can't control SAGV or don't have it.
+	 */
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+			      ret);
+	else
+		dev_priv->qgv_points_mask = new_mask;
+}
+
+static void intel_qgv_points_unmask(struct intel_atomic_state *state)
+{
+	struct drm_device *dev = state->base.dev;
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	int ret;
+	u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
+
+	/*
+	 * As we don't know initial hardware state during initial commit
+	 * we should not do anything, until we actually figure out,
+	 * what are the qgv points to mask.
+	 */
+	if (!new_mask)
+		return;
+
+	/*
+	 * Just return if we can't control SAGV or don't have it.
+	 */
+	if (!intel_has_sagv(dev_priv))
+		return;
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+	if (ret < 0)
+		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
+			      ret);
+	else
+		dev_priv->qgv_points_mask = new_mask;
+}
+
 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 {
 	struct drm_device *dev = state->base.dev;
@@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		}
 	}
 
+	if ((INTEL_GEN(dev_priv) >= 11))
+		intel_qgv_points_mask(state);
+
 	intel_commit_modeset_disables(state);
 
 	/* FIXME: Eventually get rid of our crtc->config pointer */
@@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 		 * SKL workaround: bspec recommends we disable the SAGV when we
 		 * have more then one pipe enabled
 		 */
-		if (!intel_can_enable_sagv(state))
-			intel_disable_sagv(dev_priv);
+		if (INTEL_GEN(dev_priv) < 11)
+			if (!intel_can_enable_sagv(state))
+				intel_disable_sagv(dev_priv);
 
 		intel_modeset_verify_disabled(dev_priv, state);
 	}
@@ -14883,8 +14961,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
 	if (state->modeset)
 		intel_verify_planes(state);
 
-	if (state->modeset && intel_can_enable_sagv(state))
-		intel_enable_sagv(dev_priv);
+	if (INTEL_GEN(dev_priv) < 11) {
+		if (state->modeset && intel_can_enable_sagv(state))
+			intel_enable_sagv(dev_priv);
+	} else
+		intel_qgv_points_unmask(state);
 
 	drm_atomic_helper_commit_hw_done(&state->base);
 
@@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct drm_device *dev,
 	intel_shared_dpll_swap_state(state);
 	intel_atomic_track_fbs(state);
 
-	if (state->global_state_changed) {
+	if (state->global_state_changed && state->modeset) {
 		assert_global_state_locked(dev_priv);
 
 		memcpy(dev_priv->min_cdclk, state->min_cdclk,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6a300cac883f..3535857dfed2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -534,6 +534,9 @@ struct intel_atomic_state {
 	struct i915_sw_fence commit_ready;
 
 	struct llist_node freed;
+
+	/* Gen11+ only */
+	u32 qgv_points_mask;
 };
 
 struct intel_plane_state {
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0ac9d7b006ca..54657b68010a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -850,6 +850,9 @@ enum intel_pipe_crc_source {
 	INTEL_PIPE_CRC_SOURCE_MAX,
 };
 
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
 #define INTEL_PIPE_CRC_ENTRIES_NR	128
 struct intel_pipe_crc {
 	spinlock_t lock;
@@ -1238,11 +1241,13 @@ struct drm_i915_private {
 	} dram_info;
 
 	struct intel_bw_info {
-		unsigned int deratedbw[3]; /* for each QGV point */
+		unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
 		u8 num_qgv_points;
 		u8 num_planes;
 	} max_bw[6];
 
+	u32 qgv_points_mask;
+
 	struct drm_private_obj bw_obj;
 
 	struct intel_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a4e5a4ae3885..2ea83ff681b9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -8981,6 +8981,8 @@ enum {
 #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
 #define     GEN7_PCODE_TIMEOUT			0x2
 #define     GEN7_PCODE_ILLEGAL_DATA		0x3
+#define     GEN11_PCODE_MAIL_BOX_LOCKED		0x6
+#define     GEN11_PCODE_REJECTED		0x11
 #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
 #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
 #define   GEN6_PCODE_READ_RC6VIDS		0x5
@@ -9002,6 +9004,7 @@ enum {
 #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
 #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
 #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
+#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
 #define   GEN6_PCODE_READ_D_COMP		0x10
 #define   GEN6_PCODE_WRITE_D_COMP		0x11
 #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
@@ -9014,6 +9017,8 @@ enum {
 #define     GEN9_SAGV_IS_DISABLED		0x1
 #define     GEN9_SAGV_ENABLE			0x3
 #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
+#define GEN11_PCODE_POINTS_RESTRICTED		0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
 #define GEN6_PCODE_DATA				_MMIO(0x138128)
 #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
 #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index e06b35b844a0..ff9dbed094d8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
 	}
 }
 
+static inline int gen11_check_mailbox_status(u32 mbox)
+{
+	switch (mbox & GEN6_PCODE_ERROR_MASK) {
+	case GEN6_PCODE_SUCCESS:
+		return 0;
+	case GEN6_PCODE_ILLEGAL_CMD:
+		return -ENXIO;
+	case GEN7_PCODE_TIMEOUT:
+		return -ETIMEDOUT;
+	case GEN7_PCODE_ILLEGAL_DATA:
+		return -EINVAL;
+	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+		return -EOVERFLOW;
+	case GEN11_PCODE_MAIL_BOX_LOCKED:
+		return -EAGAIN;
+	case GEN11_PCODE_REJECTED:
+		return -EACCES;
+	default:
+		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+		return 0;
+	}
+}
+
 static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
 				  u32 mbox, u32 *val, u32 *val1,
 				  int fast_timeout_us,
@@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
 	if (is_read && val1)
 		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
 
-	if (INTEL_GEN(i915) > 6)
+	if (INTEL_GEN(i915) >= 11)
+		return gen11_check_mailbox_status(mbox);
+	else if (INTEL_GEN(i915) > 6)
 		return gen7_check_mailbox_status(mbox);
 	else
 		return gen6_check_mailbox_status(mbox);
-- 
2.17.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 23+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-15 17:24   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-15 17:24 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1294bb4306ba drm/i915: Refactor intel_can_enable_sagv
-:254: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#254: FILE: drivers/gpu/drm/i915/intel_pm.c:3847:
+	for_each_new_intel_crtc_in_state(state, crtc,
+					     new_crtc_state, i) {

-:439: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#439: FILE: drivers/gpu/drm/i915/intel_pm.c:4421:
+skl_plane_wm_level(struct intel_plane *plane,
+		const struct intel_crtc_state *crtc_state,

-:562: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#562: FILE: drivers/gpu/drm/i915/intel_pm.c:4638:
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						      level, true);

-:653: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#653: FILE: drivers/gpu/drm/i915/intel_pm.c:5059:
+		skl_compute_plane_wm(crtc_state, 0, latency,
+		     wm_params, &levels[0],

-:655: CHECK:BRACES: Unbalanced braces around else statement
#655: FILE: drivers/gpu/drm/i915/intel_pm.c:5061:
+	} else

-:657: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#657: FILE: drivers/gpu/drm/i915/intel_pm.c:5063:
+		memcpy(&plane_wm->sagv_wm0, &levels[0],
+			sizeof(struct skl_wm_level));

-:740: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#740: FILE: drivers/gpu/drm/i915/intel_pm.c:5759:
+			if (!skl_plane_wm_equals(dev_priv,
+				&old_crtc_state->wm.skl.optimal.planes[plane_id],

-:790: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#790: FILE: drivers/gpu/drm/i915/intel_pm.c:5976:
+				memcpy(&wm->sagv_wm0, &wm->wm[level],
+					sizeof(struct skl_wm_level));

total: 0 errors, 0 warnings, 8 checks, 697 lines checked
885e46a4e56d drm/i915: Restrict qgv points which don't have enough bandwidth.
-:229: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#229: FILE: drivers/gpu/drm/i915/display/intel_bw.c:483:
+	if (!intel_can_enable_sagv(state)) {
+

-:396: CHECK:BRACES: braces {} should be used on all arms of this statement
#396: FILE: drivers/gpu/drm/i915/display/intel_display.c:14964:
+	if (INTEL_GEN(dev_priv) < 11) {
[...]
+	} else
[...]

-:399: CHECK:BRACES: Unbalanced braces around else statement
#399: FILE: drivers/gpu/drm/i915/display/intel_display.c:14967:
+	} else

total: 0 errors, 0 warnings, 3 checks, 405 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-15 17:24   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-15 17:24 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1294bb4306ba drm/i915: Refactor intel_can_enable_sagv
-:254: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#254: FILE: drivers/gpu/drm/i915/intel_pm.c:3847:
+	for_each_new_intel_crtc_in_state(state, crtc,
+					     new_crtc_state, i) {

-:439: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#439: FILE: drivers/gpu/drm/i915/intel_pm.c:4421:
+skl_plane_wm_level(struct intel_plane *plane,
+		const struct intel_crtc_state *crtc_state,

-:562: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#562: FILE: drivers/gpu/drm/i915/intel_pm.c:4638:
+			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
+						      level, true);

-:653: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#653: FILE: drivers/gpu/drm/i915/intel_pm.c:5059:
+		skl_compute_plane_wm(crtc_state, 0, latency,
+		     wm_params, &levels[0],

-:655: CHECK:BRACES: Unbalanced braces around else statement
#655: FILE: drivers/gpu/drm/i915/intel_pm.c:5061:
+	} else

-:657: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#657: FILE: drivers/gpu/drm/i915/intel_pm.c:5063:
+		memcpy(&plane_wm->sagv_wm0, &levels[0],
+			sizeof(struct skl_wm_level));

-:740: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#740: FILE: drivers/gpu/drm/i915/intel_pm.c:5759:
+			if (!skl_plane_wm_equals(dev_priv,
+				&old_crtc_state->wm.skl.optimal.planes[plane_id],

-:790: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#790: FILE: drivers/gpu/drm/i915/intel_pm.c:5976:
+				memcpy(&wm->sagv_wm0, &wm->wm[level],
+					sizeof(struct skl_wm_level));

total: 0 errors, 0 warnings, 8 checks, 697 lines checked
885e46a4e56d drm/i915: Restrict qgv points which don't have enough bandwidth.
-:229: CHECK:BRACES: Blank lines aren't necessary after an open brace '{'
#229: FILE: drivers/gpu/drm/i915/display/intel_bw.c:483:
+	if (!intel_can_enable_sagv(state)) {
+

-:396: CHECK:BRACES: braces {} should be used on all arms of this statement
#396: FILE: drivers/gpu/drm/i915/display/intel_display.c:14964:
+	if (INTEL_GEN(dev_priv) < 11) {
[...]
+	} else
[...]

-:399: CHECK:BRACES: Unbalanced braces around else statement
#399: FILE: drivers/gpu/drm/i915/display/intel_display.c:14967:
+	} else

total: 0 errors, 0 warnings, 3 checks, 405 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-15 17:26   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-15 17:26 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:4419:27: warning: symbol 'skl_plane_wm_level' was not declared. Should it be static?

Commit: drm/i915: Restrict qgv points which don't have enough bandwidth.
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-15 17:26   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-15 17:26 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Refactor intel_can_enable_sagv
+drivers/gpu/drm/i915/intel_pm.c:4419:27: warning: symbol 'skl_plane_wm_level' was not declared. Should it be static?

Commit: drm/i915: Restrict qgv points which don't have enough bandwidth.
Okay!

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-15 17:52   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-15 17:52 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7353 -> Patchwork_15285
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/index.html

Known issues
------------

  Here are the changes found in Patchwork_15285 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [PASS][1] -> [DMESG-WARN][2] ([fdo#112261])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-skl-6770hq:      [PASS][3] -> [DMESG-WARN][4] ([fdo#105541])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [PASS][5] -> [FAIL][6] ([fdo#109483])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
    - fi-kbl-7500u:       [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-kbl-7560u}:     [INCOMPLETE][11] ([fdo#112298]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][13] ([fdo#108511]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (51 -> 45)
------------------------------

  Additional (1): fi-cfl-guc 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7353 -> Patchwork_15285

  CI-20190529: 20190529
  CI_DRM_7353: 18d4d81004d8407cd4dbbebdafb2ccd77eb52872 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15285: 885e46a4e56d44b8230b59ae99d3f76b26be581b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

885e46a4e56d drm/i915: Restrict qgv points which don't have enough bandwidth.
1294bb4306ba drm/i915: Refactor intel_can_enable_sagv

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-15 17:52   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-15 17:52 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7353 -> Patchwork_15285
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/index.html

Known issues
------------

  Here are the changes found in Patchwork_15285 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-lmem:        [PASS][1] -> [DMESG-WARN][2] ([fdo#112261])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-skl-6770hq:      [PASS][3] -> [DMESG-WARN][4] ([fdo#105541])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-icl-u2:          [PASS][5] -> [FAIL][6] ([fdo#109483])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
    - fi-kbl-7500u:       [PASS][7] -> [FAIL][8] ([fdo#111045] / [fdo#111096])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-hsw-peppy:       [PASS][9] -> [DMESG-WARN][10] ([fdo#102614])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-kbl-7560u}:     [INCOMPLETE][11] ([fdo#112298]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][13] ([fdo#108511]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (51 -> 45)
------------------------------

  Additional (1): fi-cfl-guc 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7353 -> Patchwork_15285

  CI-20190529: 20190529
  CI_DRM_7353: 18d4d81004d8407cd4dbbebdafb2ccd77eb52872 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15285: 885e46a4e56d44b8230b59ae99d3f76b26be581b @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

885e46a4e56d drm/i915: Restrict qgv points which don't have enough bandwidth.
1294bb4306ba drm/i915: Refactor intel_can_enable_sagv

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* ✗ Fi.CI.IGT: failure for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-17  3:42   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-17  3:42 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7353_full -> Patchwork_15285_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15285_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15285_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15285_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-apl:          [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-apl4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-apl1/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb8/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_plane_cursor@pipe-a-viewport-size-64:
    - shard-tglb:         [PASS][4] -> [DMESG-WARN][5] +25 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb3/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html

  
#### Warnings ####

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][6] ([fdo#111850]) -> [DMESG-WARN][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_parse_blt@bb-secure}:
    - shard-tglb:         NOTRUN -> [SKIP][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb3/igt@gem_exec_parse_blt@bb-secure.html

  
Known issues
------------

  Here are the changes found in Patchwork_15285_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-reset:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb1/igt@gem_ctx_isolation@vcs1-reset.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb8/igt@gem_ctx_isolation@vcs1-reset.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-kbl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108566])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-kbl4/igt@gem_ctx_isolation@vcs1-s3.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-kbl7/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112080]) +6 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@gem_ctx_switch@vcs1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb3/igt@gem_ctx_switch@vcs1.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#112146]) +7 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
    - shard-snb:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb4/igt@i915_pm_rpm@system-suspend-execbuf.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb5/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@kms_color@pipe-c-gamma:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#104782])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl8/igt@kms_color@pipe-c-gamma.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl8/igt@kms_color@pipe-c-gamma.html

  * igt@kms_flip_tiling@flip-to-y-tiled:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#107931] / [fdo#108134])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl1/igt@kms_flip_tiling@flip-to-y-tiled.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl8/igt@kms_flip_tiling@flip-to-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103167]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-apl:          [PASS][29] -> [DMESG-WARN][30] ([fdo#108566])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][31] -> [FAIL][32] ([fdo#103166])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109642] / [fdo#111068])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([fdo#108341])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb5/igt@kms_psr@no_drrs.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109276]) +21 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb1/igt@prime_busy@hang-bsd2.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb5/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][41] ([fdo#112080]) -> [PASS][42] +7 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb6/igt@gem_busy@busy-vcs1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb2/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-mixed:
    - shard-iclb:         [SKIP][43] ([fdo#109276] / [fdo#112080]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb8/igt@gem_ctx_persistence@vcs1-mixed.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#112146]) -> [PASS][46] +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb3/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [SKIP][47] ([fdo#109276]) -> [PASS][48] +12 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-render:
    - shard-tglb:         [INCOMPLETE][49] ([fdo#111606] / [fdo#111677]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb6/igt@gem_exec_schedule@preempt-queue-render.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb3/igt@gem_exec_schedule@preempt-queue-render.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
    - shard-snb:          [TIMEOUT][51] ([fdo#112068 ]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html

  * igt@gem_tiled_blits@interruptible:
    - shard-kbl:          [INCOMPLETE][53] ([fdo#103665]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-kbl7/igt@gem_tiled_blits@interruptible.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-kbl3/igt@gem_tiled_blits@interruptible.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [DMESG-WARN][55] ([fdo#111870]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-hsw6/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_suspend@sysfs-reader:
    - shard-skl:          [INCOMPLETE][57] ([fdo#104108]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl1/igt@i915_suspend@sysfs-reader.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][59] ([fdo#103540]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-hsw1/igt@kms_flip@flip-vs-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-hsw5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62] +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         [FAIL][63] ([fdo#103167]) -> [PASS][64] +5 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][67] ([fdo#108145]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [SKIP][69] ([fdo#109441]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@kms_psr@psr2_basic.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb2/igt@kms_psr@psr2_basic.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][71] ([fdo#111329]) -> [SKIP][72] ([fdo#109276] / [fdo#112080])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][73] ([fdo#105411]) -> [DMESG-WARN][74] ([fdo#111780 ] / [fdo#111781])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-snb6/igt@gem_eio@kms.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-snb1/igt@gem_eio@kms.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [SKIP][75] ([fdo#111865]) -> [FAIL][76] ([fdo#111830 ])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [DMESG-WARN][77] ([fdo#107724]) -> [SKIP][78] ([fdo#109441])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_psr@psr2_suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_psr@psr2_suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
  [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111780 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111780 
  [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7353 -> Patchwork_15285

  CI-20190529: 20190529
  CI_DRM_7353: 18d4d81004d8407cd4dbbebdafb2ccd77eb52872 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15285: 885e46a4e56d44b8230b59ae99d3f76b26be581b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Refactor Gen11+ SAGV support (rev11)
@ 2019-11-17  3:42   ` Patchwork
  0 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-11-17  3:42 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev11)
URL   : https://patchwork.freedesktop.org/series/68028/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7353_full -> Patchwork_15285_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15285_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15285_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15285_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-apl:          [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-apl4/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-apl1/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
    - shard-tglb:         NOTRUN -> [DMESG-WARN][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb8/igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic.html

  * igt@kms_plane_cursor@pipe-a-viewport-size-64:
    - shard-tglb:         [PASS][4] -> [DMESG-WARN][5] +25 similar issues
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb3/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb1/igt@kms_plane_cursor@pipe-a-viewport-size-64.html

  
#### Warnings ####

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][6] ([fdo#111850]) -> [DMESG-WARN][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb6/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_parse_blt@bb-secure}:
    - shard-tglb:         NOTRUN -> [SKIP][8]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb3/igt@gem_exec_parse_blt@bb-secure.html

  
Known issues
------------

  Here are the changes found in Patchwork_15285_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs1-reset:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb1/igt@gem_ctx_isolation@vcs1-reset.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb8/igt@gem_ctx_isolation@vcs1-reset.html

  * igt@gem_ctx_isolation@vcs1-s3:
    - shard-kbl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108566])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-kbl4/igt@gem_ctx_isolation@vcs1-s3.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-kbl7/igt@gem_ctx_isolation@vcs1-s3.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112080]) +6 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@gem_ctx_switch@vcs1.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb3/igt@gem_ctx_switch@vcs1.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#112146]) +7 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb8/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-hsw:          [PASS][17] -> [DMESG-WARN][18] ([fdo#111870])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
    - shard-snb:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-tglb:         [PASS][21] -> [INCOMPLETE][22] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb4/igt@i915_pm_rpm@system-suspend-execbuf.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb5/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@kms_color@pipe-c-gamma:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#104782])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl8/igt@kms_color@pipe-c-gamma.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl8/igt@kms_color@pipe-c-gamma.html

  * igt@kms_flip_tiling@flip-to-y-tiled:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#107931] / [fdo#108134])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl1/igt@kms_flip_tiling@flip-to-y-tiled.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl8/igt@kms_flip_tiling@flip-to-y-tiled.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw:
    - shard-iclb:         [PASS][27] -> [FAIL][28] ([fdo#103167]) +2 similar issues
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-pri-indfb-multidraw.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-apl:          [PASS][29] -> [DMESG-WARN][30] ([fdo#108566])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][31] -> [FAIL][32] ([fdo#103166])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [PASS][33] -> [SKIP][34] ([fdo#109642] / [fdo#111068])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_psr2_su@page_flip.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_psr2_su@page_flip.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [PASS][35] -> [FAIL][36] ([fdo#108341])
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb5/igt@kms_psr@no_drrs.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb1/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][37] -> [SKIP][38] ([fdo#109441]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][39] -> [SKIP][40] ([fdo#109276]) +21 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb1/igt@prime_busy@hang-bsd2.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb5/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][41] ([fdo#112080]) -> [PASS][42] +7 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb6/igt@gem_busy@busy-vcs1.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb2/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_persistence@vcs1-mixed:
    - shard-iclb:         [SKIP][43] ([fdo#109276] / [fdo#112080]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb8/igt@gem_ctx_persistence@vcs1-mixed.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb4/igt@gem_ctx_persistence@vcs1-mixed.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [SKIP][45] ([fdo#112146]) -> [PASS][46] +3 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb3/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_schedule@out-order-bsd2:
    - shard-iclb:         [SKIP][47] ([fdo#109276]) -> [PASS][48] +12 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb8/igt@gem_exec_schedule@out-order-bsd2.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb4/igt@gem_exec_schedule@out-order-bsd2.html

  * igt@gem_exec_schedule@preempt-queue-render:
    - shard-tglb:         [INCOMPLETE][49] ([fdo#111606] / [fdo#111677]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb6/igt@gem_exec_schedule@preempt-queue-render.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb3/igt@gem_exec_schedule@preempt-queue-render.html

  * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
    - shard-snb:          [TIMEOUT][51] ([fdo#112068 ]) -> [PASS][52]
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html

  * igt@gem_tiled_blits@interruptible:
    - shard-kbl:          [INCOMPLETE][53] ([fdo#103665]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-kbl7/igt@gem_tiled_blits@interruptible.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-kbl3/igt@gem_tiled_blits@interruptible.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [DMESG-WARN][55] ([fdo#111870]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-hsw5/igt@gem_userptr_blits@sync-unmap-cycles.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-hsw6/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_suspend@sysfs-reader:
    - shard-skl:          [INCOMPLETE][57] ([fdo#104108]) -> [PASS][58] +1 similar issue
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl1/igt@i915_suspend@sysfs-reader.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-hsw:          [INCOMPLETE][59] ([fdo#103540]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-hsw1/igt@kms_flip@flip-vs-suspend.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-hsw5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [DMESG-WARN][61] ([fdo#108566]) -> [PASS][62] +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt:
    - shard-iclb:         [FAIL][63] ([fdo#103167]) -> [PASS][64] +5 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-blt.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [DMESG-WARN][65] ([fdo#108566]) -> [PASS][66] +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [FAIL][67] ([fdo#108145]) -> [PASS][68] +1 similar issue
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-skl10/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_basic:
    - shard-iclb:         [SKIP][69] ([fdo#109441]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@kms_psr@psr2_basic.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb2/igt@kms_psr@psr2_basic.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][71] ([fdo#111329]) -> [SKIP][72] ([fdo#109276] / [fdo#112080])
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@gem_eio@kms:
    - shard-snb:          [INCOMPLETE][73] ([fdo#105411]) -> [DMESG-WARN][74] ([fdo#111780 ] / [fdo#111781])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-snb6/igt@gem_eio@kms.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-snb1/igt@gem_eio@kms.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [SKIP][75] ([fdo#111865]) -> [FAIL][76] ([fdo#111830 ])
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-tglb6/igt@i915_pm_dc@dc6-dpms.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@kms_psr@psr2_suspend:
    - shard-iclb:         [DMESG-WARN][77] ([fdo#107724]) -> [SKIP][78] ([fdo#109441])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7353/shard-iclb2/igt@kms_psr@psr2_suspend.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/shard-iclb6/igt@kms_psr@psr2_suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104782]: https://bugs.freedesktop.org/show_bug.cgi?id=104782
  [fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#107931]: https://bugs.freedesktop.org/show_bug.cgi?id=107931
  [fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111329]: https://bugs.freedesktop.org/show_bug.cgi?id=111329
  [fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
  [fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
  [fdo#111780 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111780 
  [fdo#111781]: https://bugs.freedesktop.org/show_bug.cgi?id=111781
  [fdo#111830 ]: https://bugs.freedesktop.org/show_bug.cgi?id=111830 
  [fdo#111832]: https://bugs.freedesktop.org/show_bug.cgi?id=111832
  [fdo#111850]: https://bugs.freedesktop.org/show_bug.cgi?id=111850
  [fdo#111865]: https://bugs.freedesktop.org/show_bug.cgi?id=111865
  [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
  [fdo#112068 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112068 
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146


Participating hosts (11 -> 11)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7353 -> Patchwork_15285

  CI-20190529: 20190529
  CI_DRM_7353: 18d4d81004d8407cd4dbbebdafb2ccd77eb52872 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15285: 885e46a4e56d44b8230b59ae99d3f76b26be581b @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15285/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-19 23:13     ` Matt Roper
  0 siblings, 0 replies; 23+ messages in thread
From: Matt Roper @ 2019-11-19 23:13 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Fri, Nov 15, 2019 at 04:54:00PM +0200, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
> 
> v2:
>     - Rework watermark calculation algorithm to
>       attempt to calculate Level 0 watermark
>       with added sagv block time latency and
>       check if it fits in DBuf in order to
>       determine if SAGV can be enabled already
>       at this stage, just as BSpec 49325 states.
>       if that fails rollback to usual Level 0
>       latency and disable SAGV.
>     - Remove unneeded tabs(James Ausmus)
> 
> v3: Rebased the patch
> 
> v4: - Added back interlaced check for Gen12 and
>       added separate function for TGL SAGV check
>       (thanks to James Ausmus for spotting)
>     - Removed unneeded gen check
>     - Extracted Gen12 SAGV decision making code
>       to a separate function from skl_compute_wm
> 
> v5: - Added SAGV global state to dev_priv, because
>       we need to track all pipes, not only those
>       in atomic state. Each pipe has now correspondent
>       bit mask reflecting, whether it can tolerate
>       SAGV or not(thanks to Ville Syrjala for suggestions).
>     - Now using active flag instead of enable in crc
>       usage check.
> 
> v6: - Fixed rebase conflicts
> 
> v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
>       calls when copying level 0 water marks for enabled SAGV, to
>       fix this now simply using that field right away, without copying,
>       for that introduced a new wm_level accessor which decides which
>       wm_level to return based on SAGV state.
> 
> v8: - Protect crtc_sagv_mask same way as we do for other global state
>       changes: i.e check if changes are needed, then grab all crtc locks
>       to serialize the changes.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
>  .../drm/i915/display/intel_display_types.h    |  15 +
>  drivers/gpu/drm/i915/i915_drv.h               |   6 +
>  drivers/gpu/drm/i915/intel_pm.c               | 418 ++++++++++++++++--
>  drivers/gpu/drm/i915/intel_pm.h               |   1 +
>  5 files changed, 409 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index adf50c4b38ad..7f31e33d0b16 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13401,7 +13401,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			   (skl_wm_level_equals(&hw_plane_wm->wm[level],

If we cache the result of 'can enable sagv' into the state structure (as
I suggest farther down the patch) then we can just compare with the
right value here rather than trying both.

> +						&sw_plane_wm->sagv_wm0) &&
> +			   (level == 0)))
>  				continue;
>  
>  			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> @@ -13453,7 +13456,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
> +						&sw_plane_wm->sagv_wm0) &&
> +			   (level == 0)))
>  				continue;
>  
>  			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> @@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  							      new_crtc_state);
>  	}
>  
> +	dev_priv->crtc_sagv_mask = state->crtc_sagv_mask;
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>  		intel_post_plane_update(old_crtc_state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 83ea04149b77..6a300cac883f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,20 @@ struct intel_atomic_state {
>  	 */
>  	u8 active_pipe_changes;
>  
> +	/*
> +	 * Contains a mask which reflects whether correspondent pipe
> +	 * can tolerate SAGV or not, so that we can make a decision
> +	 * at atomic_commit_tail stage, whether we enable it or not
> +	 * based on global state in dev_priv.
> +	 */
> +	u32 crtc_sagv_mask;

I feel like your code might flow a bit more naturally if this were
inverted and used as a mask of CRTCs that currently prohibit SAGV?

> +
> +	/*
> +	 * Used to determine if the mask has been already calculated
> +	 * for this state, to avoid unnecessary calculations.
> +	 */
> +	bool crtc_sagv_mask_set;

I think this field can go away too if we just call the function once and
cache the result in the state field.

> +
>  	u8 active_pipes;
>  	/* minimum acceptable cdclk for each pipe */
>  	int min_cdclk[I915_MAX_PIPES];
> @@ -670,6 +684,7 @@ struct skl_plane_wm {
>  	struct skl_wm_level wm[8];
>  	struct skl_wm_level uv_wm[8];
>  	struct skl_wm_level trans_wm;
> +	struct skl_wm_level sagv_wm0;
>  	bool is_planar;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1779f600fcfb..0ac9d7b006ca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1171,6 +1171,12 @@ struct drm_i915_private {
>  
>  	u32 sagv_block_time_us;
>  
> +	/*
> +	 * Contains a bit mask, whether correspondent
> +	 * pipe allows SAGV or not.
> +	 */
> +	u32 crtc_sagv_mask;
> +
>  	struct {
>  		/*
>  		 * Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 05ba9e1bd247..c914bd1862ba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
>  	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
>  }
>  
> -static bool
> +bool
>  intel_has_sagv(struct drm_i915_private *dev_priv)
>  {
> -	/* HACK! */
> -	if (IS_GEN(dev_priv, 12))
> -		return false;
> -

The SAGV work you're doing is pretty complicated and this general patch
touches a lot of different platforms (SKL, ICL, TGL, etc.).  It would be
great if we could break this up into a few patches, but if that's not
easy, I'd suggest at least moving this specific change to a final patch
all of its own so that we "flip the switch" on TGL independently of the
general rework.  That way if we wind up with TGL regressions (but no
problems on SKL/ICL) we can just revert a tiny 2-line patch rather than
reverting _all_ of your work here.

>  	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
>  		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
>  }
> @@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static void skl_set_sagv_mask(struct intel_atomic_state *state)

Minor nitpick:  I know there's a lot of inconsistent terminology used
throughout the driver, but I always expect functions with names like
'set,' 'update,' etc. to touch hardware somehow.  I prefer naming
functions like this with verbs like 'compute' or 'calc' to make it a bit
more clear (at least in my mind) that we're not doing anything here yet
except analyzing the state.

>  {
>  	struct drm_device *dev = state->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  	enum pipe pipe;
>  	int level, latency;
>  
> +	if (state->crtc_sagv_mask_set)
> +		return;
> +
>  	if (!intel_has_sagv(dev_priv))
> -		return false;
> +		return;

It seems like this check should just be at the top of
intel_can_enable_sagv() rather than duplicated in each platform's
mask-calculating function?

>  
>  	/*
>  	 * If there are no active CRTCs, no additional checks need be performed
>  	 */
>  	if (hweight8(state->active_pipes) == 0)
> -		return true;
> +		return;

This also appears to be a platform-independent check that can move up to
the intel_can_enable_sagv() level?  You don't have it in the TGL
function right now, but it seems like it should apply there as well?

>  
>  	/*
>  	 * SKL+ workaround: bspec recommends we disable SAGV when we have
>  	 * more then one pipe enabled
>  	 */
>  	if (hweight8(state->active_pipes) > 1)
> -		return false;
> +		return;
>  
>  	/* Since we're now guaranteed to only have one active CRTC... */
>  	pipe = ffs(state->active_pipes) - 1;
>  	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>  	crtc_state = to_intel_crtc_state(crtc->base.state);
> +	state->crtc_sagv_mask &= ~BIT(crtc->pipe);
>  
> -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		return false;
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> +		state->crtc_sagv_mask_set = true;
> +		return;
> +	}
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
>  		struct skl_plane_wm *wm =

In the pre-existing code for this loop (that doesn't show up in the diff
here) it looks like we're looking at the already-committed plane state
to see if the old plane FB was x-tiled...should that be looking at
the new FB from the current state instead?

> @@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  		 * incur memory latencies higher than sagv_block_time_us we
>  		 * can't enable SAGV.
>  		 */
> -		if (latency < dev_priv->sagv_block_time_us)
> +		if (latency < dev_priv->sagv_block_time_us) {
> +			state->crtc_sagv_mask_set = true;
> +			return;
> +		}
> +	}
> +
> +	state->crtc_sagv_mask |= BIT(crtc->pipe);
> +	state->crtc_sagv_mask_set = true;
> +}
> +
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> +
> +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +	int level, latency;
> +	int i;
> +	int plane_id;
> +
> +	if (state->crtc_sagv_mask_set)
> +		return;
> +
> +	if (!intel_has_sagv(dev_priv))
> +		return;
> +
> +	/*
> +	 * If there are no active CRTCs, no additional checks need be performed
> +	 */
> +	if (hweight8(state->active_pipes) == 0)
> +		return;
> +
> +	for_each_new_intel_crtc_in_state(state, crtc,
> +					     new_crtc_state, i) {
> +		unsigned int flags = crtc->base.state->adjusted_mode.flags;
> +		bool can_sagv;
> +
> +		if (flags & DRM_MODE_FLAG_INTERLACE)
> +			continue;
> +
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		can_sagv = true;
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			struct skl_plane_wm *wm =
> +				&new_crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +			/* Skip this plane if it's not enabled */
> +			if (!wm->wm[0].plane_en)
> +				continue;
> +
> +			/* Find the highest enabled wm level for this plane */
> +			for (level = ilk_wm_max_level(dev_priv);
> +			     !wm->wm[level].plane_en; --level) {
> +			}
> +
> +			latency = dev_priv->wm.skl_latency[level];
> +
> +			/*
> +			 * If any of the planes on this pipe don't enable
> +			 * wm levels that incur memory latencies higher than
> +			 * sagv_block_time_us we can't enable SAGV.
> +			 */
> +			if (latency < dev_priv->sagv_block_time_us) {
> +				can_sagv = false;
> +				break;
> +			}

I still think this test is a bit problematic.  What if our memory
latency is so low that we can successfully enable all watermark levels,
and the latency for the highest watermark level is still less than ICL's
10us sagv block time?  We might be able to support SAGV just fine, but
we're giving up without actually checking.

Or another case:  say our highest enabled watermark level is 3 with a
latency of 8us.  The next level up, 4, has a latency of 30us which is
high enough that our driver had to disable level 4.  We still don't know
whether the plane could have tolerated the latency of 10us (and there's
a good chance we could have...level 4 in this example was only
impossible because it was such a big latency jump over level 3).

BTW, as I mentioned before, I'm still a bit uncomfortable with the bspec
wording here; I'm going to open a bspec defect to find out for sure how
we should interpret the directions on gen11.

> +		}
> +		if (can_sagv)
> +			state->crtc_sagv_mask |= BIT(crtc->pipe);
> +		else
> +			state->crtc_sagv_mask &= ~BIT(crtc->pipe);
> +	}
> +	state->crtc_sagv_mask_set = true;
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int ret, i;
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +
> +	/*
> +	 * Make sure we always pick global state first,
> +	 * there shouldn't be any issue as we hold only locks
> +	 * to correspondent crtcs in state, however once
> +	 * we detect that we need to change SAGV mask
> +	 * in global state, we will grab all the crtc locks
> +	 * in order to get this serialized, thus other
> +	 * racing commits having other crtc locks, will have
> +	 * to start over again, as stated by Wound-Wait
> +	 * algorithm.
> +	 */
> +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		tgl_set_sagv_mask(state);
> +	else if (INTEL_GEN(dev_priv) == 11)
> +		icl_set_sagv_mask(state);
> +	else
> +		skl_set_sagv_mask(state);
> +
> +	/*
> +	 * For SAGV we need to account all the pipes,
> +	 * not only the ones which are in state currently.
> +	 * Grab all locks if we detect that we are actually
> +	 * going to do something.
> +	 */
> +	if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) {
> +		ret = intel_atomic_serialize_global_state(state);
> +		if (ret) {
> +			DRM_DEBUG_KMS("Could not serialize global state\n");
> +			return false;
> +		}
> +	}
> +
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		u32 mask = BIT(crtc->pipe);
> +		bool state_sagv_masked = (mask & state->crtc_sagv_mask) == 0;
> +
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		if (state_sagv_masked)
>  			return false;
>  	}
>  
> @@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
>  				 int color_plane);
>  static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  				 int level,
> +				 u32 latency,
>  				 const struct skl_wm_params *wp,
>  				 const struct skl_wm_level *result_prev,
>  				 struct skl_wm_level *result /* out */);
> @@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
>  	WARN_ON(ret);
>  
>  	for (level = 0; level <= max_level; level++) {
> -		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> +		u32 latency = dev_priv->wm.skl_latency[level];
> +
> +		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> +
>  		if (wm.min_ddb_alloc == U16_MAX)
>  			break;
>  
> @@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
>  	return total_data_rate;
>  }
>  
> +static int
> +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> +			    struct skl_ddb_allocation *ddb /* out */)
> +{
> +	struct drm_crtc *crtc = crtc_state->uapi.crtc;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> +	u16 alloc_size;
> +	u16 total[I915_MAX_PLANES] = {};
> +	u64 total_data_rate;
> +	enum plane_id plane_id;
> +	int num_active;
> +	u64 plane_data_rate[I915_MAX_PLANES] = {};
> +	u32 blocks;
> +
> +	/*
> +	 * No need to check gen here, we call this only for gen12
> +	 */
> +	total_data_rate =
> +		icl_get_total_relative_data_rate(crtc_state,
> +						 plane_data_rate);
> +
> +	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> +					   total_data_rate,
> +					   ddb, alloc, &num_active);
> +	alloc_size = skl_ddb_entry_size(alloc);
> +	if (alloc_size == 0)
> +		return -ENOSPC;
> +
> +	/* Allocate fixed number of blocks for cursor. */
> +	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> +	alloc_size -= total[PLANE_CURSOR];
> +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> +		alloc->end - total[PLANE_CURSOR];
> +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;

All the above is basically a duplication of the pipe's DDB allocation we
have to figure out again later.  Basically our driver used to follow a
sequence of:

        * Calculate DDB (proportional algorithm)
        * Calculate watermarks

and then we switched it to:

        * Calculate watermarks
        * Calculate DDB (need-based algorithm)

If I recall correctly, the need-based DDB algorithm only really needs
the watermark values to divy up the intra-pipe plane DDB allocations so
we could still calculate the overall pipe allocations earlier if we
wanted to.  Doing so would allow you to avoid this duplication of logic:

        * Calculate pipe-level DDB allocations
        * Calculate watermarks
        * Calculate plane-level DDB (need-based algorithm)

> +
> +	/*
> +	 * Do check if we can fit L0 + sagv_block_time and
> +	 * disable SAGV if we can't.
> +	 */
> +	blocks = 0;
> +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		const struct skl_plane_wm *wm =
> +			&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +		if (plane_id == PLANE_CURSOR) {
> +			if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> +				    total[PLANE_CURSOR])) {
> +				blocks = U32_MAX;
> +				break;
> +			}
> +			continue;
> +		}
> +
> +		blocks += wm->sagv_wm0.min_ddb_alloc;
> +		if (blocks > alloc_size)
> +			return -ENOSPC;
> +	}
> +	return 0;
> +}
> +
> +const struct skl_wm_level *
> +skl_plane_wm_level(struct intel_plane *plane,
> +		const struct intel_crtc_state *crtc_state,
> +		int level,
> +		bool yuv)
> +{
> +	struct drm_atomic_state *state = crtc_state->uapi.state;
> +	enum plane_id plane_id = plane->id;
> +	const struct skl_plane_wm *wm =
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +	/*
> +	 * Looks ridicilous but need to check if state is not
> +	 * NULL here as it might be as some cursor plane manipulations
> +	 * seem to happen when no atomic state is actually present,
> +	 * despite crtc_state is allocated. Removing state check
> +	 * from here will result in kernel panic on boot.
> +	 * However we now need to check whether should be use SAGV
> +	 * wm levels here.
> +	 */
> +	if (state) {
> +		struct intel_atomic_state *intel_state =
> +			to_intel_atomic_state(state);
> +		if (intel_can_enable_sagv(intel_state) && !level)

I think we should calculate the 'can enable SAGV' value once and cache
it into a field of the state structure so that you don't have to keep
re-calling this on every single plane/level combination.  Also you can
then use the proper setting to figure out how to verify the hardware
readout value as noted earlier. 

Also one thing I don't see (maybe I'm just overlooking it) is that we
may also need to adjust higher watermark levels upward too:

        "The latency input to the watermark calculation for each level
        must be greater than or equal to the lower level. The latency
        increase to level 0 for SAGV requires the upper levels to be
        adjusted to meet that requirement. Use MIN(latency for this
        level, latency for next lower level) to correct the latency."

Basically it seems like we should just calculate two full sets of
watermark values for all levels and then choose between them at the end?


Matt

> +			return &wm->sagv_wm0;
> +	}
> +
> +	return yuv ? &wm->uv_wm[level] : &wm->wm[level];
> +}
> +
>  static int
>  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  		      struct skl_ddb_allocation *ddb /* out */)
> @@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	u16 uv_total[I915_MAX_PLANES] = {};
>  	u64 total_data_rate;
>  	enum plane_id plane_id;
> +	struct intel_plane *plane;
> +	const struct skl_wm_level *wm_level;
> +	const struct skl_wm_level *wm_uv_level;
>  	int num_active;
>  	u64 plane_data_rate[I915_MAX_PLANES] = {};
>  	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> @@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	 */
>  	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
>  		blocks = 0;
> -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> -			const struct skl_plane_wm *wm =
> -				&crtc_state->wm.skl.optimal.planes[plane_id];
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> +			plane_id = plane->id;
> +			wm_level = skl_plane_wm_level(plane, crtc_state,
> +						      level, false);
> +			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> +							 level, true);
>  
>  			if (plane_id == PLANE_CURSOR) {
> -				if (WARN_ON(wm->wm[level].min_ddb_alloc >
> +				if (WARN_ON(wm_level->min_ddb_alloc >
>  					    total[PLANE_CURSOR])) {
>  					blocks = U32_MAX;
>  					break;
> @@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  				continue;
>  			}
>  
> -			blocks += wm->wm[level].min_ddb_alloc;
> -			blocks += wm->uv_wm[level].min_ddb_alloc;
> +			blocks += wm_level->min_ddb_alloc;
> +			blocks += wm_uv_level->min_ddb_alloc;
>  		}
>  
>  		if (blocks <= alloc_size) {
> @@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	 * watermark level, plus an extra share of the leftover blocks
>  	 * proportional to its relative data rate.
>  	 */
> -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> -		const struct skl_plane_wm *wm =
> -			&crtc_state->wm.skl.optimal.planes[plane_id];
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
>  		u64 rate;
>  		u16 extra;
>  
> +		plane_id = plane->id;
> +		wm_level = skl_plane_wm_level(plane, crtc_state,
> +					      level, false);
> +		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> +						 level, true);
> +
>  		if (plane_id == PLANE_CURSOR)
>  			continue;
>  
> @@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  		extra = min_t(u16, alloc_size,
>  			      DIV64_U64_ROUND_UP(alloc_size * rate,
>  						 total_data_rate));
> -		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> +		total[plane_id] = wm_level->min_ddb_alloc + extra;
>  		alloc_size -= extra;
>  		total_data_rate -= rate;
>  
> @@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  		extra = min_t(u16, alloc_size,
>  			      DIV64_U64_ROUND_UP(alloc_size * rate,
>  						 total_data_rate));
> -		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> +		uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
>  		alloc_size -= extra;
>  		total_data_rate -= rate;
>  	}
> @@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	 * that aren't actually possible.
>  	 */
>  	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
>  			struct skl_plane_wm *wm =
> -				&crtc_state->wm.skl.optimal.planes[plane_id];
> +				&crtc_state->wm.skl.optimal.planes[plane->id];
> +
> +			wm_level = skl_plane_wm_level(plane, crtc_state,
> +						      level, false);
> +			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> +						      level, true);
>  
>  			/*
>  			 * We only disable the watermarks for each plane if
> @@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  			 *  planes must be enabled before the level will be used."
>  			 * So this is actually safe to do.
>  			 */
> -			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
> -			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
> -				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
> +			if (wm_level->min_ddb_alloc > total[plane->id] ||
> +			    wm_uv_level->min_ddb_alloc > uv_total[plane->id])
> +				memset(&wm->wm[level], 0,
> +				       sizeof(struct skl_wm_level));
>  
>  			/*
>  			 * Wa_1408961008:icl, ehl
> @@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  			 */
>  			if (IS_GEN(dev_priv, 11) &&
>  			    level == 1 && wm->wm[0].plane_en) {
> -				wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> -				wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> -				wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> +				wm_level = skl_plane_wm_level(plane, crtc_state,
> +							      0, false);
> +				wm->wm[level].plane_res_b =
> +					wm_level->plane_res_b;
> +				wm->wm[level].plane_res_l =
> +					wm_level->plane_res_l;
> +				wm->wm[level].ignore_lines =
> +					wm_level->ignore_lines;
>  			}
>  		}
>  	}
> @@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
>  
>  static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  				 int level,
> +				 u32 latency,
>  				 const struct skl_wm_params *wp,
>  				 const struct skl_wm_level *result_prev,
>  				 struct skl_wm_level *result /* out */)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	u32 latency = dev_priv->wm.skl_latency[level];
>  	uint_fixed_16_16_t method1, method2;
>  	uint_fixed_16_16_t selected_result;
>  	u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  static void
>  skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>  		      const struct skl_wm_params *wm_params,
> -		      struct skl_wm_level *levels)
> +		      struct skl_plane_wm *plane_wm,
> +		      bool yuv)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int level, max_level = ilk_wm_max_level(dev_priv);
> +	/*
> +	 * Check which kind of plane is it and based on that calculate
> +	 * correspondent WM levels.
> +	 */
> +	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
>  	struct skl_wm_level *result_prev = &levels[0];
>  
>  	for (level = 0; level <= max_level; level++) {
>  		struct skl_wm_level *result = &levels[level];
> +		u32 latency = dev_priv->wm.skl_latency[level];
>  
> -		skl_compute_plane_wm(crtc_state, level, wm_params,
> -				     result_prev, result);
> +		skl_compute_plane_wm(crtc_state, level, latency,
> +				     wm_params, result_prev, result);
>  
>  		result_prev = result;
>  	}
> +	/*
> +	 * For Gen12 if it is an L0 we need to also
> +	 * consider sagv_block_time when calculating
> +	 * L0 watermark - we will need that when making
> +	 * a decision whether enable SAGV or not.
> +	 * For older gens we agreed to copy L0 value for
> +	 * compatibility.
> +	 */
> +	if ((INTEL_GEN(dev_priv) >= 12)) {
> +		u32 latency = dev_priv->wm.skl_latency[0];
> +
> +		latency += dev_priv->sagv_block_time_us;
> +		skl_compute_plane_wm(crtc_state, 0, latency,
> +		     wm_params, &levels[0],
> +		    &plane_wm->sagv_wm0);
> +	} else
> +		memcpy(&plane_wm->sagv_wm0, &levels[0],
> +			sizeof(struct skl_wm_level));
>  }
>  
>  static u32
> @@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> -	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> +	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
>  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
>  
>  	return 0;
> @@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> -	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> +	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
>  
>  	return 0;
>  }
> @@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  	const struct skl_ddb_entry *ddb_uv =
>  		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> +	const struct skl_wm_level *wm_level;
>  
>  	for (level = 0; level <= max_level; level++) {
> +		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
>  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> -				   &wm->wm[level]);
> +				   wm_level);
>  	}
>  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>  			   &wm->trans_wm);
> @@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
>  		&crtc_state->wm.skl.optimal.planes[plane_id];
>  	const struct skl_ddb_entry *ddb =
>  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +	const struct skl_wm_level *wm_level;
>  
>  	for (level = 0; level <= max_level; level++) {
> +		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
>  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> -				   &wm->wm[level]);
> +				   wm_level);
>  	}
>  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>  
> @@ -5451,18 +5729,73 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +	struct intel_crtc_state *old_crtc_state;
> +	struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> +	int ret;
> +	int i;
> +	struct intel_plane *plane;
> +
> +	if (state->crtc_sagv_mask_set)
> +		return;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		int pipe_bit = BIT(crtc->pipe);
> +		bool skip = true;
> +
> +		/*
> +		 * If we had set this mast already once for this state,
> +		 * no need to waste CPU cycles for doing this again.
> +		 */
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +			enum plane_id plane_id = plane->id;
> +
> +			if (!skl_plane_wm_equals(dev_priv,
> +				&old_crtc_state->wm.skl.optimal.planes[plane_id],
> +				&new_crtc_state->wm.skl.optimal.planes[plane_id])) {
> +				skip = false;
> +				break;
> +			}
> +		}
> +
> +		/*
> +		 * Check if wm levels are actually the same as for previous
> +		 * state, which means we can just skip doing this long check
> +		 * and just  copy correspondent bit from previous state.
> +		 */
> +		if (skip)
> +			continue;
> +
> +		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> +		if (!ret)
> +			state->crtc_sagv_mask |= pipe_bit;
> +		else
> +			state->crtc_sagv_mask &= ~pipe_bit;
> +	}
> +	state->crtc_sagv_mask_set = true;
> +}
> +
>  static int
>  skl_compute_wm(struct intel_atomic_state *state)
>  {
>  	struct intel_crtc *crtc;
>  	struct intel_crtc_state *new_crtc_state;
>  	struct intel_crtc_state *old_crtc_state;
> -	struct skl_ddb_values *results = &state->wm_results;
>  	int ret, i;
> +	struct skl_ddb_values *results = &state->wm_results;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  
>  	/* Clear all dirty flags */
>  	results->dirty_pipes = 0;
>  
> +	/* If we exit before check is done */
> +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
> +
>  	ret = skl_ddb_add_affected_pipes(state);
>  	if (ret)
>  		return ret;
> @@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  				val = I915_READ(CUR_WM(pipe, level));
>  
>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> +			if (level == 0)
> +				memcpy(&wm->sagv_wm0, &wm->wm[level],
> +					sizeof(struct skl_wm_level));
>  		}
>  
>  		if (plane_id != PLANE_CURSOR)
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..53275860731a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
>  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
>  bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_has_sagv(struct drm_i915_private *dev_priv);
>  int intel_enable_sagv(struct drm_i915_private *dev_priv);
>  int intel_disable_sagv(struct drm_i915_private *dev_priv);
>  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> -- 
> 2.17.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-19 23:13     ` Matt Roper
  0 siblings, 0 replies; 23+ messages in thread
From: Matt Roper @ 2019-11-19 23:13 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Fri, Nov 15, 2019 at 04:54:00PM +0200, Stanislav Lisovskiy wrote:
> Currently intel_can_enable_sagv function contains
> a mix of workarounds for different platforms
> some of them are not valid for gens >= 11 already,
> so lets split it into separate functions.
> 
> v2:
>     - Rework watermark calculation algorithm to
>       attempt to calculate Level 0 watermark
>       with added sagv block time latency and
>       check if it fits in DBuf in order to
>       determine if SAGV can be enabled already
>       at this stage, just as BSpec 49325 states.
>       if that fails rollback to usual Level 0
>       latency and disable SAGV.
>     - Remove unneeded tabs(James Ausmus)
> 
> v3: Rebased the patch
> 
> v4: - Added back interlaced check for Gen12 and
>       added separate function for TGL SAGV check
>       (thanks to James Ausmus for spotting)
>     - Removed unneeded gen check
>     - Extracted Gen12 SAGV decision making code
>       to a separate function from skl_compute_wm
> 
> v5: - Added SAGV global state to dev_priv, because
>       we need to track all pipes, not only those
>       in atomic state. Each pipe has now correspondent
>       bit mask reflecting, whether it can tolerate
>       SAGV or not(thanks to Ville Syrjala for suggestions).
>     - Now using active flag instead of enable in crc
>       usage check.
> 
> v6: - Fixed rebase conflicts
> 
> v7: - kms_cursor_legacy seems to get broken because of multiple memcpy
>       calls when copying level 0 water marks for enabled SAGV, to
>       fix this now simply using that field right away, without copying,
>       for that introduced a new wm_level accessor which decides which
>       wm_level to return based on SAGV state.
> 
> v8: - Protect crtc_sagv_mask same way as we do for other global state
>       changes: i.e check if changes are needed, then grab all crtc locks
>       to serialize the changes.
> 
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
>  .../drm/i915/display/intel_display_types.h    |  15 +
>  drivers/gpu/drm/i915/i915_drv.h               |   6 +
>  drivers/gpu/drm/i915/intel_pm.c               | 418 ++++++++++++++++--
>  drivers/gpu/drm/i915/intel_pm.h               |   1 +
>  5 files changed, 409 insertions(+), 43 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index adf50c4b38ad..7f31e33d0b16 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -13401,7 +13401,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			   (skl_wm_level_equals(&hw_plane_wm->wm[level],

If we cache the result of 'can enable sagv' into the state structure (as
I suggest farther down the patch) then we can just compare with the
right value here rather than trying both.

> +						&sw_plane_wm->sagv_wm0) &&
> +			   (level == 0)))
>  				continue;
>  
>  			DRM_ERROR("mismatch in WM pipe %c plane %d level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> @@ -13453,7 +13456,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
>  		/* Watermarks */
>  		for (level = 0; level <= max_level; level++) {
>  			if (skl_wm_level_equals(&hw_plane_wm->wm[level],
> -						&sw_plane_wm->wm[level]))
> +						&sw_plane_wm->wm[level]) ||
> +			   (skl_wm_level_equals(&hw_plane_wm->wm[level],
> +						&sw_plane_wm->sagv_wm0) &&
> +			   (level == 0)))
>  				continue;
>  
>  			DRM_ERROR("mismatch in WM pipe %c cursor level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> @@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  							      new_crtc_state);
>  	}
>  
> +	dev_priv->crtc_sagv_mask = state->crtc_sagv_mask;
> +
>  	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
>  		intel_post_plane_update(old_crtc_state);
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 83ea04149b77..6a300cac883f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -490,6 +490,20 @@ struct intel_atomic_state {
>  	 */
>  	u8 active_pipe_changes;
>  
> +	/*
> +	 * Contains a mask which reflects whether correspondent pipe
> +	 * can tolerate SAGV or not, so that we can make a decision
> +	 * at atomic_commit_tail stage, whether we enable it or not
> +	 * based on global state in dev_priv.
> +	 */
> +	u32 crtc_sagv_mask;

I feel like your code might flow a bit more naturally if this were
inverted and used as a mask of CRTCs that currently prohibit SAGV?

> +
> +	/*
> +	 * Used to determine if the mask has been already calculated
> +	 * for this state, to avoid unnecessary calculations.
> +	 */
> +	bool crtc_sagv_mask_set;

I think this field can go away too if we just call the function once and
cache the result in the state field.

> +
>  	u8 active_pipes;
>  	/* minimum acceptable cdclk for each pipe */
>  	int min_cdclk[I915_MAX_PIPES];
> @@ -670,6 +684,7 @@ struct skl_plane_wm {
>  	struct skl_wm_level wm[8];
>  	struct skl_wm_level uv_wm[8];
>  	struct skl_wm_level trans_wm;
> +	struct skl_wm_level sagv_wm0;
>  	bool is_planar;
>  };
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 1779f600fcfb..0ac9d7b006ca 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1171,6 +1171,12 @@ struct drm_i915_private {
>  
>  	u32 sagv_block_time_us;
>  
> +	/*
> +	 * Contains a bit mask, whether correspondent
> +	 * pipe allows SAGV or not.
> +	 */
> +	u32 crtc_sagv_mask;
> +
>  	struct {
>  		/*
>  		 * Raw watermark latency values:
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 05ba9e1bd247..c914bd1862ba 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
>  	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
>  }
>  
> -static bool
> +bool
>  intel_has_sagv(struct drm_i915_private *dev_priv)
>  {
> -	/* HACK! */
> -	if (IS_GEN(dev_priv, 12))
> -		return false;
> -

The SAGV work you're doing is pretty complicated and this general patch
touches a lot of different platforms (SKL, ICL, TGL, etc.).  It would be
great if we could break this up into a few patches, but if that's not
easy, I'd suggest at least moving this specific change to a final patch
all of its own so that we "flip the switch" on TGL independently of the
general rework.  That way if we wind up with TGL regressions (but no
problems on SKL/ICL) we can just revert a tiny 2-line patch rather than
reverting _all_ of your work here.

>  	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
>  		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
>  }
> @@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
>  	return 0;
>  }
>  
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +static void skl_set_sagv_mask(struct intel_atomic_state *state)

Minor nitpick:  I know there's a lot of inconsistent terminology used
throughout the driver, but I always expect functions with names like
'set,' 'update,' etc. to touch hardware somehow.  I prefer naming
functions like this with verbs like 'compute' or 'calc' to make it a bit
more clear (at least in my mind) that we're not doing anything here yet
except analyzing the state.

>  {
>  	struct drm_device *dev = state->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  	enum pipe pipe;
>  	int level, latency;
>  
> +	if (state->crtc_sagv_mask_set)
> +		return;
> +
>  	if (!intel_has_sagv(dev_priv))
> -		return false;
> +		return;

It seems like this check should just be at the top of
intel_can_enable_sagv() rather than duplicated in each platform's
mask-calculating function?

>  
>  	/*
>  	 * If there are no active CRTCs, no additional checks need be performed
>  	 */
>  	if (hweight8(state->active_pipes) == 0)
> -		return true;
> +		return;

This also appears to be a platform-independent check that can move up to
the intel_can_enable_sagv() level?  You don't have it in the TGL
function right now, but it seems like it should apply there as well?

>  
>  	/*
>  	 * SKL+ workaround: bspec recommends we disable SAGV when we have
>  	 * more then one pipe enabled
>  	 */
>  	if (hweight8(state->active_pipes) > 1)
> -		return false;
> +		return;
>  
>  	/* Since we're now guaranteed to only have one active CRTC... */
>  	pipe = ffs(state->active_pipes) - 1;
>  	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
>  	crtc_state = to_intel_crtc_state(crtc->base.state);
> +	state->crtc_sagv_mask &= ~BIT(crtc->pipe);
>  
> -	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> -		return false;
> +	if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
> +		state->crtc_sagv_mask_set = true;
> +		return;
> +	}
>  
>  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
>  		struct skl_plane_wm *wm =

In the pre-existing code for this loop (that doesn't show up in the diff
here) it looks like we're looking at the already-committed plane state
to see if the old plane FB was x-tiled...should that be looking at
the new FB from the current state instead?

> @@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
>  		 * incur memory latencies higher than sagv_block_time_us we
>  		 * can't enable SAGV.
>  		 */
> -		if (latency < dev_priv->sagv_block_time_us)
> +		if (latency < dev_priv->sagv_block_time_us) {
> +			state->crtc_sagv_mask_set = true;
> +			return;
> +		}
> +	}
> +
> +	state->crtc_sagv_mask |= BIT(crtc->pipe);
> +	state->crtc_sagv_mask_set = true;
> +}
> +
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> +
> +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +	int level, latency;
> +	int i;
> +	int plane_id;
> +
> +	if (state->crtc_sagv_mask_set)
> +		return;
> +
> +	if (!intel_has_sagv(dev_priv))
> +		return;
> +
> +	/*
> +	 * If there are no active CRTCs, no additional checks need be performed
> +	 */
> +	if (hweight8(state->active_pipes) == 0)
> +		return;
> +
> +	for_each_new_intel_crtc_in_state(state, crtc,
> +					     new_crtc_state, i) {
> +		unsigned int flags = crtc->base.state->adjusted_mode.flags;
> +		bool can_sagv;
> +
> +		if (flags & DRM_MODE_FLAG_INTERLACE)
> +			continue;
> +
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		can_sagv = true;
> +		for_each_plane_id_on_crtc(crtc, plane_id) {
> +			struct skl_plane_wm *wm =
> +				&new_crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +			/* Skip this plane if it's not enabled */
> +			if (!wm->wm[0].plane_en)
> +				continue;
> +
> +			/* Find the highest enabled wm level for this plane */
> +			for (level = ilk_wm_max_level(dev_priv);
> +			     !wm->wm[level].plane_en; --level) {
> +			}
> +
> +			latency = dev_priv->wm.skl_latency[level];
> +
> +			/*
> +			 * If any of the planes on this pipe don't enable
> +			 * wm levels that incur memory latencies higher than
> +			 * sagv_block_time_us we can't enable SAGV.
> +			 */
> +			if (latency < dev_priv->sagv_block_time_us) {
> +				can_sagv = false;
> +				break;
> +			}

I still think this test is a bit problematic.  What if our memory
latency is so low that we can successfully enable all watermark levels,
and the latency for the highest watermark level is still less than ICL's
10us sagv block time?  We might be able to support SAGV just fine, but
we're giving up without actually checking.

Or another case:  say our highest enabled watermark level is 3 with a
latency of 8us.  The next level up, 4, has a latency of 30us which is
high enough that our driver had to disable level 4.  We still don't know
whether the plane could have tolerated the latency of 10us (and there's
a good chance we could have...level 4 in this example was only
impossible because it was such a big latency jump over level 3).

BTW, as I mentioned before, I'm still a bit uncomfortable with the bspec
wording here; I'm going to open a bspec defect to find out for sure how
we should interpret the directions on gen11.

> +		}
> +		if (can_sagv)
> +			state->crtc_sagv_mask |= BIT(crtc->pipe);
> +		else
> +			state->crtc_sagv_mask &= ~BIT(crtc->pipe);
> +	}
> +	state->crtc_sagv_mask_set = true;
> +}
> +
> +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int ret, i;
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +
> +	/*
> +	 * Make sure we always pick global state first,
> +	 * there shouldn't be any issue as we hold only locks
> +	 * to correspondent crtcs in state, however once
> +	 * we detect that we need to change SAGV mask
> +	 * in global state, we will grab all the crtc locks
> +	 * in order to get this serialized, thus other
> +	 * racing commits having other crtc locks, will have
> +	 * to start over again, as stated by Wound-Wait
> +	 * algorithm.
> +	 */
> +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
> +
> +	if (INTEL_GEN(dev_priv) >= 12)
> +		tgl_set_sagv_mask(state);
> +	else if (INTEL_GEN(dev_priv) == 11)
> +		icl_set_sagv_mask(state);
> +	else
> +		skl_set_sagv_mask(state);
> +
> +	/*
> +	 * For SAGV we need to account all the pipes,
> +	 * not only the ones which are in state currently.
> +	 * Grab all locks if we detect that we are actually
> +	 * going to do something.
> +	 */
> +	if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) {
> +		ret = intel_atomic_serialize_global_state(state);
> +		if (ret) {
> +			DRM_DEBUG_KMS("Could not serialize global state\n");
> +			return false;
> +		}
> +	}
> +
> +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> +		u32 mask = BIT(crtc->pipe);
> +		bool state_sagv_masked = (mask & state->crtc_sagv_mask) == 0;
> +
> +		if (!new_crtc_state->hw.active)
> +			continue;
> +
> +		if (state_sagv_masked)
>  			return false;
>  	}
>  
> @@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
>  				 int color_plane);
>  static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  				 int level,
> +				 u32 latency,
>  				 const struct skl_wm_params *wp,
>  				 const struct skl_wm_level *result_prev,
>  				 struct skl_wm_level *result /* out */);
> @@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct intel_crtc_state *crtc_state,
>  	WARN_ON(ret);
>  
>  	for (level = 0; level <= max_level; level++) {
> -		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> +		u32 latency = dev_priv->wm.skl_latency[level];
> +
> +		skl_compute_plane_wm(crtc_state, level, latency, &wp, &wm, &wm);
> +
>  		if (wm.min_ddb_alloc == U16_MAX)
>  			break;
>  
> @@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
>  	return total_data_rate;
>  }
>  
> +static int
> +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> +			    struct skl_ddb_allocation *ddb /* out */)
> +{
> +	struct drm_crtc *crtc = crtc_state->uapi.crtc;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> +	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> +	u16 alloc_size;
> +	u16 total[I915_MAX_PLANES] = {};
> +	u64 total_data_rate;
> +	enum plane_id plane_id;
> +	int num_active;
> +	u64 plane_data_rate[I915_MAX_PLANES] = {};
> +	u32 blocks;
> +
> +	/*
> +	 * No need to check gen here, we call this only for gen12
> +	 */
> +	total_data_rate =
> +		icl_get_total_relative_data_rate(crtc_state,
> +						 plane_data_rate);
> +
> +	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> +					   total_data_rate,
> +					   ddb, alloc, &num_active);
> +	alloc_size = skl_ddb_entry_size(alloc);
> +	if (alloc_size == 0)
> +		return -ENOSPC;
> +
> +	/* Allocate fixed number of blocks for cursor. */
> +	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state, num_active);
> +	alloc_size -= total[PLANE_CURSOR];
> +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> +		alloc->end - total[PLANE_CURSOR];
> +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;

All the above is basically a duplication of the pipe's DDB allocation we
have to figure out again later.  Basically our driver used to follow a
sequence of:

        * Calculate DDB (proportional algorithm)
        * Calculate watermarks

and then we switched it to:

        * Calculate watermarks
        * Calculate DDB (need-based algorithm)

If I recall correctly, the need-based DDB algorithm only really needs
the watermark values to divy up the intra-pipe plane DDB allocations so
we could still calculate the overall pipe allocations earlier if we
wanted to.  Doing so would allow you to avoid this duplication of logic:

        * Calculate pipe-level DDB allocations
        * Calculate watermarks
        * Calculate plane-level DDB (need-based algorithm)

> +
> +	/*
> +	 * Do check if we can fit L0 + sagv_block_time and
> +	 * disable SAGV if we can't.
> +	 */
> +	blocks = 0;
> +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		const struct skl_plane_wm *wm =
> +			&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +		if (plane_id == PLANE_CURSOR) {
> +			if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> +				    total[PLANE_CURSOR])) {
> +				blocks = U32_MAX;
> +				break;
> +			}
> +			continue;
> +		}
> +
> +		blocks += wm->sagv_wm0.min_ddb_alloc;
> +		if (blocks > alloc_size)
> +			return -ENOSPC;
> +	}
> +	return 0;
> +}
> +
> +const struct skl_wm_level *
> +skl_plane_wm_level(struct intel_plane *plane,
> +		const struct intel_crtc_state *crtc_state,
> +		int level,
> +		bool yuv)
> +{
> +	struct drm_atomic_state *state = crtc_state->uapi.state;
> +	enum plane_id plane_id = plane->id;
> +	const struct skl_plane_wm *wm =
> +		&crtc_state->wm.skl.optimal.planes[plane_id];
> +
> +	/*
> +	 * Looks ridicilous but need to check if state is not
> +	 * NULL here as it might be as some cursor plane manipulations
> +	 * seem to happen when no atomic state is actually present,
> +	 * despite crtc_state is allocated. Removing state check
> +	 * from here will result in kernel panic on boot.
> +	 * However we now need to check whether should be use SAGV
> +	 * wm levels here.
> +	 */
> +	if (state) {
> +		struct intel_atomic_state *intel_state =
> +			to_intel_atomic_state(state);
> +		if (intel_can_enable_sagv(intel_state) && !level)

I think we should calculate the 'can enable SAGV' value once and cache
it into a field of the state structure so that you don't have to keep
re-calling this on every single plane/level combination.  Also you can
then use the proper setting to figure out how to verify the hardware
readout value as noted earlier. 

Also one thing I don't see (maybe I'm just overlooking it) is that we
may also need to adjust higher watermark levels upward too:

        "The latency input to the watermark calculation for each level
        must be greater than or equal to the lower level. The latency
        increase to level 0 for SAGV requires the upper levels to be
        adjusted to meet that requirement. Use MIN(latency for this
        level, latency for next lower level) to correct the latency."

Basically it seems like we should just calculate two full sets of
watermark values for all levels and then choose between them at the end?


Matt

> +			return &wm->sagv_wm0;
> +	}
> +
> +	return yuv ? &wm->uv_wm[level] : &wm->wm[level];
> +}
> +
>  static int
>  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  		      struct skl_ddb_allocation *ddb /* out */)
> @@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	u16 uv_total[I915_MAX_PLANES] = {};
>  	u64 total_data_rate;
>  	enum plane_id plane_id;
> +	struct intel_plane *plane;
> +	const struct skl_wm_level *wm_level;
> +	const struct skl_wm_level *wm_uv_level;
>  	int num_active;
>  	u64 plane_data_rate[I915_MAX_PLANES] = {};
>  	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> @@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	 */
>  	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
>  		blocks = 0;
> -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> -			const struct skl_plane_wm *wm =
> -				&crtc_state->wm.skl.optimal.planes[plane_id];
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
> +			plane_id = plane->id;
> +			wm_level = skl_plane_wm_level(plane, crtc_state,
> +						      level, false);
> +			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> +							 level, true);
>  
>  			if (plane_id == PLANE_CURSOR) {
> -				if (WARN_ON(wm->wm[level].min_ddb_alloc >
> +				if (WARN_ON(wm_level->min_ddb_alloc >
>  					    total[PLANE_CURSOR])) {
>  					blocks = U32_MAX;
>  					break;
> @@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  				continue;
>  			}
>  
> -			blocks += wm->wm[level].min_ddb_alloc;
> -			blocks += wm->uv_wm[level].min_ddb_alloc;
> +			blocks += wm_level->min_ddb_alloc;
> +			blocks += wm_uv_level->min_ddb_alloc;
>  		}
>  
>  		if (blocks <= alloc_size) {
> @@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	 * watermark level, plus an extra share of the leftover blocks
>  	 * proportional to its relative data rate.
>  	 */
> -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> -		const struct skl_plane_wm *wm =
> -			&crtc_state->wm.skl.optimal.planes[plane_id];
> +	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
>  		u64 rate;
>  		u16 extra;
>  
> +		plane_id = plane->id;
> +		wm_level = skl_plane_wm_level(plane, crtc_state,
> +					      level, false);
> +		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> +						 level, true);
> +
>  		if (plane_id == PLANE_CURSOR)
>  			continue;
>  
> @@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  		extra = min_t(u16, alloc_size,
>  			      DIV64_U64_ROUND_UP(alloc_size * rate,
>  						 total_data_rate));
> -		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> +		total[plane_id] = wm_level->min_ddb_alloc + extra;
>  		alloc_size -= extra;
>  		total_data_rate -= rate;
>  
> @@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  		extra = min_t(u16, alloc_size,
>  			      DIV64_U64_ROUND_UP(alloc_size * rate,
>  						 total_data_rate));
> -		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
> +		uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
>  		alloc_size -= extra;
>  		total_data_rate -= rate;
>  	}
> @@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  	 * that aren't actually possible.
>  	 */
>  	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane) {
>  			struct skl_plane_wm *wm =
> -				&crtc_state->wm.skl.optimal.planes[plane_id];
> +				&crtc_state->wm.skl.optimal.planes[plane->id];
> +
> +			wm_level = skl_plane_wm_level(plane, crtc_state,
> +						      level, false);
> +			wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> +						      level, true);
>  
>  			/*
>  			 * We only disable the watermarks for each plane if
> @@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  			 *  planes must be enabled before the level will be used."
>  			 * So this is actually safe to do.
>  			 */
> -			if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
> -			    wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
> -				memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
> +			if (wm_level->min_ddb_alloc > total[plane->id] ||
> +			    wm_uv_level->min_ddb_alloc > uv_total[plane->id])
> +				memset(&wm->wm[level], 0,
> +				       sizeof(struct skl_wm_level));
>  
>  			/*
>  			 * Wa_1408961008:icl, ehl
> @@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
>  			 */
>  			if (IS_GEN(dev_priv, 11) &&
>  			    level == 1 && wm->wm[0].plane_en) {
> -				wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
> -				wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
> -				wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
> +				wm_level = skl_plane_wm_level(plane, crtc_state,
> +							      0, false);
> +				wm->wm[level].plane_res_b =
> +					wm_level->plane_res_b;
> +				wm->wm[level].plane_res_l =
> +					wm_level->plane_res_l;
> +				wm->wm[level].ignore_lines =
> +					wm_level->ignore_lines;
>  			}
>  		}
>  	}
> @@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct drm_i915_private *dev_priv, int level)
>  
>  static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  				 int level,
> +				 u32 latency,
>  				 const struct skl_wm_params *wp,
>  				 const struct skl_wm_level *result_prev,
>  				 struct skl_wm_level *result /* out */)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
> -	u32 latency = dev_priv->wm.skl_latency[level];
>  	uint_fixed_16_16_t method1, method2;
>  	uint_fixed_16_16_t selected_result;
>  	u32 res_blocks, res_lines, min_ddb_alloc = 0;
> @@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
>  static void
>  skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
>  		      const struct skl_wm_params *wm_params,
> -		      struct skl_wm_level *levels)
> +		      struct skl_plane_wm *plane_wm,
> +		      bool yuv)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
>  	int level, max_level = ilk_wm_max_level(dev_priv);
> +	/*
> +	 * Check which kind of plane is it and based on that calculate
> +	 * correspondent WM levels.
> +	 */
> +	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm->wm;
>  	struct skl_wm_level *result_prev = &levels[0];
>  
>  	for (level = 0; level <= max_level; level++) {
>  		struct skl_wm_level *result = &levels[level];
> +		u32 latency = dev_priv->wm.skl_latency[level];
>  
> -		skl_compute_plane_wm(crtc_state, level, wm_params,
> -				     result_prev, result);
> +		skl_compute_plane_wm(crtc_state, level, latency,
> +				     wm_params, result_prev, result);
>  
>  		result_prev = result;
>  	}
> +	/*
> +	 * For Gen12 if it is an L0 we need to also
> +	 * consider sagv_block_time when calculating
> +	 * L0 watermark - we will need that when making
> +	 * a decision whether enable SAGV or not.
> +	 * For older gens we agreed to copy L0 value for
> +	 * compatibility.
> +	 */
> +	if ((INTEL_GEN(dev_priv) >= 12)) {
> +		u32 latency = dev_priv->wm.skl_latency[0];
> +
> +		latency += dev_priv->sagv_block_time_us;
> +		skl_compute_plane_wm(crtc_state, 0, latency,
> +		     wm_params, &levels[0],
> +		    &plane_wm->sagv_wm0);
> +	} else
> +		memcpy(&plane_wm->sagv_wm0, &levels[0],
> +			sizeof(struct skl_wm_level));
>  }
>  
>  static u32
> @@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> -	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> +	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
>  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
>  
>  	return 0;
> @@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
>  	if (ret)
>  		return ret;
>  
> -	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> +	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
>  
>  	return 0;
>  }
> @@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
>  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
>  	const struct skl_ddb_entry *ddb_uv =
>  		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> +	const struct skl_wm_level *wm_level;
>  
>  	for (level = 0; level <= max_level; level++) {
> +		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
>  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
> -				   &wm->wm[level]);
> +				   wm_level);
>  	}
>  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
>  			   &wm->trans_wm);
> @@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
>  		&crtc_state->wm.skl.optimal.planes[plane_id];
>  	const struct skl_ddb_entry *ddb =
>  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> +	const struct skl_wm_level *wm_level;
>  
>  	for (level = 0; level <= max_level; level++) {
> +		wm_level = skl_plane_wm_level(plane, crtc_state, level, false);
> +
>  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> -				   &wm->wm[level]);
> +				   wm_level);
>  	}
>  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
>  
> @@ -5451,18 +5729,73 @@ static int skl_wm_add_affected_planes(struct intel_atomic_state *state,
>  	return 0;
>  }
>  
> +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> +{
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> +	struct intel_crtc *crtc;
> +	struct intel_crtc_state *new_crtc_state;
> +	struct intel_crtc_state *old_crtc_state;
> +	struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> +	int ret;
> +	int i;
> +	struct intel_plane *plane;
> +
> +	if (state->crtc_sagv_mask_set)
> +		return;
> +
> +	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> +					    new_crtc_state, i) {
> +		int pipe_bit = BIT(crtc->pipe);
> +		bool skip = true;
> +
> +		/*
> +		 * If we had set this mast already once for this state,
> +		 * no need to waste CPU cycles for doing this again.
> +		 */
> +		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
> +			enum plane_id plane_id = plane->id;
> +
> +			if (!skl_plane_wm_equals(dev_priv,
> +				&old_crtc_state->wm.skl.optimal.planes[plane_id],
> +				&new_crtc_state->wm.skl.optimal.planes[plane_id])) {
> +				skip = false;
> +				break;
> +			}
> +		}
> +
> +		/*
> +		 * Check if wm levels are actually the same as for previous
> +		 * state, which means we can just skip doing this long check
> +		 * and just  copy correspondent bit from previous state.
> +		 */
> +		if (skip)
> +			continue;
> +
> +		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> +		if (!ret)
> +			state->crtc_sagv_mask |= pipe_bit;
> +		else
> +			state->crtc_sagv_mask &= ~pipe_bit;
> +	}
> +	state->crtc_sagv_mask_set = true;
> +}
> +
>  static int
>  skl_compute_wm(struct intel_atomic_state *state)
>  {
>  	struct intel_crtc *crtc;
>  	struct intel_crtc_state *new_crtc_state;
>  	struct intel_crtc_state *old_crtc_state;
> -	struct skl_ddb_values *results = &state->wm_results;
>  	int ret, i;
> +	struct skl_ddb_values *results = &state->wm_results;
> +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
>  
>  	/* Clear all dirty flags */
>  	results->dirty_pipes = 0;
>  
> +	/* If we exit before check is done */
> +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
> +
>  	ret = skl_ddb_add_affected_pipes(state);
>  	if (ret)
>  		return ret;
> @@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  				val = I915_READ(CUR_WM(pipe, level));
>  
>  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> +			if (level == 0)
> +				memcpy(&wm->sagv_wm0, &wm->wm[level],
> +					sizeof(struct skl_wm_level));
>  		}
>  
>  		if (plane_id != PLANE_CURSOR)
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index b579c724b915..53275860731a 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
>  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
>  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
>  bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_has_sagv(struct drm_i915_private *dev_priv);
>  int intel_enable_sagv(struct drm_i915_private *dev_priv);
>  int intel_disable_sagv(struct drm_i915_private *dev_priv);
>  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> -- 
> 2.17.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-20  0:19     ` Matt Roper
  0 siblings, 0 replies; 23+ messages in thread
From: Matt Roper @ 2019-11-20  0:19 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Fri, Nov 15, 2019 at 04:54:01PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
>     values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
>     restricting qgv points. Put the actual restriction
>     to commit function, added serialization(thanks to Ville)
>     to prevent commit being applied out of order in case of
>     nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
>     - Change the naming of qgv point
>       masking/unmasking functions(James Ausmus).
>     - Simplify the masking/unmasking operation itself,
>       as we don't need to mask only single point per request(James Ausmus)
>     - Reject and stick to highest bandwidth point if SAGV
>       can't be enabled(BSpec)
> 
> v5:
>     - Add new mailbox reply codes, which seems to happen during boot
>       time for TGL and indicate that QGV setting is not yet available.
> 
> v6:
>     - Increase number of supported QGV points to be in sync with BSpec.
> 
> v7: - Rebased and resolved conflict to fix build failure.
>     - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
> 
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
>       can be disabled by BIOS, which is completely legal. So don't
>       make CI panic. Instead if we detect that there is only 1 QGV
>       point accessible just analyze if we can fit the required bandwidth
>       requirements, but no need in restricting.
> 
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
>       simultaneously.
> 
> v10: - Fix CDCLK corruption, because of global state getting serialized
>        without modeset, which caused copying of non-calculated cdclk
>        to be copied to dev_priv(thanks to Ville for the hint).
> 
> v11: - Remove unneeded headers and spaces(Matthew Roper)
>      - Remove unneeded intel_qgv_info qi struct from bw check and zero
>        out the needed one(Matthew Roper)
>      - Changed QGV error message to have more clear meaning(Matthew Roper)
>      - Use state->modeset_set instead of any_ms(Matthew Roper)
>      - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
>      - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
>      - Moved unrelated changes to other patch(using latency as parameter
>        for plane wm calculation, moved to SAGV refactoring patch)
> 
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_bw.c       | 134 +++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  91 +++++++++++-
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/i915_drv.h               |   7 +-
>  drivers/gpu/drm/i915/i915_reg.h               |   5 +
>  drivers/gpu/drm/i915/intel_sideband.c         |  27 +++-
>  8 files changed, 241 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 7b49623419ba..41a2a89c9bdb 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +

We appear to already have this a few lines lower in the file.


>  struct intel_crtc_state *
>  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>  			    struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 3f6e29f61323..809fc1bf99c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
> @@ -15,7 +18,7 @@ struct intel_qgv_point {
>  };
>  
>  struct intel_qgv_info {
> -	struct intel_qgv_point points[3];
> +	struct intel_qgv_point points[NUM_SAGV_POINTS];
>  	u8 num_points;
>  	u8 num_channels;
>  	u8 t_bl;
> @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>  	return 0;
>  }
>  
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask)
> +{
> +	int ret;
> +
> +	/* bspec says to keep retrying for at least 1 ms */
> +	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> +				points_mask,
> +				GEN11_PCODE_POINTS_RESTRICTED_MASK,
> +				GEN11_PCODE_POINTS_RESTRICTED,
> +				1);
> +
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>  			      struct intel_qgv_info *qi)
>  {
> @@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  		icl_get_bw_info(dev_priv, &icl_sa_info);
>  }
>  
> -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> -					int num_planes)
> -{
> -	if (INTEL_GEN(dev_priv) >= 11)
> -		/*
> -		 * FIXME with SAGV disabled maybe we can assume
> -		 * point 1 will always be used? Seems to match
> -		 * the behaviour observed in the wild.
> -		 */
> -		return min3(icl_max_bw(dev_priv, num_planes, 0),
> -			    icl_max_bw(dev_priv, num_planes, 1),
> -			    icl_max_bw(dev_priv, num_planes, 2));
> -	else
> -		return UINT_MAX;
> -}
> -
>  static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
>  {
>  	/*
> @@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  	unsigned int data_rate, max_data_rate;
>  	unsigned int num_active_planes;
>  	struct intel_crtc *crtc;
> -	int i;
> +	int i, ret;
> +	u32 allowed_points = 0;
> +	unsigned int max_bw_point = 0, max_bw = 0;
> +	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> +	u32 mask = (1 << num_qgv_points) - 1;
>  
>  	/* FIXME earlier gens need some checks too */
>  	if (INTEL_GEN(dev_priv) < 11)
> @@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  	data_rate = intel_bw_data_rate(dev_priv, bw_state);
>  	num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>  
> -	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> -
>  	data_rate = DIV_ROUND_UP(data_rate, 1000);
>  
> -	if (data_rate > max_data_rate) {
> -		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
> -			      data_rate, max_data_rate, num_active_planes);
> +	for (i = 0; i < num_qgv_points; i++) {
> +		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> +		/*
> +		 * We need to know which qgv point gives us
> +		 * maximum bandwidth in order to disable SAGV
> +		 * if we find that we exceed SAGV block time
> +		 * with watermarks. By that moment we already
> +		 * have those, as it is calculated earlier in
> +		 * intel_atomic_check,
> +		 */
> +		if (max_data_rate > max_bw) {
> +			max_bw_point = i;
> +			max_bw = max_data_rate;
> +		}
> +		if (max_data_rate >= data_rate)
> +			allowed_points |= BIT(i);
> +		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> +			      i, max_data_rate, data_rate);
> +	}
> +
> +	/*
> +	 * BSpec states that we always should have at least one allowed point
> +	 * left, so if we couldn't - simply reject the configuration for obvious
> +	 * reasons.
> +	 */
> +	if (allowed_points == 0) {
> +		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> +			      " bandwidth for display configuration.\n");
>  		return -EINVAL;
>  	}
>  
> +	/*
> +	 * In case if SAGV is disabled in BIOS, we always get 1
> +	 * SAGV point, but we can't send PCode commands to restrict it
> +	 * as it will fail and pointless anyway.
> +	 */
> +	if (num_qgv_points == 1)
> +		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> +	else
> +		dev_priv->sagv_status = I915_SAGV_ENABLED;

We should probably be doing this just once in icl_get_bw_info().

> +
> +	/*
> +	 * Leave only single point with highest bandwidth, if
> +	 * we can't enable SAGV according to BSpec.

Minor nitpick:  I'd say "...due to the increased memory latency it may
cause" rather than "...according to BSpec."

> +	 */
> +	if (!intel_can_enable_sagv(state)) {
> +

Nitpick: unnecessary blank line.

> +		/*
> +		 * This is a border line condition when we have 0 planes
> +		 * and SAGV not enabled means that we should keep QGV with
> +		 * highest bandwidth, however algorithm returns wrong result
> +		 * for 0 planes and 0 data rate, so just stick to last config
> +		 * then. Otherwise use the QGV point with highest BW according
> +		 * to BSpec.

I'm not sure I follow this.  "SAGV not enabled" in the BIOS or because
we've explicitly disabled it ourselves?  If the BIOS has it turned off,
then we should only have a single QGV point, right?  And if we turned
the SAGV off, then maybe intel_can_enable_sagv() will return true
instead of false if we flip around the sagv mask from allowed-pipes to
prohibited pipes like I suggested on the previous patch?

> +		 */
> +		if (!data_rate && !num_active_planes) {
> +			DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> +			allowed_points = (~dev_priv->qgv_points_mask) & mask;
> +		} else {
> +			allowed_points = 1 << max_bw_point;
> +			DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> +				      max_bw_point);
> +		}
> +	}
> +	/*
> +	 * We store the ones which need to be masked as that is what PCode
> +	 * actually accepts as a parameter.
> +	 */
> +	state->qgv_points_mask = (~allowed_points) & mask;
> +
> +	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> +		      state, state->qgv_points_mask);
> +
> +	/*
> +	 * If the actual mask had changed we need to make sure that
> +	 * the commits are serialized(in case this is a nomodeset, nonblocking)
> +	 */
> +	if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> +		ret = intel_atomic_serialize_global_state(state);
> +		if (ret) {
> +			DRM_DEBUG_KMS("Could not serialize global state\n");
> +			return ret;
> +		}
> +	}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 9db10af012f4..66bf9bc10b73 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
>  int intel_bw_atomic_check(struct intel_atomic_state *state);
>  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>  			  const struct intel_crtc_state *crtc_state);
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask);
>  
>  #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7f31e33d0b16..fd35d0b0699c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14755,6 +14755,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
>  	intel_atomic_helper_free_state(i915);
>  }
>  
> +static void intel_qgv_points_mask(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int ret;
> +	u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
> +	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> +	unsigned int mask = (1 << num_qgv_points) - 1;
> +
> +	/*
> +	 * As we don't know initial hardware state during initial commit
> +	 * we should not do anything, until we actually figure out,
> +	 * what are the qgv points to mask.
> +	 */
> +	if (!new_mask)
> +		return;
> +
> +	WARN_ON(new_mask == mask);
> +
> +	/*
> +	 * Just return if we can't control SAGV or don't have it.
> +	 */
> +	if (!intel_has_sagv(dev_priv))
> +		return;
> +
> +	/*
> +	 * Restrict required qgv points before updating the configuration.
> +	 * According to BSpec we can't mask and unmask qgv points at the same
> +	 * time. Also masking should be done before updating the configuration
> +	 * and unmasking afterwards.
> +	 */
> +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> +	if (ret < 0)
> +		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> +			      ret);
> +	else
> +		dev_priv->qgv_points_mask = new_mask;
> +}
> +
> +static void intel_qgv_points_unmask(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int ret;
> +	u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
> +
> +	/*
> +	 * As we don't know initial hardware state during initial commit
> +	 * we should not do anything, until we actually figure out,
> +	 * what are the qgv points to mask.
> +	 */
> +	if (!new_mask)
> +		return;

This makes sense on the mask, but it doesn't seem like we'd want this on
the unmask.  Unmask happens once we've finished the transition to a new
state, right?  Allowing additional points to be used should definitely
be safe then, right?

> +
> +	/*
> +	 * Just return if we can't control SAGV or don't have it.
> +	 */
> +	if (!intel_has_sagv(dev_priv))
> +		return;
> +
> +	/*
> +	 * Allow required qgv points after updating the configuration.
> +	 * According to BSpec we can't mask and unmask qgv points at the same
> +	 * time. Also masking should be done before updating the configuration
> +	 * and unmasking afterwards.
> +	 */
> +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> +	if (ret < 0)
> +		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> +			      ret);

This message seems a bit misleading; we're removing restrictions here
instead of adding them.


Matt

> +	else
> +		dev_priv->qgv_points_mask = new_mask;
> +}
> +
>  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  {
>  	struct drm_device *dev = state->base.dev;
> @@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		}
>  	}
>  
> +	if ((INTEL_GEN(dev_priv) >= 11))
> +		intel_qgv_points_mask(state);
> +
>  	intel_commit_modeset_disables(state);
>  
>  	/* FIXME: Eventually get rid of our crtc->config pointer */
> @@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 * SKL workaround: bspec recommends we disable the SAGV when we
>  		 * have more then one pipe enabled
>  		 */
> -		if (!intel_can_enable_sagv(state))
> -			intel_disable_sagv(dev_priv);
> +		if (INTEL_GEN(dev_priv) < 11)
> +			if (!intel_can_enable_sagv(state))
> +				intel_disable_sagv(dev_priv);
>  
>  		intel_modeset_verify_disabled(dev_priv, state);
>  	}
> @@ -14883,8 +14961,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	if (state->modeset)
>  		intel_verify_planes(state);
>  
> -	if (state->modeset && intel_can_enable_sagv(state))
> -		intel_enable_sagv(dev_priv);
> +	if (INTEL_GEN(dev_priv) < 11) {
> +		if (state->modeset && intel_can_enable_sagv(state))
> +			intel_enable_sagv(dev_priv);
> +	} else
> +		intel_qgv_points_unmask(state);
>  
>  	drm_atomic_helper_commit_hw_done(&state->base);
>  
> @@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>  	intel_shared_dpll_swap_state(state);
>  	intel_atomic_track_fbs(state);
>  
> -	if (state->global_state_changed) {
> +	if (state->global_state_changed && state->modeset) {
>  		assert_global_state_locked(dev_priv);
>  
>  		memcpy(dev_priv->min_cdclk, state->min_cdclk,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6a300cac883f..3535857dfed2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -534,6 +534,9 @@ struct intel_atomic_state {
>  	struct i915_sw_fence commit_ready;
>  
>  	struct llist_node freed;
> +
> +	/* Gen11+ only */
> +	u32 qgv_points_mask;
>  };
>  
>  struct intel_plane_state {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0ac9d7b006ca..54657b68010a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -850,6 +850,9 @@ enum intel_pipe_crc_source {
>  	INTEL_PIPE_CRC_SOURCE_MAX,
>  };
>  
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 8
> +
>  #define INTEL_PIPE_CRC_ENTRIES_NR	128
>  struct intel_pipe_crc {
>  	spinlock_t lock;
> @@ -1238,11 +1241,13 @@ struct drm_i915_private {
>  	} dram_info;
>  
>  	struct intel_bw_info {
> -		unsigned int deratedbw[3]; /* for each QGV point */
> +		unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
>  		u8 num_qgv_points;
>  		u8 num_planes;
>  	} max_bw[6];
>  
> +	u32 qgv_points_mask;
> +
>  	struct drm_private_obj bw_obj;
>  
>  	struct intel_runtime_pm runtime_pm;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a4e5a4ae3885..2ea83ff681b9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8981,6 +8981,8 @@ enum {
>  #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
>  #define     GEN7_PCODE_TIMEOUT			0x2
>  #define     GEN7_PCODE_ILLEGAL_DATA		0x3
> +#define     GEN11_PCODE_MAIL_BOX_LOCKED		0x6
> +#define     GEN11_PCODE_REJECTED		0x11
>  #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
>  #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
>  #define   GEN6_PCODE_READ_RC6VIDS		0x5
> @@ -9002,6 +9004,7 @@ enum {
>  #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
>  #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
>  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
> +#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
>  #define   GEN6_PCODE_READ_D_COMP		0x10
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> @@ -9014,6 +9017,8 @@ enum {
>  #define     GEN9_SAGV_IS_DISABLED		0x1
>  #define     GEN9_SAGV_ENABLE			0x3
>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> +#define GEN11_PCODE_POINTS_RESTRICTED		0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index e06b35b844a0..ff9dbed094d8 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
>  	}
>  }
>  
> +static inline int gen11_check_mailbox_status(u32 mbox)
> +{
> +	switch (mbox & GEN6_PCODE_ERROR_MASK) {
> +	case GEN6_PCODE_SUCCESS:
> +		return 0;
> +	case GEN6_PCODE_ILLEGAL_CMD:
> +		return -ENXIO;
> +	case GEN7_PCODE_TIMEOUT:
> +		return -ETIMEDOUT;
> +	case GEN7_PCODE_ILLEGAL_DATA:
> +		return -EINVAL;
> +	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> +		return -EOVERFLOW;
> +	case GEN11_PCODE_MAIL_BOX_LOCKED:
> +		return -EAGAIN;
> +	case GEN11_PCODE_REJECTED:
> +		return -EACCES;
> +	default:
> +		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> +		return 0;
> +	}
> +}
> +
>  static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>  				  u32 mbox, u32 *val, u32 *val1,
>  				  int fast_timeout_us,
> @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>  	if (is_read && val1)
>  		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
>  
> -	if (INTEL_GEN(i915) > 6)
> +	if (INTEL_GEN(i915) >= 11)
> +		return gen11_check_mailbox_status(mbox);
> +	else if (INTEL_GEN(i915) > 6)
>  		return gen7_check_mailbox_status(mbox);
>  	else
>  		return gen6_check_mailbox_status(mbox);
> -- 
> 2.17.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-20  0:19     ` Matt Roper
  0 siblings, 0 replies; 23+ messages in thread
From: Matt Roper @ 2019-11-20  0:19 UTC (permalink / raw)
  To: Stanislav Lisovskiy; +Cc: intel-gfx

On Fri, Nov 15, 2019 at 04:54:01PM +0200, Stanislav Lisovskiy wrote:
> According to BSpec 53998, we should try to
> restrict qgv points, which can't provide
> enough bandwidth for desired display configuration.
> 
> Currently we are just comparing against all of
> those and take minimum(worst case).
> 
> v2: Fixed wrong PCode reply mask, removed hardcoded
>     values.
> 
> v3: Forbid simultaneous legacy SAGV PCode requests and
>     restricting qgv points. Put the actual restriction
>     to commit function, added serialization(thanks to Ville)
>     to prevent commit being applied out of order in case of
>     nonblocking and/or nomodeset commits.
> 
> v4:
>     - Minor code refactoring, fixed few typos(thanks to James Ausmus)
>     - Change the naming of qgv point
>       masking/unmasking functions(James Ausmus).
>     - Simplify the masking/unmasking operation itself,
>       as we don't need to mask only single point per request(James Ausmus)
>     - Reject and stick to highest bandwidth point if SAGV
>       can't be enabled(BSpec)
> 
> v5:
>     - Add new mailbox reply codes, which seems to happen during boot
>       time for TGL and indicate that QGV setting is not yet available.
> 
> v6:
>     - Increase number of supported QGV points to be in sync with BSpec.
> 
> v7: - Rebased and resolved conflict to fix build failure.
>     - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
> 
> v8: - Don't report an error if we can't restrict qgv points, as SAGV
>       can be disabled by BIOS, which is completely legal. So don't
>       make CI panic. Instead if we detect that there is only 1 QGV
>       point accessible just analyze if we can fit the required bandwidth
>       requirements, but no need in restricting.
> 
> v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
>       simultaneously.
> 
> v10: - Fix CDCLK corruption, because of global state getting serialized
>        without modeset, which caused copying of non-calculated cdclk
>        to be copied to dev_priv(thanks to Ville for the hint).
> 
> v11: - Remove unneeded headers and spaces(Matthew Roper)
>      - Remove unneeded intel_qgv_info qi struct from bw check and zero
>        out the needed one(Matthew Roper)
>      - Changed QGV error message to have more clear meaning(Matthew Roper)
>      - Use state->modeset_set instead of any_ms(Matthew Roper)
>      - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
>      - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
>      - Moved unrelated changes to other patch(using latency as parameter
>        for plane wm calculation, moved to SAGV refactoring patch)
> 
> Reviewed-by: James Ausmus <james.ausmus@intel.com>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
>  drivers/gpu/drm/i915/display/intel_bw.c       | 134 +++++++++++++++---
>  drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
>  drivers/gpu/drm/i915/display/intel_display.c  |  91 +++++++++++-
>  .../drm/i915/display/intel_display_types.h    |   3 +
>  drivers/gpu/drm/i915/i915_drv.h               |   7 +-
>  drivers/gpu/drm/i915/i915_reg.h               |   5 +
>  drivers/gpu/drm/i915/intel_sideband.c         |  27 +++-
>  8 files changed, 241 insertions(+), 30 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index 7b49623419ba..41a2a89c9bdb 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct intel_crtc_state *crtc_state);
>  struct drm_atomic_state *intel_atomic_state_alloc(struct drm_device *dev);
>  void intel_atomic_state_clear(struct drm_atomic_state *state);
>  
> +int intel_atomic_serialize_global_state(struct intel_atomic_state *state);
> +

We appear to already have this a few lines lower in the file.


>  struct intel_crtc_state *
>  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>  			    struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
> index 3f6e29f61323..809fc1bf99c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.c
> +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> @@ -8,6 +8,9 @@
>  #include "intel_bw.h"
>  #include "intel_display_types.h"
>  #include "intel_sideband.h"
> +#include "intel_atomic.h"
> +#include "intel_pm.h"
> +
>  
>  /* Parameters for Qclk Geyserville (QGV) */
>  struct intel_qgv_point {
> @@ -15,7 +18,7 @@ struct intel_qgv_point {
>  };
>  
>  struct intel_qgv_info {
> -	struct intel_qgv_point points[3];
> +	struct intel_qgv_point points[NUM_SAGV_POINTS];
>  	u8 num_points;
>  	u8 num_channels;
>  	u8 t_bl;
> @@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
>  	return 0;
>  }
>  
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask)
> +{
> +	int ret;
> +
> +	/* bspec says to keep retrying for at least 1 ms */
> +	ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> +				points_mask,
> +				GEN11_PCODE_POINTS_RESTRICTED_MASK,
> +				GEN11_PCODE_POINTS_RESTRICTED,
> +				1);
> +
> +	if (ret < 0) {
> +		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
>  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
>  			      struct intel_qgv_info *qi)
>  {
> @@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
>  		icl_get_bw_info(dev_priv, &icl_sa_info);
>  }
>  
> -static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
> -					int num_planes)
> -{
> -	if (INTEL_GEN(dev_priv) >= 11)
> -		/*
> -		 * FIXME with SAGV disabled maybe we can assume
> -		 * point 1 will always be used? Seems to match
> -		 * the behaviour observed in the wild.
> -		 */
> -		return min3(icl_max_bw(dev_priv, num_planes, 0),
> -			    icl_max_bw(dev_priv, num_planes, 1),
> -			    icl_max_bw(dev_priv, num_planes, 2));
> -	else
> -		return UINT_MAX;
> -}
> -
>  static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
>  {
>  	/*
> @@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  	unsigned int data_rate, max_data_rate;
>  	unsigned int num_active_planes;
>  	struct intel_crtc *crtc;
> -	int i;
> +	int i, ret;
> +	u32 allowed_points = 0;
> +	unsigned int max_bw_point = 0, max_bw = 0;
> +	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> +	u32 mask = (1 << num_qgv_points) - 1;
>  
>  	/* FIXME earlier gens need some checks too */
>  	if (INTEL_GEN(dev_priv) < 11)
> @@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
>  	data_rate = intel_bw_data_rate(dev_priv, bw_state);
>  	num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
>  
> -	max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
> -
>  	data_rate = DIV_ROUND_UP(data_rate, 1000);
>  
> -	if (data_rate > max_data_rate) {
> -		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
> -			      data_rate, max_data_rate, num_active_planes);
> +	for (i = 0; i < num_qgv_points; i++) {
> +		max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
> +		/*
> +		 * We need to know which qgv point gives us
> +		 * maximum bandwidth in order to disable SAGV
> +		 * if we find that we exceed SAGV block time
> +		 * with watermarks. By that moment we already
> +		 * have those, as it is calculated earlier in
> +		 * intel_atomic_check,
> +		 */
> +		if (max_data_rate > max_bw) {
> +			max_bw_point = i;
> +			max_bw = max_data_rate;
> +		}
> +		if (max_data_rate >= data_rate)
> +			allowed_points |= BIT(i);
> +		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> +			      i, max_data_rate, data_rate);
> +	}
> +
> +	/*
> +	 * BSpec states that we always should have at least one allowed point
> +	 * left, so if we couldn't - simply reject the configuration for obvious
> +	 * reasons.
> +	 */
> +	if (allowed_points == 0) {
> +		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> +			      " bandwidth for display configuration.\n");
>  		return -EINVAL;
>  	}
>  
> +	/*
> +	 * In case if SAGV is disabled in BIOS, we always get 1
> +	 * SAGV point, but we can't send PCode commands to restrict it
> +	 * as it will fail and pointless anyway.
> +	 */
> +	if (num_qgv_points == 1)
> +		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> +	else
> +		dev_priv->sagv_status = I915_SAGV_ENABLED;

We should probably be doing this just once in icl_get_bw_info().

> +
> +	/*
> +	 * Leave only single point with highest bandwidth, if
> +	 * we can't enable SAGV according to BSpec.

Minor nitpick:  I'd say "...due to the increased memory latency it may
cause" rather than "...according to BSpec."

> +	 */
> +	if (!intel_can_enable_sagv(state)) {
> +

Nitpick: unnecessary blank line.

> +		/*
> +		 * This is a border line condition when we have 0 planes
> +		 * and SAGV not enabled means that we should keep QGV with
> +		 * highest bandwidth, however algorithm returns wrong result
> +		 * for 0 planes and 0 data rate, so just stick to last config
> +		 * then. Otherwise use the QGV point with highest BW according
> +		 * to BSpec.

I'm not sure I follow this.  "SAGV not enabled" in the BIOS or because
we've explicitly disabled it ourselves?  If the BIOS has it turned off,
then we should only have a single QGV point, right?  And if we turned
the SAGV off, then maybe intel_can_enable_sagv() will return true
instead of false if we flip around the sagv mask from allowed-pipes to
prohibited pipes like I suggested on the previous patch?

> +		 */
> +		if (!data_rate && !num_active_planes) {
> +			DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> +			allowed_points = (~dev_priv->qgv_points_mask) & mask;
> +		} else {
> +			allowed_points = 1 << max_bw_point;
> +			DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
> +				      max_bw_point);
> +		}
> +	}
> +	/*
> +	 * We store the ones which need to be masked as that is what PCode
> +	 * actually accepts as a parameter.
> +	 */
> +	state->qgv_points_mask = (~allowed_points) & mask;
> +
> +	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> +		      state, state->qgv_points_mask);
> +
> +	/*
> +	 * If the actual mask had changed we need to make sure that
> +	 * the commits are serialized(in case this is a nomodeset, nonblocking)
> +	 */
> +	if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> +		ret = intel_atomic_serialize_global_state(state);
> +		if (ret) {
> +			DRM_DEBUG_KMS("Could not serialize global state\n");
> +			return ret;
> +		}
> +	}
> +
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index 9db10af012f4..66bf9bc10b73 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
>  int intel_bw_atomic_check(struct intel_atomic_state *state);
>  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
>  			  const struct intel_crtc_state *crtc_state);
> +int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
> +				  u32 points_mask);
>  
>  #endif /* __INTEL_BW_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 7f31e33d0b16..fd35d0b0699c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -14755,6 +14755,80 @@ static void intel_atomic_cleanup_work(struct work_struct *work)
>  	intel_atomic_helper_free_state(i915);
>  }
>  
> +static void intel_qgv_points_mask(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int ret;
> +	u32 new_mask = dev_priv->qgv_points_mask | state->qgv_points_mask;
> +	unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
> +	unsigned int mask = (1 << num_qgv_points) - 1;
> +
> +	/*
> +	 * As we don't know initial hardware state during initial commit
> +	 * we should not do anything, until we actually figure out,
> +	 * what are the qgv points to mask.
> +	 */
> +	if (!new_mask)
> +		return;
> +
> +	WARN_ON(new_mask == mask);
> +
> +	/*
> +	 * Just return if we can't control SAGV or don't have it.
> +	 */
> +	if (!intel_has_sagv(dev_priv))
> +		return;
> +
> +	/*
> +	 * Restrict required qgv points before updating the configuration.
> +	 * According to BSpec we can't mask and unmask qgv points at the same
> +	 * time. Also masking should be done before updating the configuration
> +	 * and unmasking afterwards.
> +	 */
> +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> +	if (ret < 0)
> +		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> +			      ret);
> +	else
> +		dev_priv->qgv_points_mask = new_mask;
> +}
> +
> +static void intel_qgv_points_unmask(struct intel_atomic_state *state)
> +{
> +	struct drm_device *dev = state->base.dev;
> +	struct drm_i915_private *dev_priv = to_i915(dev);
> +	int ret;
> +	u32 new_mask = dev_priv->qgv_points_mask & state->qgv_points_mask;
> +
> +	/*
> +	 * As we don't know initial hardware state during initial commit
> +	 * we should not do anything, until we actually figure out,
> +	 * what are the qgv points to mask.
> +	 */
> +	if (!new_mask)
> +		return;

This makes sense on the mask, but it doesn't seem like we'd want this on
the unmask.  Unmask happens once we've finished the transition to a new
state, right?  Allowing additional points to be used should definitely
be safe then, right?

> +
> +	/*
> +	 * Just return if we can't control SAGV or don't have it.
> +	 */
> +	if (!intel_has_sagv(dev_priv))
> +		return;
> +
> +	/*
> +	 * Allow required qgv points after updating the configuration.
> +	 * According to BSpec we can't mask and unmask qgv points at the same
> +	 * time. Also masking should be done before updating the configuration
> +	 * and unmasking afterwards.
> +	 */
> +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> +	if (ret < 0)
> +		DRM_DEBUG_KMS("Could not restrict required qgv points(%d)\n",
> +			      ret);

This message seems a bit misleading; we're removing restrictions here
instead of adding them.


Matt

> +	else
> +		dev_priv->qgv_points_mask = new_mask;
> +}
> +
>  static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  {
>  	struct drm_device *dev = state->base.dev;
> @@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		}
>  	}
>  
> +	if ((INTEL_GEN(dev_priv) >= 11))
> +		intel_qgv_points_mask(state);
> +
>  	intel_commit_modeset_disables(state);
>  
>  	/* FIXME: Eventually get rid of our crtc->config pointer */
> @@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  		 * SKL workaround: bspec recommends we disable the SAGV when we
>  		 * have more then one pipe enabled
>  		 */
> -		if (!intel_can_enable_sagv(state))
> -			intel_disable_sagv(dev_priv);
> +		if (INTEL_GEN(dev_priv) < 11)
> +			if (!intel_can_enable_sagv(state))
> +				intel_disable_sagv(dev_priv);
>  
>  		intel_modeset_verify_disabled(dev_priv, state);
>  	}
> @@ -14883,8 +14961,11 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
>  	if (state->modeset)
>  		intel_verify_planes(state);
>  
> -	if (state->modeset && intel_can_enable_sagv(state))
> -		intel_enable_sagv(dev_priv);
> +	if (INTEL_GEN(dev_priv) < 11) {
> +		if (state->modeset && intel_can_enable_sagv(state))
> +			intel_enable_sagv(dev_priv);
> +	} else
> +		intel_qgv_points_unmask(state);
>  
>  	drm_atomic_helper_commit_hw_done(&state->base);
>  
> @@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct drm_device *dev,
>  	intel_shared_dpll_swap_state(state);
>  	intel_atomic_track_fbs(state);
>  
> -	if (state->global_state_changed) {
> +	if (state->global_state_changed && state->modeset) {
>  		assert_global_state_locked(dev_priv);
>  
>  		memcpy(dev_priv->min_cdclk, state->min_cdclk,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 6a300cac883f..3535857dfed2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -534,6 +534,9 @@ struct intel_atomic_state {
>  	struct i915_sw_fence commit_ready;
>  
>  	struct llist_node freed;
> +
> +	/* Gen11+ only */
> +	u32 qgv_points_mask;
>  };
>  
>  struct intel_plane_state {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0ac9d7b006ca..54657b68010a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -850,6 +850,9 @@ enum intel_pipe_crc_source {
>  	INTEL_PIPE_CRC_SOURCE_MAX,
>  };
>  
> +/* BSpec precisely defines this */
> +#define NUM_SAGV_POINTS 8
> +
>  #define INTEL_PIPE_CRC_ENTRIES_NR	128
>  struct intel_pipe_crc {
>  	spinlock_t lock;
> @@ -1238,11 +1241,13 @@ struct drm_i915_private {
>  	} dram_info;
>  
>  	struct intel_bw_info {
> -		unsigned int deratedbw[3]; /* for each QGV point */
> +		unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each QGV point */
>  		u8 num_qgv_points;
>  		u8 num_planes;
>  	} max_bw[6];
>  
> +	u32 qgv_points_mask;
> +
>  	struct drm_private_obj bw_obj;
>  
>  	struct intel_runtime_pm runtime_pm;
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index a4e5a4ae3885..2ea83ff681b9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -8981,6 +8981,8 @@ enum {
>  #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
>  #define     GEN7_PCODE_TIMEOUT			0x2
>  #define     GEN7_PCODE_ILLEGAL_DATA		0x3
> +#define     GEN11_PCODE_MAIL_BOX_LOCKED		0x6
> +#define     GEN11_PCODE_REJECTED		0x11
>  #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
>  #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
>  #define   GEN6_PCODE_READ_RC6VIDS		0x5
> @@ -9002,6 +9004,7 @@ enum {
>  #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
>  #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
>  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((point) << 16) | (0x1 << 8))
> +#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
>  #define   GEN6_PCODE_READ_D_COMP		0x10
>  #define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> @@ -9014,6 +9017,8 @@ enum {
>  #define     GEN9_SAGV_IS_DISABLED		0x1
>  #define     GEN9_SAGV_ENABLE			0x3
>  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> +#define GEN11_PCODE_POINTS_RESTRICTED		0x0
> +#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
>  #define GEN6_PCODE_DATA				_MMIO(0x138128)
>  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
>  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index e06b35b844a0..ff9dbed094d8 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -371,6 +371,29 @@ static inline int gen7_check_mailbox_status(u32 mbox)
>  	}
>  }
>  
> +static inline int gen11_check_mailbox_status(u32 mbox)
> +{
> +	switch (mbox & GEN6_PCODE_ERROR_MASK) {
> +	case GEN6_PCODE_SUCCESS:
> +		return 0;
> +	case GEN6_PCODE_ILLEGAL_CMD:
> +		return -ENXIO;
> +	case GEN7_PCODE_TIMEOUT:
> +		return -ETIMEDOUT;
> +	case GEN7_PCODE_ILLEGAL_DATA:
> +		return -EINVAL;
> +	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> +		return -EOVERFLOW;
> +	case GEN11_PCODE_MAIL_BOX_LOCKED:
> +		return -EAGAIN;
> +	case GEN11_PCODE_REJECTED:
> +		return -EACCES;
> +	default:
> +		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> +		return 0;
> +	}
> +}
> +
>  static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>  				  u32 mbox, u32 *val, u32 *val1,
>  				  int fast_timeout_us,
> @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
>  	if (is_read && val1)
>  		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
>  
> -	if (INTEL_GEN(i915) > 6)
> +	if (INTEL_GEN(i915) >= 11)
> +		return gen11_check_mailbox_status(mbox);
> +	else if (INTEL_GEN(i915) > 6)
>  		return gen7_check_mailbox_status(mbox);
>  	else
>  		return gen6_check_mailbox_status(mbox);
> -- 
> 2.17.1
> 

-- 
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-20  9:16       ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 23+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-20  9:16 UTC (permalink / raw)
  To: Roper, Matthew D; +Cc: intel-gfx

On Tue, 2019-11-19 at 16:19 -0800, Matt Roper wrote:
> On Fri, Nov 15, 2019 at 04:54:01PM +0200, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> > 
> > Currently we are just comparing against all of
> > those and take minimum(worst case).
> > 
> > v2: Fixed wrong PCode reply mask, removed hardcoded
> >     values.
> > 
> > v3: Forbid simultaneous legacy SAGV PCode requests and
> >     restricting qgv points. Put the actual restriction
> >     to commit function, added serialization(thanks to Ville)
> >     to prevent commit being applied out of order in case of
> >     nonblocking and/or nomodeset commits.
> > 
> > v4:
> >     - Minor code refactoring, fixed few typos(thanks to James
> > Ausmus)
> >     - Change the naming of qgv point
> >       masking/unmasking functions(James Ausmus).
> >     - Simplify the masking/unmasking operation itself,
> >       as we don't need to mask only single point per request(James
> > Ausmus)
> >     - Reject and stick to highest bandwidth point if SAGV
> >       can't be enabled(BSpec)
> > 
> > v5:
> >     - Add new mailbox reply codes, which seems to happen during
> > boot
> >       time for TGL and indicate that QGV setting is not yet
> > available.
> > 
> > v6:
> >     - Increase number of supported QGV points to be in sync with
> > BSpec.
> > 
> > v7: - Rebased and resolved conflict to fix build failure.
> >     - Fix NUM_QGV_POINTS to 8 and moved that to header file(James
> > Ausmus)
> > 
> > v8: - Don't report an error if we can't restrict qgv points, as
> > SAGV
> >       can be disabled by BIOS, which is completely legal. So don't
> >       make CI panic. Instead if we detect that there is only 1 QGV
> >       point accessible just analyze if we can fit the required
> > bandwidth
> >       requirements, but no need in restricting.
> > 
> > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> >       simultaneously.
> > 
> > v10: - Fix CDCLK corruption, because of global state getting
> > serialized
> >        without modeset, which caused copying of non-calculated
> > cdclk
> >        to be copied to dev_priv(thanks to Ville for the hint).
> > 
> > v11: - Remove unneeded headers and spaces(Matthew Roper)
> >      - Remove unneeded intel_qgv_info qi struct from bw check and
> > zero
> >        out the needed one(Matthew Roper)
> >      - Changed QGV error message to have more clear meaning(Matthew
> > Roper)
> >      - Use state->modeset_set instead of any_ms(Matthew Roper)
> >      - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where
> > it's used
> >      - Keep using crtc_state->hw.active instead of .enable(Matthew
> > Roper)
> >      - Moved unrelated changes to other patch(using latency as
> > parameter
> >        for plane wm calculation, moved to SAGV refactoring patch)
> > 
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
> >  drivers/gpu/drm/i915/display/intel_bw.c       | 134
> > +++++++++++++++---
> >  drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
> >  drivers/gpu/drm/i915/display/intel_display.c  |  91 +++++++++++-
> >  .../drm/i915/display/intel_display_types.h    |   3 +
> >  drivers/gpu/drm/i915/i915_drv.h               |   7 +-
> >  drivers/gpu/drm/i915/i915_reg.h               |   5 +
> >  drivers/gpu/drm/i915/intel_sideband.c         |  27 +++-
> >  8 files changed, 241 insertions(+), 30 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> > b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 7b49623419ba..41a2a89c9bdb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct
> > intel_crtc_state *crtc_state);
> >  struct drm_atomic_state *intel_atomic_state_alloc(struct
> > drm_device *dev);
> >  void intel_atomic_state_clear(struct drm_atomic_state *state);
> >  
> > +int intel_atomic_serialize_global_state(struct intel_atomic_state
> > *state);
> > +
> 
> We appear to already have this a few lines lower in the file.

Thanks for spotting!

> 
> 
> >  struct intel_crtc_state *
> >  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> >  			    struct intel_crtc *crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 3f6e29f61323..809fc1bf99c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -8,6 +8,9 @@
> >  #include "intel_bw.h"
> >  #include "intel_display_types.h"
> >  #include "intel_sideband.h"
> > +#include "intel_atomic.h"
> > +#include "intel_pm.h"
> > +
> >  
> >  /* Parameters for Qclk Geyserville (QGV) */
> >  struct intel_qgv_point {
> > @@ -15,7 +18,7 @@ struct intel_qgv_point {
> >  };
> >  
> >  struct intel_qgv_info {
> > -	struct intel_qgv_point points[3];
> > +	struct intel_qgv_point points[NUM_SAGV_POINTS];
> >  	u8 num_points;
> >  	u8 num_channels;
> >  	u8 t_bl;
> > @@ -113,6 +116,26 @@ static int
> > icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> >  	return 0;
> >  }
> >  
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > +				  u32 points_mask)
> > +{
> > +	int ret;
> > +
> > +	/* bspec says to keep retrying for at least 1 ms */
> > +	ret = skl_pcode_request(dev_priv,
> > ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> > +				points_mask,
> > +				GEN11_PCODE_POINTS_RESTRICTED_MASK,
> > +				GEN11_PCODE_POINTS_RESTRICTED,
> > +				1);
> > +
> > +	if (ret < 0) {
> > +		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> >  			      struct intel_qgv_info *qi)
> >  {
> > @@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private
> > *dev_priv)
> >  		icl_get_bw_info(dev_priv, &icl_sa_info);
> >  }
> >  
> > -static unsigned int intel_max_data_rate(struct drm_i915_private
> > *dev_priv,
> > -					int num_planes)
> > -{
> > -	if (INTEL_GEN(dev_priv) >= 11)
> > -		/*
> > -		 * FIXME with SAGV disabled maybe we can assume
> > -		 * point 1 will always be used? Seems to match
> > -		 * the behaviour observed in the wild.
> > -		 */
> > -		return min3(icl_max_bw(dev_priv, num_planes, 0),
> > -			    icl_max_bw(dev_priv, num_planes, 1),
> > -			    icl_max_bw(dev_priv, num_planes, 2));
> > -	else
> > -		return UINT_MAX;
> > -}
> > -
> >  static unsigned int intel_bw_crtc_num_active_planes(const struct
> > intel_crtc_state *crtc_state)
> >  {
> >  	/*
> > @@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> >  	unsigned int data_rate, max_data_rate;
> >  	unsigned int num_active_planes;
> >  	struct intel_crtc *crtc;
> > -	int i;
> > +	int i, ret;
> > +	u32 allowed_points = 0;
> > +	unsigned int max_bw_point = 0, max_bw = 0;
> > +	unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > +	u32 mask = (1 << num_qgv_points) - 1;
> >  
> >  	/* FIXME earlier gens need some checks too */
> >  	if (INTEL_GEN(dev_priv) < 11)
> > @@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> >  	data_rate = intel_bw_data_rate(dev_priv, bw_state);
> >  	num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> >  
> > -	max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > -
> >  	data_rate = DIV_ROUND_UP(data_rate, 1000);
> >  
> > -	if (data_rate > max_data_rate) {
> > -		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available
> > %d MB/s (%d active planes)\n",
> > -			      data_rate, max_data_rate,
> > num_active_planes);
> > +	for (i = 0; i < num_qgv_points; i++) {
> > +		max_data_rate = icl_max_bw(dev_priv, num_active_planes,
> > i);
> > +		/*
> > +		 * We need to know which qgv point gives us
> > +		 * maximum bandwidth in order to disable SAGV
> > +		 * if we find that we exceed SAGV block time
> > +		 * with watermarks. By that moment we already
> > +		 * have those, as it is calculated earlier in
> > +		 * intel_atomic_check,
> > +		 */
> > +		if (max_data_rate > max_bw) {
> > +			max_bw_point = i;
> > +			max_bw = max_data_rate;
> > +		}
> > +		if (max_data_rate >= data_rate)
> > +			allowed_points |= BIT(i);
> > +		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> > +			      i, max_data_rate, data_rate);
> > +	}
> > +
> > +	/*
> > +	 * BSpec states that we always should have at least one allowed
> > point
> > +	 * left, so if we couldn't - simply reject the configuration
> > for obvious
> > +	 * reasons.
> > +	 */
> > +	if (allowed_points == 0) {
> > +		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> > +			      " bandwidth for display
> > configuration.\n");
> >  		return -EINVAL;
> >  	}
> >  
> > +	/*
> > +	 * In case if SAGV is disabled in BIOS, we always get 1
> > +	 * SAGV point, but we can't send PCode commands to restrict it
> > +	 * as it will fail and pointless anyway.
> > +	 */
> > +	if (num_qgv_points == 1)
> > +		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> > +	else
> > +		dev_priv->sagv_status = I915_SAGV_ENABLED;
> 
> We should probably be doing this just once in icl_get_bw_info().

Makes sense.

> 
> > +
> > +	/*
> > +	 * Leave only single point with highest bandwidth, if
> > +	 * we can't enable SAGV according to BSpec.
> 
> Minor nitpick:  I'd say "...due to the increased memory latency it
> may
> cause" rather than "...according to BSpec."
> 
> > +	 */
> > +	if (!intel_can_enable_sagv(state)) {
> > +
> 
> Nitpick: unnecessary blank line.
> 
> > +		/*
> > +		 * This is a border line condition when we have 0
> > planes
> > +		 * and SAGV not enabled means that we should keep QGV
> > with
> > +		 * highest bandwidth, however algorithm returns wrong
> > result
> > +		 * for 0 planes and 0 data rate, so just stick to last
> > config
> > +		 * then. Otherwise use the QGV point with highest BW
> > according
> > +		 * to BSpec.
> 
> I'm not sure I follow this.  "SAGV not enabled" in the BIOS or
> because
> we've explicitly disabled it ourselves?  If the BIOS has it turned
> off,
> then we should only have a single QGV point, right?  And if we turned
> the SAGV off, then maybe intel_can_enable_sagv() will return true
> instead of false if we flip around the sagv mask from allowed-pipes
> to
> prohibited pipes like I suggested on the previous patch?

So there are basically few states: 1) SAGV on, everything is great,
2) SAGV is on but we can't enable it as it's WM0 doesn't fit into DBuf
3) SAGV is disabled in BIOS

If SAGV is disabled we are instructed to take the QGV point with the
highest bandwidth. So I do pick one with highest bandwidth.
That is fine. However I discovered that sometimes
we are doing commit with 0 planes, so we get 0 data rate and also 
algorithm returns same max bw values for 0 planes. So it ends up 
picking the first QGV point, despite it might be not the best choice.
So in that case if there are no active planes I simply use the last 
one, to prevent this wrong transition.
May be this is still not the best way to do though.

> 
> > +		 */
> > +		if (!data_rate && !num_active_planes) {
> > +			DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> > +			allowed_points = (~dev_priv->qgv_points_mask) &
> > mask;
> > +		} else {
> > +			allowed_points = 1 << max_bw_point;
> > +			DRM_DEBUG_KMS("No SAGV, using single QGV point
> > %d\n",
> > +				      max_bw_point);
> > +		}
> > +	}
> > +	/*
> > +	 * We store the ones which need to be masked as that is what
> > PCode
> > +	 * actually accepts as a parameter.
> > +	 */
> > +	state->qgv_points_mask = (~allowed_points) & mask;
> > +
> > +	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> > +		      state, state->qgv_points_mask);
> > +
> > +	/*
> > +	 * If the actual mask had changed we need to make sure that
> > +	 * the commits are serialized(in case this is a nomodeset,
> > nonblocking)
> > +	 */
> > +	if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> > +		ret = intel_atomic_serialize_global_state(state);
> > +		if (ret) {
> > +			DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > +			return ret;
> > +		}
> > +	}
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index 9db10af012f4..66bf9bc10b73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv);
> >  int intel_bw_atomic_check(struct intel_atomic_state *state);
> >  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> >  			  const struct intel_crtc_state *crtc_state);
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > +				  u32 points_mask);
> >  
> >  #endif /* __INTEL_BW_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7f31e33d0b16..fd35d0b0699c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14755,6 +14755,80 @@ static void
> > intel_atomic_cleanup_work(struct work_struct *work)
> >  	intel_atomic_helper_free_state(i915);
> >  }
> >  
> > +static void intel_qgv_points_mask(struct intel_atomic_state
> > *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int ret;
> > +	u32 new_mask = dev_priv->qgv_points_mask | state-
> > >qgv_points_mask;
> > +	unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > +	unsigned int mask = (1 << num_qgv_points) - 1;
> > +
> > +	/*
> > +	 * As we don't know initial hardware state during initial
> > commit
> > +	 * we should not do anything, until we actually figure out,
> > +	 * what are the qgv points to mask.
> > +	 */
> > +	if (!new_mask)
> > +		return;
> > +
> > +	WARN_ON(new_mask == mask);
> > +
> > +	/*
> > +	 * Just return if we can't control SAGV or don't have it.
> > +	 */
> > +	if (!intel_has_sagv(dev_priv))
> > +		return;
> > +
> > +	/*
> > +	 * Restrict required qgv points before updating the
> > configuration.
> > +	 * According to BSpec we can't mask and unmask qgv points at
> > the same
> > +	 * time. Also masking should be done before updating the
> > configuration
> > +	 * and unmasking afterwards.
> > +	 */
> > +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > +	if (ret < 0)
> > +		DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > +			      ret);
> > +	else
> > +		dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> > +static void intel_qgv_points_unmask(struct intel_atomic_state
> > *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int ret;
> > +	u32 new_mask = dev_priv->qgv_points_mask & state-
> > >qgv_points_mask;
> > +
> > +	/*
> > +	 * As we don't know initial hardware state during initial
> > commit
> > +	 * we should not do anything, until we actually figure out,
> > +	 * what are the qgv points to mask.
> > +	 */
> > +	if (!new_mask)
> > +		return;
> 
> This makes sense on the mask, but it doesn't seem like we'd want this
> on
> the unmask.  Unmask happens once we've finished the transition to a
> new
> state, right?  Allowing additional points to be used should
> definitely
> be safe then, right?

Right, thanks for spotting this condition actually came once
I discovered issues in CI, that when it makes initial commit
it simply tries to commit all 0 regardless of real hw state,
having this here is deeply wrong as I will then forbid unmasking
all points same time.
I was kind of busy with the main SAGV issue here(commit serialization,
which still doesn't work properly for SAGV) that forgot this thing
completely..

> 
> > +
> > +	/*
> > +	 * Just return if we can't control SAGV or don't have it.
> > +	 */
> > +	if (!intel_has_sagv(dev_priv))
> > +		return;
> > +
> > +	/*
> > +	 * Allow required qgv points after updating the configuration.
> > +	 * According to BSpec we can't mask and unmask qgv points at
> > the same
> > +	 * time. Also masking should be done before updating the
> > configuration
> > +	 * and unmasking afterwards.
> > +	 */
> > +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > +	if (ret < 0)
> > +		DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > +			      ret);
> 
> This message seems a bit misleading; we're removing restrictions here
> instead of adding them.

Yes.

> 
> 
> Matt
> 
> > +	else
> > +		dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> >  static void intel_atomic_commit_tail(struct intel_atomic_state
> > *state)
> >  {
> >  	struct drm_device *dev = state->base.dev;
> > @@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  		}
> >  	}
> >  
> > +	if ((INTEL_GEN(dev_priv) >= 11))
> > +		intel_qgv_points_mask(state);
> > +
> >  	intel_commit_modeset_disables(state);
> >  
> >  	/* FIXME: Eventually get rid of our crtc->config pointer */
> > @@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  		 * SKL workaround: bspec recommends we disable the SAGV
> > when we
> >  		 * have more then one pipe enabled
> >  		 */
> > -		if (!intel_can_enable_sagv(state))
> > -			intel_disable_sagv(dev_priv);
> > +		if (INTEL_GEN(dev_priv) < 11)
> > +			if (!intel_can_enable_sagv(state))
> > +				intel_disable_sagv(dev_priv);
> >  
> >  		intel_modeset_verify_disabled(dev_priv, state);
> >  	}
> > @@ -14883,8 +14961,11 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  	if (state->modeset)
> >  		intel_verify_planes(state);
> >  
> > -	if (state->modeset && intel_can_enable_sagv(state))
> > -		intel_enable_sagv(dev_priv);
> > +	if (INTEL_GEN(dev_priv) < 11) {
> > +		if (state->modeset && intel_can_enable_sagv(state))
> > +			intel_enable_sagv(dev_priv);
> > +	} else
> > +		intel_qgv_points_unmask(state);
> >  
> >  	drm_atomic_helper_commit_hw_done(&state->base);
> >  
> > @@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> >  	intel_shared_dpll_swap_state(state);
> >  	intel_atomic_track_fbs(state);
> >  
> > -	if (state->global_state_changed) {
> > +	if (state->global_state_changed && state->modeset) {
> >  		assert_global_state_locked(dev_priv);
> >  
> >  		memcpy(dev_priv->min_cdclk, state->min_cdclk,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 6a300cac883f..3535857dfed2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -534,6 +534,9 @@ struct intel_atomic_state {
> >  	struct i915_sw_fence commit_ready;
> >  
> >  	struct llist_node freed;
> > +
> > +	/* Gen11+ only */
> > +	u32 qgv_points_mask;
> >  };
> >  
> >  struct intel_plane_state {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 0ac9d7b006ca..54657b68010a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -850,6 +850,9 @@ enum intel_pipe_crc_source {
> >  	INTEL_PIPE_CRC_SOURCE_MAX,
> >  };
> >  
> > +/* BSpec precisely defines this */
> > +#define NUM_SAGV_POINTS 8
> > +
> >  #define INTEL_PIPE_CRC_ENTRIES_NR	128
> >  struct intel_pipe_crc {
> >  	spinlock_t lock;
> > @@ -1238,11 +1241,13 @@ struct drm_i915_private {
> >  	} dram_info;
> >  
> >  	struct intel_bw_info {
> > -		unsigned int deratedbw[3]; /* for each QGV point */
> > +		unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each
> > QGV point */
> >  		u8 num_qgv_points;
> >  		u8 num_planes;
> >  	} max_bw[6];
> >  
> > +	u32 qgv_points_mask;
> > +
> >  	struct drm_private_obj bw_obj;
> >  
> >  	struct intel_runtime_pm runtime_pm;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a4e5a4ae3885..2ea83ff681b9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8981,6 +8981,8 @@ enum {
> >  #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
> >  #define     GEN7_PCODE_TIMEOUT			0x2
> >  #define     GEN7_PCODE_ILLEGAL_DATA		0x3
> > +#define     GEN11_PCODE_MAIL_BOX_LOCKED		0x6
> > +#define     GEN11_PCODE_REJECTED		0x11
> >  #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> >  #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
> >  #define   GEN6_PCODE_READ_RC6VIDS		0x5
> > @@ -9002,6 +9004,7 @@ enum {
> >  #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
> >  #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
> >  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((poin
> > t) << 16) | (0x1 << 8))
> > +#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
> >  #define   GEN6_PCODE_READ_D_COMP		0x10
> >  #define   GEN6_PCODE_WRITE_D_COMP		0x11
> >  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> > @@ -9014,6 +9017,8 @@ enum {
> >  #define     GEN9_SAGV_IS_DISABLED		0x1
> >  #define     GEN9_SAGV_ENABLE			0x3
> >  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> > +#define GEN11_PCODE_POINTS_RESTRICTED		0x0
> > +#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
> >  #define GEN6_PCODE_DATA				_MMIO(0x138128)
> >  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> >  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> > b/drivers/gpu/drm/i915/intel_sideband.c
> > index e06b35b844a0..ff9dbed094d8 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > @@ -371,6 +371,29 @@ static inline int
> > gen7_check_mailbox_status(u32 mbox)
> >  	}
> >  }
> >  
> > +static inline int gen11_check_mailbox_status(u32 mbox)
> > +{
> > +	switch (mbox & GEN6_PCODE_ERROR_MASK) {
> > +	case GEN6_PCODE_SUCCESS:
> > +		return 0;
> > +	case GEN6_PCODE_ILLEGAL_CMD:
> > +		return -ENXIO;
> > +	case GEN7_PCODE_TIMEOUT:
> > +		return -ETIMEDOUT;
> > +	case GEN7_PCODE_ILLEGAL_DATA:
> > +		return -EINVAL;
> > +	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> > +		return -EOVERFLOW;
> > +	case GEN11_PCODE_MAIL_BOX_LOCKED:
> > +		return -EAGAIN;
> > +	case GEN11_PCODE_REJECTED:
> > +		return -EACCES;
> > +	default:
> > +		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> > +		return 0;
> > +	}
> > +}
> > +
> >  static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> >  				  u32 mbox, u32 *val, u32 *val1,
> >  				  int fast_timeout_us,
> > @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct
> > drm_i915_private *i915,
> >  	if (is_read && val1)
> >  		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
> >  
> > -	if (INTEL_GEN(i915) > 6)
> > +	if (INTEL_GEN(i915) >= 11)
> > +		return gen11_check_mailbox_status(mbox);
> > +	else if (INTEL_GEN(i915) > 6)
> >  		return gen7_check_mailbox_status(mbox);
> >  	else
> >  		return gen6_check_mailbox_status(mbox);
> > -- 
> > 2.17.1
> > 
> 
> 
_______________________________________________
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth.
@ 2019-11-20  9:16       ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 23+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-20  9:16 UTC (permalink / raw)
  To: Roper, Matthew D; +Cc: intel-gfx

On Tue, 2019-11-19 at 16:19 -0800, Matt Roper wrote:
> On Fri, Nov 15, 2019 at 04:54:01PM +0200, Stanislav Lisovskiy wrote:
> > According to BSpec 53998, we should try to
> > restrict qgv points, which can't provide
> > enough bandwidth for desired display configuration.
> > 
> > Currently we are just comparing against all of
> > those and take minimum(worst case).
> > 
> > v2: Fixed wrong PCode reply mask, removed hardcoded
> >     values.
> > 
> > v3: Forbid simultaneous legacy SAGV PCode requests and
> >     restricting qgv points. Put the actual restriction
> >     to commit function, added serialization(thanks to Ville)
> >     to prevent commit being applied out of order in case of
> >     nonblocking and/or nomodeset commits.
> > 
> > v4:
> >     - Minor code refactoring, fixed few typos(thanks to James
> > Ausmus)
> >     - Change the naming of qgv point
> >       masking/unmasking functions(James Ausmus).
> >     - Simplify the masking/unmasking operation itself,
> >       as we don't need to mask only single point per request(James
> > Ausmus)
> >     - Reject and stick to highest bandwidth point if SAGV
> >       can't be enabled(BSpec)
> > 
> > v5:
> >     - Add new mailbox reply codes, which seems to happen during
> > boot
> >       time for TGL and indicate that QGV setting is not yet
> > available.
> > 
> > v6:
> >     - Increase number of supported QGV points to be in sync with
> > BSpec.
> > 
> > v7: - Rebased and resolved conflict to fix build failure.
> >     - Fix NUM_QGV_POINTS to 8 and moved that to header file(James
> > Ausmus)
> > 
> > v8: - Don't report an error if we can't restrict qgv points, as
> > SAGV
> >       can be disabled by BIOS, which is completely legal. So don't
> >       make CI panic. Instead if we detect that there is only 1 QGV
> >       point accessible just analyze if we can fit the required
> > bandwidth
> >       requirements, but no need in restricting.
> > 
> > v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
> >       simultaneously.
> > 
> > v10: - Fix CDCLK corruption, because of global state getting
> > serialized
> >        without modeset, which caused copying of non-calculated
> > cdclk
> >        to be copied to dev_priv(thanks to Ville for the hint).
> > 
> > v11: - Remove unneeded headers and spaces(Matthew Roper)
> >      - Remove unneeded intel_qgv_info qi struct from bw check and
> > zero
> >        out the needed one(Matthew Roper)
> >      - Changed QGV error message to have more clear meaning(Matthew
> > Roper)
> >      - Use state->modeset_set instead of any_ms(Matthew Roper)
> >      - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where
> > it's used
> >      - Keep using crtc_state->hw.active instead of .enable(Matthew
> > Roper)
> >      - Moved unrelated changes to other patch(using latency as
> > parameter
> >        for plane wm calculation, moved to SAGV refactoring patch)
> > 
> > Reviewed-by: James Ausmus <james.ausmus@intel.com>
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_atomic.h   |   2 +
> >  drivers/gpu/drm/i915/display/intel_bw.c       | 134
> > +++++++++++++++---
> >  drivers/gpu/drm/i915/display/intel_bw.h       |   2 +
> >  drivers/gpu/drm/i915/display/intel_display.c  |  91 +++++++++++-
> >  .../drm/i915/display/intel_display_types.h    |   3 +
> >  drivers/gpu/drm/i915/i915_drv.h               |   7 +-
> >  drivers/gpu/drm/i915/i915_reg.h               |   5 +
> >  drivers/gpu/drm/i915/intel_sideband.c         |  27 +++-
> >  8 files changed, 241 insertions(+), 30 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h
> > b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index 7b49623419ba..41a2a89c9bdb 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -41,6 +41,8 @@ void intel_crtc_copy_color_blobs(struct
> > intel_crtc_state *crtc_state);
> >  struct drm_atomic_state *intel_atomic_state_alloc(struct
> > drm_device *dev);
> >  void intel_atomic_state_clear(struct drm_atomic_state *state);
> >  
> > +int intel_atomic_serialize_global_state(struct intel_atomic_state
> > *state);
> > +
> 
> We appear to already have this a few lines lower in the file.

Thanks for spotting!

> 
> 
> >  struct intel_crtc_state *
> >  intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> >  			    struct intel_crtc *crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c
> > b/drivers/gpu/drm/i915/display/intel_bw.c
> > index 3f6e29f61323..809fc1bf99c5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.c
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.c
> > @@ -8,6 +8,9 @@
> >  #include "intel_bw.h"
> >  #include "intel_display_types.h"
> >  #include "intel_sideband.h"
> > +#include "intel_atomic.h"
> > +#include "intel_pm.h"
> > +
> >  
> >  /* Parameters for Qclk Geyserville (QGV) */
> >  struct intel_qgv_point {
> > @@ -15,7 +18,7 @@ struct intel_qgv_point {
> >  };
> >  
> >  struct intel_qgv_info {
> > -	struct intel_qgv_point points[3];
> > +	struct intel_qgv_point points[NUM_SAGV_POINTS];
> >  	u8 num_points;
> >  	u8 num_channels;
> >  	u8 t_bl;
> > @@ -113,6 +116,26 @@ static int
> > icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
> >  	return 0;
> >  }
> >  
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > +				  u32 points_mask)
> > +{
> > +	int ret;
> > +
> > +	/* bspec says to keep retrying for at least 1 ms */
> > +	ret = skl_pcode_request(dev_priv,
> > ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
> > +				points_mask,
> > +				GEN11_PCODE_POINTS_RESTRICTED_MASK,
> > +				GEN11_PCODE_POINTS_RESTRICTED,
> > +				1);
> > +
> > +	if (ret < 0) {
> > +		DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
> > +		return ret;
> > +	}
> > +
> > +	return 0;
> > +}
> > +
> >  static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
> >  			      struct intel_qgv_info *qi)
> >  {
> > @@ -270,22 +293,6 @@ void intel_bw_init_hw(struct drm_i915_private
> > *dev_priv)
> >  		icl_get_bw_info(dev_priv, &icl_sa_info);
> >  }
> >  
> > -static unsigned int intel_max_data_rate(struct drm_i915_private
> > *dev_priv,
> > -					int num_planes)
> > -{
> > -	if (INTEL_GEN(dev_priv) >= 11)
> > -		/*
> > -		 * FIXME with SAGV disabled maybe we can assume
> > -		 * point 1 will always be used? Seems to match
> > -		 * the behaviour observed in the wild.
> > -		 */
> > -		return min3(icl_max_bw(dev_priv, num_planes, 0),
> > -			    icl_max_bw(dev_priv, num_planes, 1),
> > -			    icl_max_bw(dev_priv, num_planes, 2));
> > -	else
> > -		return UINT_MAX;
> > -}
> > -
> >  static unsigned int intel_bw_crtc_num_active_planes(const struct
> > intel_crtc_state *crtc_state)
> >  {
> >  	/*
> > @@ -377,7 +384,11 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> >  	unsigned int data_rate, max_data_rate;
> >  	unsigned int num_active_planes;
> >  	struct intel_crtc *crtc;
> > -	int i;
> > +	int i, ret;
> > +	u32 allowed_points = 0;
> > +	unsigned int max_bw_point = 0, max_bw = 0;
> > +	unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > +	u32 mask = (1 << num_qgv_points) - 1;
> >  
> >  	/* FIXME earlier gens need some checks too */
> >  	if (INTEL_GEN(dev_priv) < 11)
> > @@ -421,16 +432,93 @@ int intel_bw_atomic_check(struct
> > intel_atomic_state *state)
> >  	data_rate = intel_bw_data_rate(dev_priv, bw_state);
> >  	num_active_planes = intel_bw_num_active_planes(dev_priv,
> > bw_state);
> >  
> > -	max_data_rate = intel_max_data_rate(dev_priv,
> > num_active_planes);
> > -
> >  	data_rate = DIV_ROUND_UP(data_rate, 1000);
> >  
> > -	if (data_rate > max_data_rate) {
> > -		DRM_DEBUG_KMS("Bandwidth %u MB/s exceeds max available
> > %d MB/s (%d active planes)\n",
> > -			      data_rate, max_data_rate,
> > num_active_planes);
> > +	for (i = 0; i < num_qgv_points; i++) {
> > +		max_data_rate = icl_max_bw(dev_priv, num_active_planes,
> > i);
> > +		/*
> > +		 * We need to know which qgv point gives us
> > +		 * maximum bandwidth in order to disable SAGV
> > +		 * if we find that we exceed SAGV block time
> > +		 * with watermarks. By that moment we already
> > +		 * have those, as it is calculated earlier in
> > +		 * intel_atomic_check,
> > +		 */
> > +		if (max_data_rate > max_bw) {
> > +			max_bw_point = i;
> > +			max_bw = max_data_rate;
> > +		}
> > +		if (max_data_rate >= data_rate)
> > +			allowed_points |= BIT(i);
> > +		DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
> > +			      i, max_data_rate, data_rate);
> > +	}
> > +
> > +	/*
> > +	 * BSpec states that we always should have at least one allowed
> > point
> > +	 * left, so if we couldn't - simply reject the configuration
> > for obvious
> > +	 * reasons.
> > +	 */
> > +	if (allowed_points == 0) {
> > +		DRM_DEBUG_KMS("No QGV points provide sufficient memory"
> > +			      " bandwidth for display
> > configuration.\n");
> >  		return -EINVAL;
> >  	}
> >  
> > +	/*
> > +	 * In case if SAGV is disabled in BIOS, we always get 1
> > +	 * SAGV point, but we can't send PCode commands to restrict it
> > +	 * as it will fail and pointless anyway.
> > +	 */
> > +	if (num_qgv_points == 1)
> > +		dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
> > +	else
> > +		dev_priv->sagv_status = I915_SAGV_ENABLED;
> 
> We should probably be doing this just once in icl_get_bw_info().

Makes sense.

> 
> > +
> > +	/*
> > +	 * Leave only single point with highest bandwidth, if
> > +	 * we can't enable SAGV according to BSpec.
> 
> Minor nitpick:  I'd say "...due to the increased memory latency it
> may
> cause" rather than "...according to BSpec."
> 
> > +	 */
> > +	if (!intel_can_enable_sagv(state)) {
> > +
> 
> Nitpick: unnecessary blank line.
> 
> > +		/*
> > +		 * This is a border line condition when we have 0
> > planes
> > +		 * and SAGV not enabled means that we should keep QGV
> > with
> > +		 * highest bandwidth, however algorithm returns wrong
> > result
> > +		 * for 0 planes and 0 data rate, so just stick to last
> > config
> > +		 * then. Otherwise use the QGV point with highest BW
> > according
> > +		 * to BSpec.
> 
> I'm not sure I follow this.  "SAGV not enabled" in the BIOS or
> because
> we've explicitly disabled it ourselves?  If the BIOS has it turned
> off,
> then we should only have a single QGV point, right?  And if we turned
> the SAGV off, then maybe intel_can_enable_sagv() will return true
> instead of false if we flip around the sagv mask from allowed-pipes
> to
> prohibited pipes like I suggested on the previous patch?

So there are basically few states: 1) SAGV on, everything is great,
2) SAGV is on but we can't enable it as it's WM0 doesn't fit into DBuf
3) SAGV is disabled in BIOS

If SAGV is disabled we are instructed to take the QGV point with the
highest bandwidth. So I do pick one with highest bandwidth.
That is fine. However I discovered that sometimes
we are doing commit with 0 planes, so we get 0 data rate and also 
algorithm returns same max bw values for 0 planes. So it ends up 
picking the first QGV point, despite it might be not the best choice.
So in that case if there are no active planes I simply use the last 
one, to prevent this wrong transition.
May be this is still not the best way to do though.

> 
> > +		 */
> > +		if (!data_rate && !num_active_planes) {
> > +			DRM_DEBUG_KMS("No SAGV, using old QGV mask\n");
> > +			allowed_points = (~dev_priv->qgv_points_mask) &
> > mask;
> > +		} else {
> > +			allowed_points = 1 << max_bw_point;
> > +			DRM_DEBUG_KMS("No SAGV, using single QGV point
> > %d\n",
> > +				      max_bw_point);
> > +		}
> > +	}
> > +	/*
> > +	 * We store the ones which need to be masked as that is what
> > PCode
> > +	 * actually accepts as a parameter.
> > +	 */
> > +	state->qgv_points_mask = (~allowed_points) & mask;
> > +
> > +	DRM_DEBUG_KMS("New state %p qgv mask %x\n",
> > +		      state, state->qgv_points_mask);
> > +
> > +	/*
> > +	 * If the actual mask had changed we need to make sure that
> > +	 * the commits are serialized(in case this is a nomodeset,
> > nonblocking)
> > +	 */
> > +	if (state->qgv_points_mask != dev_priv->qgv_points_mask) {
> > +		ret = intel_atomic_serialize_global_state(state);
> > +		if (ret) {
> > +			DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > +			return ret;
> > +		}
> > +	}
> > +
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h
> > b/drivers/gpu/drm/i915/display/intel_bw.h
> > index 9db10af012f4..66bf9bc10b73 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -28,5 +28,7 @@ int intel_bw_init(struct drm_i915_private
> > *dev_priv);
> >  int intel_bw_atomic_check(struct intel_atomic_state *state);
> >  void intel_bw_crtc_update(struct intel_bw_state *bw_state,
> >  			  const struct intel_crtc_state *crtc_state);
> > +int icl_pcode_restrict_qgv_points(struct drm_i915_private
> > *dev_priv,
> > +				  u32 points_mask);
> >  
> >  #endif /* __INTEL_BW_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index 7f31e33d0b16..fd35d0b0699c 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -14755,6 +14755,80 @@ static void
> > intel_atomic_cleanup_work(struct work_struct *work)
> >  	intel_atomic_helper_free_state(i915);
> >  }
> >  
> > +static void intel_qgv_points_mask(struct intel_atomic_state
> > *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int ret;
> > +	u32 new_mask = dev_priv->qgv_points_mask | state-
> > >qgv_points_mask;
> > +	unsigned int num_qgv_points = dev_priv-
> > >max_bw[0].num_qgv_points;
> > +	unsigned int mask = (1 << num_qgv_points) - 1;
> > +
> > +	/*
> > +	 * As we don't know initial hardware state during initial
> > commit
> > +	 * we should not do anything, until we actually figure out,
> > +	 * what are the qgv points to mask.
> > +	 */
> > +	if (!new_mask)
> > +		return;
> > +
> > +	WARN_ON(new_mask == mask);
> > +
> > +	/*
> > +	 * Just return if we can't control SAGV or don't have it.
> > +	 */
> > +	if (!intel_has_sagv(dev_priv))
> > +		return;
> > +
> > +	/*
> > +	 * Restrict required qgv points before updating the
> > configuration.
> > +	 * According to BSpec we can't mask and unmask qgv points at
> > the same
> > +	 * time. Also masking should be done before updating the
> > configuration
> > +	 * and unmasking afterwards.
> > +	 */
> > +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > +	if (ret < 0)
> > +		DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > +			      ret);
> > +	else
> > +		dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> > +static void intel_qgv_points_unmask(struct intel_atomic_state
> > *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int ret;
> > +	u32 new_mask = dev_priv->qgv_points_mask & state-
> > >qgv_points_mask;
> > +
> > +	/*
> > +	 * As we don't know initial hardware state during initial
> > commit
> > +	 * we should not do anything, until we actually figure out,
> > +	 * what are the qgv points to mask.
> > +	 */
> > +	if (!new_mask)
> > +		return;
> 
> This makes sense on the mask, but it doesn't seem like we'd want this
> on
> the unmask.  Unmask happens once we've finished the transition to a
> new
> state, right?  Allowing additional points to be used should
> definitely
> be safe then, right?

Right, thanks for spotting this condition actually came once
I discovered issues in CI, that when it makes initial commit
it simply tries to commit all 0 regardless of real hw state,
having this here is deeply wrong as I will then forbid unmasking
all points same time.
I was kind of busy with the main SAGV issue here(commit serialization,
which still doesn't work properly for SAGV) that forgot this thing
completely..

> 
> > +
> > +	/*
> > +	 * Just return if we can't control SAGV or don't have it.
> > +	 */
> > +	if (!intel_has_sagv(dev_priv))
> > +		return;
> > +
> > +	/*
> > +	 * Allow required qgv points after updating the configuration.
> > +	 * According to BSpec we can't mask and unmask qgv points at
> > the same
> > +	 * time. Also masking should be done before updating the
> > configuration
> > +	 * and unmasking afterwards.
> > +	 */
> > +	ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
> > +	if (ret < 0)
> > +		DRM_DEBUG_KMS("Could not restrict required qgv
> > points(%d)\n",
> > +			      ret);
> 
> This message seems a bit misleading; we're removing restrictions here
> instead of adding them.

Yes.

> 
> 
> Matt
> 
> > +	else
> > +		dev_priv->qgv_points_mask = new_mask;
> > +}
> > +
> >  static void intel_atomic_commit_tail(struct intel_atomic_state
> > *state)
> >  {
> >  	struct drm_device *dev = state->base.dev;
> > @@ -14782,6 +14856,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  		}
> >  	}
> >  
> > +	if ((INTEL_GEN(dev_priv) >= 11))
> > +		intel_qgv_points_mask(state);
> > +
> >  	intel_commit_modeset_disables(state);
> >  
> >  	/* FIXME: Eventually get rid of our crtc->config pointer */
> > @@ -14800,8 +14877,9 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  		 * SKL workaround: bspec recommends we disable the SAGV
> > when we
> >  		 * have more then one pipe enabled
> >  		 */
> > -		if (!intel_can_enable_sagv(state))
> > -			intel_disable_sagv(dev_priv);
> > +		if (INTEL_GEN(dev_priv) < 11)
> > +			if (!intel_can_enable_sagv(state))
> > +				intel_disable_sagv(dev_priv);
> >  
> >  		intel_modeset_verify_disabled(dev_priv, state);
> >  	}
> > @@ -14883,8 +14961,11 @@ static void
> > intel_atomic_commit_tail(struct intel_atomic_state *state)
> >  	if (state->modeset)
> >  		intel_verify_planes(state);
> >  
> > -	if (state->modeset && intel_can_enable_sagv(state))
> > -		intel_enable_sagv(dev_priv);
> > +	if (INTEL_GEN(dev_priv) < 11) {
> > +		if (state->modeset && intel_can_enable_sagv(state))
> > +			intel_enable_sagv(dev_priv);
> > +	} else
> > +		intel_qgv_points_unmask(state);
> >  
> >  	drm_atomic_helper_commit_hw_done(&state->base);
> >  
> > @@ -15031,7 +15112,7 @@ static int intel_atomic_commit(struct
> > drm_device *dev,
> >  	intel_shared_dpll_swap_state(state);
> >  	intel_atomic_track_fbs(state);
> >  
> > -	if (state->global_state_changed) {
> > +	if (state->global_state_changed && state->modeset) {
> >  		assert_global_state_locked(dev_priv);
> >  
> >  		memcpy(dev_priv->min_cdclk, state->min_cdclk,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 6a300cac883f..3535857dfed2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -534,6 +534,9 @@ struct intel_atomic_state {
> >  	struct i915_sw_fence commit_ready;
> >  
> >  	struct llist_node freed;
> > +
> > +	/* Gen11+ only */
> > +	u32 qgv_points_mask;
> >  };
> >  
> >  struct intel_plane_state {
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 0ac9d7b006ca..54657b68010a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -850,6 +850,9 @@ enum intel_pipe_crc_source {
> >  	INTEL_PIPE_CRC_SOURCE_MAX,
> >  };
> >  
> > +/* BSpec precisely defines this */
> > +#define NUM_SAGV_POINTS 8
> > +
> >  #define INTEL_PIPE_CRC_ENTRIES_NR	128
> >  struct intel_pipe_crc {
> >  	spinlock_t lock;
> > @@ -1238,11 +1241,13 @@ struct drm_i915_private {
> >  	} dram_info;
> >  
> >  	struct intel_bw_info {
> > -		unsigned int deratedbw[3]; /* for each QGV point */
> > +		unsigned int deratedbw[NUM_SAGV_POINTS]; /* for each
> > QGV point */
> >  		u8 num_qgv_points;
> >  		u8 num_planes;
> >  	} max_bw[6];
> >  
> > +	u32 qgv_points_mask;
> > +
> >  	struct drm_private_obj bw_obj;
> >  
> >  	struct intel_runtime_pm runtime_pm;
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h
> > index a4e5a4ae3885..2ea83ff681b9 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -8981,6 +8981,8 @@ enum {
> >  #define     GEN6_PCODE_UNIMPLEMENTED_CMD	0xFF
> >  #define     GEN7_PCODE_TIMEOUT			0x2
> >  #define     GEN7_PCODE_ILLEGAL_DATA		0x3
> > +#define     GEN11_PCODE_MAIL_BOX_LOCKED		0x6
> > +#define     GEN11_PCODE_REJECTED		0x11
> >  #define     GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
> >  #define   GEN6_PCODE_WRITE_RC6VIDS		0x4
> >  #define   GEN6_PCODE_READ_RC6VIDS		0x5
> > @@ -9002,6 +9004,7 @@ enum {
> >  #define   ICL_PCODE_MEM_SUBSYSYSTEM_INFO	0xd
> >  #define     ICL_PCODE_MEM_SS_READ_GLOBAL_INFO	(0x0 << 8)
> >  #define     ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point)	(((poin
> > t) << 16) | (0x1 << 8))
> > +#define   ICL_PCODE_SAGV_DE_MEM_SS_CONFIG	0xe
> >  #define   GEN6_PCODE_READ_D_COMP		0x10
> >  #define   GEN6_PCODE_WRITE_D_COMP		0x11
> >  #define   HSW_PCODE_DE_WRITE_FREQ_REQ		0x17
> > @@ -9014,6 +9017,8 @@ enum {
> >  #define     GEN9_SAGV_IS_DISABLED		0x1
> >  #define     GEN9_SAGV_ENABLE			0x3
> >  #define GEN12_PCODE_READ_SAGV_BLOCK_TIME_US	0x23
> > +#define GEN11_PCODE_POINTS_RESTRICTED		0x0
> > +#define GEN11_PCODE_POINTS_RESTRICTED_MASK	0x1
> >  #define GEN6_PCODE_DATA				_MMIO(0x138128)
> >  #define   GEN6_PCODE_FREQ_IA_RATIO_SHIFT	8
> >  #define   GEN6_PCODE_FREQ_RING_RATIO_SHIFT	16
> > diff --git a/drivers/gpu/drm/i915/intel_sideband.c
> > b/drivers/gpu/drm/i915/intel_sideband.c
> > index e06b35b844a0..ff9dbed094d8 100644
> > --- a/drivers/gpu/drm/i915/intel_sideband.c
> > +++ b/drivers/gpu/drm/i915/intel_sideband.c
> > @@ -371,6 +371,29 @@ static inline int
> > gen7_check_mailbox_status(u32 mbox)
> >  	}
> >  }
> >  
> > +static inline int gen11_check_mailbox_status(u32 mbox)
> > +{
> > +	switch (mbox & GEN6_PCODE_ERROR_MASK) {
> > +	case GEN6_PCODE_SUCCESS:
> > +		return 0;
> > +	case GEN6_PCODE_ILLEGAL_CMD:
> > +		return -ENXIO;
> > +	case GEN7_PCODE_TIMEOUT:
> > +		return -ETIMEDOUT;
> > +	case GEN7_PCODE_ILLEGAL_DATA:
> > +		return -EINVAL;
> > +	case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> > +		return -EOVERFLOW;
> > +	case GEN11_PCODE_MAIL_BOX_LOCKED:
> > +		return -EAGAIN;
> > +	case GEN11_PCODE_REJECTED:
> > +		return -EACCES;
> > +	default:
> > +		MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> > +		return 0;
> > +	}
> > +}
> > +
> >  static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> >  				  u32 mbox, u32 *val, u32 *val1,
> >  				  int fast_timeout_us,
> > @@ -408,7 +431,9 @@ static int __sandybridge_pcode_rw(struct
> > drm_i915_private *i915,
> >  	if (is_read && val1)
> >  		*val1 = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA1);
> >  
> > -	if (INTEL_GEN(i915) > 6)
> > +	if (INTEL_GEN(i915) >= 11)
> > +		return gen11_check_mailbox_status(mbox);
> > +	else if (INTEL_GEN(i915) > 6)
> >  		return gen7_check_mailbox_status(mbox);
> >  	else
> >  		return gen6_check_mailbox_status(mbox);
> > -- 
> > 2.17.1
> > 
> 
> 
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-20  9:58       ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 23+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-20  9:58 UTC (permalink / raw)
  To: Roper, Matthew D; +Cc: intel-gfx

On Tue, 2019-11-19 at 15:13 -0800, Matt Roper wrote:
> On Fri, Nov 15, 2019 at 04:54:00PM +0200, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets split it into separate functions.
> > 
> > v2:
> >     - Rework watermark calculation algorithm to
> >       attempt to calculate Level 0 watermark
> >       with added sagv block time latency and
> >       check if it fits in DBuf in order to
> >       determine if SAGV can be enabled already
> >       at this stage, just as BSpec 49325 states.
> >       if that fails rollback to usual Level 0
> >       latency and disable SAGV.
> >     - Remove unneeded tabs(James Ausmus)
> > 
> > v3: Rebased the patch
> > 
> > v4: - Added back interlaced check for Gen12 and
> >       added separate function for TGL SAGV check
> >       (thanks to James Ausmus for spotting)
> >     - Removed unneeded gen check
> >     - Extracted Gen12 SAGV decision making code
> >       to a separate function from skl_compute_wm
> > 
> > v5: - Added SAGV global state to dev_priv, because
> >       we need to track all pipes, not only those
> >       in atomic state. Each pipe has now correspondent
> >       bit mask reflecting, whether it can tolerate
> >       SAGV or not(thanks to Ville Syrjala for suggestions).
> >     - Now using active flag instead of enable in crc
> >       usage check.
> > 
> > v6: - Fixed rebase conflicts
> > 
> > v7: - kms_cursor_legacy seems to get broken because of multiple
> > memcpy
> >       calls when copying level 0 water marks for enabled SAGV, to
> >       fix this now simply using that field right away, without
> > copying,
> >       for that introduced a new wm_level accessor which decides
> > which
> >       wm_level to return based on SAGV state.
> > 
> > v8: - Protect crtc_sagv_mask same way as we do for other global
> > state
> >       changes: i.e check if changes are needed, then grab all crtc
> > locks
> >       to serialize the changes.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>


Hi Matt,

Thanks for really valid comments. I should mention that currently 
I'm mostly tried to figure out how to do it properly as current
way we serialize commits seems to be a bit problematic.

I.e when I detect that I need to change a mask which stores which
pipes tolerate SAGV, according to current Ville's paradigm I should
grab all the crtcs, that locking the global state that way and
serializing access, preventing contention which might occur if
different commits read global state and modify different crtcs
at the same time.
However in CI I get comlains then like:

 WARNING: CPU: 6 PID: 1084 at drivers/gpu/drm/drm_modeset_lock.c:228
drm_modeset_drop_locks+0x35/0x40
<4> [369.766202] Modules linked in: vgem snd_hda_codec_hdmi mei_hdcp
i915 x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul
ghash_clmulni_intel snd_hda_intel snd_intel_dspcfg cdc_ether usbnet
snd_hda_codec mii snd_hwdep snd_hda_core snd_pcm mei_me mei
prime_numbers
<4> [369.766225] RIP: 0010:drm_modeset_drop_locks+0x35/0x40
<4> [369.766265]  drm_mode_cursor_common+0xf3/0x230
<4> [369.766273]  ? drm_mode_setplane+0x190/0x190
<4> [369.766275]  drm_mode_cursor_ioctl+0x48/0x70
<4> [369.766280]  drm_ioctl_kernel+0xa7/0xf0
<4> [369.766283]  drm_ioctl+0x2e1/0x390
<4> [369.766287]  ? drm_mode_setplane+0x190/0x190

Which means that WARN happens when EDADLK(possible deadlock happens)

This most likely happens because for example if there are
two racing commits:

Commit 1            Commit 2          Global state in dev_priv:

locked crtc 0        locked crtc1        00 (SAGV is off for both)

reads global state
  as 00
                     reads global state
	                as 00
figures out
that SAGV is 
ok for pipe 0
tries lock the global
   state
(bails out as other
 crtc is locked,
according to WW mutex
algorithm commit starts 
from begining)
                          ...



Guess this happens for both one of those manages grab all the locks,
so basically current way serializing commits seems to be wrong
if there is a real intense contention. Or am I missing something here?


> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
> >  .../drm/i915/display/intel_display_types.h    |  15 +
> >  drivers/gpu/drm/i915/i915_drv.h               |   6 +
> >  drivers/gpu/drm/i915/intel_pm.c               | 418
> > ++++++++++++++++--
> >  drivers/gpu/drm/i915/intel_pm.h               |   1 +
> >  5 files changed, 409 insertions(+), 43 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index adf50c4b38ad..7f31e33d0b16 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13401,7 +13401,10 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> >  		/* Watermarks */
> >  		for (level = 0; level <= max_level; level++) {
> >  			if (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> > -						&sw_plane_wm-
> > >wm[level]))
> > +						&sw_plane_wm-
> > >wm[level]) ||
> > +			   (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> 
> If we cache the result of 'can enable sagv' into the state structure
> (as
> I suggest farther down the patch) then we can just compare with the
> right value here rather than trying both.

Could be, however my concern was that hw state might not always match
our current state, however as we seem to do that check already after
we commit the values, probably yes we can optimize it that way.


> 
> > +						&sw_plane_wm->sagv_wm0) 
> > &&
> > +			   (level == 0)))
> >  				continue;
> >  
> >  			DRM_ERROR("mismatch in WM pipe %c plane %d
> > level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> > @@ -13453,7 +13456,10 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> >  		/* Watermarks */
> >  		for (level = 0; level <= max_level; level++) {
> >  			if (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> > -						&sw_plane_wm-
> > >wm[level]))
> > +						&sw_plane_wm-
> > >wm[level]) ||
> > +			   (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> > +						&sw_plane_wm->sagv_wm0) 
> > &&
> > +			   (level == 0)))
> >  				continue;
> >  
> >  			DRM_ERROR("mismatch in WM pipe %c cursor level
> > %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> > @@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  							      new_crtc_
> > state);
> >  	}
> >  
> > +	dev_priv->crtc_sagv_mask = state->crtc_sagv_mask;
> > +
> >  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> >  		intel_post_plane_update(old_crtc_state);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 83ea04149b77..6a300cac883f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -490,6 +490,20 @@ struct intel_atomic_state {
> >  	 */
> >  	u8 active_pipe_changes;
> >  
> > +	/*
> > +	 * Contains a mask which reflects whether correspondent pipe
> > +	 * can tolerate SAGV or not, so that we can make a decision
> > +	 * at atomic_commit_tail stage, whether we enable it or not
> > +	 * based on global state in dev_priv.
> > +	 */
> > +	u32 crtc_sagv_mask;
> 
> I feel like your code might flow a bit more naturally if this were
> inverted and used as a mask of CRTCs that currently prohibit SAGV?

I think it should be fine both ways.

> 
> > +
> > +	/*
> > +	 * Used to determine if the mask has been already calculated
> > +	 * for this state, to avoid unnecessary calculations.
> > +	 */
> > +	bool crtc_sagv_mask_set;
> 
> I think this field can go away too if we just call the function once
> and
> cache the result in the state field.


Yes I think it can be cached. Need again still to rule out possible
complications from simultaneous global state mask modification from
different commits with different crtcs, as in fact it is global state
which determines if SAGV can be enabled or not. As current state
only might contain some crtcs, but not all.

> 
> > +
> >  	u8 active_pipes;
> >  	/* minimum acceptable cdclk for each pipe */
> >  	int min_cdclk[I915_MAX_PIPES];
> > @@ -670,6 +684,7 @@ struct skl_plane_wm {
> >  	struct skl_wm_level wm[8];
> >  	struct skl_wm_level uv_wm[8];
> >  	struct skl_wm_level trans_wm;
> > +	struct skl_wm_level sagv_wm0;
> >  	bool is_planar;
> >  };
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 1779f600fcfb..0ac9d7b006ca 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1171,6 +1171,12 @@ struct drm_i915_private {
> >  
> >  	u32 sagv_block_time_us;
> >  
> > +	/*
> > +	 * Contains a bit mask, whether correspondent
> > +	 * pipe allows SAGV or not.
> > +	 */
> > +	u32 crtc_sagv_mask;
> > +
> >  	struct {
> >  		/*
> >  		 * Raw watermark latency values:
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 05ba9e1bd247..c914bd1862ba 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct
> > drm_i915_private *dev_priv)
> >  	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> >  }
> >  
> > -static bool
> > +bool
> >  intel_has_sagv(struct drm_i915_private *dev_priv)
> >  {
> > -	/* HACK! */
> > -	if (IS_GEN(dev_priv, 12))
> > -		return false;
> > -
> 
> The SAGV work you're doing is pretty complicated and this general
> patch
> touches a lot of different platforms (SKL, ICL, TGL, etc.).  It would
> be
> great if we could break this up into a few patches, but if that's not
> easy, I'd suggest at least moving this specific change to a final
> patch
> all of its own so that we "flip the switch" on TGL independently of
> the
> general rework.  That way if we wind up with TGL regressions (but no
> problems on SKL/ICL) we can just revert a tiny 2-line patch rather
> than
> reverting _all_ of your work here.

Agree, the amount of issues which arise or might arise is skyrocketing.
Probably need to split it into smaller chunks, however still prefer
that some crucial related stuff is modified in the same patch,
otherwise this gets really hard to track.

> 
> >  	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> >  		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> >  }
> > @@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private
> > *dev_priv)
> >  	return 0;
> >  }
> >  
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +static void skl_set_sagv_mask(struct intel_atomic_state *state)
> 
> Minor nitpick:  I know there's a lot of inconsistent terminology used
> throughout the driver, but I always expect functions with names like
> 'set,' 'update,' etc. to touch hardware somehow.  I prefer naming
> functions like this with verbs like 'compute' or 'calc' to make it a
> bit
> more clear (at least in my mind) that we're not doing anything here
> yet
> except analyzing the state.

Makes sense. Will rename it.

> 
> >  {
> >  	struct drm_device *dev = state->base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> >  	enum pipe pipe;
> >  	int level, latency;
> >  
> > +	if (state->crtc_sagv_mask_set)
> > +		return;
> > +
> >  	if (!intel_has_sagv(dev_priv))
> > -		return false;
> > +		return;
> 
> It seems like this check should just be at the top of
> intel_can_enable_sagv() rather than duplicated in each platform's
> mask-calculating function?

Agree.

> 
> >  
> >  	/*
> >  	 * If there are no active CRTCs, no additional checks need be
> > performed
> >  	 */
> >  	if (hweight8(state->active_pipes) == 0)
> > -		return true;
> > +		return;
> 
> This also appears to be a platform-independent check that can move up
> to
> the intel_can_enable_sagv() level?  You don't have it in the TGL
> function right now, but it seems like it should apply there as well?

Agree.

> 
> >  
> >  	/*
> >  	 * SKL+ workaround: bspec recommends we disable SAGV when we
> > have
> >  	 * more then one pipe enabled
> >  	 */
> >  	if (hweight8(state->active_pipes) > 1)
> > -		return false;
> > +		return;
> >  
> >  	/* Since we're now guaranteed to only have one active CRTC...
> > */
> >  	pipe = ffs(state->active_pipes) - 1;
> >  	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> >  	crtc_state = to_intel_crtc_state(crtc->base.state);
> > +	state->crtc_sagv_mask &= ~BIT(crtc->pipe);
> >  
> > -	if (crtc_state->hw.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE)
> > -		return false;
> > +	if (crtc_state->hw.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE) {
> > +		state->crtc_sagv_mask_set = true;
> > +		return;
> > +	}
> >  
> >  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> >  		struct skl_plane_wm *wm =
> 
> In the pre-existing code for this loop (that doesn't show up in the
> diff
> here) it looks like we're looking at the already-committed plane
> state
> to see if the old plane FB was x-tiled...should that be looking at
> the new FB from the current state instead?

Hm.. I just copied that code for skl, need to figure this out.

> 
> > @@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> >  		 * incur memory latencies higher than
> > sagv_block_time_us we
> >  		 * can't enable SAGV.
> >  		 */
> > -		if (latency < dev_priv->sagv_block_time_us)
> > +		if (latency < dev_priv->sagv_block_time_us) {
> > +			state->crtc_sagv_mask_set = true;
> > +			return;
> > +		}
> > +	}
> > +
> > +	state->crtc_sagv_mask |= BIT(crtc->pipe);
> > +	state->crtc_sagv_mask_set = true;
> > +}
> > +
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> > +
> > +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +	int level, latency;
> > +	int i;
> > +	int plane_id;
> > +
> > +	if (state->crtc_sagv_mask_set)
> > +		return;
> > +
> > +	if (!intel_has_sagv(dev_priv))
> > +		return;
> > +
> > +	/*
> > +	 * If there are no active CRTCs, no additional checks need be
> > performed
> > +	 */
> > +	if (hweight8(state->active_pipes) == 0)
> > +		return;
> > +
> > +	for_each_new_intel_crtc_in_state(state, crtc,
> > +					     new_crtc_state, i) {
> > +		unsigned int flags = crtc->base.state-
> > >adjusted_mode.flags;
> > +		bool can_sagv;
> > +
> > +		if (flags & DRM_MODE_FLAG_INTERLACE)
> > +			continue;
> > +
> > +		if (!new_crtc_state->hw.active)
> > +			continue;
> > +
> > +		can_sagv = true;
> > +		for_each_plane_id_on_crtc(crtc, plane_id) {
> > +			struct skl_plane_wm *wm =
> > +				&new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +
> > +			/* Skip this plane if it's not enabled */
> > +			if (!wm->wm[0].plane_en)
> > +				continue;
> > +
> > +			/* Find the highest enabled wm level for this
> > plane */
> > +			for (level = ilk_wm_max_level(dev_priv);
> > +			     !wm->wm[level].plane_en; --level) {
> > +			}
> > +
> > +			latency = dev_priv->wm.skl_latency[level];
> > +
> > +			/*
> > +			 * If any of the planes on this pipe don't
> > enable
> > +			 * wm levels that incur memory latencies higher
> > than
> > +			 * sagv_block_time_us we can't enable SAGV.
> > +			 */
> > +			if (latency < dev_priv->sagv_block_time_us) {
> > +				can_sagv = false;
> > +				break;
> > +			}
> 
> I still think this test is a bit problematic.  What if our memory
> latency is so low that we can successfully enable all watermark
> levels,
> and the latency for the highest watermark level is still less than
> ICL's
> 10us sagv block time?  We might be able to support SAGV just fine,
> but
> we're giving up without actually checking.
> 
> Or another case:  say our highest enabled watermark level is 3 with a
> latency of 8us.  The next level up, 4, has a latency of 30us which is
> high enough that our driver had to disable level 4.  We still don't
> know
> whether the plane could have tolerated the latency of 10us (and
> there's
> a good chance we could have...level 4 in this example was only
> impossible because it was such a big latency jump over level 3).
> 
> BTW, as I mentioned before, I'm still a bit uncomfortable with the
> bspec
> wording here; I'm going to open a bspec defect to find out for sure
> how
> we should interpret the directions on gen11.

I agree this seems weird. Lets clarify this first and get fixed in
BSpec.

> 
> > +		}
> > +		if (can_sagv)
> > +			state->crtc_sagv_mask |= BIT(crtc->pipe);
> > +		else
> > +			state->crtc_sagv_mask &= ~BIT(crtc->pipe);
> > +	}
> > +	state->crtc_sagv_mask_set = true;
> > +}
> > +
> > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int ret, i;
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +
> > +	/*
> > +	 * Make sure we always pick global state first,
> > +	 * there shouldn't be any issue as we hold only locks
> > +	 * to correspondent crtcs in state, however once
> > +	 * we detect that we need to change SAGV mask
> > +	 * in global state, we will grab all the crtc locks
> > +	 * in order to get this serialized, thus other
> > +	 * racing commits having other crtc locks, will have
> > +	 * to start over again, as stated by Wound-Wait
> > +	 * algorithm.
> > +	 */
> > +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;

probably we need to figure out solution here.

> > +
> > +	if (INTEL_GEN(dev_priv) >= 12)
> > +		tgl_set_sagv_mask(state);
> > +	else if (INTEL_GEN(dev_priv) == 11)
> > +		icl_set_sagv_mask(state);
> > +	else
> > +		skl_set_sagv_mask(state);
> > +
> > +	/*
> > +	 * For SAGV we need to account all the pipes,
> > +	 * not only the ones which are in state currently.
> > +	 * Grab all locks if we detect that we are actually
> > +	 * going to do something.
> > +	 */
> > +	if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) {
> > +		ret = intel_atomic_serialize_global_state(state);
> > +		if (ret) {
> > +			DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > +			return false;
> > +		}
> > +	}
> > +
> > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> > i) {
> > +		u32 mask = BIT(crtc->pipe);
> > +		bool state_sagv_masked = (mask & state->crtc_sagv_mask) 
> > == 0;
> > +
> > +		if (!new_crtc_state->hw.active)
> > +			continue;
> > +
> > +		if (state_sagv_masked)
> >  			return false;
> >  	}
> >  
> > @@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> >  				 int color_plane);
> >  static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> >  				 int level,
> > +				 u32 latency,
> >  				 const struct skl_wm_params *wp,
> >  				 const struct skl_wm_level
> > *result_prev,
> >  				 struct skl_wm_level *result /* out
> > */);
> > @@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct
> > intel_crtc_state *crtc_state,
> >  	WARN_ON(ret);
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > -		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> > +		u32 latency = dev_priv->wm.skl_latency[level];
> > +
> > +		skl_compute_plane_wm(crtc_state, level, latency, &wp,
> > &wm, &wm);
> > +
> >  		if (wm.min_ddb_alloc == U16_MAX)
> >  			break;
> >  
> > @@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> >  	return total_data_rate;
> >  }
> >  
> > +static int
> > +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> > +			    struct skl_ddb_allocation *ddb /* out */)
> > +{
> > +	struct drm_crtc *crtc = crtc_state->uapi.crtc;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > +	u16 alloc_size;
> > +	u16 total[I915_MAX_PLANES] = {};
> > +	u64 total_data_rate;
> > +	enum plane_id plane_id;
> > +	int num_active;
> > +	u64 plane_data_rate[I915_MAX_PLANES] = {};
> > +	u32 blocks;
> > +
> > +	/*
> > +	 * No need to check gen here, we call this only for gen12
> > +	 */
> > +	total_data_rate =
> > +		icl_get_total_relative_data_rate(crtc_state,
> > +						 plane_data_rate);
> > +
> > +	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> > +					   total_data_rate,
> > +					   ddb, alloc, &num_active);
> > +	alloc_size = skl_ddb_entry_size(alloc);
> > +	if (alloc_size == 0)
> > +		return -ENOSPC;
> > +
> > +	/* Allocate fixed number of blocks for cursor. */
> > +	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state,
> > num_active);
> > +	alloc_size -= total[PLANE_CURSOR];
> > +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> > +		alloc->end - total[PLANE_CURSOR];
> > +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> 
> All the above is basically a duplication of the pipe's DDB allocation
> we
> have to figure out again later.  Basically our driver used to follow
> a
> sequence of:
> 
>         * Calculate DDB (proportional algorithm)
>         * Calculate watermarks
> 
> and then we switched it to:
> 
>         * Calculate watermarks
>         * Calculate DDB (need-based algorithm)
> 
> If I recall correctly, the need-based DDB algorithm only really needs
> the watermark values to divy up the intra-pipe plane DDB allocations
> so
> we could still calculate the overall pipe allocations earlier if we
> wanted to.  Doing so would allow you to avoid this duplication of
> logic:
> 
>         * Calculate pipe-level DDB allocations
>         * Calculate watermarks
>         * Calculate plane-level DDB (need-based algorithm)

Yep, I had to take part of the ddb allocation code as we need to
figure out if we are actually fitting the SAGV watermarks(which are
higher) succesfully. And we need to do that before we actually do 
a real DBuf allocation.
Pipe level allocation simply gives each pipe a ddb entries in
proportion to pipe width, currently this is called simultaneously
when we are checking if plane ddb blocks are not exceeding the
alloc_size per pipe.

However for SAGV we need to know already which watermarks are we
fitting, because if SAGV watermarks are not fitting we have to
roll back and do everything from the begining.


> 
> > +
> > +	/*
> > +	 * Do check if we can fit L0 + sagv_block_time and
> > +	 * disable SAGV if we can't.
> > +	 */
> > +	blocks = 0;
> > +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +		const struct skl_plane_wm *wm =
> > +			&crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > +		if (plane_id == PLANE_CURSOR) {
> > +			if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> > +				    total[PLANE_CURSOR])) {
> > +				blocks = U32_MAX;
> > +				break;
> > +			}
> > +			continue;
> > +		}
> > +
> > +		blocks += wm->sagv_wm0.min_ddb_alloc;
> > +		if (blocks > alloc_size)
> > +			return -ENOSPC;
> > +	}
> > +	return 0;
> > +}
> > +
> > +const struct skl_wm_level *
> > +skl_plane_wm_level(struct intel_plane *plane,
> > +		const struct intel_crtc_state *crtc_state,
> > +		int level,
> > +		bool yuv)
> > +{
> > +	struct drm_atomic_state *state = crtc_state->uapi.state;
> > +	enum plane_id plane_id = plane->id;
> > +	const struct skl_plane_wm *wm =
> > +		&crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > +	/*
> > +	 * Looks ridicilous but need to check if state is not
> > +	 * NULL here as it might be as some cursor plane manipulations
> > +	 * seem to happen when no atomic state is actually present,
> > +	 * despite crtc_state is allocated. Removing state check
> > +	 * from here will result in kernel panic on boot.
> > +	 * However we now need to check whether should be use SAGV
> > +	 * wm levels here.
> > +	 */
> > +	if (state) {
> > +		struct intel_atomic_state *intel_state =
> > +			to_intel_atomic_state(state);
> > +		if (intel_can_enable_sagv(intel_state) && !level)
> 
> I think we should calculate the 'can enable SAGV' value once and
> cache
> it into a field of the state structure so that you don't have to keep
> re-calling this on every single plane/level combination.  Also you
> can
> then use the proper setting to figure out how to verify the hardware
> readout value as noted earlier. 
> 
> Also one thing I don't see (maybe I'm just overlooking it) is that we
> may also need to adjust higher watermark levels upward too:
> 
>         "The latency input to the watermark calculation for each
> level
>         must be greater than or equal to the lower level. The latency
>         increase to level 0 for SAGV requires the upper levels to be
>         adjusted to meet that requirement. Use MIN(latency for this
>         level, latency for next lower level) to correct the latency."
> 
> Basically it seems like we should just calculate two full sets of
> watermark values for all levels and then choose between them at the
> end?
> 

Exactly which again means that we need some function to check first
which set we should use(which is basically dictated if we can fit that
into DDB or not).

Stan

> 
> Matt
> 
> > +			return &wm->sagv_wm0;
> > +	}
> > +
> > +	return yuv ? &wm->uv_wm[level] : &wm->wm[level];
> > +}
> > +
> >  static int
> >  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> >  		      struct skl_ddb_allocation *ddb /* out */)
> > @@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  	u16 uv_total[I915_MAX_PLANES] = {};
> >  	u64 total_data_rate;
> >  	enum plane_id plane_id;
> > +	struct intel_plane *plane;
> > +	const struct skl_wm_level *wm_level;
> > +	const struct skl_wm_level *wm_uv_level;
> >  	int num_active;
> >  	u64 plane_data_rate[I915_MAX_PLANES] = {};
> >  	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> > @@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  	 */
> >  	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> >  		blocks = 0;
> > -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > -			const struct skl_plane_wm *wm =
> > -				&crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm,
> > intel_crtc, plane) {
> > +			plane_id = plane->id;
> > +			wm_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +						      level, false);
> > +			wm_uv_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +							 level, true);
> >  
> >  			if (plane_id == PLANE_CURSOR) {
> > -				if (WARN_ON(wm->wm[level].min_ddb_alloc 
> > >
> > +				if (WARN_ON(wm_level->min_ddb_alloc >
> >  					    total[PLANE_CURSOR])) {
> >  					blocks = U32_MAX;
> >  					break;
> > @@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  				continue;
> >  			}
> >  
> > -			blocks += wm->wm[level].min_ddb_alloc;
> > -			blocks += wm->uv_wm[level].min_ddb_alloc;
> > +			blocks += wm_level->min_ddb_alloc;
> > +			blocks += wm_uv_level->min_ddb_alloc;
> >  		}
> >  
> >  		if (blocks <= alloc_size) {
> > @@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  	 * watermark level, plus an extra share of the leftover blocks
> >  	 * proportional to its relative data rate.
> >  	 */
> > -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > -		const struct skl_plane_wm *wm =
> > -			&crtc_state->wm.skl.optimal.planes[plane_id];
> > +	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane)
> > {
> >  		u64 rate;
> >  		u16 extra;
> >  
> > +		plane_id = plane->id;
> > +		wm_level = skl_plane_wm_level(plane, crtc_state,
> > +					      level, false);
> > +		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> > +						 level, true);
> > +
> >  		if (plane_id == PLANE_CURSOR)
> >  			continue;
> >  
> > @@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  		extra = min_t(u16, alloc_size,
> >  			      DIV64_U64_ROUND_UP(alloc_size * rate,
> >  						 total_data_rate));
> > -		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> > +		total[plane_id] = wm_level->min_ddb_alloc + extra;
> >  		alloc_size -= extra;
> >  		total_data_rate -= rate;
> >  
> > @@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  		extra = min_t(u16, alloc_size,
> >  			      DIV64_U64_ROUND_UP(alloc_size * rate,
> >  						 total_data_rate));
> > -		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc +
> > extra;
> > +		uv_total[plane_id] = wm_uv_level->min_ddb_alloc +
> > extra;
> >  		alloc_size -= extra;
> >  		total_data_rate -= rate;
> >  	}
> > @@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  	 * that aren't actually possible.
> >  	 */
> >  	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> > -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm,
> > intel_crtc, plane) {
> >  			struct skl_plane_wm *wm =
> > -				&crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +				&crtc_state-
> > >wm.skl.optimal.planes[plane->id];
> > +
> > +			wm_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +						      level, false);
> > +			wm_uv_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +						      level, true);
> >  
> >  			/*
> >  			 * We only disable the watermarks for each
> > plane if
> > @@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  			 *  planes must be enabled before the level
> > will be used."
> >  			 * So this is actually safe to do.
> >  			 */
> > -			if (wm->wm[level].min_ddb_alloc >
> > total[plane_id] ||
> > -			    wm->uv_wm[level].min_ddb_alloc >
> > uv_total[plane_id])
> > -				memset(&wm->wm[level], 0, sizeof(wm-
> > >wm[level]));
> > +			if (wm_level->min_ddb_alloc > total[plane->id]
> > ||
> > +			    wm_uv_level->min_ddb_alloc >
> > uv_total[plane->id])
> > +				memset(&wm->wm[level], 0,
> > +				       sizeof(struct skl_wm_level));
> >  
> >  			/*
> >  			 * Wa_1408961008:icl, ehl
> > @@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  			 */
> >  			if (IS_GEN(dev_priv, 11) &&
> >  			    level == 1 && wm->wm[0].plane_en) {
> > -				wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > -				wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l;
> > -				wm->wm[level].ignore_lines = wm-
> > >wm[0].ignore_lines;
> > +				wm_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +							      0,
> > false);
> > +				wm->wm[level].plane_res_b =
> > +					wm_level->plane_res_b;
> > +				wm->wm[level].plane_res_l =
> > +					wm_level->plane_res_l;
> > +				wm->wm[level].ignore_lines =
> > +					wm_level->ignore_lines;
> >  			}
> >  		}
> >  	}
> > @@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct
> > drm_i915_private *dev_priv, int level)
> >  
> >  static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> >  				 int level,
> > +				 u32 latency,
> >  				 const struct skl_wm_params *wp,
> >  				 const struct skl_wm_level
> > *result_prev,
> >  				 struct skl_wm_level *result /* out */)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > -	u32 latency = dev_priv->wm.skl_latency[level];
> >  	uint_fixed_16_16_t method1, method2;
> >  	uint_fixed_16_16_t selected_result;
> >  	u32 res_blocks, res_lines, min_ddb_alloc = 0;
> > @@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const
> > struct intel_crtc_state *crtc_state,
> >  static void
> >  skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> >  		      const struct skl_wm_params *wm_params,
> > -		      struct skl_wm_level *levels)
> > +		      struct skl_plane_wm *plane_wm,
> > +		      bool yuv)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> >  	int level, max_level = ilk_wm_max_level(dev_priv);
> > +	/*
> > +	 * Check which kind of plane is it and based on that calculate
> > +	 * correspondent WM levels.
> > +	 */
> > +	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm-
> > >wm;
> >  	struct skl_wm_level *result_prev = &levels[0];
> >  
> >  	for (level = 0; level <= max_level; level++) {
> >  		struct skl_wm_level *result = &levels[level];
> > +		u32 latency = dev_priv->wm.skl_latency[level];
> >  
> > -		skl_compute_plane_wm(crtc_state, level, wm_params,
> > -				     result_prev, result);
> > +		skl_compute_plane_wm(crtc_state, level, latency,
> > +				     wm_params, result_prev, result);
> >  
> >  		result_prev = result;
> >  	}
> > +	/*
> > +	 * For Gen12 if it is an L0 we need to also
> > +	 * consider sagv_block_time when calculating
> > +	 * L0 watermark - we will need that when making
> > +	 * a decision whether enable SAGV or not.
> > +	 * For older gens we agreed to copy L0 value for
> > +	 * compatibility.
> > +	 */
> > +	if ((INTEL_GEN(dev_priv) >= 12)) {
> > +		u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > +		latency += dev_priv->sagv_block_time_us;
> > +		skl_compute_plane_wm(crtc_state, 0, latency,
> > +		     wm_params, &levels[0],
> > +		    &plane_wm->sagv_wm0);
> > +	} else
> > +		memcpy(&plane_wm->sagv_wm0, &levels[0],
> > +			sizeof(struct skl_wm_level));
> >  }
> >  
> >  static u32
> > @@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct
> > intel_crtc_state *crtc_state,
> >  	if (ret)
> >  		return ret;
> >  
> > -	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > +	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> >  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >  
> >  	return 0;
> > @@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct
> > intel_crtc_state *crtc_state,
> >  	if (ret)
> >  		return ret;
> >  
> > -	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > +	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
> >  
> >  	return 0;
> >  }
> > @@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane
> > *plane,
> >  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> >  	const struct skl_ddb_entry *ddb_uv =
> >  		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> > +	const struct skl_wm_level *wm_level;
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > +		wm_level = skl_plane_wm_level(plane, crtc_state, level,
> > false);
> > +
> >  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id,
> > level),
> > -				   &wm->wm[level]);
> > +				   wm_level);
> >  	}
> >  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> >  			   &wm->trans_wm);
> > @@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane
> > *plane,
> >  		&crtc_state->wm.skl.optimal.planes[plane_id];
> >  	const struct skl_ddb_entry *ddb =
> >  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +	const struct skl_wm_level *wm_level;
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > +		wm_level = skl_plane_wm_level(plane, crtc_state, level,
> > false);
> > +
> >  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> > -				   &wm->wm[level]);
> > +				   wm_level);
> >  	}
> >  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm-
> > >trans_wm);
> >  
> > @@ -5451,18 +5729,73 @@ static int
> > skl_wm_add_affected_planes(struct intel_atomic_state *state,
> >  	return 0;
> >  }
> >  
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +	struct intel_crtc_state *old_crtc_state;
> > +	struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> > +	int ret;
> > +	int i;
> > +	struct intel_plane *plane;
> > +
> > +	if (state->crtc_sagv_mask_set)
> > +		return;
> > +
> > +	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > +					    new_crtc_state, i) {
> > +		int pipe_bit = BIT(crtc->pipe);
> > +		bool skip = true;
> > +
> > +		/*
> > +		 * If we had set this mast already once for this state,
> > +		 * no need to waste CPU cycles for doing this again.
> > +		 */
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc,
> > plane) {
> > +			enum plane_id plane_id = plane->id;
> > +
> > +			if (!skl_plane_wm_equals(dev_priv,
> > +				&old_crtc_state-
> > >wm.skl.optimal.planes[plane_id],
> > +				&new_crtc_state-
> > >wm.skl.optimal.planes[plane_id])) {
> > +				skip = false;
> > +				break;
> > +			}
> > +		}
> > +
> > +		/*
> > +		 * Check if wm levels are actually the same as for
> > previous
> > +		 * state, which means we can just skip doing this long
> > check
> > +		 * and just  copy correspondent bit from previous
> > state.
> > +		 */
> > +		if (skip)
> > +			continue;
> > +
> > +		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > +		if (!ret)
> > +			state->crtc_sagv_mask |= pipe_bit;
> > +		else
> > +			state->crtc_sagv_mask &= ~pipe_bit;
> > +	}
> > +	state->crtc_sagv_mask_set = true;
> > +}
> > +
> >  static int
> >  skl_compute_wm(struct intel_atomic_state *state)
> >  {
> >  	struct intel_crtc *crtc;
> >  	struct intel_crtc_state *new_crtc_state;
> >  	struct intel_crtc_state *old_crtc_state;
> > -	struct skl_ddb_values *results = &state->wm_results;
> >  	int ret, i;
> > +	struct skl_ddb_values *results = &state->wm_results;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >  
> >  	/* Clear all dirty flags */
> >  	results->dirty_pipes = 0;
> >  
> > +	/* If we exit before check is done */
> > +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
> > +
> >  	ret = skl_ddb_add_affected_pipes(state);
> >  	if (ret)
> >  		return ret;
> > @@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct
> > intel_crtc *crtc,
> >  				val = I915_READ(CUR_WM(pipe, level));
> >  
> >  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > +			if (level == 0)
> > +				memcpy(&wm->sagv_wm0, &wm->wm[level],
> > +					sizeof(struct skl_wm_level));
> >  		}
> >  
> >  		if (plane_id != PLANE_CURSOR)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h
> > index b579c724b915..53275860731a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc
> > *crtc,
> >  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> >  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> >  bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> >  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > -- 
> > 2.17.1
> > 
> 
> 
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^ permalink raw reply	[flat|nested] 23+ messages in thread
* Re: [Intel-gfx] [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv
@ 2019-11-20  9:58       ` Lisovskiy, Stanislav
  0 siblings, 0 replies; 23+ messages in thread
From: Lisovskiy, Stanislav @ 2019-11-20  9:58 UTC (permalink / raw)
  To: Roper, Matthew D; +Cc: intel-gfx

On Tue, 2019-11-19 at 15:13 -0800, Matt Roper wrote:
> On Fri, Nov 15, 2019 at 04:54:00PM +0200, Stanislav Lisovskiy wrote:
> > Currently intel_can_enable_sagv function contains
> > a mix of workarounds for different platforms
> > some of them are not valid for gens >= 11 already,
> > so lets split it into separate functions.
> > 
> > v2:
> >     - Rework watermark calculation algorithm to
> >       attempt to calculate Level 0 watermark
> >       with added sagv block time latency and
> >       check if it fits in DBuf in order to
> >       determine if SAGV can be enabled already
> >       at this stage, just as BSpec 49325 states.
> >       if that fails rollback to usual Level 0
> >       latency and disable SAGV.
> >     - Remove unneeded tabs(James Ausmus)
> > 
> > v3: Rebased the patch
> > 
> > v4: - Added back interlaced check for Gen12 and
> >       added separate function for TGL SAGV check
> >       (thanks to James Ausmus for spotting)
> >     - Removed unneeded gen check
> >     - Extracted Gen12 SAGV decision making code
> >       to a separate function from skl_compute_wm
> > 
> > v5: - Added SAGV global state to dev_priv, because
> >       we need to track all pipes, not only those
> >       in atomic state. Each pipe has now correspondent
> >       bit mask reflecting, whether it can tolerate
> >       SAGV or not(thanks to Ville Syrjala for suggestions).
> >     - Now using active flag instead of enable in crc
> >       usage check.
> > 
> > v6: - Fixed rebase conflicts
> > 
> > v7: - kms_cursor_legacy seems to get broken because of multiple
> > memcpy
> >       calls when copying level 0 water marks for enabled SAGV, to
> >       fix this now simply using that field right away, without
> > copying,
> >       for that introduced a new wm_level accessor which decides
> > which
> >       wm_level to return based on SAGV state.
> > 
> > v8: - Protect crtc_sagv_mask same way as we do for other global
> > state
> >       changes: i.e check if changes are needed, then grab all crtc
> > locks
> >       to serialize the changes.
> > 
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>


Hi Matt,

Thanks for really valid comments. I should mention that currently 
I'm mostly tried to figure out how to do it properly as current
way we serialize commits seems to be a bit problematic.

I.e when I detect that I need to change a mask which stores which
pipes tolerate SAGV, according to current Ville's paradigm I should
grab all the crtcs, that locking the global state that way and
serializing access, preventing contention which might occur if
different commits read global state and modify different crtcs
at the same time.
However in CI I get comlains then like:

 WARNING: CPU: 6 PID: 1084 at drivers/gpu/drm/drm_modeset_lock.c:228
drm_modeset_drop_locks+0x35/0x40
<4> [369.766202] Modules linked in: vgem snd_hda_codec_hdmi mei_hdcp
i915 x86_pkg_temp_thermal coretemp crct10dif_pclmul crc32_pclmul
ghash_clmulni_intel snd_hda_intel snd_intel_dspcfg cdc_ether usbnet
snd_hda_codec mii snd_hwdep snd_hda_core snd_pcm mei_me mei
prime_numbers
<4> [369.766225] RIP: 0010:drm_modeset_drop_locks+0x35/0x40
<4> [369.766265]  drm_mode_cursor_common+0xf3/0x230
<4> [369.766273]  ? drm_mode_setplane+0x190/0x190
<4> [369.766275]  drm_mode_cursor_ioctl+0x48/0x70
<4> [369.766280]  drm_ioctl_kernel+0xa7/0xf0
<4> [369.766283]  drm_ioctl+0x2e1/0x390
<4> [369.766287]  ? drm_mode_setplane+0x190/0x190

Which means that WARN happens when EDADLK(possible deadlock happens)

This most likely happens because for example if there are
two racing commits:

Commit 1            Commit 2          Global state in dev_priv:

locked crtc 0        locked crtc1        00 (SAGV is off for both)

reads global state
  as 00
                     reads global state
	                as 00
figures out
that SAGV is 
ok for pipe 0
tries lock the global
   state
(bails out as other
 crtc is locked,
according to WW mutex
algorithm commit starts 
from begining)
                          ...



Guess this happens for both one of those manages grab all the locks,
so basically current way serializing commits seems to be wrong
if there is a real intense contention. Or am I missing something here?


> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |  12 +-
> >  .../drm/i915/display/intel_display_types.h    |  15 +
> >  drivers/gpu/drm/i915/i915_drv.h               |   6 +
> >  drivers/gpu/drm/i915/intel_pm.c               | 418
> > ++++++++++++++++--
> >  drivers/gpu/drm/i915/intel_pm.h               |   1 +
> >  5 files changed, 409 insertions(+), 43 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index adf50c4b38ad..7f31e33d0b16 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -13401,7 +13401,10 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> >  		/* Watermarks */
> >  		for (level = 0; level <= max_level; level++) {
> >  			if (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> > -						&sw_plane_wm-
> > >wm[level]))
> > +						&sw_plane_wm-
> > >wm[level]) ||
> > +			   (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> 
> If we cache the result of 'can enable sagv' into the state structure
> (as
> I suggest farther down the patch) then we can just compare with the
> right value here rather than trying both.

Could be, however my concern was that hw state might not always match
our current state, however as we seem to do that check already after
we commit the values, probably yes we can optimize it that way.


> 
> > +						&sw_plane_wm->sagv_wm0) 
> > &&
> > +			   (level == 0)))
> >  				continue;
> >  
> >  			DRM_ERROR("mismatch in WM pipe %c plane %d
> > level %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> > @@ -13453,7 +13456,10 @@ static void verify_wm_state(struct
> > intel_crtc *crtc,
> >  		/* Watermarks */
> >  		for (level = 0; level <= max_level; level++) {
> >  			if (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> > -						&sw_plane_wm-
> > >wm[level]))
> > +						&sw_plane_wm-
> > >wm[level]) ||
> > +			   (skl_wm_level_equals(&hw_plane_wm-
> > >wm[level],
> > +						&sw_plane_wm->sagv_wm0) 
> > &&
> > +			   (level == 0)))
> >  				continue;
> >  
> >  			DRM_ERROR("mismatch in WM pipe %c cursor level
> > %d (expected e=%d b=%u l=%u, got e=%d b=%u l=%u)\n",
> > @@ -14863,6 +14869,8 @@ static void intel_atomic_commit_tail(struct
> > intel_atomic_state *state)
> >  							      new_crtc_
> > state);
> >  	}
> >  
> > +	dev_priv->crtc_sagv_mask = state->crtc_sagv_mask;
> > +
> >  	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state, new_crtc_state, i) {
> >  		intel_post_plane_update(old_crtc_state);
> >  
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> > b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 83ea04149b77..6a300cac883f 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -490,6 +490,20 @@ struct intel_atomic_state {
> >  	 */
> >  	u8 active_pipe_changes;
> >  
> > +	/*
> > +	 * Contains a mask which reflects whether correspondent pipe
> > +	 * can tolerate SAGV or not, so that we can make a decision
> > +	 * at atomic_commit_tail stage, whether we enable it or not
> > +	 * based on global state in dev_priv.
> > +	 */
> > +	u32 crtc_sagv_mask;
> 
> I feel like your code might flow a bit more naturally if this were
> inverted and used as a mask of CRTCs that currently prohibit SAGV?

I think it should be fine both ways.

> 
> > +
> > +	/*
> > +	 * Used to determine if the mask has been already calculated
> > +	 * for this state, to avoid unnecessary calculations.
> > +	 */
> > +	bool crtc_sagv_mask_set;
> 
> I think this field can go away too if we just call the function once
> and
> cache the result in the state field.


Yes I think it can be cached. Need again still to rule out possible
complications from simultaneous global state mask modification from
different commits with different crtcs, as in fact it is global state
which determines if SAGV can be enabled or not. As current state
only might contain some crtcs, but not all.

> 
> > +
> >  	u8 active_pipes;
> >  	/* minimum acceptable cdclk for each pipe */
> >  	int min_cdclk[I915_MAX_PIPES];
> > @@ -670,6 +684,7 @@ struct skl_plane_wm {
> >  	struct skl_wm_level wm[8];
> >  	struct skl_wm_level uv_wm[8];
> >  	struct skl_wm_level trans_wm;
> > +	struct skl_wm_level sagv_wm0;
> >  	bool is_planar;
> >  };
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h
> > index 1779f600fcfb..0ac9d7b006ca 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1171,6 +1171,12 @@ struct drm_i915_private {
> >  
> >  	u32 sagv_block_time_us;
> >  
> > +	/*
> > +	 * Contains a bit mask, whether correspondent
> > +	 * pipe allows SAGV or not.
> > +	 */
> > +	u32 crtc_sagv_mask;
> > +
> >  	struct {
> >  		/*
> >  		 * Raw watermark latency values:
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c
> > b/drivers/gpu/drm/i915/intel_pm.c
> > index 05ba9e1bd247..c914bd1862ba 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -3625,13 +3625,9 @@ static bool skl_needs_memory_bw_wa(struct
> > drm_i915_private *dev_priv)
> >  	return IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv);
> >  }
> >  
> > -static bool
> > +bool
> >  intel_has_sagv(struct drm_i915_private *dev_priv)
> >  {
> > -	/* HACK! */
> > -	if (IS_GEN(dev_priv, 12))
> > -		return false;
> > -
> 
> The SAGV work you're doing is pretty complicated and this general
> patch
> touches a lot of different platforms (SKL, ICL, TGL, etc.).  It would
> be
> great if we could break this up into a few patches, but if that's not
> easy, I'd suggest at least moving this specific change to a final
> patch
> all of its own so that we "flip the switch" on TGL independently of
> the
> general rework.  That way if we wind up with TGL regressions (but no
> problems on SKL/ICL) we can just revert a tiny 2-line patch rather
> than
> reverting _all_ of your work here.

Agree, the amount of issues which arise or might arise is skyrocketing.
Probably need to split it into smaller chunks, however still prefer
that some crucial related stuff is modified in the same patch,
otherwise this gets really hard to track.

> 
> >  	return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
> >  		dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
> >  }
> > @@ -3748,7 +3744,7 @@ intel_disable_sagv(struct drm_i915_private
> > *dev_priv)
> >  	return 0;
> >  }
> >  
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +static void skl_set_sagv_mask(struct intel_atomic_state *state)
> 
> Minor nitpick:  I know there's a lot of inconsistent terminology used
> throughout the driver, but I always expect functions with names like
> 'set,' 'update,' etc. to touch hardware somehow.  I prefer naming
> functions like this with verbs like 'compute' or 'calc' to make it a
> bit
> more clear (at least in my mind) that we're not doing anything here
> yet
> except analyzing the state.

Makes sense. Will rename it.

> 
> >  {
> >  	struct drm_device *dev = state->base.dev;
> >  	struct drm_i915_private *dev_priv = to_i915(dev);
> > @@ -3758,29 +3754,35 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> >  	enum pipe pipe;
> >  	int level, latency;
> >  
> > +	if (state->crtc_sagv_mask_set)
> > +		return;
> > +
> >  	if (!intel_has_sagv(dev_priv))
> > -		return false;
> > +		return;
> 
> It seems like this check should just be at the top of
> intel_can_enable_sagv() rather than duplicated in each platform's
> mask-calculating function?

Agree.

> 
> >  
> >  	/*
> >  	 * If there are no active CRTCs, no additional checks need be
> > performed
> >  	 */
> >  	if (hweight8(state->active_pipes) == 0)
> > -		return true;
> > +		return;
> 
> This also appears to be a platform-independent check that can move up
> to
> the intel_can_enable_sagv() level?  You don't have it in the TGL
> function right now, but it seems like it should apply there as well?

Agree.

> 
> >  
> >  	/*
> >  	 * SKL+ workaround: bspec recommends we disable SAGV when we
> > have
> >  	 * more then one pipe enabled
> >  	 */
> >  	if (hweight8(state->active_pipes) > 1)
> > -		return false;
> > +		return;
> >  
> >  	/* Since we're now guaranteed to only have one active CRTC...
> > */
> >  	pipe = ffs(state->active_pipes) - 1;
> >  	crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> >  	crtc_state = to_intel_crtc_state(crtc->base.state);
> > +	state->crtc_sagv_mask &= ~BIT(crtc->pipe);
> >  
> > -	if (crtc_state->hw.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE)
> > -		return false;
> > +	if (crtc_state->hw.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE) {
> > +		state->crtc_sagv_mask_set = true;
> > +		return;
> > +	}
> >  
> >  	for_each_intel_plane_on_crtc(dev, crtc, plane) {
> >  		struct skl_plane_wm *wm =
> 
> In the pre-existing code for this loop (that doesn't show up in the
> diff
> here) it looks like we're looking at the already-committed plane
> state
> to see if the old plane FB was x-tiled...should that be looking at
> the new FB from the current state instead?

Hm.. I just copied that code for skl, need to figure this out.

> 
> > @@ -3807,7 +3809,135 @@ bool intel_can_enable_sagv(struct
> > intel_atomic_state *state)
> >  		 * incur memory latencies higher than
> > sagv_block_time_us we
> >  		 * can't enable SAGV.
> >  		 */
> > -		if (latency < dev_priv->sagv_block_time_us)
> > +		if (latency < dev_priv->sagv_block_time_us) {
> > +			state->crtc_sagv_mask_set = true;
> > +			return;
> > +		}
> > +	}
> > +
> > +	state->crtc_sagv_mask |= BIT(crtc->pipe);
> > +	state->crtc_sagv_mask_set = true;
> > +}
> > +
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state);
> > +
> > +static void icl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +	int level, latency;
> > +	int i;
> > +	int plane_id;
> > +
> > +	if (state->crtc_sagv_mask_set)
> > +		return;
> > +
> > +	if (!intel_has_sagv(dev_priv))
> > +		return;
> > +
> > +	/*
> > +	 * If there are no active CRTCs, no additional checks need be
> > performed
> > +	 */
> > +	if (hweight8(state->active_pipes) == 0)
> > +		return;
> > +
> > +	for_each_new_intel_crtc_in_state(state, crtc,
> > +					     new_crtc_state, i) {
> > +		unsigned int flags = crtc->base.state-
> > >adjusted_mode.flags;
> > +		bool can_sagv;
> > +
> > +		if (flags & DRM_MODE_FLAG_INTERLACE)
> > +			continue;
> > +
> > +		if (!new_crtc_state->hw.active)
> > +			continue;
> > +
> > +		can_sagv = true;
> > +		for_each_plane_id_on_crtc(crtc, plane_id) {
> > +			struct skl_plane_wm *wm =
> > +				&new_crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +
> > +			/* Skip this plane if it's not enabled */
> > +			if (!wm->wm[0].plane_en)
> > +				continue;
> > +
> > +			/* Find the highest enabled wm level for this
> > plane */
> > +			for (level = ilk_wm_max_level(dev_priv);
> > +			     !wm->wm[level].plane_en; --level) {
> > +			}
> > +
> > +			latency = dev_priv->wm.skl_latency[level];
> > +
> > +			/*
> > +			 * If any of the planes on this pipe don't
> > enable
> > +			 * wm levels that incur memory latencies higher
> > than
> > +			 * sagv_block_time_us we can't enable SAGV.
> > +			 */
> > +			if (latency < dev_priv->sagv_block_time_us) {
> > +				can_sagv = false;
> > +				break;
> > +			}
> 
> I still think this test is a bit problematic.  What if our memory
> latency is so low that we can successfully enable all watermark
> levels,
> and the latency for the highest watermark level is still less than
> ICL's
> 10us sagv block time?  We might be able to support SAGV just fine,
> but
> we're giving up without actually checking.
> 
> Or another case:  say our highest enabled watermark level is 3 with a
> latency of 8us.  The next level up, 4, has a latency of 30us which is
> high enough that our driver had to disable level 4.  We still don't
> know
> whether the plane could have tolerated the latency of 10us (and
> there's
> a good chance we could have...level 4 in this example was only
> impossible because it was such a big latency jump over level 3).
> 
> BTW, as I mentioned before, I'm still a bit uncomfortable with the
> bspec
> wording here; I'm going to open a bspec defect to find out for sure
> how
> we should interpret the directions on gen11.

I agree this seems weird. Lets clarify this first and get fixed in
BSpec.

> 
> > +		}
> > +		if (can_sagv)
> > +			state->crtc_sagv_mask |= BIT(crtc->pipe);
> > +		else
> > +			state->crtc_sagv_mask &= ~BIT(crtc->pipe);
> > +	}
> > +	state->crtc_sagv_mask_set = true;
> > +}
> > +
> > +bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +{
> > +	struct drm_device *dev = state->base.dev;
> > +	struct drm_i915_private *dev_priv = to_i915(dev);
> > +	int ret, i;
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +
> > +	/*
> > +	 * Make sure we always pick global state first,
> > +	 * there shouldn't be any issue as we hold only locks
> > +	 * to correspondent crtcs in state, however once
> > +	 * we detect that we need to change SAGV mask
> > +	 * in global state, we will grab all the crtc locks
> > +	 * in order to get this serialized, thus other
> > +	 * racing commits having other crtc locks, will have
> > +	 * to start over again, as stated by Wound-Wait
> > +	 * algorithm.
> > +	 */
> > +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;

probably we need to figure out solution here.

> > +
> > +	if (INTEL_GEN(dev_priv) >= 12)
> > +		tgl_set_sagv_mask(state);
> > +	else if (INTEL_GEN(dev_priv) == 11)
> > +		icl_set_sagv_mask(state);
> > +	else
> > +		skl_set_sagv_mask(state);
> > +
> > +	/*
> > +	 * For SAGV we need to account all the pipes,
> > +	 * not only the ones which are in state currently.
> > +	 * Grab all locks if we detect that we are actually
> > +	 * going to do something.
> > +	 */
> > +	if (state->crtc_sagv_mask != dev_priv->crtc_sagv_mask) {
> > +		ret = intel_atomic_serialize_global_state(state);
> > +		if (ret) {
> > +			DRM_DEBUG_KMS("Could not serialize global
> > state\n");
> > +			return false;
> > +		}
> > +	}
> > +
> > +	for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state,
> > i) {
> > +		u32 mask = BIT(crtc->pipe);
> > +		bool state_sagv_masked = (mask & state->crtc_sagv_mask) 
> > == 0;
> > +
> > +		if (!new_crtc_state->hw.active)
> > +			continue;
> > +
> > +		if (state_sagv_masked)
> >  			return false;
> >  	}
> >  
> > @@ -3933,6 +4063,7 @@ static int skl_compute_wm_params(const struct
> > intel_crtc_state *crtc_state,
> >  				 int color_plane);
> >  static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> >  				 int level,
> > +				 u32 latency,
> >  				 const struct skl_wm_params *wp,
> >  				 const struct skl_wm_level
> > *result_prev,
> >  				 struct skl_wm_level *result /* out
> > */);
> > @@ -3955,7 +4086,10 @@ skl_cursor_allocation(const struct
> > intel_crtc_state *crtc_state,
> >  	WARN_ON(ret);
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > -		skl_compute_plane_wm(crtc_state, level, &wp, &wm, &wm);
> > +		u32 latency = dev_priv->wm.skl_latency[level];
> > +
> > +		skl_compute_plane_wm(crtc_state, level, latency, &wp,
> > &wm, &wm);
> > +
> >  		if (wm.min_ddb_alloc == U16_MAX)
> >  			break;
> >  
> > @@ -4220,6 +4354,98 @@ icl_get_total_relative_data_rate(struct
> > intel_crtc_state *crtc_state,
> >  	return total_data_rate;
> >  }
> >  
> > +static int
> > +tgl_check_pipe_fits_sagv_wm(struct intel_crtc_state *crtc_state,
> > +			    struct skl_ddb_allocation *ddb /* out */)
> > +{
> > +	struct drm_crtc *crtc = crtc_state->uapi.crtc;
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->dev);
> > +	struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
> > +	struct skl_ddb_entry *alloc = &crtc_state->wm.skl.ddb;
> > +	u16 alloc_size;
> > +	u16 total[I915_MAX_PLANES] = {};
> > +	u64 total_data_rate;
> > +	enum plane_id plane_id;
> > +	int num_active;
> > +	u64 plane_data_rate[I915_MAX_PLANES] = {};
> > +	u32 blocks;
> > +
> > +	/*
> > +	 * No need to check gen here, we call this only for gen12
> > +	 */
> > +	total_data_rate =
> > +		icl_get_total_relative_data_rate(crtc_state,
> > +						 plane_data_rate);
> > +
> > +	skl_ddb_get_pipe_allocation_limits(dev_priv, crtc_state,
> > +					   total_data_rate,
> > +					   ddb, alloc, &num_active);
> > +	alloc_size = skl_ddb_entry_size(alloc);
> > +	if (alloc_size == 0)
> > +		return -ENOSPC;
> > +
> > +	/* Allocate fixed number of blocks for cursor. */
> > +	total[PLANE_CURSOR] = skl_cursor_allocation(crtc_state,
> > num_active);
> > +	alloc_size -= total[PLANE_CURSOR];
> > +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].start =
> > +		alloc->end - total[PLANE_CURSOR];
> > +	crtc_state->wm.skl.plane_ddb_y[PLANE_CURSOR].end = alloc->end;
> 
> All the above is basically a duplication of the pipe's DDB allocation
> we
> have to figure out again later.  Basically our driver used to follow
> a
> sequence of:
> 
>         * Calculate DDB (proportional algorithm)
>         * Calculate watermarks
> 
> and then we switched it to:
> 
>         * Calculate watermarks
>         * Calculate DDB (need-based algorithm)
> 
> If I recall correctly, the need-based DDB algorithm only really needs
> the watermark values to divy up the intra-pipe plane DDB allocations
> so
> we could still calculate the overall pipe allocations earlier if we
> wanted to.  Doing so would allow you to avoid this duplication of
> logic:
> 
>         * Calculate pipe-level DDB allocations
>         * Calculate watermarks
>         * Calculate plane-level DDB (need-based algorithm)

Yep, I had to take part of the ddb allocation code as we need to
figure out if we are actually fitting the SAGV watermarks(which are
higher) succesfully. And we need to do that before we actually do 
a real DBuf allocation.
Pipe level allocation simply gives each pipe a ddb entries in
proportion to pipe width, currently this is called simultaneously
when we are checking if plane ddb blocks are not exceeding the
alloc_size per pipe.

However for SAGV we need to know already which watermarks are we
fitting, because if SAGV watermarks are not fitting we have to
roll back and do everything from the begining.


> 
> > +
> > +	/*
> > +	 * Do check if we can fit L0 + sagv_block_time and
> > +	 * disable SAGV if we can't.
> > +	 */
> > +	blocks = 0;
> > +	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +		const struct skl_plane_wm *wm =
> > +			&crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > +		if (plane_id == PLANE_CURSOR) {
> > +			if (WARN_ON(wm->sagv_wm0.min_ddb_alloc >
> > +				    total[PLANE_CURSOR])) {
> > +				blocks = U32_MAX;
> > +				break;
> > +			}
> > +			continue;
> > +		}
> > +
> > +		blocks += wm->sagv_wm0.min_ddb_alloc;
> > +		if (blocks > alloc_size)
> > +			return -ENOSPC;
> > +	}
> > +	return 0;
> > +}
> > +
> > +const struct skl_wm_level *
> > +skl_plane_wm_level(struct intel_plane *plane,
> > +		const struct intel_crtc_state *crtc_state,
> > +		int level,
> > +		bool yuv)
> > +{
> > +	struct drm_atomic_state *state = crtc_state->uapi.state;
> > +	enum plane_id plane_id = plane->id;
> > +	const struct skl_plane_wm *wm =
> > +		&crtc_state->wm.skl.optimal.planes[plane_id];
> > +
> > +	/*
> > +	 * Looks ridicilous but need to check if state is not
> > +	 * NULL here as it might be as some cursor plane manipulations
> > +	 * seem to happen when no atomic state is actually present,
> > +	 * despite crtc_state is allocated. Removing state check
> > +	 * from here will result in kernel panic on boot.
> > +	 * However we now need to check whether should be use SAGV
> > +	 * wm levels here.
> > +	 */
> > +	if (state) {
> > +		struct intel_atomic_state *intel_state =
> > +			to_intel_atomic_state(state);
> > +		if (intel_can_enable_sagv(intel_state) && !level)
> 
> I think we should calculate the 'can enable SAGV' value once and
> cache
> it into a field of the state structure so that you don't have to keep
> re-calling this on every single plane/level combination.  Also you
> can
> then use the proper setting to figure out how to verify the hardware
> readout value as noted earlier. 
> 
> Also one thing I don't see (maybe I'm just overlooking it) is that we
> may also need to adjust higher watermark levels upward too:
> 
>         "The latency input to the watermark calculation for each
> level
>         must be greater than or equal to the lower level. The latency
>         increase to level 0 for SAGV requires the upper levels to be
>         adjusted to meet that requirement. Use MIN(latency for this
>         level, latency for next lower level) to correct the latency."
> 
> Basically it seems like we should just calculate two full sets of
> watermark values for all levels and then choose between them at the
> end?
> 

Exactly which again means that we need some function to check first
which set we should use(which is basically dictated if we can fit that
into DDB or not).

Stan

> 
> Matt
> 
> > +			return &wm->sagv_wm0;
> > +	}
> > +
> > +	return yuv ? &wm->uv_wm[level] : &wm->wm[level];
> > +}
> > +
> >  static int
> >  skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
> >  		      struct skl_ddb_allocation *ddb /* out */)
> > @@ -4234,6 +4460,9 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  	u16 uv_total[I915_MAX_PLANES] = {};
> >  	u64 total_data_rate;
> >  	enum plane_id plane_id;
> > +	struct intel_plane *plane;
> > +	const struct skl_wm_level *wm_level;
> > +	const struct skl_wm_level *wm_uv_level;
> >  	int num_active;
> >  	u64 plane_data_rate[I915_MAX_PLANES] = {};
> >  	u64 uv_plane_data_rate[I915_MAX_PLANES] = {};
> > @@ -4285,12 +4514,15 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  	 */
> >  	for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
> >  		blocks = 0;
> > -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > -			const struct skl_plane_wm *wm =
> > -				&crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm,
> > intel_crtc, plane) {
> > +			plane_id = plane->id;
> > +			wm_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +						      level, false);
> > +			wm_uv_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +							 level, true);
> >  
> >  			if (plane_id == PLANE_CURSOR) {
> > -				if (WARN_ON(wm->wm[level].min_ddb_alloc 
> > >
> > +				if (WARN_ON(wm_level->min_ddb_alloc >
> >  					    total[PLANE_CURSOR])) {
> >  					blocks = U32_MAX;
> >  					break;
> > @@ -4298,8 +4530,8 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  				continue;
> >  			}
> >  
> > -			blocks += wm->wm[level].min_ddb_alloc;
> > -			blocks += wm->uv_wm[level].min_ddb_alloc;
> > +			blocks += wm_level->min_ddb_alloc;
> > +			blocks += wm_uv_level->min_ddb_alloc;
> >  		}
> >  
> >  		if (blocks <= alloc_size) {
> > @@ -4320,12 +4552,16 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  	 * watermark level, plus an extra share of the leftover blocks
> >  	 * proportional to its relative data rate.
> >  	 */
> > -	for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > -		const struct skl_plane_wm *wm =
> > -			&crtc_state->wm.skl.optimal.planes[plane_id];
> > +	for_each_intel_plane_on_crtc(&dev_priv->drm, intel_crtc, plane)
> > {
> >  		u64 rate;
> >  		u16 extra;
> >  
> > +		plane_id = plane->id;
> > +		wm_level = skl_plane_wm_level(plane, crtc_state,
> > +					      level, false);
> > +		wm_uv_level = skl_plane_wm_level(plane, crtc_state,
> > +						 level, true);
> > +
> >  		if (plane_id == PLANE_CURSOR)
> >  			continue;
> >  
> > @@ -4340,7 +4576,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  		extra = min_t(u16, alloc_size,
> >  			      DIV64_U64_ROUND_UP(alloc_size * rate,
> >  						 total_data_rate));
> > -		total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
> > +		total[plane_id] = wm_level->min_ddb_alloc + extra;
> >  		alloc_size -= extra;
> >  		total_data_rate -= rate;
> >  
> > @@ -4351,7 +4587,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state
> > *crtc_state,
> >  		extra = min_t(u16, alloc_size,
> >  			      DIV64_U64_ROUND_UP(alloc_size * rate,
> >  						 total_data_rate));
> > -		uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc +
> > extra;
> > +		uv_total[plane_id] = wm_uv_level->min_ddb_alloc +
> > extra;
> >  		alloc_size -= extra;
> >  		total_data_rate -= rate;
> >  	}
> > @@ -4392,9 +4628,14 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  	 * that aren't actually possible.
> >  	 */
> >  	for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
> > -		for_each_plane_id_on_crtc(intel_crtc, plane_id) {
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm,
> > intel_crtc, plane) {
> >  			struct skl_plane_wm *wm =
> > -				&crtc_state-
> > >wm.skl.optimal.planes[plane_id];
> > +				&crtc_state-
> > >wm.skl.optimal.planes[plane->id];
> > +
> > +			wm_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +						      level, false);
> > +			wm_uv_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +						      level, true);
> >  
> >  			/*
> >  			 * We only disable the watermarks for each
> > plane if
> > @@ -4408,9 +4649,10 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  			 *  planes must be enabled before the level
> > will be used."
> >  			 * So this is actually safe to do.
> >  			 */
> > -			if (wm->wm[level].min_ddb_alloc >
> > total[plane_id] ||
> > -			    wm->uv_wm[level].min_ddb_alloc >
> > uv_total[plane_id])
> > -				memset(&wm->wm[level], 0, sizeof(wm-
> > >wm[level]));
> > +			if (wm_level->min_ddb_alloc > total[plane->id]
> > ||
> > +			    wm_uv_level->min_ddb_alloc >
> > uv_total[plane->id])
> > +				memset(&wm->wm[level], 0,
> > +				       sizeof(struct skl_wm_level));
> >  
> >  			/*
> >  			 * Wa_1408961008:icl, ehl
> > @@ -4418,9 +4660,14 @@ skl_allocate_pipe_ddb(struct
> > intel_crtc_state *crtc_state,
> >  			 */
> >  			if (IS_GEN(dev_priv, 11) &&
> >  			    level == 1 && wm->wm[0].plane_en) {
> > -				wm->wm[level].plane_res_b = wm-
> > >wm[0].plane_res_b;
> > -				wm->wm[level].plane_res_l = wm-
> > >wm[0].plane_res_l;
> > -				wm->wm[level].ignore_lines = wm-
> > >wm[0].ignore_lines;
> > +				wm_level = skl_plane_wm_level(plane,
> > crtc_state,
> > +							      0,
> > false);
> > +				wm->wm[level].plane_res_b =
> > +					wm_level->plane_res_b;
> > +				wm->wm[level].plane_res_l =
> > +					wm_level->plane_res_l;
> > +				wm->wm[level].ignore_lines =
> > +					wm_level->ignore_lines;
> >  			}
> >  		}
> >  	}
> > @@ -4649,12 +4896,12 @@ static bool skl_wm_has_lines(struct
> > drm_i915_private *dev_priv, int level)
> >  
> >  static void skl_compute_plane_wm(const struct intel_crtc_state
> > *crtc_state,
> >  				 int level,
> > +				 u32 latency,
> >  				 const struct skl_wm_params *wp,
> >  				 const struct skl_wm_level
> > *result_prev,
> >  				 struct skl_wm_level *result /* out */)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> > -	u32 latency = dev_priv->wm.skl_latency[level];
> >  	uint_fixed_16_16_t method1, method2;
> >  	uint_fixed_16_16_t selected_result;
> >  	u32 res_blocks, res_lines, min_ddb_alloc = 0;
> > @@ -4775,20 +5022,45 @@ static void skl_compute_plane_wm(const
> > struct intel_crtc_state *crtc_state,
> >  static void
> >  skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
> >  		      const struct skl_wm_params *wm_params,
> > -		      struct skl_wm_level *levels)
> > +		      struct skl_plane_wm *plane_wm,
> > +		      bool yuv)
> >  {
> >  	struct drm_i915_private *dev_priv = to_i915(crtc_state-
> > >uapi.crtc->dev);
> >  	int level, max_level = ilk_wm_max_level(dev_priv);
> > +	/*
> > +	 * Check which kind of plane is it and based on that calculate
> > +	 * correspondent WM levels.
> > +	 */
> > +	struct skl_wm_level *levels = yuv ? plane_wm->uv_wm : plane_wm-
> > >wm;
> >  	struct skl_wm_level *result_prev = &levels[0];
> >  
> >  	for (level = 0; level <= max_level; level++) {
> >  		struct skl_wm_level *result = &levels[level];
> > +		u32 latency = dev_priv->wm.skl_latency[level];
> >  
> > -		skl_compute_plane_wm(crtc_state, level, wm_params,
> > -				     result_prev, result);
> > +		skl_compute_plane_wm(crtc_state, level, latency,
> > +				     wm_params, result_prev, result);
> >  
> >  		result_prev = result;
> >  	}
> > +	/*
> > +	 * For Gen12 if it is an L0 we need to also
> > +	 * consider sagv_block_time when calculating
> > +	 * L0 watermark - we will need that when making
> > +	 * a decision whether enable SAGV or not.
> > +	 * For older gens we agreed to copy L0 value for
> > +	 * compatibility.
> > +	 */
> > +	if ((INTEL_GEN(dev_priv) >= 12)) {
> > +		u32 latency = dev_priv->wm.skl_latency[0];
> > +
> > +		latency += dev_priv->sagv_block_time_us;
> > +		skl_compute_plane_wm(crtc_state, 0, latency,
> > +		     wm_params, &levels[0],
> > +		    &plane_wm->sagv_wm0);
> > +	} else
> > +		memcpy(&plane_wm->sagv_wm0, &levels[0],
> > +			sizeof(struct skl_wm_level));
> >  }
> >  
> >  static u32
> > @@ -4881,7 +5153,7 @@ static int skl_build_plane_wm_single(struct
> > intel_crtc_state *crtc_state,
> >  	if (ret)
> >  		return ret;
> >  
> > -	skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
> > +	skl_compute_wm_levels(crtc_state, &wm_params, wm, false);
> >  	skl_compute_transition_wm(crtc_state, &wm_params, wm);
> >  
> >  	return 0;
> > @@ -4903,7 +5175,7 @@ static int skl_build_plane_wm_uv(struct
> > intel_crtc_state *crtc_state,
> >  	if (ret)
> >  		return ret;
> >  
> > -	skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
> > +	skl_compute_wm_levels(crtc_state, &wm_params, wm, true);
> >  
> >  	return 0;
> >  }
> > @@ -5040,10 +5312,13 @@ void skl_write_plane_wm(struct intel_plane
> > *plane,
> >  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> >  	const struct skl_ddb_entry *ddb_uv =
> >  		&crtc_state->wm.skl.plane_ddb_uv[plane_id];
> > +	const struct skl_wm_level *wm_level;
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > +		wm_level = skl_plane_wm_level(plane, crtc_state, level,
> > false);
> > +
> >  		skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id,
> > level),
> > -				   &wm->wm[level]);
> > +				   wm_level);
> >  	}
> >  	skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
> >  			   &wm->trans_wm);
> > @@ -5074,10 +5349,13 @@ void skl_write_cursor_wm(struct intel_plane
> > *plane,
> >  		&crtc_state->wm.skl.optimal.planes[plane_id];
> >  	const struct skl_ddb_entry *ddb =
> >  		&crtc_state->wm.skl.plane_ddb_y[plane_id];
> > +	const struct skl_wm_level *wm_level;
> >  
> >  	for (level = 0; level <= max_level; level++) {
> > +		wm_level = skl_plane_wm_level(plane, crtc_state, level,
> > false);
> > +
> >  		skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
> > -				   &wm->wm[level]);
> > +				   wm_level);
> >  	}
> >  	skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm-
> > >trans_wm);
> >  
> > @@ -5451,18 +5729,73 @@ static int
> > skl_wm_add_affected_planes(struct intel_atomic_state *state,
> >  	return 0;
> >  }
> >  
> > +static void tgl_set_sagv_mask(struct intel_atomic_state *state)
> > +{
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > +	struct intel_crtc *crtc;
> > +	struct intel_crtc_state *new_crtc_state;
> > +	struct intel_crtc_state *old_crtc_state;
> > +	struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
> > +	int ret;
> > +	int i;
> > +	struct intel_plane *plane;
> > +
> > +	if (state->crtc_sagv_mask_set)
> > +		return;
> > +
> > +	for_each_oldnew_intel_crtc_in_state(state, crtc,
> > old_crtc_state,
> > +					    new_crtc_state, i) {
> > +		int pipe_bit = BIT(crtc->pipe);
> > +		bool skip = true;
> > +
> > +		/*
> > +		 * If we had set this mast already once for this state,
> > +		 * no need to waste CPU cycles for doing this again.
> > +		 */
> > +		for_each_intel_plane_on_crtc(&dev_priv->drm, crtc,
> > plane) {
> > +			enum plane_id plane_id = plane->id;
> > +
> > +			if (!skl_plane_wm_equals(dev_priv,
> > +				&old_crtc_state-
> > >wm.skl.optimal.planes[plane_id],
> > +				&new_crtc_state-
> > >wm.skl.optimal.planes[plane_id])) {
> > +				skip = false;
> > +				break;
> > +			}
> > +		}
> > +
> > +		/*
> > +		 * Check if wm levels are actually the same as for
> > previous
> > +		 * state, which means we can just skip doing this long
> > check
> > +		 * and just  copy correspondent bit from previous
> > state.
> > +		 */
> > +		if (skip)
> > +			continue;
> > +
> > +		ret = tgl_check_pipe_fits_sagv_wm(new_crtc_state, ddb);
> > +		if (!ret)
> > +			state->crtc_sagv_mask |= pipe_bit;
> > +		else
> > +			state->crtc_sagv_mask &= ~pipe_bit;
> > +	}
> > +	state->crtc_sagv_mask_set = true;
> > +}
> > +
> >  static int
> >  skl_compute_wm(struct intel_atomic_state *state)
> >  {
> >  	struct intel_crtc *crtc;
> >  	struct intel_crtc_state *new_crtc_state;
> >  	struct intel_crtc_state *old_crtc_state;
> > -	struct skl_ddb_values *results = &state->wm_results;
> >  	int ret, i;
> > +	struct skl_ddb_values *results = &state->wm_results;
> > +	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> >  
> >  	/* Clear all dirty flags */
> >  	results->dirty_pipes = 0;
> >  
> > +	/* If we exit before check is done */
> > +	state->crtc_sagv_mask = dev_priv->crtc_sagv_mask;
> > +
> >  	ret = skl_ddb_add_affected_pipes(state);
> >  	if (ret)
> >  		return ret;
> > @@ -5638,6 +5971,9 @@ void skl_pipe_wm_get_hw_state(struct
> > intel_crtc *crtc,
> >  				val = I915_READ(CUR_WM(pipe, level));
> >  
> >  			skl_wm_level_from_reg_val(val, &wm->wm[level]);
> > +			if (level == 0)
> > +				memcpy(&wm->sagv_wm0, &wm->wm[level],
> > +					sizeof(struct skl_wm_level));
> >  		}
> >  
> >  		if (plane_id != PLANE_CURSOR)
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h
> > b/drivers/gpu/drm/i915/intel_pm.h
> > index b579c724b915..53275860731a 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -43,6 +43,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc
> > *crtc,
> >  void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> >  void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> >  bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_has_sagv(struct drm_i915_private *dev_priv);
> >  int intel_enable_sagv(struct drm_i915_private *dev_priv);
> >  int intel_disable_sagv(struct drm_i915_private *dev_priv);
> >  bool skl_wm_level_equals(const struct skl_wm_level *l1,
> > -- 
> > 2.17.1
> > 
> 
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor Gen11+ SAGV support (rev12)
  2019-11-15 14:53 ` [Intel-gfx] " Stanislav Lisovskiy
                   ` (6 preceding siblings ...)
  (?)
@ 2019-12-03 16:15 ` Patchwork
  -1 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-12-03 16:15 UTC (permalink / raw)
  To: Lisovskiy, Stanislav; +Cc: intel-gfx

== Series Details ==

Series: Refactor Gen11+ SAGV support (rev12)
URL   : https://patchwork.freedesktop.org/series/68028/
State : failure

== Summary ==

Applying: drm/i915: Refactor intel_can_enable_sagv
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_display.c
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/intel_pm.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/intel_pm.c
Auto-merging drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
Applying: drm/i915: Restrict qgv points which don't have enough bandwidth.
Using index info to reconstruct a base tree...
M	drivers/gpu/drm/i915/display/intel_bw.c
M	drivers/gpu/drm/i915/display/intel_display.c
M	drivers/gpu/drm/i915/i915_drv.h
M	drivers/gpu/drm/i915/i915_reg.h
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/i915_reg.h
Auto-merging drivers/gpu/drm/i915/i915_drv.h
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/i915_drv.h
Auto-merging drivers/gpu/drm/i915/display/intel_display.c
Auto-merging drivers/gpu/drm/i915/display/intel_bw.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_bw.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch' to see the failed patch
Patch failed at 0002 drm/i915: Restrict qgv points which don't have enough bandwidth.
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 23+ messages in thread
end of thread, other threads:[~2019-12-03 16:15 UTC | newest]

Thread overview: 23+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-15 14:53 [PATCH v12 0/2] Refactor Gen11+ SAGV support Stanislav Lisovskiy
2019-11-15 14:53 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-15 14:54 ` [PATCH v12 1/2] drm/i915: Refactor intel_can_enable_sagv Stanislav Lisovskiy
2019-11-15 14:54   ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-19 23:13   ` Matt Roper
2019-11-19 23:13     ` [Intel-gfx] " Matt Roper
2019-11-20  9:58     ` Lisovskiy, Stanislav
2019-11-20  9:58       ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-15 14:54 ` [PATCH v12 2/2] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
2019-11-15 14:54   ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-20  0:19   ` Matt Roper
2019-11-20  0:19     ` [Intel-gfx] " Matt Roper
2019-11-20  9:16     ` Lisovskiy, Stanislav
2019-11-20  9:16       ` [Intel-gfx] " Lisovskiy, Stanislav
2019-11-15 17:24 ` ✗ Fi.CI.CHECKPATCH: warning for Refactor Gen11+ SAGV support (rev11) Patchwork
2019-11-15 17:24   ` [Intel-gfx] " Patchwork
2019-11-15 17:26 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-15 17:26   ` [Intel-gfx] " Patchwork
2019-11-15 17:52 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-15 17:52   ` [Intel-gfx] " Patchwork
2019-11-17  3:42 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-17  3:42   ` [Intel-gfx] " Patchwork
2019-12-03 16:15 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for Refactor Gen11+ SAGV support (rev12) Patchwork

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