[PATCH v2 00/10] drm/i915/dsi: enable DSC

[PATCH v2 00/10] drm/i915/dsi: enable DSC

[Jani Nikula]

2nd try at enabling DSC on ICL+ DSI. Fingers still crossed.

BR,
Jani.

Jani Nikula (10):
  drm/i915/bios: pass devdata to parse_ddi_port
  drm/i915/bios: parse compression parameters block
  drm/i915/bios: add support for querying DSC details for encoder
  drm/i915/dsc: move DP specific compute params to intel_dp.c
  drm/i915/dsc: move slice height calculation to encoder
  drm/i915/dsc: add support for computing and writing PPS for DSI
    encoders
  drm/i915/dsi: set pipe_bpp on ICL configure config
  drm/i915/dsi: abstract afe_clk calculation
  drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
  drm/i915/dsi: add support for DSC

 drivers/gpu/drm/i915/display/icl_dsi.c        | 130 +++++++++++---
 drivers/gpu/drm/i915/display/intel_bios.c     | 159 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bios.h     |   5 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  59 ++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  85 +++-------
 6 files changed, 353 insertions(+), 87 deletions(-)

-- 
2.20.1

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[Intel-gfx] [PATCH v2 00/10] drm/i915/dsi: enable DSC

[Jani Nikula]

2nd try at enabling DSC on ICL+ DSI. Fingers still crossed.

BR,
Jani.

Jani Nikula (10):
  drm/i915/bios: pass devdata to parse_ddi_port
  drm/i915/bios: parse compression parameters block
  drm/i915/bios: add support for querying DSC details for encoder
  drm/i915/dsc: move DP specific compute params to intel_dp.c
  drm/i915/dsc: move slice height calculation to encoder
  drm/i915/dsc: add support for computing and writing PPS for DSI
    encoders
  drm/i915/dsi: set pipe_bpp on ICL configure config
  drm/i915/dsi: abstract afe_clk calculation
  drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
  drm/i915/dsi: add support for DSC

 drivers/gpu/drm/i915/display/icl_dsi.c        | 130 +++++++++++---
 drivers/gpu/drm/i915/display/intel_bios.c     | 159 +++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bios.h     |   5 +
 drivers/gpu/drm/i915/display/intel_dp.c       |  59 ++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
 drivers/gpu/drm/i915/display/intel_vdsc.c     |  85 +++-------
 6 files changed, 353 insertions(+), 87 deletions(-)

-- 
2.20.1

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[PATCH v2 01/10] drm/i915/bios: pass devdata to parse_ddi_port

[Jani Nikula]

Allow accessing the parent structure later on. Drop const for allowing
future modification as well.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 6d7b1a83cb07..2cda96324a73 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1425,9 +1425,10 @@ static enum port dvo_port_to_port(u8 dvo_port)
 }
 
 static void parse_ddi_port(struct drm_i915_private *dev_priv,
-			   const struct child_device_config *child,
+			   struct display_device_data *devdata,
 			   u8 bdb_version)
 {
+	const struct child_device_config *child = &devdata->child;
 	struct ddi_vbt_port_info *info;
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
 	enum port port;
@@ -1579,7 +1580,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
 
 static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
 {
-	const struct display_device_data *devdata;
+	struct display_device_data *devdata;
 
 	if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		return;
@@ -1588,7 +1589,7 @@ static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
 		return;
 
 	list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
-		parse_ddi_port(dev_priv, &devdata->child, bdb_version);
+		parse_ddi_port(dev_priv, devdata, bdb_version);
 }
 
 static void
-- 
2.20.1

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[Intel-gfx] [PATCH v2 01/10] drm/i915/bios: pass devdata to parse_ddi_port

[Jani Nikula]

Allow accessing the parent structure later on. Drop const for allowing
future modification as well.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 6d7b1a83cb07..2cda96324a73 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -1425,9 +1425,10 @@ static enum port dvo_port_to_port(u8 dvo_port)
 }
 
 static void parse_ddi_port(struct drm_i915_private *dev_priv,
-			   const struct child_device_config *child,
+			   struct display_device_data *devdata,
 			   u8 bdb_version)
 {
+	const struct child_device_config *child = &devdata->child;
 	struct ddi_vbt_port_info *info;
 	bool is_dvi, is_hdmi, is_dp, is_edp, is_crt;
 	enum port port;
@@ -1579,7 +1580,7 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
 
 static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
 {
-	const struct display_device_data *devdata;
+	struct display_device_data *devdata;
 
 	if (!HAS_DDI(dev_priv) && !IS_CHERRYVIEW(dev_priv))
 		return;
@@ -1588,7 +1589,7 @@ static void parse_ddi_ports(struct drm_i915_private *dev_priv, u8 bdb_version)
 		return;
 
 	list_for_each_entry(devdata, &dev_priv->vbt.display_devices, node)
-		parse_ddi_port(dev_priv, &devdata->child, bdb_version);
+		parse_ddi_port(dev_priv, devdata, bdb_version);
 }
 
 static void
-- 
2.20.1

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[PATCH v2 02/10] drm/i915/bios: parse compression parameters block

[Jani Nikula]

Check for child devices that specify compression, and store the device
specific compression parameters in the display device data struct for
later use. Warn if compression is requested but not available.

Use fairly rigid checks for compression data for starters. These can be
made more dynamic later.

Log about DSC presence in DDI port parse, though this is not universal
across platforms.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 61 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  2 +-
 2 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 2cda96324a73..1584e7db54b1 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -61,6 +61,7 @@
 /* Wrapper for VBT child device config */
 struct display_device_data {
 	struct child_device_config child;
+	struct dsc_compression_parameters_entry *dsc;
 	struct list_head node;
 };
 
@@ -1237,6 +1238,57 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv,
 	memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
 }
 
+static void
+parse_compression_parameters(struct drm_i915_private *i915,
+			     const struct bdb_header *bdb)
+{
+	const struct bdb_compression_parameters *params;
+	struct display_device_data *devdata;
+	const struct child_device_config *child;
+	u16 block_size;
+	int index;
+
+	if (bdb->version < 198)
+		return;
+
+	params = find_section(bdb, BDB_COMPRESSION_PARAMETERS);
+	if (params) {
+		/* Sanity checks */
+		if (params->entry_size != sizeof(params->data[0])) {
+			DRM_DEBUG_KMS("unsupported compression param entry size\n");
+			return;
+		}
+
+		block_size = get_blocksize(params);
+		if (block_size < sizeof(*params)) {
+			DRM_DEBUG_KMS("expecting 16 compression param entries\n");
+			return;
+		}
+	}
+
+	list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+		child = &devdata->child;
+
+		if (!child->compression_enable)
+			continue;
+
+		if (!params) {
+			DRM_DEBUG_KMS("child wants compression, unavailable\n");
+			continue;
+		}
+
+		if (child->compression_method_cps) {
+			DRM_DEBUG_KMS("CPS compression not supported\n");
+			continue;
+		}
+
+		index = child->compression_structure_index;
+
+		devdata->dsc = kmemdup(&params->data[index],
+				       sizeof(*devdata->dsc), GFP_KERNEL);
+	}
+}
+
 static u8 translate_iboost(u8 val)
 {
 	static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
@@ -1469,10 +1521,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
 	if (bdb_version >= 209)
 		info->supports_tbt = child->tbt;
 
-	DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n",
+	DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
 		      port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
 		      HAS_LSPCON(dev_priv) && child->lspcon,
-		      info->supports_typec_usb, info->supports_tbt);
+		      info->supports_typec_usb, info->supports_tbt,
+		      devdata->dsc != NULL);
 
 	if (is_edp && is_dvi)
 		DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
@@ -1878,6 +1931,9 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
 	parse_mipi_config(dev_priv, bdb);
 	parse_mipi_sequence(dev_priv, bdb);
 
+	/* Depends on child device list */
+	parse_compression_parameters(dev_priv, bdb);
+
 	/* Further processing on pre-parsed data */
 	parse_sdvo_device_mapping(dev_priv, bdb->version);
 	parse_ddi_ports(dev_priv, bdb->version);
@@ -1902,6 +1958,7 @@ void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
 
 	list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices, node) {
 		list_del(&devdata->node);
+		kfree(devdata->dsc);
 		kfree(devdata);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 69a7cb1fa121..372d8b62ba1a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -368,7 +368,7 @@ struct child_device_config {
 			u16 dtd_buf_ptr;			/* 161 */
 			u8 edidless_efp:1;			/* 161 */
 			u8 compression_enable:1;		/* 198 */
-			u8 compression_method:1;		/* 198 */
+			u8 compression_method_cps:1;		/* 198 */
 			u8 ganged_edp:1;			/* 202 */
 			u8 reserved0:4;
 			u8 compression_structure_index:4;	/* 198 */
-- 
2.20.1

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[Intel-gfx] [PATCH v2 02/10] drm/i915/bios: parse compression parameters block

[Jani Nikula]

Check for child devices that specify compression, and store the device
specific compression parameters in the display device data struct for
later use. Warn if compression is requested but not available.

Use fairly rigid checks for compression data for starters. These can be
made more dynamic later.

Log about DSC presence in DDI port parse, though this is not universal
across platforms.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c     | 61 ++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |  2 +-
 2 files changed, 60 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 2cda96324a73..1584e7db54b1 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -61,6 +61,7 @@
 /* Wrapper for VBT child device config */
 struct display_device_data {
 	struct child_device_config child;
+	struct dsc_compression_parameters_entry *dsc;
 	struct list_head node;
 };
 
@@ -1237,6 +1238,57 @@ parse_mipi_sequence(struct drm_i915_private *dev_priv,
 	memset(dev_priv->vbt.dsi.sequence, 0, sizeof(dev_priv->vbt.dsi.sequence));
 }
 
+static void
+parse_compression_parameters(struct drm_i915_private *i915,
+			     const struct bdb_header *bdb)
+{
+	const struct bdb_compression_parameters *params;
+	struct display_device_data *devdata;
+	const struct child_device_config *child;
+	u16 block_size;
+	int index;
+
+	if (bdb->version < 198)
+		return;
+
+	params = find_section(bdb, BDB_COMPRESSION_PARAMETERS);
+	if (params) {
+		/* Sanity checks */
+		if (params->entry_size != sizeof(params->data[0])) {
+			DRM_DEBUG_KMS("unsupported compression param entry size\n");
+			return;
+		}
+
+		block_size = get_blocksize(params);
+		if (block_size < sizeof(*params)) {
+			DRM_DEBUG_KMS("expecting 16 compression param entries\n");
+			return;
+		}
+	}
+
+	list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+		child = &devdata->child;
+
+		if (!child->compression_enable)
+			continue;
+
+		if (!params) {
+			DRM_DEBUG_KMS("child wants compression, unavailable\n");
+			continue;
+		}
+
+		if (child->compression_method_cps) {
+			DRM_DEBUG_KMS("CPS compression not supported\n");
+			continue;
+		}
+
+		index = child->compression_structure_index;
+
+		devdata->dsc = kmemdup(&params->data[index],
+				       sizeof(*devdata->dsc), GFP_KERNEL);
+	}
+}
+
 static u8 translate_iboost(u8 val)
 {
 	static const u8 mapping[] = { 1, 3, 7 }; /* See VBT spec */
@@ -1469,10 +1521,11 @@ static void parse_ddi_port(struct drm_i915_private *dev_priv,
 	if (bdb_version >= 209)
 		info->supports_tbt = child->tbt;
 
-	DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d\n",
+	DRM_DEBUG_KMS("Port %c VBT info: CRT:%d DVI:%d HDMI:%d DP:%d eDP:%d LSPCON:%d USB-Type-C:%d TBT:%d DSC:%d\n",
 		      port_name(port), is_crt, is_dvi, is_hdmi, is_dp, is_edp,
 		      HAS_LSPCON(dev_priv) && child->lspcon,
-		      info->supports_typec_usb, info->supports_tbt);
+		      info->supports_typec_usb, info->supports_tbt,
+		      devdata->dsc != NULL);
 
 	if (is_edp && is_dvi)
 		DRM_DEBUG_KMS("Internal DP port %c is TMDS compatible\n",
@@ -1878,6 +1931,9 @@ void intel_bios_init(struct drm_i915_private *dev_priv)
 	parse_mipi_config(dev_priv, bdb);
 	parse_mipi_sequence(dev_priv, bdb);
 
+	/* Depends on child device list */
+	parse_compression_parameters(dev_priv, bdb);
+
 	/* Further processing on pre-parsed data */
 	parse_sdvo_device_mapping(dev_priv, bdb->version);
 	parse_ddi_ports(dev_priv, bdb->version);
@@ -1902,6 +1958,7 @@ void intel_bios_driver_remove(struct drm_i915_private *dev_priv)
 
 	list_for_each_entry_safe(devdata, n, &dev_priv->vbt.display_devices, node) {
 		list_del(&devdata->node);
+		kfree(devdata->dsc);
 		kfree(devdata);
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 69a7cb1fa121..372d8b62ba1a 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -368,7 +368,7 @@ struct child_device_config {
 			u16 dtd_buf_ptr;			/* 161 */
 			u8 edidless_efp:1;			/* 161 */
 			u8 compression_enable:1;		/* 198 */
-			u8 compression_method:1;		/* 198 */
+			u8 compression_method_cps:1;		/* 198 */
 			u8 ganged_edp:1;			/* 202 */
 			u8 reserved0:4;
 			u8 compression_structure_index:4;	/* 198 */
-- 
2.20.1

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[PATCH v2 03/10] drm/i915/bios: add support for querying DSC details for encoder

[Jani Nikula]

Add function for retrieving the DSC data for an encoder.

Initially, this is DSI specific, as DP does not use VBT settings for DSC
at all. It's also not very pretty.

In the future we might have a pointer from encoder to the child device,
which would make the child device list query here so much more sensible.

v2: make more robust, debug log errors better

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 91 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_bios.h |  5 ++
 2 files changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 1584e7db54b1..8ba02533e97d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -29,6 +29,7 @@
 #include <drm/i915_drm.h>
 
 #include "display/intel_display.h"
+#include "display/intel_display_types.h"
 #include "display/intel_gmbus.h"
 
 #include "i915_drv.h"
@@ -2236,6 +2237,96 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
 	return false;
 }
 
+static void fill_dsc(struct intel_crtc_state *pipe_config,
+		     struct dsc_compression_parameters_entry *dsc,
+		     int dsc_max_bpc)
+{
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
+	int bpc = 8;
+
+	vdsc_cfg->dsc_version_major = dsc->version_major;
+	vdsc_cfg->dsc_version_minor = dsc->version_minor;
+
+	if (dsc->support_12bpc && dsc_max_bpc >= 12)
+		bpc = 12;
+	else if (dsc->support_10bpc && dsc_max_bpc >= 10)
+		bpc = 10;
+	else if (dsc->support_8bpc && dsc_max_bpc >= 8)
+		bpc = 8;
+	else
+		DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
+			      dsc_max_bpc);
+
+	pipe_config->pipe_bpp = bpc * 3;
+
+	pipe_config->dsc.compressed_bpp = min(pipe_config->pipe_bpp,
+					      VBT_DSC_MAX_BPP(dsc->max_bpp));
+
+	/*
+	 * FIXME: This is ugly, and slice count should take DSC engine
+	 * throughput etc. into account.
+	 *
+	 * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.
+	 */
+	if (dsc->slices_per_line & BIT(2)) {
+		pipe_config->dsc.slice_count = 4;
+	} else if (dsc->slices_per_line & BIT(1)) {
+		pipe_config->dsc.slice_count = 2;
+	} else {
+		/* FIXME */
+		if (!(dsc->slices_per_line & BIT(0)))
+			DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
+
+		pipe_config->dsc.slice_count = 1;
+	}
+
+	if (pipe_config->hw.adjusted_mode.crtc_hdisplay %
+	    pipe_config->dsc.slice_count != 0)
+		DRM_DEBUG_KMS("DSC hdisplay %d not divisible by slice count %d\n",
+			      pipe_config->hw.adjusted_mode.crtc_hdisplay,
+			      pipe_config->dsc.slice_count);
+
+	/* FIXME: rc_buffer_block_size, using defaults in intel_vdsc.c */
+
+	/* FIXME: rc_buffer_size, using defaults in intel_vdsc.c */
+
+	/* FIXME: DSI spec says bpc + 1 for this one */
+	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
+
+	vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
+
+	vdsc_cfg->slice_height = dsc->slice_height;
+}
+
+/* FIXME: initially DSI specific */
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+			       struct intel_crtc_state *pipe_config,
+			       int dsc_max_bpc)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct display_device_data *devdata;
+	const struct child_device_config *child;
+
+	list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+		child = &devdata->child;
+
+		if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
+			continue;
+
+		if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
+			if (!devdata->dsc)
+				return false;
+
+			if (pipe_config)
+				fill_dsc(pipe_config, devdata->dsc, dsc_max_bpc);
+
+			return true;
+		}
+	}
+
+	return true;
+}
+
 /**
  * intel_bios_is_port_hpd_inverted - is HPD inverted for %port
  * @i915:	i915 device instance
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 98f064828a57..fe1a11d3d6b6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,8 @@
 #include <drm/i915_drm.h>
 
 struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
 enum port;
 
 enum intel_backlight_type {
@@ -242,5 +244,8 @@ bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
 				  enum port port);
 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+			       struct intel_crtc_state *pipe_config,
+			       int dsc_max_bpc);
 
 #endif /* _INTEL_BIOS_H_ */
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 03/10] drm/i915/bios: add support for querying DSC details for encoder

[Jani Nikula]

Add function for retrieving the DSC data for an encoder.

Initially, this is DSI specific, as DP does not use VBT settings for DSC
at all. It's also not very pretty.

In the future we might have a pointer from encoder to the child device,
which would make the child device list query here so much more sensible.

v2: make more robust, debug log errors better

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.c | 91 +++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_bios.h |  5 ++
 2 files changed, 96 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 1584e7db54b1..8ba02533e97d 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -29,6 +29,7 @@
 #include <drm/i915_drm.h>
 
 #include "display/intel_display.h"
+#include "display/intel_display_types.h"
 #include "display/intel_gmbus.h"
 
 #include "i915_drv.h"
@@ -2236,6 +2237,96 @@ bool intel_bios_is_dsi_present(struct drm_i915_private *dev_priv,
 	return false;
 }
 
+static void fill_dsc(struct intel_crtc_state *pipe_config,
+		     struct dsc_compression_parameters_entry *dsc,
+		     int dsc_max_bpc)
+{
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
+	int bpc = 8;
+
+	vdsc_cfg->dsc_version_major = dsc->version_major;
+	vdsc_cfg->dsc_version_minor = dsc->version_minor;
+
+	if (dsc->support_12bpc && dsc_max_bpc >= 12)
+		bpc = 12;
+	else if (dsc->support_10bpc && dsc_max_bpc >= 10)
+		bpc = 10;
+	else if (dsc->support_8bpc && dsc_max_bpc >= 8)
+		bpc = 8;
+	else
+		DRM_DEBUG_KMS("VBT: Unsupported BPC %d for DCS\n",
+			      dsc_max_bpc);
+
+	pipe_config->pipe_bpp = bpc * 3;
+
+	pipe_config->dsc.compressed_bpp = min(pipe_config->pipe_bpp,
+					      VBT_DSC_MAX_BPP(dsc->max_bpp));
+
+	/*
+	 * FIXME: This is ugly, and slice count should take DSC engine
+	 * throughput etc. into account.
+	 *
+	 * Also, per spec DSI supports 1, 2, 3 or 4 horizontal slices.
+	 */
+	if (dsc->slices_per_line & BIT(2)) {
+		pipe_config->dsc.slice_count = 4;
+	} else if (dsc->slices_per_line & BIT(1)) {
+		pipe_config->dsc.slice_count = 2;
+	} else {
+		/* FIXME */
+		if (!(dsc->slices_per_line & BIT(0)))
+			DRM_DEBUG_KMS("VBT: Unsupported DSC slice count for DSI\n");
+
+		pipe_config->dsc.slice_count = 1;
+	}
+
+	if (pipe_config->hw.adjusted_mode.crtc_hdisplay %
+	    pipe_config->dsc.slice_count != 0)
+		DRM_DEBUG_KMS("DSC hdisplay %d not divisible by slice count %d\n",
+			      pipe_config->hw.adjusted_mode.crtc_hdisplay,
+			      pipe_config->dsc.slice_count);
+
+	/* FIXME: rc_buffer_block_size, using defaults in intel_vdsc.c */
+
+	/* FIXME: rc_buffer_size, using defaults in intel_vdsc.c */
+
+	/* FIXME: DSI spec says bpc + 1 for this one */
+	vdsc_cfg->line_buf_depth = VBT_DSC_LINE_BUFFER_DEPTH(dsc->line_buffer_depth);
+
+	vdsc_cfg->block_pred_enable = dsc->block_prediction_enable;
+
+	vdsc_cfg->slice_height = dsc->slice_height;
+}
+
+/* FIXME: initially DSI specific */
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+			       struct intel_crtc_state *pipe_config,
+			       int dsc_max_bpc)
+{
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+	const struct display_device_data *devdata;
+	const struct child_device_config *child;
+
+	list_for_each_entry(devdata, &i915->vbt.display_devices, node) {
+		child = &devdata->child;
+
+		if (!(child->device_type & DEVICE_TYPE_MIPI_OUTPUT))
+			continue;
+
+		if (child->dvo_port - DVO_PORT_MIPIA == encoder->port) {
+			if (!devdata->dsc)
+				return false;
+
+			if (pipe_config)
+				fill_dsc(pipe_config, devdata->dsc, dsc_max_bpc);
+
+			return true;
+		}
+	}
+
+	return true;
+}
+
 /**
  * intel_bios_is_port_hpd_inverted - is HPD inverted for %port
  * @i915:	i915 device instance
diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 98f064828a57..fe1a11d3d6b6 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -35,6 +35,8 @@
 #include <drm/i915_drm.h>
 
 struct drm_i915_private;
+struct intel_crtc_state;
+struct intel_encoder;
 enum port;
 
 enum intel_backlight_type {
@@ -242,5 +244,8 @@ bool intel_bios_is_port_hpd_inverted(const struct drm_i915_private *i915,
 bool intel_bios_is_lspcon_present(const struct drm_i915_private *i915,
 				  enum port port);
 enum aux_ch intel_bios_port_aux_ch(struct drm_i915_private *dev_priv, enum port port);
+bool intel_bios_get_dsc_params(struct intel_encoder *encoder,
+			       struct intel_crtc_state *pipe_config,
+			       int dsc_max_bpc);
 
 #endif /* _INTEL_BIOS_H_ */
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 04/10] drm/i915/dsc: move DP specific compute params to intel_dp.c

[Jani Nikula]

Turns out future DSI specific parameters aren't workable with the
approach of having the encoder specific functions in intel_vdsc.c. Make
intel_dsc_compute_params() a helper that does the encoder independent
parts, and have encoder code call it. Move intel_dsc_dp_compute_params()
to intel_dp.c as intel_dp_dsc_compute_params().

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 47 +++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 48 +----------------------
 2 files changed, 47 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..899af5d587cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2046,6 +2046,51 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
 	return 0;
 }
 
+#define DSC_SUPPORTED_VERSION_MIN		1
+
+static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
+				       struct intel_crtc_state *pipe_config)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
+	u8 line_buf_depth;
+	int ret;
+
+	ret = intel_dsc_compute_params(encoder, pipe_config);
+	if (ret)
+		return ret;
+
+	vdsc_cfg->dsc_version_major =
+		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
+	vdsc_cfg->dsc_version_minor =
+		min(DSC_SUPPORTED_VERSION_MIN,
+		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+
+	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+		DP_DSC_RGB;
+
+	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
+	if (!line_buf_depth) {
+		DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
+		return -EINVAL;
+	}
+
+	if (vdsc_cfg->dsc_version_minor == 2)
+		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
+			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
+	else
+		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
+			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
+
+	vdsc_cfg->block_pred_enable =
+			intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
+		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+	return drm_dsc_compute_rc_parameters(vdsc_cfg);
+}
+
 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				       struct intel_crtc_state *pipe_config,
 				       struct drm_connector_state *conn_state,
@@ -2132,7 +2177,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		}
 	}
 
-	ret = intel_dsc_compute_params(&dig_port->base, pipe_config);
+	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
 	if (ret < 0) {
 		DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
 			      "Compressed BPP = %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b23ba8d108db..834d665a47d2 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -30,8 +30,6 @@ enum COLUMN_INDEX_BPC {
 	MAX_COLUMN_INDEX
 };
 
-#define DSC_SUPPORTED_VERSION_MIN		1
-
 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
 static const u16 rc_buf_thresh[] = {
 	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
@@ -335,45 +333,6 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
 	return &rc_parameters[row_index][column_index];
 }
 
-/* Values filled from DSC Sink DPCD */
-static int intel_dsc_dp_compute_params(struct intel_encoder *encoder,
-				       struct intel_crtc_state *pipe_config)
-{
-	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
-	u8 line_buf_depth;
-
-	vdsc_cfg->dsc_version_major =
-		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
-		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
-	vdsc_cfg->dsc_version_minor =
-		min(DSC_SUPPORTED_VERSION_MIN,
-		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
-		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
-
-	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
-	if (!line_buf_depth) {
-		DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
-		return -EINVAL;
-	}
-
-	if (vdsc_cfg->dsc_version_minor == 2)
-		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
-			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
-	else
-		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
-			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
-
-	vdsc_cfg->block_pred_enable =
-			intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
-		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
-
-	return 0;
-}
-
 int intel_dsc_compute_params(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
 {
@@ -381,7 +340,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 	const struct rc_parameters *rc_params;
 	u8 i = 0;
-	int ret;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
@@ -470,11 +428,7 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 
-	ret = intel_dsc_dp_compute_params(encoder, pipe_config);
-	if (ret)
-		return ret;
-
-	return drm_dsc_compute_rc_parameters(vdsc_cfg);
+	return 0;
 }
 
 enum intel_display_power_domain
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 04/10] drm/i915/dsc: move DP specific compute params to intel_dp.c

[Jani Nikula]

Turns out future DSI specific parameters aren't workable with the
approach of having the encoder specific functions in intel_vdsc.c. Make
intel_dsc_compute_params() a helper that does the encoder independent
parts, and have encoder code call it. Move intel_dsc_dp_compute_params()
to intel_dp.c as intel_dp_dsc_compute_params().

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 47 +++++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_vdsc.c | 48 +----------------------
 2 files changed, 47 insertions(+), 48 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 3123958e2081..899af5d587cc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2046,6 +2046,51 @@ static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc)
 	return 0;
 }
 
+#define DSC_SUPPORTED_VERSION_MIN		1
+
+static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
+				       struct intel_crtc_state *pipe_config)
+{
+	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
+	u8 line_buf_depth;
+	int ret;
+
+	ret = intel_dsc_compute_params(encoder, pipe_config);
+	if (ret)
+		return ret;
+
+	vdsc_cfg->dsc_version_major =
+		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
+	vdsc_cfg->dsc_version_minor =
+		min(DSC_SUPPORTED_VERSION_MIN,
+		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
+		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
+
+	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
+		DP_DSC_RGB;
+
+	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
+	if (!line_buf_depth) {
+		DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
+		return -EINVAL;
+	}
+
+	if (vdsc_cfg->dsc_version_minor == 2)
+		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
+			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
+	else
+		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
+			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
+
+	vdsc_cfg->block_pred_enable =
+			intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
+		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
+
+	return drm_dsc_compute_rc_parameters(vdsc_cfg);
+}
+
 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 				       struct intel_crtc_state *pipe_config,
 				       struct drm_connector_state *conn_state,
@@ -2132,7 +2177,7 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
 		}
 	}
 
-	ret = intel_dsc_compute_params(&dig_port->base, pipe_config);
+	ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config);
 	if (ret < 0) {
 		DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d "
 			      "Compressed BPP = %d\n",
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index b23ba8d108db..834d665a47d2 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -30,8 +30,6 @@ enum COLUMN_INDEX_BPC {
 	MAX_COLUMN_INDEX
 };
 
-#define DSC_SUPPORTED_VERSION_MIN		1
-
 /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */
 static const u16 rc_buf_thresh[] = {
 	896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616,
@@ -335,45 +333,6 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp,
 	return &rc_parameters[row_index][column_index];
 }
 
-/* Values filled from DSC Sink DPCD */
-static int intel_dsc_dp_compute_params(struct intel_encoder *encoder,
-				       struct intel_crtc_state *pipe_config)
-{
-	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
-	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
-	u8 line_buf_depth;
-
-	vdsc_cfg->dsc_version_major =
-		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
-		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
-	vdsc_cfg->dsc_version_minor =
-		min(DSC_SUPPORTED_VERSION_MIN,
-		    (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
-		     DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT);
-
-	vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] &
-		DP_DSC_RGB;
-
-	line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd);
-	if (!line_buf_depth) {
-		DRM_DEBUG_KMS("DSC Sink Line Buffer Depth invalid\n");
-		return -EINVAL;
-	}
-
-	if (vdsc_cfg->dsc_version_minor == 2)
-		vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ?
-			DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth;
-	else
-		vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ?
-			DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth;
-
-	vdsc_cfg->block_pred_enable =
-			intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] &
-		DP_DSC_BLK_PREDICTION_IS_SUPPORTED;
-
-	return 0;
-}
-
 int intel_dsc_compute_params(struct intel_encoder *encoder,
 			     struct intel_crtc_state *pipe_config)
 {
@@ -381,7 +340,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	u16 compressed_bpp = pipe_config->dsc.compressed_bpp;
 	const struct rc_parameters *rc_params;
 	u8 i = 0;
-	int ret;
 
 	vdsc_cfg->pic_width = pipe_config->hw.adjusted_mode.crtc_hdisplay;
 	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
@@ -470,11 +428,7 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->initial_scale_value = (vdsc_cfg->rc_model_size << 3) /
 		(vdsc_cfg->rc_model_size - vdsc_cfg->initial_offset);
 
-	ret = intel_dsc_dp_compute_params(encoder, pipe_config);
-	if (ret)
-		return ret;
-
-	return drm_dsc_compute_rc_parameters(vdsc_cfg);
+	return 0;
 }
 
 enum intel_display_power_domain
-- 
2.20.1

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[PATCH v2 05/10] drm/i915/dsc: move slice height calculation to encoder

[Jani Nikula]

Turns out this isn't compatible with DSI.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c | 11 -----------
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 899af5d587cc..b083e45785ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2060,6 +2060,18 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
+	/*
+	 * Slice Height of 8 works for all currently available panels. So start
+	 * with that if pic_height is an integral multiple of 8.
+	 * Eventually add logic to try multiple slice heights.
+	 */
+	if (vdsc_cfg->pic_height % 8 == 0)
+		vdsc_cfg->slice_height = 8;
+	else if (vdsc_cfg->pic_height % 4 == 0)
+		vdsc_cfg->slice_height = 4;
+	else
+		vdsc_cfg->slice_height = 2;
+
 	vdsc_cfg->dsc_version_major =
 		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 834d665a47d2..c53024dfb1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -345,17 +345,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-	/*
-	 * Slice Height of 8 works for all currently available panels. So start
-	 * with that if pic_height is an integral multiple of 8.
-	 * Eventually add logic to try multiple slice heights.
-	 */
-	if (vdsc_cfg->pic_height % 8 == 0)
-		vdsc_cfg->slice_height = 8;
-	else if (vdsc_cfg->pic_height % 4 == 0)
-		vdsc_cfg->slice_height = 4;
-	else
-		vdsc_cfg->slice_height = 2;
 
 	/* Gen 11 does not support YCbCr */
 	vdsc_cfg->simple_422 = false;
-- 
2.20.1

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[Intel-gfx] [PATCH v2 05/10] drm/i915/dsc: move slice height calculation to encoder

[Jani Nikula]

Turns out this isn't compatible with DSI.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c   | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_vdsc.c | 11 -----------
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 899af5d587cc..b083e45785ea 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2060,6 +2060,18 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder,
 	if (ret)
 		return ret;
 
+	/*
+	 * Slice Height of 8 works for all currently available panels. So start
+	 * with that if pic_height is an integral multiple of 8.
+	 * Eventually add logic to try multiple slice heights.
+	 */
+	if (vdsc_cfg->pic_height % 8 == 0)
+		vdsc_cfg->slice_height = 8;
+	else if (vdsc_cfg->pic_height % 4 == 0)
+		vdsc_cfg->slice_height = 4;
+	else
+		vdsc_cfg->slice_height = 2;
+
 	vdsc_cfg->dsc_version_major =
 		(intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] &
 		 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT;
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index 834d665a47d2..c53024dfb1ec 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -345,17 +345,6 @@ int intel_dsc_compute_params(struct intel_encoder *encoder,
 	vdsc_cfg->pic_height = pipe_config->hw.adjusted_mode.crtc_vdisplay;
 	vdsc_cfg->slice_width = DIV_ROUND_UP(vdsc_cfg->pic_width,
 					     pipe_config->dsc.slice_count);
-	/*
-	 * Slice Height of 8 works for all currently available panels. So start
-	 * with that if pic_height is an integral multiple of 8.
-	 * Eventually add logic to try multiple slice heights.
-	 */
-	if (vdsc_cfg->pic_height % 8 == 0)
-		vdsc_cfg->slice_height = 8;
-	else if (vdsc_cfg->pic_height % 4 == 0)
-		vdsc_cfg->slice_height = 4;
-	else
-		vdsc_cfg->slice_height = 2;
 
 	/* Gen 11 does not support YCbCr */
 	vdsc_cfg->simple_422 = false;
-- 
2.20.1

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[PATCH v2 06/10] drm/i915/dsc: add support for computing and writing PPS for DSI encoders

[Jani Nikula]

Add DSI specific computation and transmission to display of PPS.

With hopes that this approach will work for both DP and DSI encoders.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 26 ++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c53024dfb1ec..76deeb31f32f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -10,6 +10,7 @@
 
 #include "i915_drv.h"
 #include "intel_display_types.h"
+#include "intel_dsi.h"
 #include "intel_vdsc.h"
 
 enum ROW_INDEX_BPP {
@@ -844,6 +845,26 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
 	}
 }
 
+static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct mipi_dsi_device *dsi;
+	struct drm_dsc_picture_parameter_set pps;
+	enum port port;
+
+	drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi = intel_dsi->dsi_hosts[port]->device;
+
+		/* FIXME: location and order of these two calls? */
+		mipi_dsi_picture_parameter_set(dsi, &pps);
+		mipi_dsi_compression_mode(dsi, true);
+	}
+}
+
 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -882,7 +903,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 	intel_dsc_pps_configure(encoder, crtc_state);
 
-	intel_dsc_dp_pps_write(encoder, crtc_state);
+	if (encoder->type == INTEL_OUTPUT_DSI)
+		intel_dsc_dsi_pps_write(encoder, crtc_state);
+	else
+		intel_dsc_dp_pps_write(encoder, crtc_state);
 
 	if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 		dss_ctl1_reg = DSS_CTL1;
-- 
2.20.1

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[Intel-gfx] [PATCH v2 06/10] drm/i915/dsc: add support for computing and writing PPS for DSI encoders

[Jani Nikula]

Add DSI specific computation and transmission to display of PPS.

With hopes that this approach will work for both DP and DSI encoders.

Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vdsc.c | 26 ++++++++++++++++++++++-
 1 file changed, 25 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index c53024dfb1ec..76deeb31f32f 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -10,6 +10,7 @@
 
 #include "i915_drv.h"
 #include "intel_display_types.h"
+#include "intel_dsi.h"
 #include "intel_vdsc.h"
 
 enum ROW_INDEX_BPP {
@@ -844,6 +845,26 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder,
 	}
 }
 
+static void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
+				    const struct intel_crtc_state *crtc_state)
+{
+	const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	struct mipi_dsi_device *dsi;
+	struct drm_dsc_picture_parameter_set pps;
+	enum port port;
+
+	drm_dsc_pps_payload_pack(&pps, vdsc_cfg);
+
+	for_each_dsi_port(port, intel_dsi->ports) {
+		dsi = intel_dsi->dsi_hosts[port]->device;
+
+		/* FIXME: location and order of these two calls? */
+		mipi_dsi_picture_parameter_set(dsi, &pps);
+		mipi_dsi_compression_mode(dsi, true);
+	}
+}
+
 static void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
 				   const struct intel_crtc_state *crtc_state)
 {
@@ -882,7 +903,10 @@ void intel_dsc_enable(struct intel_encoder *encoder,
 
 	intel_dsc_pps_configure(encoder, crtc_state);
 
-	intel_dsc_dp_pps_write(encoder, crtc_state);
+	if (encoder->type == INTEL_OUTPUT_DSI)
+		intel_dsc_dsi_pps_write(encoder, crtc_state);
+	else
+		intel_dsc_dp_pps_write(encoder, crtc_state);
 
 	if (crtc_state->cpu_transcoder == TRANSCODER_EDP) {
 		dss_ctl1_reg = DSS_CTL1;
-- 
2.20.1

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[PATCH v2 07/10] drm/i915/dsi: set pipe_bpp on ICL configure config

[Jani Nikula]

The ICL DSI pipe_bpp currently comes from
compute_baseline_pipe_bpp(). Fix it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f688207932e0..ef53ed6d3ecf 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1286,6 +1286,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	else
 		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
 
+	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
+		pipe_config->pipe_bpp = 24;
+	else
+		pipe_config->pipe_bpp = 18;
+
 	pipe_config->clock_set = true;
 	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
 
-- 
2.20.1

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[Intel-gfx] [PATCH v2 07/10] drm/i915/dsi: set pipe_bpp on ICL configure config

[Jani Nikula]

The ICL DSI pipe_bpp currently comes from
compute_baseline_pipe_bpp(). Fix it.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f688207932e0..ef53ed6d3ecf 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -1286,6 +1286,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 	else
 		pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
 
+	if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
+		pipe_config->pipe_bpp = 24;
+	else
+		pipe_config->pipe_bpp = 18;
+
 	pipe_config->clock_set = true;
 	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
 
-- 
2.20.1

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[PATCH v2 08/10] drm/i915/dsi: abstract afe_clk calculation

[Jani Nikula]

We'll make more use of it in the future.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ef53ed6d3ecf..de3743233dcb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -301,18 +301,26 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 	I915_WRITE(DSS_CTL1, dss_ctl1);
 }
 
+/* aka DSI 8X clock */
+static int afe_clk(struct intel_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	int bpp;
+
+	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
-	u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
-	u32 afe_clk_khz; /* 8X Clock */
+	int afe_clk_khz;
 	u32 esc_clk_div_m;
 
-	afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
-					intel_dsi->lane_count);
-
+	afe_clk_khz = afe_clk(encoder);
 	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
2.20.1

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[Intel-gfx] [PATCH v2 08/10] drm/i915/dsi: abstract afe_clk calculation

[Jani Nikula]

We'll make more use of it in the future.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index ef53ed6d3ecf..de3743233dcb 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -301,18 +301,26 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 	I915_WRITE(DSS_CTL1, dss_ctl1);
 }
 
+/* aka DSI 8X clock */
+static int afe_clk(struct intel_encoder *encoder)
+{
+	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
+	int bpp;
+
+	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+
+	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
+}
+
 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	enum port port;
-	u32 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
-	u32 afe_clk_khz; /* 8X Clock */
+	int afe_clk_khz;
 	u32 esc_clk_div_m;
 
-	afe_clk_khz = DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp,
-					intel_dsi->lane_count);
-
+	afe_clk_khz = afe_clk(encoder);
 	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
-- 
2.20.1

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[PATCH v2 09/10] drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()

[Jani Nikula]

We'll be expanding afe_clk() to take DSC into account. Switch to using
it where DSC matters. Which is really everywhere that
intel_dsi_bitrate() is currently used in ICL DSI code.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index de3743233dcb..d576f29cef75 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -539,7 +539,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	 * leave all fields at HW default values.
 	 */
 	if (IS_GEN(dev_priv, 11)) {
-		if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+		if (afe_clk(encoder) <= 800000) {
 			for_each_dsi_port(port, intel_dsi->ports) {
 				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 				tmp &= ~TA_SURE_MASK;
@@ -649,7 +649,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			tmp |= EOTP_DISABLED;
 
 		/* enable link calibration if freq > 1.5Gbps */
-		if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+		if (afe_clk(encoder) >= 1500 * 1000) {
 			tmp &= ~LINK_CALIBRATION_MASK;
 			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 		}
@@ -930,7 +930,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 	 */
-	divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
+	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
 	mul = 8 * 1000000;
 	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 				     divisor);
@@ -1300,7 +1300,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 		pipe_config->pipe_bpp = 18;
 
 	pipe_config->clock_set = true;
-	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
+	pipe_config->port_clock = afe_clk(encoder) / 5;
 
 	return 0;
 }
-- 
2.20.1

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[Intel-gfx] [PATCH v2 09/10] drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()

[Jani Nikula]

We'll be expanding afe_clk() to take DSC into account. Switch to using
it where DSC matters. Which is really everywhere that
intel_dsi_bitrate() is currently used in ICL DSI code.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index de3743233dcb..d576f29cef75 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -539,7 +539,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	 * leave all fields at HW default values.
 	 */
 	if (IS_GEN(dev_priv, 11)) {
-		if (intel_dsi_bitrate(intel_dsi) <= 800000) {
+		if (afe_clk(encoder) <= 800000) {
 			for_each_dsi_port(port, intel_dsi->ports) {
 				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 				tmp &= ~TA_SURE_MASK;
@@ -649,7 +649,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			tmp |= EOTP_DISABLED;
 
 		/* enable link calibration if freq > 1.5Gbps */
-		if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
+		if (afe_clk(encoder) >= 1500 * 1000) {
 			tmp &= ~LINK_CALIBRATION_MASK;
 			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 		}
@@ -930,7 +930,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 	 */
-	divisor = intel_dsi_tlpx_ns(intel_dsi) * intel_dsi_bitrate(intel_dsi) * 1000;
+	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
 	mul = 8 * 1000000;
 	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 				     divisor);
@@ -1300,7 +1300,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 		pipe_config->pipe_bpp = 18;
 
 	pipe_config->clock_set = true;
-	pipe_config->port_clock = intel_dsi_bitrate(intel_dsi) / 5;
+	pipe_config->port_clock = afe_clk(encoder) / 5;
 
 	return 0;
 }
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH v2 10/10] drm/i915/dsi: add support for DSC

[Jani Nikula]

Enable DSC for DSI, if specified in VBT.

This is now excessively dynamic, being enabled at compute config. I
don't expect us to need to switch between DSC and non-DSC for the same
panel. Cargo culting the DP DSC shows.

Mode valid lacks a sensible implementation, as does get config.

v3: take compressed bpp into account

v2: Nuke conn_state->max_requested_bpc, it's not used on DSI

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

The burst mode stuff wrt DSC are still whatever, but at least we should
be taking DSC better into account in port clock calculations.
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 113 ++++++++++++++++++++-----
 1 file changed, 94 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d576f29cef75..dc87134f5c27 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,6 +34,7 @@
 #include "intel_ddi.h"
 #include "intel_dsi.h"
 #include "intel_panel.h"
+#include "intel_vdsc.h"
 
 static inline int header_credits_available(struct drm_i915_private *dev_priv,
 					   enum transcoder dsi_trans)
@@ -302,17 +303,22 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 }
 
 /* aka DSI 8X clock */
-static int afe_clk(struct intel_encoder *encoder)
+static int afe_clk(struct intel_encoder *encoder,
+		   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	int bpp;
 
-	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+	if (crtc_state->dsc.compression_enable)
+		bpp = crtc_state->dsc.compressed_bpp;
+	else
+		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 }
 
-static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
+static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -320,7 +326,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 	int afe_clk_khz;
 	u32 esc_clk_div_m;
 
-	afe_clk_khz = afe_clk(encoder);
+	afe_clk_khz = afe_clk(encoder, crtc_state);
 	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
@@ -498,7 +504,9 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 	}
 }
 
-static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+static void
+gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -539,7 +547,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	 * leave all fields at HW default values.
 	 */
 	if (IS_GEN(dev_priv, 11)) {
-		if (afe_clk(encoder) <= 800000) {
+		if (afe_clk(encoder, crtc_state) <= 800000) {
 			for_each_dsi_port(port, intel_dsi->ports) {
 				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 				tmp &= ~TA_SURE_MASK;
@@ -649,7 +657,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			tmp |= EOTP_DISABLED;
 
 		/* enable link calibration if freq > 1.5Gbps */
-		if (afe_clk(encoder) >= 1500 * 1000) {
+		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 			tmp &= ~LINK_CALIBRATION_MASK;
 			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 		}
@@ -915,7 +923,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 	}
 }
 
-static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -930,7 +939,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 	 */
-	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
+	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
 	mul = 8 * 1000000;
 	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 				     divisor);
@@ -966,7 +975,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
-			      const struct intel_crtc_state *pipe_config)
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
@@ -983,13 +992,13 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	gen11_dsi_enable_ddi_buffer(encoder);
 
 	/* setup D-PHY timings */
-	gen11_dsi_setup_dphy_timings(encoder);
+	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
 
 	/* step 4h: setup DSI protocol timeouts */
-	gen11_dsi_setup_timeouts(encoder);
+	gen11_dsi_setup_timeouts(encoder, crtc_state);
 
 	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
-	gen11_dsi_configure_transcoder(encoder, pipe_config);
+	gen11_dsi_configure_transcoder(encoder, crtc_state);
 
 	/* Step 4l: Gate DDI clocks */
 	if (IS_GEN(dev_priv, 11))
@@ -1036,14 +1045,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 }
 
 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *pipe_config,
+				     const struct intel_crtc_state *crtc_state,
 				     const struct drm_connector_state *conn_state)
 {
 	/* step2: enable IO power */
 	gen11_dsi_enable_io_power(encoder);
 
 	/* step3: enable DSI PLL */
-	gen11_dsi_program_esc_clk_div(encoder);
+	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
 }
 
 static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
@@ -1061,6 +1070,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	/* step5: program and powerup panel */
 	gen11_dsi_powerup_panel(encoder);
 
+	/* FIXME: location? */
+	intel_dsc_enable(encoder, pipe_config);
+
 	/* step6c: configure transcoder timings */
 	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
 
@@ -1222,6 +1234,13 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
+						 struct drm_display_mode *mode)
+{
+	/* FIXME: DSC? */
+	return intel_dsi_mode_valid(connector, mode);
+}
+
 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 				  struct intel_crtc_state *pipe_config)
 {
@@ -1269,6 +1288,53 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
 }
 
+static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
+					struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
+	bool use_dsc;
+	int ret;
+
+	use_dsc = intel_bios_get_dsc_params(encoder, pipe_config, dsc_max_bpc);
+	if (!use_dsc)
+		return 0;
+
+	if (pipe_config->pipe_bpp < 8 * 3)
+		return -EINVAL;
+
+	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
+		if (pipe_config->dsc.slice_count > 1) {
+			pipe_config->dsc.dsc_split = true;
+		} else {
+			DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
+			return -EINVAL;
+		}
+	}
+
+	vdsc_cfg->convert_rgb = false;
+
+	ret = intel_dsc_compute_params(encoder, pipe_config);
+	if (ret)
+		return ret;
+
+	/* DSI specific sanity checks on the common code */
+	WARN_ON(vdsc_cfg->vbr_enable);
+	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
+	WARN_ON(vdsc_cfg->slice_height < 8);
+	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
+
+	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
+	if (ret)
+		return ret;
+
+	pipe_config->dsc.compression_enable = true;
+
+	return 0;
+}
+
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 				    struct intel_crtc_state *pipe_config,
 				    struct drm_connector_state *conn_state)
@@ -1300,7 +1366,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 		pipe_config->pipe_bpp = 18;
 
 	pipe_config->clock_set = true;
-	pipe_config->port_clock = afe_clk(encoder) / 5;
+
+	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
+		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
+
+	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
 
 	return 0;
 }
@@ -1308,8 +1378,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
 					struct intel_crtc_state *crtc_state)
 {
-	get_dsi_io_power_domains(to_i915(encoder->base.dev),
-				 enc_to_intel_dsi(&encoder->base));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder->base));
+
+	if (crtc_state->dsc.compression_enable)
+		intel_display_power_get(i915,
+					intel_dsc_power_domain(crtc_state));
 }
 
 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -1379,7 +1454,7 @@ static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
 
 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
 	.get_modes = intel_dsi_get_modes,
-	.mode_valid = intel_dsi_mode_valid,
+	.mode_valid = gen11_dsi_mode_valid,
 	.atomic_check = intel_digital_connector_atomic_check,
 };
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] [PATCH v2 10/10] drm/i915/dsi: add support for DSC

[Jani Nikula]

Enable DSC for DSI, if specified in VBT.

This is now excessively dynamic, being enabled at compute config. I
don't expect us to need to switch between DSC and non-DSC for the same
panel. Cargo culting the DP DSC shows.

Mode valid lacks a sensible implementation, as does get config.

v3: take compressed bpp into account

v2: Nuke conn_state->max_requested_bpc, it's not used on DSI

Signed-off-by: Jani Nikula <jani.nikula@intel.com>

---

The burst mode stuff wrt DSC are still whatever, but at least we should
be taking DSC better into account in port clock calculations.
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 113 ++++++++++++++++++++-----
 1 file changed, 94 insertions(+), 19 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index d576f29cef75..dc87134f5c27 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -34,6 +34,7 @@
 #include "intel_ddi.h"
 #include "intel_dsi.h"
 #include "intel_panel.h"
+#include "intel_vdsc.h"
 
 static inline int header_credits_available(struct drm_i915_private *dev_priv,
 					   enum transcoder dsi_trans)
@@ -302,17 +303,22 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
 }
 
 /* aka DSI 8X clock */
-static int afe_clk(struct intel_encoder *encoder)
+static int afe_clk(struct intel_encoder *encoder,
+		   const struct intel_crtc_state *crtc_state)
 {
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
 	int bpp;
 
-	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
+	if (crtc_state->dsc.compression_enable)
+		bpp = crtc_state->dsc.compressed_bpp;
+	else
+		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 
 	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 }
 
-static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
+static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
+					  const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -320,7 +326,7 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
 	int afe_clk_khz;
 	u32 esc_clk_div_m;
 
-	afe_clk_khz = afe_clk(encoder);
+	afe_clk_khz = afe_clk(encoder, crtc_state);
 	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 
 	for_each_dsi_port(port, intel_dsi->ports) {
@@ -498,7 +504,9 @@ static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 	}
 }
 
-static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
+static void
+gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -539,7 +547,7 @@ static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
 	 * leave all fields at HW default values.
 	 */
 	if (IS_GEN(dev_priv, 11)) {
-		if (afe_clk(encoder) <= 800000) {
+		if (afe_clk(encoder, crtc_state) <= 800000) {
 			for_each_dsi_port(port, intel_dsi->ports) {
 				tmp = I915_READ(DPHY_TA_TIMING_PARAM(port));
 				tmp &= ~TA_SURE_MASK;
@@ -649,7 +657,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 			tmp |= EOTP_DISABLED;
 
 		/* enable link calibration if freq > 1.5Gbps */
-		if (afe_clk(encoder) >= 1500 * 1000) {
+		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 			tmp &= ~LINK_CALIBRATION_MASK;
 			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 		}
@@ -915,7 +923,8 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 	}
 }
 
-static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
+static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
+				     const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
@@ -930,7 +939,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
 	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
 	 */
-	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
+	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
 	mul = 8 * 1000000;
 	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
 				     divisor);
@@ -966,7 +975,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
 
 static void
 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
-			      const struct intel_crtc_state *pipe_config)
+			      const struct intel_crtc_state *crtc_state)
 {
 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 
@@ -983,13 +992,13 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
 	gen11_dsi_enable_ddi_buffer(encoder);
 
 	/* setup D-PHY timings */
-	gen11_dsi_setup_dphy_timings(encoder);
+	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
 
 	/* step 4h: setup DSI protocol timeouts */
-	gen11_dsi_setup_timeouts(encoder);
+	gen11_dsi_setup_timeouts(encoder, crtc_state);
 
 	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
-	gen11_dsi_configure_transcoder(encoder, pipe_config);
+	gen11_dsi_configure_transcoder(encoder, crtc_state);
 
 	/* Step 4l: Gate DDI clocks */
 	if (IS_GEN(dev_priv, 11))
@@ -1036,14 +1045,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
 }
 
 static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
-				     const struct intel_crtc_state *pipe_config,
+				     const struct intel_crtc_state *crtc_state,
 				     const struct drm_connector_state *conn_state)
 {
 	/* step2: enable IO power */
 	gen11_dsi_enable_io_power(encoder);
 
 	/* step3: enable DSI PLL */
-	gen11_dsi_program_esc_clk_div(encoder);
+	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
 }
 
 static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
@@ -1061,6 +1070,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder *encoder,
 	/* step5: program and powerup panel */
 	gen11_dsi_powerup_panel(encoder);
 
+	/* FIXME: location? */
+	intel_dsc_enable(encoder, pipe_config);
+
 	/* step6c: configure transcoder timings */
 	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
 
@@ -1222,6 +1234,13 @@ static void gen11_dsi_disable(struct intel_encoder *encoder,
 	gen11_dsi_disable_io_power(encoder);
 }
 
+static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
+						 struct drm_display_mode *mode)
+{
+	/* FIXME: DSC? */
+	return intel_dsi_mode_valid(connector, mode);
+}
+
 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
 				  struct intel_crtc_state *pipe_config)
 {
@@ -1269,6 +1288,53 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
 	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);
 }
 
+static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
+					struct intel_crtc_state *pipe_config)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
+	struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
+	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
+	bool use_dsc;
+	int ret;
+
+	use_dsc = intel_bios_get_dsc_params(encoder, pipe_config, dsc_max_bpc);
+	if (!use_dsc)
+		return 0;
+
+	if (pipe_config->pipe_bpp < 8 * 3)
+		return -EINVAL;
+
+	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
+		if (pipe_config->dsc.slice_count > 1) {
+			pipe_config->dsc.dsc_split = true;
+		} else {
+			DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n");
+			return -EINVAL;
+		}
+	}
+
+	vdsc_cfg->convert_rgb = false;
+
+	ret = intel_dsc_compute_params(encoder, pipe_config);
+	if (ret)
+		return ret;
+
+	/* DSI specific sanity checks on the common code */
+	WARN_ON(vdsc_cfg->vbr_enable);
+	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
+	WARN_ON(vdsc_cfg->slice_height < 8);
+	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
+
+	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
+	if (ret)
+		return ret;
+
+	pipe_config->dsc.compression_enable = true;
+
+	return 0;
+}
+
 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 				    struct intel_crtc_state *pipe_config,
 				    struct drm_connector_state *conn_state)
@@ -1300,7 +1366,11 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 		pipe_config->pipe_bpp = 18;
 
 	pipe_config->clock_set = true;
-	pipe_config->port_clock = afe_clk(encoder) / 5;
+
+	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
+		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
+
+	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
 
 	return 0;
 }
@@ -1308,8 +1378,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
 					struct intel_crtc_state *crtc_state)
 {
-	get_dsi_io_power_domains(to_i915(encoder->base.dev),
-				 enc_to_intel_dsi(&encoder->base));
+	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+
+	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder->base));
+
+	if (crtc_state->dsc.compression_enable)
+		intel_display_power_get(i915,
+					intel_dsc_power_domain(crtc_state));
 }
 
 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
@@ -1379,7 +1454,7 @@ static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
 
 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
 	.get_modes = intel_dsi_get_modes,
-	.mode_valid = intel_dsi_mode_valid,
+	.mode_valid = gen11_dsi_mode_valid,
 	.atomic_check = intel_digital_connector_atomic_check,
 };
 
-- 
2.20.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69540/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
dc583bcee91e drm/i915/bios: pass devdata to parse_ddi_port
b567762a0b2a drm/i915/bios: parse compression parameters block
-:98: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#98: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1528:
+		      devdata->dsc != NULL);

total: 0 errors, 0 warnings, 1 checks, 101 lines checked
cfda91238c7c drm/i915/bios: add support for querying DSC details for encoder
aed845a88e0f drm/i915/dsc: move DP specific compute params to intel_dp.c
f7ac672ad0ac drm/i915/dsc: move slice height calculation to encoder
24d5af9226d6 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
795b06e0b07e drm/i915/dsi: set pipe_bpp on ICL configure config
1cfcf6e53fd7 drm/i915/dsi: abstract afe_clk calculation
be01484fce55 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
8d4c47084499 drm/i915/dsi: add support for DSC

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69540/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
dc583bcee91e drm/i915/bios: pass devdata to parse_ddi_port
b567762a0b2a drm/i915/bios: parse compression parameters block
-:98: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#98: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1528:
+		      devdata->dsc != NULL);

total: 0 errors, 0 warnings, 1 checks, 101 lines checked
cfda91238c7c drm/i915/bios: add support for querying DSC details for encoder
aed845a88e0f drm/i915/dsc: move DP specific compute params to intel_dp.c
f7ac672ad0ac drm/i915/dsc: move slice height calculation to encoder
24d5af9226d6 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
795b06e0b07e drm/i915/dsi: set pipe_bpp on ICL configure config
1cfcf6e53fd7 drm/i915/dsi: abstract afe_clk calculation
be01484fce55 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
8d4c47084499 drm/i915/dsi: add support for DSC

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.BAT: success for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69540/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7354 -> Patchwork_15287
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/index.html

Known issues
------------

  Here are the changes found in Patchwork_15287 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_cpu_reloc@basic:
    - fi-icl-dsi:         [PASS][1] -> [DMESG-WARN][2] ([fdo#106107])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-icl-dsi/igt@gem_cpu_reloc@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-icl-dsi/igt@gem_cpu_reloc@basic.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][3] -> [DMESG-WARN][4] ([fdo#112261])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
    - fi-skl-lmem:        [PASS][5] -> [DMESG-WARN][6] ([fdo#112261])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-skl-6770hq:      [PASS][7] -> [DMESG-WARN][8] ([fdo#105541])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][9] -> [FAIL][10] ([fdo#109635 ] / [fdo#110387])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [PASS][11] -> [FAIL][12] ([fdo#109483])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-kbl-7560u}:     [INCOMPLETE][13] ([fdo#109964] / [fdo#112298]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-guc:         [FAIL][15] ([fdo#103167]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
    - fi-hsw-peppy:       [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [WARN][19] ([fdo#112252]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [DMESG-WARN][21] ([fdo#102505] / [fdo#110390]) -> [FAIL][22] ([fdo#109483])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
  [fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7354 -> Patchwork_15287

  CI-20190529: 20190529
  CI_DRM_7354: ba190714c20f10f70a35caaa46ce908ae7831e96 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15287: 8d4c4708449934939b6151dc2c64644054b1e818 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8d4c47084499 drm/i915/dsi: add support for DSC
be01484fce55 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
1cfcf6e53fd7 drm/i915/dsi: abstract afe_clk calculation
795b06e0b07e drm/i915/dsi: set pipe_bpp on ICL configure config
24d5af9226d6 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
f7ac672ad0ac drm/i915/dsc: move slice height calculation to encoder
aed845a88e0f drm/i915/dsc: move DP specific compute params to intel_dp.c
cfda91238c7c drm/i915/bios: add support for querying DSC details for encoder
b567762a0b2a drm/i915/bios: parse compression parameters block
dc583bcee91e drm/i915/bios: pass devdata to parse_ddi_port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69540/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7354 -> Patchwork_15287
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/index.html

Known issues
------------

  Here are the changes found in Patchwork_15287 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_cpu_reloc@basic:
    - fi-icl-dsi:         [PASS][1] -> [DMESG-WARN][2] ([fdo#106107])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-icl-dsi/igt@gem_cpu_reloc@basic.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-icl-dsi/igt@gem_cpu_reloc@basic.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [PASS][3] -> [DMESG-WARN][4] ([fdo#112261])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
    - fi-skl-lmem:        [PASS][5] -> [DMESG-WARN][6] ([fdo#112261])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html

  * igt@kms_busy@basic-flip-pipe-b:
    - fi-skl-6770hq:      [PASS][7] -> [DMESG-WARN][8] ([fdo#105541])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-6770hq/igt@kms_busy@basic-flip-pipe-b.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [PASS][9] -> [FAIL][10] ([fdo#109635 ] / [fdo#110387])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-edid-read:
    - fi-kbl-7500u:       [PASS][11] -> [FAIL][12] ([fdo#109483])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-kbl-7500u/igt@kms_chamelium@hdmi-edid-read.html

  
#### Possible fixes ####

  * igt@i915_module_load@reload-with-fault-injection:
    - {fi-kbl-7560u}:     [INCOMPLETE][13] ([fdo#109964] / [fdo#112298]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-guc:         [FAIL][15] ([fdo#103167]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-icl-guc/igt@kms_frontbuffer_tracking@basic.html
    - fi-hsw-peppy:       [DMESG-WARN][17] ([fdo#102614]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-hsw-peppy/igt@kms_frontbuffer_tracking@basic.html

  * igt@kms_setmode@basic-clone-single-crtc:
    - fi-skl-6770hq:      [WARN][19] ([fdo#112252]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-skl-6770hq/igt@kms_setmode@basic-clone-single-crtc.html

  
#### Warnings ####

  * igt@kms_chamelium@common-hpd-after-suspend:
    - fi-icl-u2:          [DMESG-WARN][21] ([fdo#102505] / [fdo#110390]) -> [FAIL][22] ([fdo#109483])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/fi-icl-u2/igt@kms_chamelium@common-hpd-after-suspend.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#102505]: https://bugs.freedesktop.org/show_bug.cgi?id=102505
  [fdo#102614]: https://bugs.freedesktop.org/show_bug.cgi?id=102614
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#105541]: https://bugs.freedesktop.org/show_bug.cgi?id=105541
  [fdo#106107]: https://bugs.freedesktop.org/show_bug.cgi?id=106107
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#110390]: https://bugs.freedesktop.org/show_bug.cgi?id=110390
  [fdo#112252]: https://bugs.freedesktop.org/show_bug.cgi?id=112252
  [fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (52 -> 45)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7354 -> Patchwork_15287

  CI-20190529: 20190529
  CI_DRM_7354: ba190714c20f10f70a35caaa46ce908ae7831e96 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5288: ff4551e36cd8e573ceb1e450d17a12e3298dc04c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15287: 8d4c4708449934939b6151dc2c64644054b1e818 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

8d4c47084499 drm/i915/dsi: add support for DSC
be01484fce55 drm/i915/dsi: use afe_clk() instead of intel_dsi_bitrate()
1cfcf6e53fd7 drm/i915/dsi: abstract afe_clk calculation
795b06e0b07e drm/i915/dsi: set pipe_bpp on ICL configure config
24d5af9226d6 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
f7ac672ad0ac drm/i915/dsc: move slice height calculation to encoder
aed845a88e0f drm/i915/dsc: move DP specific compute params to intel_dp.c
cfda91238c7c drm/i915/bios: add support for querying DSC details for encoder
b567762a0b2a drm/i915/bios: parse compression parameters block
dc583bcee91e drm/i915/bios: pass devdata to parse_ddi_port

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/index.html
_______________________________________________
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✗ Fi.CI.IGT: failure for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69540/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7354_full -> Patchwork_15287_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15287_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15287_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15287_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-apl:          [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_parse_blt@batch-invalid-length}:
    - shard-tglb:         NOTRUN -> [SKIP][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb9/igt@gem_exec_parse_blt@batch-invalid-length.html

  * {igt@gem_exec_parse_blt@bb-start-cmd}:
    - shard-iclb:         NOTRUN -> [SKIP][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb6/igt@gem_exec_parse_blt@bb-start-cmd.html

  
Known issues
------------

  Here are the changes found in Patchwork_15287_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +13 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb4/igt@gem_busy@busy-vcs1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb5/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111832])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb7/igt@gem_ctx_isolation@bcs0-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb1/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +7 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#111736] / [fdo#111850])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb1/igt@gem_exec_suspend@basic-s3.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb8/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_sync@basic-all:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111647])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb7/igt@gem_sync@basic-all.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb6/igt@gem_sync@basic-all.html

  * igt@gem_sync@basic-each:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#111998])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb4/igt@gem_sync@basic-each.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb7/igt@gem_sync@basic-each.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-hsw:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-snb7/igt@gem_userptr_blits@sync-unmap-cycles.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][23] -> [DMESG-FAIL][24] ([fdo#111991])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw7/igt@i915_selftest@live_hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw7/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@sysfs-reader:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb3/igt@i915_suspend@sysfs-reader.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_color@pipe-a-ctm-red-to-blue:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#107201])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl5/igt@kms_color@pipe-a-ctm-red-to-blue.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl10/igt@kms_color@pipe-a-ctm-red-to-blue.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#111747] / [fdo#111832] / [fdo#111850])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +8 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-tglb:         [PASS][35] -> [FAIL][36] ([fdo#103167]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [PASS][37] -> [DMESG-WARN][38] ([fdo#108566]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][39] -> [FAIL][40] ([fdo#103166])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb4/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - shard-tglb:         [PASS][43] -> [INCOMPLETE][44] ([fdo#111850]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][45] -> [SKIP][46] ([fdo#109276]) +21 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@prime_busy@hang-bsd2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb3/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-tglb:         [INCOMPLETE][49] ([fdo#111832]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb7/igt@gem_ctx_isolation@vecs0-s3.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb8/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][51] ([fdo#109276] / [fdo#112080]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb3/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][53] ([fdo#110841]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_ctx_switch@queue-light:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111672]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@gem_ctx_switch@queue-light.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb9/igt@gem_ctx_switch@queue-light.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [SKIP][57] ([fdo#112080]) -> [PASS][58] +9 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb3/igt@gem_ctx_switch@vcs1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@gem_ctx_switch@vcs1.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][59] ([fdo#110854]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb8/igt@gem_exec_balancer@smoke.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb4/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_nop@basic-series:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111747]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@gem_exec_nop@basic-series.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb2/igt@gem_exec_nop@basic-series.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt:
    - shard-tglb:         [INCOMPLETE][63] ([fdo#111606] / [fdo#111677]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb4/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
    - shard-iclb:         [SKIP][65] ([fdo#112146]) -> [PASS][66] +8 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][67] ([fdo#109276]) -> [PASS][68] +22 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb8/igt@gem_exec_schedule@promotion-bsd1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-apl:          [TIMEOUT][69] ([fdo#112113]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl8/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl3/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-hsw:          [FAIL][71] ([fdo#112037]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-glk:          [DMESG-FAIL][73] -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-glk9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-glk9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [DMESG-WARN][75] ([fdo#111870]) -> [PASS][76] +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw1/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][77] ([fdo#111830 ]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb3/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-skl:          [INCOMPLETE][79] ([fdo#104108] / [fdo#107807]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl5/igt@i915_pm_rpm@system-suspend-execbuf.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         [FAIL][81] ([fdo#111409]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb7/igt@i915_pm_rps@min-max-config-loaded.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-glk:          [FAIL][83] ([fdo#100368]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@dpms-vs-vblank-race-interruptible:
    - shard-hsw:          [DMESG-FAIL][85] ([fdo#102614]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw5/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw2/igt@kms_flip@dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          [INCOMPLETE][87] ([fdo#103540]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - shard-tglb:         [FAIL][89] ([fdo#103167]) -> [PASS][90] +4 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][91] ([fdo#103167]) -> [PASS][92] +4 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [DMESG-WARN][93] ([fdo#108566]) -> [PASS][94] +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-skl:          [INCOMPLETE][95] ([fdo#104108]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
    - shard-tglb:         [INCOMPLETE][97] ([fdo#111832] / [fdo#111850]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][99] ([fdo#108145]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][101] ([fdo#109642] / [fdo#111068]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_sprite_plane_mo

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69540/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7354_full -> Patchwork_15287_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15287_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15287_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15287_full:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-apl:          [PASS][1] -> [DMESG-FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  
#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_exec_parse_blt@batch-invalid-length}:
    - shard-tglb:         NOTRUN -> [SKIP][3] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb9/igt@gem_exec_parse_blt@batch-invalid-length.html

  * {igt@gem_exec_parse_blt@bb-start-cmd}:
    - shard-iclb:         NOTRUN -> [SKIP][4]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb6/igt@gem_exec_parse_blt@bb-start-cmd.html

  
Known issues
------------

  Here are the changes found in Patchwork_15287_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [PASS][5] -> [SKIP][6] ([fdo#112080]) +13 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb4/igt@gem_busy@busy-vcs1.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb5/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([fdo#111832])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb7/igt@gem_ctx_isolation@bcs0-s3.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb1/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276] / [fdo#112080]) +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([fdo#112146]) +7 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-tglb:         [PASS][13] -> [INCOMPLETE][14] ([fdo#111736] / [fdo#111850])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb1/igt@gem_exec_suspend@basic-s3.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb8/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_sync@basic-all:
    - shard-tglb:         [PASS][15] -> [INCOMPLETE][16] ([fdo#111647])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb7/igt@gem_sync@basic-all.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb6/igt@gem_sync@basic-all.html

  * igt@gem_sync@basic-each:
    - shard-tglb:         [PASS][17] -> [INCOMPLETE][18] ([fdo#111998])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb4/igt@gem_sync@basic-each.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb7/igt@gem_sync@basic-each.html

  * igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
    - shard-hsw:          [PASS][19] -> [DMESG-WARN][20] ([fdo#111870])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw2/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw5/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-snb:          [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +2 similar issues
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-snb7/igt@gem_userptr_blits@sync-unmap-cycles.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-snb1/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][23] -> [DMESG-FAIL][24] ([fdo#111991])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw7/igt@i915_selftest@live_hangcheck.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw7/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@sysfs-reader:
    - shard-tglb:         [PASS][25] -> [INCOMPLETE][26] ([fdo#111832] / [fdo#111850]) +2 similar issues
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb3/igt@i915_suspend@sysfs-reader.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb8/igt@i915_suspend@sysfs-reader.html

  * igt@kms_color@pipe-a-ctm-red-to-blue:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#107201])
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl5/igt@kms_color@pipe-a-ctm-red-to-blue.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl10/igt@kms_color@pipe-a-ctm-red-to-blue.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-tglb:         [PASS][29] -> [INCOMPLETE][30] ([fdo#111747] / [fdo#111832] / [fdo#111850])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@kms_fbcon_fbt@fbc-suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb4/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][31] -> [DMESG-WARN][32] ([fdo#108566]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-iclb:         [PASS][33] -> [FAIL][34] ([fdo#103167]) +8 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_frontbuffer_tracking@fbcpsr-stridechange:
    - shard-tglb:         [PASS][35] -> [FAIL][36] ([fdo#103167]) +1 similar issue
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-stridechange.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [PASS][37] -> [DMESG-WARN][38] ([fdo#108566]) +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-kbl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane_lowres@pipe-a-tiling-x:
    - shard-iclb:         [PASS][39] -> [FAIL][40] ([fdo#103166])
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb6/igt@kms_plane_lowres@pipe-a-tiling-x.html

  * igt@kms_psr@psr2_cursor_render:
    - shard-iclb:         [PASS][41] -> [SKIP][42] ([fdo#109441]) +1 similar issue
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb4/igt@kms_psr@psr2_cursor_render.html

  * igt@kms_vblank@pipe-d-ts-continuation-suspend:
    - shard-tglb:         [PASS][43] -> [INCOMPLETE][44] ([fdo#111850]) +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-suspend.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb3/igt@kms_vblank@pipe-d-ts-continuation-suspend.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [PASS][45] -> [SKIP][46] ([fdo#109276]) +21 similar issues
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@prime_busy@hang-bsd2.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb3/igt@prime_busy@hang-bsd2.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@rcs0-s3:
    - shard-apl:          [DMESG-WARN][47] ([fdo#108566]) -> [PASS][48] +2 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl4/igt@gem_ctx_isolation@rcs0-s3.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl8/igt@gem_ctx_isolation@rcs0-s3.html

  * igt@gem_ctx_isolation@vecs0-s3:
    - shard-tglb:         [INCOMPLETE][49] ([fdo#111832]) -> [PASS][50]
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb7/igt@gem_ctx_isolation@vecs0-s3.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb8/igt@gem_ctx_isolation@vecs0-s3.html

  * igt@gem_ctx_persistence@vcs1-mixed-process:
    - shard-iclb:         [SKIP][51] ([fdo#109276] / [fdo#112080]) -> [PASS][52] +5 similar issues
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb3/igt@gem_ctx_persistence@vcs1-mixed-process.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed-process.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][53] ([fdo#110841]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_ctx_switch@queue-light:
    - shard-tglb:         [INCOMPLETE][55] ([fdo#111672]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@gem_ctx_switch@queue-light.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb9/igt@gem_ctx_switch@queue-light.html

  * igt@gem_ctx_switch@vcs1:
    - shard-iclb:         [SKIP][57] ([fdo#112080]) -> [PASS][58] +9 similar issues
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb3/igt@gem_ctx_switch@vcs1.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@gem_ctx_switch@vcs1.html

  * igt@gem_exec_balancer@smoke:
    - shard-iclb:         [SKIP][59] ([fdo#110854]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb8/igt@gem_exec_balancer@smoke.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb4/igt@gem_exec_balancer@smoke.html

  * igt@gem_exec_nop@basic-series:
    - shard-tglb:         [INCOMPLETE][61] ([fdo#111747]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@gem_exec_nop@basic-series.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb2/igt@gem_exec_nop@basic-series.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-blt:
    - shard-tglb:         [INCOMPLETE][63] ([fdo#111606] / [fdo#111677]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb4/igt@gem_exec_schedule@preempt-queue-contexts-chain-blt.html

  * igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd:
    - shard-iclb:         [SKIP][65] ([fdo#112146]) -> [PASS][66] +8 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb1/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb7/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd.html

  * igt@gem_exec_schedule@promotion-bsd1:
    - shard-iclb:         [SKIP][67] ([fdo#109276]) -> [PASS][68] +22 similar issues
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb8/igt@gem_exec_schedule@promotion-bsd1.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb4/igt@gem_exec_schedule@promotion-bsd1.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive:
    - shard-apl:          [TIMEOUT][69] ([fdo#112113]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-apl8/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-apl3/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
    - shard-hsw:          [FAIL][71] ([fdo#112037]) -> [PASS][72]
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-glk:          [DMESG-FAIL][73] -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-glk9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-glk9/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_userptr_blits@sync-unmap-cycles:
    - shard-hsw:          [DMESG-WARN][75] ([fdo#111870]) -> [PASS][76] +2 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw2/igt@gem_userptr_blits@sync-unmap-cycles.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw1/igt@gem_userptr_blits@sync-unmap-cycles.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][77] ([fdo#111830 ]) -> [PASS][78]
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb4/igt@i915_pm_dc@dc6-psr.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb3/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-skl:          [INCOMPLETE][79] ([fdo#104108] / [fdo#107807]) -> [PASS][80]
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl5/igt@i915_pm_rpm@system-suspend-execbuf.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl6/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         [FAIL][81] ([fdo#111409]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb7/igt@i915_pm_rps@min-max-config-loaded.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb1/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
    - shard-glk:          [FAIL][83] ([fdo#100368]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-glk1/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate-interruptible.html

  * igt@kms_flip@dpms-vs-vblank-race-interruptible:
    - shard-hsw:          [DMESG-FAIL][85] ([fdo#102614]) -> [PASS][86] +1 similar issue
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw5/igt@kms_flip@dpms-vs-vblank-race-interruptible.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw2/igt@kms_flip@dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-hsw:          [INCOMPLETE][87] ([fdo#103540]) -> [PASS][88]
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-hsw2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-hsw1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
    - shard-tglb:         [FAIL][89] ([fdo#103167]) -> [PASS][90] +4 similar issues
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite:
    - shard-iclb:         [FAIL][91] ([fdo#103167]) -> [PASS][92] +4 similar issues
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-pri-indfb-draw-pwrite.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [DMESG-WARN][93] ([fdo#108566]) -> [PASS][94] +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
    - shard-skl:          [INCOMPLETE][95] ([fdo#104108]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
    - shard-tglb:         [INCOMPLETE][97] ([fdo#111832] / [fdo#111850]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-tglb1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-tglb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html

  * igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
    - shard-skl:          [FAIL][99] ([fdo#108145]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-skl2/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][101] ([fdo#109642] / [fdo#111068]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7354/shard-iclb3/igt@kms_psr2_su@frontbuffer.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_sprite_plane_mo

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15287/index.html
_______________________________________________
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Re: [PATCH v2 10/10] drm/i915/dsi: add support for DSC

[Kulkarni, Vandita]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Friday, November 15, 2019 9:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com
> Subject: [PATCH v2 10/10] drm/i915/dsi: add support for DSC
> 
> Enable DSC for DSI, if specified in VBT.
> 
> This is now excessively dynamic, being enabled at compute config. I don't
> expect us to need to switch between DSC and non-DSC for the same panel.
> Cargo culting the DP DSC shows.
> 
> Mode valid lacks a sensible implementation, as does get config.
> 
> v3: take compressed bpp into account
> 
> v2: Nuke conn_state->max_requested_bpc, it's not used on DSI
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> 
> ---
> 
> The burst mode stuff wrt DSC are still whatever, but at least we should be
> taking DSC better into account in port clock calculations.
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 113 ++++++++++++++++++++-----
>  1 file changed, 94 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index d576f29cef75..dc87134f5c27 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,6 +34,7 @@
>  #include "intel_ddi.h"
>  #include "intel_dsi.h"
>  #include "intel_panel.h"
> +#include "intel_vdsc.h"
> 
>  static inline int header_credits_available(struct drm_i915_private *dev_priv,
>  					   enum transcoder dsi_trans)
> @@ -302,17 +303,22 @@ static void configure_dual_link_mode(struct
> intel_encoder *encoder,  }
> 
>  /* aka DSI 8X clock */
> -static int afe_clk(struct intel_encoder *encoder)
> +static int afe_clk(struct intel_encoder *encoder,
> +		   const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	int bpp;
> 
> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> +	if (crtc_state->dsc.compression_enable)
> +		bpp = crtc_state->dsc.compressed_bpp;
> +	else
> +		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
>  	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi-
> >lane_count);  }
> 
> -static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
> +static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
> +					  const struct intel_crtc_state
> *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 320,7 +326,7 @@ static void gen11_dsi_program_esc_clk_div(struct
> intel_encoder *encoder)
>  	int afe_clk_khz;
>  	u32 esc_clk_div_m;
> 
> -	afe_clk_khz = afe_clk(encoder);
> +	afe_clk_khz = afe_clk(encoder, crtc_state);
>  	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
> 
>  	for_each_dsi_port(port, intel_dsi->ports) { @@ -498,7 +504,9 @@
> static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>  	}
>  }
> 
> -static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> +static void
> +gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 539,7 +547,7 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
>  	 * leave all fields at HW default values.
>  	 */
>  	if (IS_GEN(dev_priv, 11)) {
> -		if (afe_clk(encoder) <= 800000) {
> +		if (afe_clk(encoder, crtc_state) <= 800000) {
>  			for_each_dsi_port(port, intel_dsi->ports) {
>  				tmp =
> I915_READ(DPHY_TA_TIMING_PARAM(port));
>  				tmp &= ~TA_SURE_MASK;
> @@ -649,7 +657,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder
> *encoder,
>  			tmp |= EOTP_DISABLED;
> 
>  		/* enable link calibration if freq > 1.5Gbps */
> -		if (afe_clk(encoder) >= 1500 * 1000) {
> +		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
>  			tmp &= ~LINK_CALIBRATION_MASK;
>  			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
>  		}
> @@ -915,7 +923,8 @@ static void gen11_dsi_enable_transcoder(struct
> intel_encoder *encoder)
>  	}
>  }
> 
> -static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
> +				     const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 930,7 +939,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder
> *encoder)
>  	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
>  	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
>  	 */
> -	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
> +	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state)
> +* 1000;
>  	mul = 8 * 1000000;
>  	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
>  				     divisor);
> @@ -966,7 +975,7 @@ static void gen11_dsi_setup_timeouts(struct
> intel_encoder *encoder)
> 
>  static void
>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> -			      const struct intel_crtc_state *pipe_config)
> +			      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
> @@ -983,13 +992,13 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
>  	gen11_dsi_enable_ddi_buffer(encoder);
> 
>  	/* setup D-PHY timings */
> -	gen11_dsi_setup_dphy_timings(encoder);
> +	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
> 
>  	/* step 4h: setup DSI protocol timeouts */
> -	gen11_dsi_setup_timeouts(encoder);
> +	gen11_dsi_setup_timeouts(encoder, crtc_state);
> 
>  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> -	gen11_dsi_configure_transcoder(encoder, pipe_config);
> +	gen11_dsi_configure_transcoder(encoder, crtc_state);
> 
>  	/* Step 4l: Gate DDI clocks */
>  	if (IS_GEN(dev_priv, 11))
> @@ -1036,14 +1045,14 @@ static void gen11_dsi_powerup_panel(struct
> intel_encoder *encoder)  }
> 
>  static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
> -				     const struct intel_crtc_state *pipe_config,
> +				     const struct intel_crtc_state *crtc_state,
>  				     const struct drm_connector_state
> *conn_state)  {
>  	/* step2: enable IO power */
>  	gen11_dsi_enable_io_power(encoder);
> 
>  	/* step3: enable DSI PLL */
> -	gen11_dsi_program_esc_clk_div(encoder);
> +	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
>  }
> 
>  static void gen11_dsi_pre_enable(struct intel_encoder *encoder, @@ -
> 1061,6 +1070,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder
> *encoder,
>  	/* step5: program and powerup panel */
>  	gen11_dsi_powerup_panel(encoder);
> 
> +	/* FIXME: location? */
> +	intel_dsc_enable(encoder, pipe_config);
> +
>  	/* step6c: configure transcoder timings */
>  	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> 
> @@ -1222,6 +1234,13 @@ static void gen11_dsi_disable(struct
> intel_encoder *encoder,
>  	gen11_dsi_disable_io_power(encoder);
>  }
> 
> +static enum drm_mode_status gen11_dsi_mode_valid(struct
> drm_connector *connector,
> +						 struct drm_display_mode
> *mode)
> +{
> +	/* FIXME: DSC? */
> +	return intel_dsi_mode_valid(connector, mode); }
> +
>  static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>  				  struct intel_crtc_state *pipe_config)  { @@ -
> 1269,6 +1288,53 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
>  	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);  }
> 
> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
> +					struct intel_crtc_state *pipe_config) {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> +	struct drm_display_mode *adjusted_mode = &pipe_config-
> >hw.adjusted_mode;
> +	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
> +	bool use_dsc;
> +	int ret;
> +
> +	use_dsc = intel_bios_get_dsc_params(encoder, pipe_config,
> dsc_max_bpc);
> +	if (!use_dsc)
> +		return 0;
> +
> +	if (pipe_config->pipe_bpp < 8 * 3)
> +		return -EINVAL;
> +
> +	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
> +		if (pipe_config->dsc.slice_count > 1) {
> +			pipe_config->dsc.dsc_split = true;
> +		} else {
> +			DRM_DEBUG_KMS("Cannot split stream to use 2
> VDSC instances\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	vdsc_cfg->convert_rgb = false;
> +
> +	ret = intel_dsc_compute_params(encoder, pipe_config);
> +	if (ret)
> +		return ret;
> +
> +	/* DSI specific sanity checks on the common code */
> +	WARN_ON(vdsc_cfg->vbr_enable);
> +	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
> +	WARN_ON(vdsc_cfg->slice_height < 8);
> +	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
> +
> +	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
> +	if (ret)
> +		return ret;
> +
> +	pipe_config->dsc.compression_enable = true;
> +
> +	return 0;
> +}
> +
>  static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>  				    struct intel_crtc_state *pipe_config,
>  				    struct drm_connector_state *conn_state)
> @@ -1300,7 +1366,11 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
>  		pipe_config->pipe_bpp = 18;

TRANS_DSI_FUNC_CONF register needs to be updated with pixel format as compressed(0x6)
Should we be having pipe_config->output_format = compressed ?

Thanks,
Vandita
> 
>  	pipe_config->clock_set = true;
> -	pipe_config->port_clock = afe_clk(encoder) / 5;
> +
> +	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
> +		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
> +
> +	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
> 
>  	return 0;
>  }
> @@ -1308,8 +1378,13 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,  static void gen11_dsi_get_power_domains(struct
> intel_encoder *encoder,
>  					struct intel_crtc_state *crtc_state)  {
> -	get_dsi_io_power_domains(to_i915(encoder->base.dev),
> -				 enc_to_intel_dsi(&encoder->base));
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> +	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
> >base));
> +
> +	if (crtc_state->dsc.compression_enable)
> +		intel_display_power_get(i915,
> +
> 	intel_dsc_power_domain(crtc_state));
>  }
> 
>  static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
> 1379,7 +1454,7 @@ static const struct drm_connector_funcs
> gen11_dsi_connector_funcs = {
> 
>  static const struct drm_connector_helper_funcs
> gen11_dsi_connector_helper_funcs = {
>  	.get_modes = intel_dsi_get_modes,
> -	.mode_valid = intel_dsi_mode_valid,
> +	.mode_valid = gen11_dsi_mode_valid,
>  	.atomic_check = intel_digital_connector_atomic_check,
>  };
> 
> --
> 2.20.1

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Re: [Intel-gfx] [PATCH v2 10/10] drm/i915/dsi: add support for DSC

[Kulkarni, Vandita]

> -----Original Message-----
> From: Jani Nikula <jani.nikula@intel.com>
> Sent: Friday, November 15, 2019 9:04 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com
> Subject: [PATCH v2 10/10] drm/i915/dsi: add support for DSC
> 
> Enable DSC for DSI, if specified in VBT.
> 
> This is now excessively dynamic, being enabled at compute config. I don't
> expect us to need to switch between DSC and non-DSC for the same panel.
> Cargo culting the DP DSC shows.
> 
> Mode valid lacks a sensible implementation, as does get config.
> 
> v3: take compressed bpp into account
> 
> v2: Nuke conn_state->max_requested_bpc, it's not used on DSI
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> 
> ---
> 
> The burst mode stuff wrt DSC are still whatever, but at least we should be
> taking DSC better into account in port clock calculations.
> ---
>  drivers/gpu/drm/i915/display/icl_dsi.c | 113 ++++++++++++++++++++-----
>  1 file changed, 94 insertions(+), 19 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
> b/drivers/gpu/drm/i915/display/icl_dsi.c
> index d576f29cef75..dc87134f5c27 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -34,6 +34,7 @@
>  #include "intel_ddi.h"
>  #include "intel_dsi.h"
>  #include "intel_panel.h"
> +#include "intel_vdsc.h"
> 
>  static inline int header_credits_available(struct drm_i915_private *dev_priv,
>  					   enum transcoder dsi_trans)
> @@ -302,17 +303,22 @@ static void configure_dual_link_mode(struct
> intel_encoder *encoder,  }
> 
>  /* aka DSI 8X clock */
> -static int afe_clk(struct intel_encoder *encoder)
> +static int afe_clk(struct intel_encoder *encoder,
> +		   const struct intel_crtc_state *crtc_state)
>  {
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>  	int bpp;
> 
> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
> +	if (crtc_state->dsc.compression_enable)
> +		bpp = crtc_state->dsc.compressed_bpp;
> +	else
> +		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
> >pixel_format);
> 
>  	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi-
> >lane_count);  }
> 
> -static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
> +static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
> +					  const struct intel_crtc_state
> *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 320,7 +326,7 @@ static void gen11_dsi_program_esc_clk_div(struct
> intel_encoder *encoder)
>  	int afe_clk_khz;
>  	u32 esc_clk_div_m;
> 
> -	afe_clk_khz = afe_clk(encoder);
> +	afe_clk_khz = afe_clk(encoder, crtc_state);
>  	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
> 
>  	for_each_dsi_port(port, intel_dsi->ports) { @@ -498,7 +504,9 @@
> static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>  	}
>  }
> 
> -static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
> +static void
> +gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
> +			     const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 539,7 +547,7 @@ static void gen11_dsi_setup_dphy_timings(struct
> intel_encoder *encoder)
>  	 * leave all fields at HW default values.
>  	 */
>  	if (IS_GEN(dev_priv, 11)) {
> -		if (afe_clk(encoder) <= 800000) {
> +		if (afe_clk(encoder, crtc_state) <= 800000) {
>  			for_each_dsi_port(port, intel_dsi->ports) {
>  				tmp =
> I915_READ(DPHY_TA_TIMING_PARAM(port));
>  				tmp &= ~TA_SURE_MASK;
> @@ -649,7 +657,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder
> *encoder,
>  			tmp |= EOTP_DISABLED;
> 
>  		/* enable link calibration if freq > 1.5Gbps */
> -		if (afe_clk(encoder) >= 1500 * 1000) {
> +		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
>  			tmp &= ~LINK_CALIBRATION_MASK;
>  			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
>  		}
> @@ -915,7 +923,8 @@ static void gen11_dsi_enable_transcoder(struct
> intel_encoder *encoder)
>  	}
>  }
> 
> -static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
> +				     const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
> 930,7 +939,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder
> *encoder)
>  	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
>  	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
>  	 */
> -	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
> +	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state)
> +* 1000;
>  	mul = 8 * 1000000;
>  	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
>  				     divisor);
> @@ -966,7 +975,7 @@ static void gen11_dsi_setup_timeouts(struct
> intel_encoder *encoder)
> 
>  static void
>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
> -			      const struct intel_crtc_state *pipe_config)
> +			      const struct intel_crtc_state *crtc_state)
>  {
>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> 
> @@ -983,13 +992,13 @@ gen11_dsi_enable_port_and_phy(struct
> intel_encoder *encoder,
>  	gen11_dsi_enable_ddi_buffer(encoder);
> 
>  	/* setup D-PHY timings */
> -	gen11_dsi_setup_dphy_timings(encoder);
> +	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
> 
>  	/* step 4h: setup DSI protocol timeouts */
> -	gen11_dsi_setup_timeouts(encoder);
> +	gen11_dsi_setup_timeouts(encoder, crtc_state);
> 
>  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
> -	gen11_dsi_configure_transcoder(encoder, pipe_config);
> +	gen11_dsi_configure_transcoder(encoder, crtc_state);
> 
>  	/* Step 4l: Gate DDI clocks */
>  	if (IS_GEN(dev_priv, 11))
> @@ -1036,14 +1045,14 @@ static void gen11_dsi_powerup_panel(struct
> intel_encoder *encoder)  }
> 
>  static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
> -				     const struct intel_crtc_state *pipe_config,
> +				     const struct intel_crtc_state *crtc_state,
>  				     const struct drm_connector_state
> *conn_state)  {
>  	/* step2: enable IO power */
>  	gen11_dsi_enable_io_power(encoder);
> 
>  	/* step3: enable DSI PLL */
> -	gen11_dsi_program_esc_clk_div(encoder);
> +	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
>  }
> 
>  static void gen11_dsi_pre_enable(struct intel_encoder *encoder, @@ -
> 1061,6 +1070,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder
> *encoder,
>  	/* step5: program and powerup panel */
>  	gen11_dsi_powerup_panel(encoder);
> 
> +	/* FIXME: location? */
> +	intel_dsc_enable(encoder, pipe_config);
> +
>  	/* step6c: configure transcoder timings */
>  	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
> 
> @@ -1222,6 +1234,13 @@ static void gen11_dsi_disable(struct
> intel_encoder *encoder,
>  	gen11_dsi_disable_io_power(encoder);
>  }
> 
> +static enum drm_mode_status gen11_dsi_mode_valid(struct
> drm_connector *connector,
> +						 struct drm_display_mode
> *mode)
> +{
> +	/* FIXME: DSC? */
> +	return intel_dsi_mode_valid(connector, mode); }
> +
>  static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>  				  struct intel_crtc_state *pipe_config)  { @@ -
> 1269,6 +1288,53 @@ static void gen11_dsi_get_config(struct intel_encoder
> *encoder,
>  	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);  }
> 
> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
> +					struct intel_crtc_state *pipe_config) {
> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> +	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
> +	struct drm_display_mode *adjusted_mode = &pipe_config-
> >hw.adjusted_mode;
> +	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
> +	bool use_dsc;
> +	int ret;
> +
> +	use_dsc = intel_bios_get_dsc_params(encoder, pipe_config,
> dsc_max_bpc);
> +	if (!use_dsc)
> +		return 0;
> +
> +	if (pipe_config->pipe_bpp < 8 * 3)
> +		return -EINVAL;
> +
> +	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
> +		if (pipe_config->dsc.slice_count > 1) {
> +			pipe_config->dsc.dsc_split = true;
> +		} else {
> +			DRM_DEBUG_KMS("Cannot split stream to use 2
> VDSC instances\n");
> +			return -EINVAL;
> +		}
> +	}
> +
> +	vdsc_cfg->convert_rgb = false;
> +
> +	ret = intel_dsc_compute_params(encoder, pipe_config);
> +	if (ret)
> +		return ret;
> +
> +	/* DSI specific sanity checks on the common code */
> +	WARN_ON(vdsc_cfg->vbr_enable);
> +	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
> +	WARN_ON(vdsc_cfg->slice_height < 8);
> +	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
> +
> +	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
> +	if (ret)
> +		return ret;
> +
> +	pipe_config->dsc.compression_enable = true;
> +
> +	return 0;
> +}
> +
>  static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>  				    struct intel_crtc_state *pipe_config,
>  				    struct drm_connector_state *conn_state)
> @@ -1300,7 +1366,11 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,
>  		pipe_config->pipe_bpp = 18;

TRANS_DSI_FUNC_CONF register needs to be updated with pixel format as compressed(0x6)
Should we be having pipe_config->output_format = compressed ?

Thanks,
Vandita
> 
>  	pipe_config->clock_set = true;
> -	pipe_config->port_clock = afe_clk(encoder) / 5;
> +
> +	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
> +		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
> +
> +	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
> 
>  	return 0;
>  }
> @@ -1308,8 +1378,13 @@ static int gen11_dsi_compute_config(struct
> intel_encoder *encoder,  static void gen11_dsi_get_power_domains(struct
> intel_encoder *encoder,
>  					struct intel_crtc_state *crtc_state)  {
> -	get_dsi_io_power_domains(to_i915(encoder->base.dev),
> -				 enc_to_intel_dsi(&encoder->base));
> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> +
> +	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
> >base));
> +
> +	if (crtc_state->dsc.compression_enable)
> +		intel_display_power_get(i915,
> +
> 	intel_dsc_power_domain(crtc_state));
>  }
> 
>  static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
> 1379,7 +1454,7 @@ static const struct drm_connector_funcs
> gen11_dsi_connector_funcs = {
> 
>  static const struct drm_connector_helper_funcs
> gen11_dsi_connector_helper_funcs = {
>  	.get_modes = intel_dsi_get_modes,
> -	.mode_valid = intel_dsi_mode_valid,
> +	.mode_valid = gen11_dsi_mode_valid,
>  	.atomic_check = intel_digital_connector_atomic_check,
>  };
> 
> --
> 2.20.1

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Re: [PATCH v2 10/10] drm/i915/dsi: add support for DSC

[Jani Nikula]

On Wed, 20 Nov 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@intel.com>
>> Sent: Friday, November 15, 2019 9:04 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com
>> Subject: [PATCH v2 10/10] drm/i915/dsi: add support for DSC
>> 
>> Enable DSC for DSI, if specified in VBT.
>> 
>> This is now excessively dynamic, being enabled at compute config. I don't
>> expect us to need to switch between DSC and non-DSC for the same panel.
>> Cargo culting the DP DSC shows.
>> 
>> Mode valid lacks a sensible implementation, as does get config.
>> 
>> v3: take compressed bpp into account
>> 
>> v2: Nuke conn_state->max_requested_bpc, it's not used on DSI
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> ---
>> 
>> The burst mode stuff wrt DSC are still whatever, but at least we should be
>> taking DSC better into account in port clock calculations.
>> ---
>>  drivers/gpu/drm/i915/display/icl_dsi.c | 113 ++++++++++++++++++++-----
>>  1 file changed, 94 insertions(+), 19 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index d576f29cef75..dc87134f5c27 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -34,6 +34,7 @@
>>  #include "intel_ddi.h"
>>  #include "intel_dsi.h"
>>  #include "intel_panel.h"
>> +#include "intel_vdsc.h"
>> 
>>  static inline int header_credits_available(struct drm_i915_private *dev_priv,
>>  					   enum transcoder dsi_trans)
>> @@ -302,17 +303,22 @@ static void configure_dual_link_mode(struct
>> intel_encoder *encoder,  }
>> 
>>  /* aka DSI 8X clock */
>> -static int afe_clk(struct intel_encoder *encoder)
>> +static int afe_clk(struct intel_encoder *encoder,
>> +		   const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>  	int bpp;
>> 
>> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>> +	if (crtc_state->dsc.compression_enable)
>> +		bpp = crtc_state->dsc.compressed_bpp;
>> +	else
>> +		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
>> >pixel_format);
>> 
>>  	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi-
>> >lane_count);  }
>> 
>> -static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>> +static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
>> +					  const struct intel_crtc_state
>> *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
>> 320,7 +326,7 @@ static void gen11_dsi_program_esc_clk_div(struct
>> intel_encoder *encoder)
>>  	int afe_clk_khz;
>>  	u32 esc_clk_div_m;
>> 
>> -	afe_clk_khz = afe_clk(encoder);
>> +	afe_clk_khz = afe_clk(encoder, crtc_state);
>>  	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
>> 
>>  	for_each_dsi_port(port, intel_dsi->ports) { @@ -498,7 +504,9 @@
>> static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>>  	}
>>  }
>> 
>> -static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>> +static void
>> +gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
>> +			     const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
>> 539,7 +547,7 @@ static void gen11_dsi_setup_dphy_timings(struct
>> intel_encoder *encoder)
>>  	 * leave all fields at HW default values.
>>  	 */
>>  	if (IS_GEN(dev_priv, 11)) {
>> -		if (afe_clk(encoder) <= 800000) {
>> +		if (afe_clk(encoder, crtc_state) <= 800000) {
>>  			for_each_dsi_port(port, intel_dsi->ports) {
>>  				tmp =
>> I915_READ(DPHY_TA_TIMING_PARAM(port));
>>  				tmp &= ~TA_SURE_MASK;
>> @@ -649,7 +657,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder
>> *encoder,
>>  			tmp |= EOTP_DISABLED;
>> 
>>  		/* enable link calibration if freq > 1.5Gbps */
>> -		if (afe_clk(encoder) >= 1500 * 1000) {
>> +		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
>>  			tmp &= ~LINK_CALIBRATION_MASK;
>>  			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
>>  		}
>> @@ -915,7 +923,8 @@ static void gen11_dsi_enable_transcoder(struct
>> intel_encoder *encoder)
>>  	}
>>  }
>> 
>> -static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
>> +				     const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
>> 930,7 +939,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder
>> *encoder)
>>  	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
>>  	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
>>  	 */
>> -	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
>> +	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state)
>> +* 1000;
>>  	mul = 8 * 1000000;
>>  	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
>>  				     divisor);
>> @@ -966,7 +975,7 @@ static void gen11_dsi_setup_timeouts(struct
>> intel_encoder *encoder)
>> 
>>  static void
>>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> -			      const struct intel_crtc_state *pipe_config)
>> +			      const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> 
>> @@ -983,13 +992,13 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>>  	gen11_dsi_enable_ddi_buffer(encoder);
>> 
>>  	/* setup D-PHY timings */
>> -	gen11_dsi_setup_dphy_timings(encoder);
>> +	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
>> 
>>  	/* step 4h: setup DSI protocol timeouts */
>> -	gen11_dsi_setup_timeouts(encoder);
>> +	gen11_dsi_setup_timeouts(encoder, crtc_state);
>> 
>>  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> -	gen11_dsi_configure_transcoder(encoder, pipe_config);
>> +	gen11_dsi_configure_transcoder(encoder, crtc_state);
>> 
>>  	/* Step 4l: Gate DDI clocks */
>>  	if (IS_GEN(dev_priv, 11))
>> @@ -1036,14 +1045,14 @@ static void gen11_dsi_powerup_panel(struct
>> intel_encoder *encoder)  }
>> 
>>  static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
>> -				     const struct intel_crtc_state *pipe_config,
>> +				     const struct intel_crtc_state *crtc_state,
>>  				     const struct drm_connector_state
>> *conn_state)  {
>>  	/* step2: enable IO power */
>>  	gen11_dsi_enable_io_power(encoder);
>> 
>>  	/* step3: enable DSI PLL */
>> -	gen11_dsi_program_esc_clk_div(encoder);
>> +	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
>>  }
>> 
>>  static void gen11_dsi_pre_enable(struct intel_encoder *encoder, @@ -
>> 1061,6 +1070,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder
>> *encoder,
>>  	/* step5: program and powerup panel */
>>  	gen11_dsi_powerup_panel(encoder);
>> 
>> +	/* FIXME: location? */
>> +	intel_dsc_enable(encoder, pipe_config);
>> +
>>  	/* step6c: configure transcoder timings */
>>  	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>> 
>> @@ -1222,6 +1234,13 @@ static void gen11_dsi_disable(struct
>> intel_encoder *encoder,
>>  	gen11_dsi_disable_io_power(encoder);
>>  }
>> 
>> +static enum drm_mode_status gen11_dsi_mode_valid(struct
>> drm_connector *connector,
>> +						 struct drm_display_mode
>> *mode)
>> +{
>> +	/* FIXME: DSC? */
>> +	return intel_dsi_mode_valid(connector, mode); }
>> +
>>  static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>>  				  struct intel_crtc_state *pipe_config)  { @@ -
>> 1269,6 +1288,53 @@ static void gen11_dsi_get_config(struct intel_encoder
>> *encoder,
>>  	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);  }
>> 
>> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>> +					struct intel_crtc_state *pipe_config) {
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
>> +	struct drm_display_mode *adjusted_mode = &pipe_config-
>> >hw.adjusted_mode;
>> +	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
>> +	bool use_dsc;
>> +	int ret;
>> +
>> +	use_dsc = intel_bios_get_dsc_params(encoder, pipe_config,
>> dsc_max_bpc);
>> +	if (!use_dsc)
>> +		return 0;
>> +
>> +	if (pipe_config->pipe_bpp < 8 * 3)
>> +		return -EINVAL;
>> +
>> +	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
>> +		if (pipe_config->dsc.slice_count > 1) {
>> +			pipe_config->dsc.dsc_split = true;
>> +		} else {
>> +			DRM_DEBUG_KMS("Cannot split stream to use 2
>> VDSC instances\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	vdsc_cfg->convert_rgb = false;
>> +
>> +	ret = intel_dsc_compute_params(encoder, pipe_config);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* DSI specific sanity checks on the common code */
>> +	WARN_ON(vdsc_cfg->vbr_enable);
>> +	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
>> +	WARN_ON(vdsc_cfg->slice_height < 8);
>> +	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
>> +
>> +	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
>> +	if (ret)
>> +		return ret;
>> +
>> +	pipe_config->dsc.compression_enable = true;
>> +
>> +	return 0;
>> +}
>> +
>>  static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>>  				    struct intel_crtc_state *pipe_config,
>>  				    struct drm_connector_state *conn_state)
>> @@ -1300,7 +1366,11 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>>  		pipe_config->pipe_bpp = 18;
>
> TRANS_DSI_FUNC_CONF register needs to be updated with pixel format as
> compressed(0x6)

Absolutely, this was a bit of a facepalm for me, as well as the
horizontal timing changes. Thanks for catching.

On that note, burst mode is also broken for ICL DSI, but that's another
worry for another day.

> Should we be having pipe_config->output_format = compressed ?

No, I think we need the real value there for actual pre-DSC engine pipe
stuff.

I'll send a couple of more patches in reply to the cover letter for
testing. They'll need to be made part of the series better but I'm too
tired now.

BR,
Jani.


>
> Thanks,
> Vandita
>> 
>>  	pipe_config->clock_set = true;
>> -	pipe_config->port_clock = afe_clk(encoder) / 5;
>> +
>> +	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
>> +		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
>> +
>> +	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>> 
>>  	return 0;
>>  }
>> @@ -1308,8 +1378,13 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,  static void gen11_dsi_get_power_domains(struct
>> intel_encoder *encoder,
>>  					struct intel_crtc_state *crtc_state)  {
>> -	get_dsi_io_power_domains(to_i915(encoder->base.dev),
>> -				 enc_to_intel_dsi(&encoder->base));
>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +
>> +	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
>> >base));
>> +
>> +	if (crtc_state->dsc.compression_enable)
>> +		intel_display_power_get(i915,
>> +
>> 	intel_dsc_power_domain(crtc_state));
>>  }
>> 
>>  static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
>> 1379,7 +1454,7 @@ static const struct drm_connector_funcs
>> gen11_dsi_connector_funcs = {
>> 
>>  static const struct drm_connector_helper_funcs
>> gen11_dsi_connector_helper_funcs = {
>>  	.get_modes = intel_dsi_get_modes,
>> -	.mode_valid = intel_dsi_mode_valid,
>> +	.mode_valid = gen11_dsi_mode_valid,
>>  	.atomic_check = intel_digital_connector_atomic_check,
>>  };
>> 
>> --
>> 2.20.1
>

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [Intel-gfx] [PATCH v2 10/10] drm/i915/dsi: add support for DSC

[Jani Nikula]

On Wed, 20 Nov 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote:
>> -----Original Message-----
>> From: Jani Nikula <jani.nikula@intel.com>
>> Sent: Friday, November 15, 2019 9:04 PM
>> To: intel-gfx@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Kulkarni, Vandita
>> <vandita.kulkarni@intel.com>; ville.syrjala@linux.intel.com
>> Subject: [PATCH v2 10/10] drm/i915/dsi: add support for DSC
>> 
>> Enable DSC for DSI, if specified in VBT.
>> 
>> This is now excessively dynamic, being enabled at compute config. I don't
>> expect us to need to switch between DSC and non-DSC for the same panel.
>> Cargo culting the DP DSC shows.
>> 
>> Mode valid lacks a sensible implementation, as does get config.
>> 
>> v3: take compressed bpp into account
>> 
>> v2: Nuke conn_state->max_requested_bpc, it's not used on DSI
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> 
>> ---
>> 
>> The burst mode stuff wrt DSC are still whatever, but at least we should be
>> taking DSC better into account in port clock calculations.
>> ---
>>  drivers/gpu/drm/i915/display/icl_dsi.c | 113 ++++++++++++++++++++-----
>>  1 file changed, 94 insertions(+), 19 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c
>> b/drivers/gpu/drm/i915/display/icl_dsi.c
>> index d576f29cef75..dc87134f5c27 100644
>> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
>> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
>> @@ -34,6 +34,7 @@
>>  #include "intel_ddi.h"
>>  #include "intel_dsi.h"
>>  #include "intel_panel.h"
>> +#include "intel_vdsc.h"
>> 
>>  static inline int header_credits_available(struct drm_i915_private *dev_priv,
>>  					   enum transcoder dsi_trans)
>> @@ -302,17 +303,22 @@ static void configure_dual_link_mode(struct
>> intel_encoder *encoder,  }
>> 
>>  /* aka DSI 8X clock */
>> -static int afe_clk(struct intel_encoder *encoder)
>> +static int afe_clk(struct intel_encoder *encoder,
>> +		   const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
>>  	int bpp;
>> 
>> -	bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
>> +	if (crtc_state->dsc.compression_enable)
>> +		bpp = crtc_state->dsc.compressed_bpp;
>> +	else
>> +		bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi-
>> >pixel_format);
>> 
>>  	return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi-
>> >lane_count);  }
>> 
>> -static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder)
>> +static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
>> +					  const struct intel_crtc_state
>> *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
>> 320,7 +326,7 @@ static void gen11_dsi_program_esc_clk_div(struct
>> intel_encoder *encoder)
>>  	int afe_clk_khz;
>>  	u32 esc_clk_div_m;
>> 
>> -	afe_clk_khz = afe_clk(encoder);
>> +	afe_clk_khz = afe_clk(encoder, crtc_state);
>>  	esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
>> 
>>  	for_each_dsi_port(port, intel_dsi->ports) { @@ -498,7 +504,9 @@
>> static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
>>  	}
>>  }
>> 
>> -static void gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder)
>> +static void
>> +gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
>> +			     const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
>> 539,7 +547,7 @@ static void gen11_dsi_setup_dphy_timings(struct
>> intel_encoder *encoder)
>>  	 * leave all fields at HW default values.
>>  	 */
>>  	if (IS_GEN(dev_priv, 11)) {
>> -		if (afe_clk(encoder) <= 800000) {
>> +		if (afe_clk(encoder, crtc_state) <= 800000) {
>>  			for_each_dsi_port(port, intel_dsi->ports) {
>>  				tmp =
>> I915_READ(DPHY_TA_TIMING_PARAM(port));
>>  				tmp &= ~TA_SURE_MASK;
>> @@ -649,7 +657,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder
>> *encoder,
>>  			tmp |= EOTP_DISABLED;
>> 
>>  		/* enable link calibration if freq > 1.5Gbps */
>> -		if (afe_clk(encoder) >= 1500 * 1000) {
>> +		if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
>>  			tmp &= ~LINK_CALIBRATION_MASK;
>>  			tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
>>  		}
>> @@ -915,7 +923,8 @@ static void gen11_dsi_enable_transcoder(struct
>> intel_encoder *encoder)
>>  	}
>>  }
>> 
>> -static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder)
>> +static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
>> +				     const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>>  	struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); @@ -
>> 930,7 +939,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder
>> *encoder)
>>  	 * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
>>  	 * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
>>  	 */
>> -	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder) * 1000;
>> +	divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state)
>> +* 1000;
>>  	mul = 8 * 1000000;
>>  	hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
>>  				     divisor);
>> @@ -966,7 +975,7 @@ static void gen11_dsi_setup_timeouts(struct
>> intel_encoder *encoder)
>> 
>>  static void
>>  gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>> -			      const struct intel_crtc_state *pipe_config)
>> +			      const struct intel_crtc_state *crtc_state)
>>  {
>>  	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> 
>> @@ -983,13 +992,13 @@ gen11_dsi_enable_port_and_phy(struct
>> intel_encoder *encoder,
>>  	gen11_dsi_enable_ddi_buffer(encoder);
>> 
>>  	/* setup D-PHY timings */
>> -	gen11_dsi_setup_dphy_timings(encoder);
>> +	gen11_dsi_setup_dphy_timings(encoder, crtc_state);
>> 
>>  	/* step 4h: setup DSI protocol timeouts */
>> -	gen11_dsi_setup_timeouts(encoder);
>> +	gen11_dsi_setup_timeouts(encoder, crtc_state);
>> 
>>  	/* Step (4h, 4i, 4j, 4k): Configure transcoder */
>> -	gen11_dsi_configure_transcoder(encoder, pipe_config);
>> +	gen11_dsi_configure_transcoder(encoder, crtc_state);
>> 
>>  	/* Step 4l: Gate DDI clocks */
>>  	if (IS_GEN(dev_priv, 11))
>> @@ -1036,14 +1045,14 @@ static void gen11_dsi_powerup_panel(struct
>> intel_encoder *encoder)  }
>> 
>>  static void gen11_dsi_pre_pll_enable(struct intel_encoder *encoder,
>> -				     const struct intel_crtc_state *pipe_config,
>> +				     const struct intel_crtc_state *crtc_state,
>>  				     const struct drm_connector_state
>> *conn_state)  {
>>  	/* step2: enable IO power */
>>  	gen11_dsi_enable_io_power(encoder);
>> 
>>  	/* step3: enable DSI PLL */
>> -	gen11_dsi_program_esc_clk_div(encoder);
>> +	gen11_dsi_program_esc_clk_div(encoder, crtc_state);
>>  }
>> 
>>  static void gen11_dsi_pre_enable(struct intel_encoder *encoder, @@ -
>> 1061,6 +1070,9 @@ static void gen11_dsi_pre_enable(struct intel_encoder
>> *encoder,
>>  	/* step5: program and powerup panel */
>>  	gen11_dsi_powerup_panel(encoder);
>> 
>> +	/* FIXME: location? */
>> +	intel_dsc_enable(encoder, pipe_config);
>> +
>>  	/* step6c: configure transcoder timings */
>>  	gen11_dsi_set_transcoder_timings(encoder, pipe_config);
>> 
>> @@ -1222,6 +1234,13 @@ static void gen11_dsi_disable(struct
>> intel_encoder *encoder,
>>  	gen11_dsi_disable_io_power(encoder);
>>  }
>> 
>> +static enum drm_mode_status gen11_dsi_mode_valid(struct
>> drm_connector *connector,
>> +						 struct drm_display_mode
>> *mode)
>> +{
>> +	/* FIXME: DSC? */
>> +	return intel_dsi_mode_valid(connector, mode); }
>> +
>>  static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>>  				  struct intel_crtc_state *pipe_config)  { @@ -
>> 1269,6 +1288,53 @@ static void gen11_dsi_get_config(struct intel_encoder
>> *encoder,
>>  	pipe_config->pipe_bpp = bdw_get_pipemisc_bpp(crtc);  }
>> 
>> +static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
>> +					struct intel_crtc_state *pipe_config) {
>> +	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>> +	struct drm_dsc_config *vdsc_cfg = &pipe_config->dsc.config;
>> +	struct drm_display_mode *adjusted_mode = &pipe_config-
>> >hw.adjusted_mode;
>> +	int dsc_max_bpc = INTEL_GEN(dev_priv) >= 12 ? 12 : 10;
>> +	bool use_dsc;
>> +	int ret;
>> +
>> +	use_dsc = intel_bios_get_dsc_params(encoder, pipe_config,
>> dsc_max_bpc);
>> +	if (!use_dsc)
>> +		return 0;
>> +
>> +	if (pipe_config->pipe_bpp < 8 * 3)
>> +		return -EINVAL;
>> +
>> +	if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) {
>> +		if (pipe_config->dsc.slice_count > 1) {
>> +			pipe_config->dsc.dsc_split = true;
>> +		} else {
>> +			DRM_DEBUG_KMS("Cannot split stream to use 2
>> VDSC instances\n");
>> +			return -EINVAL;
>> +		}
>> +	}
>> +
>> +	vdsc_cfg->convert_rgb = false;
>> +
>> +	ret = intel_dsc_compute_params(encoder, pipe_config);
>> +	if (ret)
>> +		return ret;
>> +
>> +	/* DSI specific sanity checks on the common code */
>> +	WARN_ON(vdsc_cfg->vbr_enable);
>> +	WARN_ON(vdsc_cfg->pic_width % vdsc_cfg->slice_width);
>> +	WARN_ON(vdsc_cfg->slice_height < 8);
>> +	WARN_ON(vdsc_cfg->pic_height % vdsc_cfg->slice_height);
>> +
>> +	ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
>> +	if (ret)
>> +		return ret;
>> +
>> +	pipe_config->dsc.compression_enable = true;
>> +
>> +	return 0;
>> +}
>> +
>>  static int gen11_dsi_compute_config(struct intel_encoder *encoder,
>>  				    struct intel_crtc_state *pipe_config,
>>  				    struct drm_connector_state *conn_state)
>> @@ -1300,7 +1366,11 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,
>>  		pipe_config->pipe_bpp = 18;
>
> TRANS_DSI_FUNC_CONF register needs to be updated with pixel format as
> compressed(0x6)

Absolutely, this was a bit of a facepalm for me, as well as the
horizontal timing changes. Thanks for catching.

On that note, burst mode is also broken for ICL DSI, but that's another
worry for another day.

> Should we be having pipe_config->output_format = compressed ?

No, I think we need the real value there for actual pre-DSC engine pipe
stuff.

I'll send a couple of more patches in reply to the cover letter for
testing. They'll need to be made part of the series better but I'm too
tired now.

BR,
Jani.


>
> Thanks,
> Vandita
>> 
>>  	pipe_config->clock_set = true;
>> -	pipe_config->port_clock = afe_clk(encoder) / 5;
>> +
>> +	if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
>> +		DRM_DEBUG_KMS("Attempting to use DSC failed\n");
>> +
>> +	pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>> 
>>  	return 0;
>>  }
>> @@ -1308,8 +1378,13 @@ static int gen11_dsi_compute_config(struct
>> intel_encoder *encoder,  static void gen11_dsi_get_power_domains(struct
>> intel_encoder *encoder,
>>  					struct intel_crtc_state *crtc_state)  {
>> -	get_dsi_io_power_domains(to_i915(encoder->base.dev),
>> -				 enc_to_intel_dsi(&encoder->base));
>> +	struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>> +
>> +	get_dsi_io_power_domains(i915, enc_to_intel_dsi(&encoder-
>> >base));
>> +
>> +	if (crtc_state->dsc.compression_enable)
>> +		intel_display_power_get(i915,
>> +
>> 	intel_dsc_power_domain(crtc_state));
>>  }
>> 
>>  static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder, @@ -
>> 1379,7 +1454,7 @@ static const struct drm_connector_funcs
>> gen11_dsi_connector_funcs = {
>> 
>>  static const struct drm_connector_helper_funcs
>> gen11_dsi_connector_helper_funcs = {
>>  	.get_modes = intel_dsi_get_modes,
>> -	.mode_valid = intel_dsi_mode_valid,
>> +	.mode_valid = gen11_dsi_mode_valid,
>>  	.atomic_check = intel_digital_connector_atomic_check,
>>  };
>> 
>> --
>> 2.20.1
>

-- 
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[PATCH 1/2] drm/i915/dsi: use compressed pixel format for DSC

[Jani Nikula]

FIXME: To be squashed to another patch.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index dc87134f5c27..f09e2e37d442 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -683,22 +683,26 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 
 		/* select pixel format */
 		tmp &= ~PIX_FMT_MASK;
-		switch (intel_dsi->pixel_format) {
-		default:
-			MISSING_CASE(intel_dsi->pixel_format);
-			/* fallthrough */
-		case MIPI_DSI_FMT_RGB565:
-			tmp |= PIX_FMT_RGB565;
-			break;
-		case MIPI_DSI_FMT_RGB666_PACKED:
-			tmp |= PIX_FMT_RGB666_PACKED;
-			break;
-		case MIPI_DSI_FMT_RGB666:
-			tmp |= PIX_FMT_RGB666_LOOSE;
-			break;
-		case MIPI_DSI_FMT_RGB888:
-			tmp |= PIX_FMT_RGB888;
-			break;
+		if (pipe_config->dsc.compression_enable) {
+			tmp |= PIX_FMT_COMPRESSED;
+		} else {
+			switch (intel_dsi->pixel_format) {
+			default:
+				MISSING_CASE(intel_dsi->pixel_format);
+				/* fallthrough */
+			case MIPI_DSI_FMT_RGB565:
+				tmp |= PIX_FMT_RGB565;
+				break;
+			case MIPI_DSI_FMT_RGB666_PACKED:
+				tmp |= PIX_FMT_RGB666_PACKED;
+				break;
+			case MIPI_DSI_FMT_RGB666:
+				tmp |= PIX_FMT_RGB666_LOOSE;
+				break;
+			case MIPI_DSI_FMT_RGB888:
+				tmp |= PIX_FMT_RGB888;
+				break;
+			}
 		}
 
 		if (INTEL_GEN(dev_priv) >= 12) {
-- 
2.20.1

_______________________________________________
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[Intel-gfx] [PATCH 1/2] drm/i915/dsi: use compressed pixel format for DSC

[Jani Nikula]

FIXME: To be squashed to another patch.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 36 ++++++++++++++------------
 1 file changed, 20 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index dc87134f5c27..f09e2e37d442 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -683,22 +683,26 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 
 		/* select pixel format */
 		tmp &= ~PIX_FMT_MASK;
-		switch (intel_dsi->pixel_format) {
-		default:
-			MISSING_CASE(intel_dsi->pixel_format);
-			/* fallthrough */
-		case MIPI_DSI_FMT_RGB565:
-			tmp |= PIX_FMT_RGB565;
-			break;
-		case MIPI_DSI_FMT_RGB666_PACKED:
-			tmp |= PIX_FMT_RGB666_PACKED;
-			break;
-		case MIPI_DSI_FMT_RGB666:
-			tmp |= PIX_FMT_RGB666_LOOSE;
-			break;
-		case MIPI_DSI_FMT_RGB888:
-			tmp |= PIX_FMT_RGB888;
-			break;
+		if (pipe_config->dsc.compression_enable) {
+			tmp |= PIX_FMT_COMPRESSED;
+		} else {
+			switch (intel_dsi->pixel_format) {
+			default:
+				MISSING_CASE(intel_dsi->pixel_format);
+				/* fallthrough */
+			case MIPI_DSI_FMT_RGB565:
+				tmp |= PIX_FMT_RGB565;
+				break;
+			case MIPI_DSI_FMT_RGB666_PACKED:
+				tmp |= PIX_FMT_RGB666_PACKED;
+				break;
+			case MIPI_DSI_FMT_RGB666:
+				tmp |= PIX_FMT_RGB666_LOOSE;
+				break;
+			case MIPI_DSI_FMT_RGB888:
+				tmp |= PIX_FMT_RGB888;
+				break;
+			}
 		}
 
 		if (INTEL_GEN(dev_priv) >= 12) {
-- 
2.20.1

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[PATCH 2/2] drm/i915/dsi: account for slower link in transcoder timings for DSC

[Jani Nikula]

FIXME: To be squashed to another patch.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f09e2e37d442..e343e476dbb5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -799,11 +799,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+	int cfr;
+
+	/*
+	 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
+	 * for slower link speed if DSC is enabled.
+	 *
+	 * cfr for compression frequency ratio.
+	 *
+	 * FIXME: The clock sources are ugly.
+	 */
+	if (pipe_config->dsc.compression_enable)
+		cfr = DIV_ROUND_UP(100 * afe_clk(encoder, pipe_config),
+				   intel_dsi_bitrate(intel_dsi));
+	else
+		cfr = 100;
 
 	hactive = adjusted_mode->crtc_hdisplay;
-	htotal = adjusted_mode->crtc_htotal;
-	hsync_start = adjusted_mode->crtc_hsync_start;
-	hsync_end = adjusted_mode->crtc_hsync_end;
+	htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * cfr, 100);
+	hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * cfr, 100);
+	hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * cfr, 100);
 	hsync_size  = hsync_end - hsync_start;
 	hback_porch = (adjusted_mode->crtc_htotal -
 		       adjusted_mode->crtc_hsync_end);
-- 
2.20.1

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[Intel-gfx] [PATCH 2/2] drm/i915/dsi: account for slower link in transcoder timings for DSC

[Jani Nikula]

FIXME: To be squashed to another patch.

Cc: Vandita Kulkarni <vandita.kulkarni@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/icl_dsi.c | 21 ++++++++++++++++++---
 1 file changed, 18 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index f09e2e37d442..e343e476dbb5 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -799,11 +799,26 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 	u16 hback_porch;
 	/* vertical timings */
 	u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
+	int cfr;
+
+	/*
+	 * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
+	 * for slower link speed if DSC is enabled.
+	 *
+	 * cfr for compression frequency ratio.
+	 *
+	 * FIXME: The clock sources are ugly.
+	 */
+	if (pipe_config->dsc.compression_enable)
+		cfr = DIV_ROUND_UP(100 * afe_clk(encoder, pipe_config),
+				   intel_dsi_bitrate(intel_dsi));
+	else
+		cfr = 100;
 
 	hactive = adjusted_mode->crtc_hdisplay;
-	htotal = adjusted_mode->crtc_htotal;
-	hsync_start = adjusted_mode->crtc_hsync_start;
-	hsync_end = adjusted_mode->crtc_hsync_end;
+	htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * cfr, 100);
+	hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * cfr, 100);
+	hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * cfr, 100);
 	hsync_size  = hsync_end - hsync_start;
 	hback_porch = (adjusted_mode->crtc_htotal -
 		       adjusted_mode->crtc_hsync_end);
-- 
2.20.1

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✗ Fi.CI.BUILD: failure for drm/i915/dsi: enable DSC (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC (rev2)
URL   : https://patchwork.freedesktop.org/series/69540/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK     include/generated/compile.h
  AR      drivers/gpu/drm/i915/built-in.a
  CC [M]  drivers/gpu/drm/i915/display/intel_bios.o
drivers/gpu/drm/i915/display/intel_bios.c: In function ‘intel_bios_get_dsc_params’:
drivers/gpu/drm/i915/display/intel_bios.c:2361:16: error: ‘const struct display_device_data’ has no member named ‘dsc’
    if (!devdata->dsc)
                ^~
drivers/gpu/drm/i915/display/intel_bios.c:2365:34: error: ‘const struct display_device_data’ has no member named ‘dsc’
     fill_dsc(pipe_config, devdata->dsc, dsc_max_bpc);
                                  ^~
scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/display/intel_bios.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_bios.o] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1652: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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[Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915/dsi: enable DSC (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC (rev2)
URL   : https://patchwork.freedesktop.org/series/69540/
State : failure

== Summary ==

CALL    scripts/checksyscalls.sh
  CALL    scripts/atomic/check-atomics.sh
  DESCEND  objtool
  CHK     include/generated/compile.h
  AR      drivers/gpu/drm/i915/built-in.a
  CC [M]  drivers/gpu/drm/i915/display/intel_bios.o
drivers/gpu/drm/i915/display/intel_bios.c: In function ‘intel_bios_get_dsc_params’:
drivers/gpu/drm/i915/display/intel_bios.c:2361:16: error: ‘const struct display_device_data’ has no member named ‘dsc’
    if (!devdata->dsc)
                ^~
drivers/gpu/drm/i915/display/intel_bios.c:2365:34: error: ‘const struct display_device_data’ has no member named ‘dsc’
     fill_dsc(pipe_config, devdata->dsc, dsc_max_bpc);
                                  ^~
scripts/Makefile.build:265: recipe for target 'drivers/gpu/drm/i915/display/intel_bios.o' failed
make[4]: *** [drivers/gpu/drm/i915/display/intel_bios.o] Error 1
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm/i915' failed
make[3]: *** [drivers/gpu/drm/i915] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu/drm' failed
make[2]: *** [drivers/gpu/drm] Error 2
scripts/Makefile.build:509: recipe for target 'drivers/gpu' failed
make[1]: *** [drivers/gpu] Error 2
Makefile:1652: recipe for target 'drivers' failed
make: *** [drivers] Error 2

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✗ Fi.CI.CHECKPATCH: warning for drm/i915/dsi: enable DSC

[Patchwork]

== Series Details ==

Series: drm/i915/dsi: enable DSC
URL   : https://patchwork.freedesktop.org/series/69202/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a5c514d75474 drm/i915/bios: use a flag for vbt hdmi level shift presence
af24a1b0a92c drm/i915/bios: store child devices in a list
d5251f660966 drm/i915/bios: pass devdata to parse_ddi_port
33a264f49a5c drm/i915/bios: parse compression parameters block
-:98: CHECK:COMPARISON_TO_NULL: Comparison to NULL could be written "devdata->dsc"
#98: FILE: drivers/gpu/drm/i915/display/intel_bios.c:1528:
+		      devdata->dsc != NULL);

total: 0 errors, 0 warnings, 1 checks, 101 lines checked
bfda0b2963dd drm/i915/bios: add support for querying DSC details for encoder
d3b5ec793ae8 drm/i915/dsc: move DP specific compute params to intel_dp.c
df30419003c1 drm/i915/dsc: move slice height calculation to encoder
5940f47d1ff4 drm/i915/dsc: add support for computing and writing PPS for DSI encoders
9ac145cbd597 drm/i915/dsi: add support for DSC

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