* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected
@ 2019-08-28 21:45 Kurt Miller
2019-09-13 22:02 ` Kurt Miller
` (2 more replies)
0 siblings, 3 replies; 13+ messages in thread
From: Kurt Miller @ 2019-08-28 21:45 UTC (permalink / raw)
To: u-boot
The board has 4G memory but only 2G is detected by TPL. Please
let me know if additional information is needed.
With u-boot master TPL output:
U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
256B stride
Trying to boot from BOOTROM
Returning to boot ROM...
With rkbin rk3399_ddr_800MHz_v1.23.bin output:
DDR Version 1.23 20190709
In
channel 0
CS = 0
MR0=0xB8
MR4=0x2
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0xB8
MR4=0x2
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
change freq to 416MHz 0,1
Channel 0: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
Channel 1: LPDDR4,416MHz
Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
256B stride
channel 0
CS = 0
MR0=0xB8
MR4=0x2
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 1
CS = 0
MR0=0xB8
MR4=0x2
MR5=0xFF
MR8=0x10
MR12=0x72
MR14=0x72
MR18=0x0
MR19=0x0
MR24=0x8
MR25=0x0
channel 0 training pass!
channel 1 training pass!
channel 0, cs 0, advanced training done
channel 1, cs 0, advanced training done
change freq to 856MHz 1,0
ch 0 ddrconfig = 0x101, ddrsize = 0x40
ch 1 ddrconfig = 0x101, ddrsize = 0x40
pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
OUT
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected
2019-08-28 21:45 [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
@ 2019-09-13 22:02 ` Kurt Miller
2019-09-17 2:57 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected Kever Yang
2019-09-17 9:25 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
2019-09-17 9:32 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
2 siblings, 1 reply; 13+ messages in thread
From: Kurt Miller @ 2019-09-13 22:02 UTC (permalink / raw)
To: u-boot
Re-testing with master as of Sep 12 and the wrong memory
size continues to be detected (2G detected while the
board has 4G).
The board has the following marking on it:
Rockpro64_V2.1 2018-07-02
RAM Chips:
PS052-053 BT
83RL
I'd be happy to test any proposed patches to correct
the memory size detection on this board.
On Wed, 2019-08-28 at 17:45 -0400, Kurt Miller wrote:
> The board has 4G memory but only 2G is detected by TPL. Please
> let me know if additional information is needed.
>
> With u-boot master TPL output:
>
> U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> With rkbin rk3399_ddr_800MHz_v1.23.bin output:
>
> DDR Version 1.23 20190709
> In
> channel 0
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 1
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 0 training pass!
> channel 1 training pass!
> change freq to 416MHz 0,1
> Channel 0: LPDDR4,416MHz
> Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
> Channel 1: LPDDR4,416MHz
> Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
> 256B stride
> channel 0
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 1
> CS = 0
> MR0=0xB8
> MR4=0x2
> MR5=0xFF
> MR8=0x10
> MR12=0x72
> MR14=0x72
> MR18=0x0
> MR19=0x0
> MR24=0x8
> MR25=0x0
> channel 0 training pass!
> channel 1 training pass!
> channel 0, cs 0, advanced training done
> channel 1, cs 0, advanced training done
> change freq to 856MHz 1,0
> ch 0 ddrconfig = 0x101, ddrsize = 0x40
> ch 1 ddrconfig = 0x101, ddrsize = 0x40
> pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
> OUT
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected
2019-09-13 22:02 ` Kurt Miller
@ 2019-09-17 2:57 ` Kever Yang
2019-09-17 16:02 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
0 siblings, 1 reply; 13+ messages in thread
From: Kever Yang @ 2019-09-17 2:57 UTC (permalink / raw)
To: u-boot
Hi Kurt,
Could you try with below update:
diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
index 4a4414a960..dc9db047cb 100644
--- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
+++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
@@ -13,8 +13,8 @@
0x2
0x1
0x0
- 0xf
- 0xf
+ 0x10
+ 0x10
1
0x80241d22
0x15050f08
@@ -28,8 +28,8 @@
0x2
0x1
0x0
- 0xf
- 0xf
+ 0x10
+ 0x10
1
0x80241d22
0x15050f08
Thanks,
- Kever
On 2019/9/14 上午6:02, Kurt Miller wrote:
> Re-testing with master as of Sep 12 and the wrong memory
> size continues to be detected (2G detected while the
> board has 4G).
>
> The board has the following marking on it:
>
> Rockpro64_V2.1 2018-07-02
>
> RAM Chips:
> PS052-053 BT
> 83RL
>
> I'd be happy to test any proposed patches to correct
> the memory size detection on this board.
>
> On Wed, 2019-08-28 at 17:45 -0400, Kurt Miller wrote:
>> The board has 4G memory but only 2G is detected by TPL. Please
>> let me know if additional information is needed.
>>
>> With u-boot master TPL output:
>>
>> U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
>> LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
>> LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
>> 256B stride
>> Trying to boot from BOOTROM
>> Returning to boot ROM...
>>
>> With rkbin rk3399_ddr_800MHz_v1.23.bin output:
>>
>> DDR Version 1.23 20190709
>> In
>> channel 0
>> CS = 0
>> MR0=0xB8
>> MR4=0x2
>> MR5=0xFF
>> MR8=0x10
>> MR12=0x72
>> MR14=0x72
>> MR18=0x0
>> MR19=0x0
>> MR24=0x8
>> MR25=0x0
>> channel 1
>> CS = 0
>> MR0=0xB8
>> MR4=0x2
>> MR5=0xFF
>> MR8=0x10
>> MR12=0x72
>> MR14=0x72
>> MR18=0x0
>> MR19=0x0
>> MR24=0x8
>> MR25=0x0
>> channel 0 training pass!
>> channel 1 training pass!
>> change freq to 416MHz 0,1
>> Channel 0: LPDDR4,416MHz
>> Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
>> Channel 1: LPDDR4,416MHz
>> Bus Width=32 Col=10 Bank=8 Row=16 CS=1 Die Bus-Width=16 Size=2048MB
>> 256B stride
>> channel 0
>> CS = 0
>> MR0=0xB8
>> MR4=0x2
>> MR5=0xFF
>> MR8=0x10
>> MR12=0x72
>> MR14=0x72
>> MR18=0x0
>> MR19=0x0
>> MR24=0x8
>> MR25=0x0
>> channel 1
>> CS = 0
>> MR0=0xB8
>> MR4=0x2
>> MR5=0xFF
>> MR8=0x10
>> MR12=0x72
>> MR14=0x72
>> MR18=0x0
>> MR19=0x0
>> MR24=0x8
>> MR25=0x0
>> channel 0 training pass!
>> channel 1 training pass!
>> channel 0, cs 0, advanced training done
>> channel 1, cs 0, advanced training done
>> change freq to 856MHz 1,0
>> ch 0 ddrconfig = 0x101, ddrsize = 0x40
>> ch 1 ddrconfig = 0x101, ddrsize = 0x40
>> pmugrf_os_reg[2] = 0x32C1F2C1, stride = 0xD
>> OUT
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected
2019-08-28 21:45 [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
2019-09-13 22:02 ` Kurt Miller
@ 2019-09-17 9:25 ` Jagan Teki
2019-09-18 3:38 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected Kever Yang
2019-09-17 9:32 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
2 siblings, 1 reply; 13+ messages in thread
From: Jagan Teki @ 2019-09-17 9:25 UTC (permalink / raw)
To: u-boot
On Thu, Aug 29, 2019 at 3:15 AM Kurt Miller <lists@intricatesoftware.com> wrote:
>
> The board has 4G memory but only 2G is detected by TPL. Please
> let me know if additional information is needed.
>
> With u-boot master TPL output:
>
> U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> Trying to boot from BOOTROM
> Returning to boot ROM...
U-Boot TPL 2019.10-rc3-00333-g5d07dd3f42-dirty (Sep 17 2019 - 14:52:32)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
lpddr4_set_rate: change freq to 400 mhz 0, 1
lpddr4_set_rate: change freq to 800 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...
Please check it I can able to detect 2GB each channel, so total 4GB.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected
2019-08-28 21:45 [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
2019-09-13 22:02 ` Kurt Miller
2019-09-17 9:25 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
@ 2019-09-17 9:32 ` Jagan Teki
2 siblings, 0 replies; 13+ messages in thread
From: Jagan Teki @ 2019-09-17 9:32 UTC (permalink / raw)
To: u-boot
On Thu, Aug 29, 2019 at 3:15 AM Kurt Miller <lists@intricatesoftware.com> wrote:
>
> The board has 4G memory but only 2G is detected by TPL. Please
> let me know if additional information is needed.
>
> With u-boot master TPL output:
>
> U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> Trying to boot from BOOTROM
> Returning to boot ROM...
So, even tired the same commit.
U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Sep 17 2019 - 15:01:07)
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
256B stride
lpddr4_set_rate: change freq to 400 mhz 0, 1
lpddr4_set_rate: change freq to 800 mhz 1, 0
Trying to boot from BOOTROM
Returning to boot ROM...
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected
2019-09-17 2:57 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected Kever Yang
@ 2019-09-17 16:02 ` Kurt Miller
2019-11-13 18:44 ` Kurt Miller
0 siblings, 1 reply; 13+ messages in thread
From: Kurt Miller @ 2019-09-17 16:02 UTC (permalink / raw)
To: u-boot
On Tue, 2019-09-17 at 10:57 +0800, Kever Yang wrote:
> Hi Kurt,
>
> Could you try with below update:
>
>
> diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> index 4a4414a960..dc9db047cb 100644
> --- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> @@ -13,8 +13,8 @@
> 0x2
> 0x1
> 0x0
> - 0xf
> - 0xf
> + 0x10
> + 0x10
> 1
> 0x80241d22
> 0x15050f08
> @@ -28,8 +28,8 @@
> 0x2
> 0x1
> 0x0
> - 0xf
> - 0xf
> + 0x10
> + 0x10
> 1
> 0x80241d22
> 0x15050f08
>
> Thanks,
> - Kever
Hi Kever,
Yes, that diff does correct the memory size detection
for my board:
U-Boot TPL 2019.10-rc3-00332-ga314ec1bfd-dirty (Sep 17 2019 - 11:55:26)
con reg
cru , cic , grf , sgrf , pmucru , pmu
Starting SDRAM initialization...
sdram_init: data trained for rank 1, ch 0
sdram_init: data trained for rank 1, ch 1
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
256B stride
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 400 mhz 0, 1
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 800 mhz 1, 0
Finish SDRAM initialization...
Trying to boot from BOOTROM
Returning to boot ROM...
Thank you,
-Kurt
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected
2019-09-17 9:25 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
@ 2019-09-18 3:38 ` Kever Yang
2019-09-18 5:01 ` Jagan Teki
0 siblings, 1 reply; 13+ messages in thread
From: Kever Yang @ 2019-09-18 3:38 UTC (permalink / raw)
To: u-boot
Hi Jagan,
Seems like your and Kurt's board have different DRAM type:
- 16bit row + 1 CS
- 15bit row + 2 CS
Capacity detect function is missing for the driver now, and it's not able
to detect the correct size like Kurt is using.
Thanks,
- Kever
On 2019/9/17 下午5:25, Jagan Teki wrote:
> On Thu, Aug 29, 2019 at 3:15 AM Kurt Miller <lists@intricatesoftware.com> wrote:
>> The board has 4G memory but only 2G is detected by TPL. Please
>> let me know if additional information is needed.
>>
>> With u-boot master TPL output:
>>
>> U-Boot TPL 2019.10-rc3-00020-ge4b8dd9b34-dirty (Aug 28 2019 - 17:26:44)
>> LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
>> LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
>> 256B stride
>> Trying to boot from BOOTROM
>> Returning to boot ROM...
> U-Boot TPL 2019.10-rc3-00333-g5d07dd3f42-dirty (Sep 17 2019 - 14:52:32)
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB
> 256B stride
> lpddr4_set_rate: change freq to 400 mhz 0, 1
> lpddr4_set_rate: change freq to 800 mhz 1, 0
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> Please check it I can able to detect 2GB each channel, so total 4GB.
> _______________________________________________
> U-Boot mailing list
> U-Boot at lists.denx.de
> https://lists.denx.de/listinfo/u-boot
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected
2019-09-18 3:38 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected Kever Yang
@ 2019-09-18 5:01 ` Jagan Teki
2019-09-19 5:33 ` Jagan Teki
0 siblings, 1 reply; 13+ messages in thread
From: Jagan Teki @ 2019-09-18 5:01 UTC (permalink / raw)
To: u-boot
On Wed, Sep 18, 2019 at 9:09 AM Kever Yang <kever.yang@rock-chips.com> wrote:
>
> Hi Jagan,
>
> Seems like your and Kurt's board have different DRAM type:
>
> - 16bit row + 1 CS
>
> - 15bit row + 2 CS
>
> Capacity detect function is missing for the driver now, and it's not able
>
> to detect the correct size like Kurt is using.
Got it. let me send the quick check patch, thanks.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected
2019-09-18 5:01 ` Jagan Teki
@ 2019-09-19 5:33 ` Jagan Teki
2019-09-26 12:53 ` Kurt Miller
0 siblings, 1 reply; 13+ messages in thread
From: Jagan Teki @ 2019-09-19 5:33 UTC (permalink / raw)
To: u-boot
Hi Kever,
On Wed, Sep 18, 2019 at 10:31 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
>
> On Wed, Sep 18, 2019 at 9:09 AM Kever Yang <kever.yang@rock-chips.com> wrote:
> >
> > Hi Jagan,
> >
> > Seems like your and Kurt's board have different DRAM type:
> >
> > - 16bit row + 1 CS
> >
> > - 15bit row + 2 CS
> >
> > Capacity detect function is missing for the driver now, and it's not able
> >
> > to detect the correct size like Kurt is using.
>
> Got it. let me send the quick check patch, thanks.
Are you looking to fix this for the release? if yes, then we can
create another sdram*.dtsi for this specific dram board otherwise we
can fix this MW. Adding cap detection would alter the existing
behaviour of sdram driver, which indeed a risky to do at this point of
time since we are close to release.
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected
2019-09-19 5:33 ` Jagan Teki
@ 2019-09-26 12:53 ` Kurt Miller
0 siblings, 0 replies; 13+ messages in thread
From: Kurt Miller @ 2019-09-26 12:53 UTC (permalink / raw)
To: u-boot
On Thu, 2019-09-19 at 11:03 +0530, Jagan Teki wrote:
> Hi Kever,
>
> On Wed, Sep 18, 2019 at 10:31 AM Jagan Teki <jagan@amarulasolutions.com> wrote:
> >
> >
> > On Wed, Sep 18, 2019 at 9:09 AM Kever Yang <kever.yang@rock-chips.com> wrote:
> > >
> > >
> > > Hi Jagan,
> > >
> > > Seems like your and Kurt's board have different DRAM type:
> > >
> > > - 16bit row + 1 CS
> > >
> > > - 15bit row + 2 CS
> > >
> > > Capacity detect function is missing for the driver now, and it's not able
> > >
> > > to detect the correct size like Kurt is using.
> > Got it. let me send the quick check patch, thanks.
> Are you looking to fix this for the release? if yes, then we can
> create another sdram*.dtsi for this specific dram board otherwise we
> can fix this MW. Adding cap detection would alter the existing
> behaviour of sdram driver, which indeed a risky to do at this point of
> time since we are close to release.
Hi Kever, Jagen,
Is this being considered for fixing prior to release?
My offer to test patches is still available.
Thank you,
-Kurt
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected
2019-09-17 16:02 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
@ 2019-11-13 18:44 ` Kurt Miller
2019-11-18 3:05 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由lists.intricate@gmail.com代发】 Kever Yang
0 siblings, 1 reply; 13+ messages in thread
From: Kurt Miller @ 2019-11-13 18:44 UTC (permalink / raw)
To: u-boot
On Tue, 2019-09-17 at 12:02 -0400, Kurt Miller wrote:
> On Tue, 2019-09-17 at 10:57 +0800, Kever Yang wrote:
> >
> > Hi Kurt,
> >
> > Could you try with below update:
> >
> >
> > diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > index 4a4414a960..dc9db047cb 100644
> > --- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > @@ -13,8 +13,8 @@
> > 0x2
> > 0x1
> > 0x0
> > - 0xf
> > - 0xf
> > + 0x10
> > + 0x10
> > 1
> > 0x80241d22
> > 0x15050f08
> > @@ -28,8 +28,8 @@
> > 0x2
> > 0x1
> > 0x0
> > - 0xf
> > - 0xf
> > + 0x10
> > + 0x10
> > 1
> > 0x80241d22
> > 0x15050f08
> >
> > Thanks,
> > - Kever
> Hi Kever,
>
> Yes, that diff does correct the memory size detection
> for my board:
>
> U-Boot TPL 2019.10-rc3-00332-ga314ec1bfd-dirty (Sep 17 2019 - 11:55:26)
> con reg
> cru , cic , grf , sgrf , pmucru , pmu
> Starting SDRAM initialization...
> sdram_init: data trained for rank 1, ch 0
> sdram_init: data trained for rank 1, ch 1
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> 256B stride
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 400 mhz 0, 1
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 800 mhz 1, 0
> Finish SDRAM initialization...
> Trying to boot from BOOTROM
> Returning to boot ROM...
Hi Kever,
Following up on this issue. I retested 2020.01-rc2 to see if
memory size detection has been fixed yet. Without your diff above
applied, 2020.01-rc2 still detects 2G memory instead of 4G:
U-Boot TPL 2020.01-rc2-dirty (Nov 13 2019 - 13:18:40)
con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
Starting SDRAM initialization...
sdram_init: data trained for rank 1, ch 0
sdram_init: data trained for rank 1, ch 1
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
256B stride
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 400 mhz 0, 1
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 800 mhz 1, 0
Finish SDRAM initialization...
Trying to boot from BOOTROM
Returning to boot ROM...
With your diff above applied I get 4G correctly:
U-Boot TPL 2020.01-rc2-dirty (Nov 13 2019 - 13:23:22)
con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
Starting SDRAM initialization...
sdram_init: data trained for rank 1, ch 0
sdram_init: data trained for rank 1, ch 1
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
256B stride
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 400 mhz 0, 1
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 800 mhz 1, 0
Finish SDRAM initialization...
Trying to boot from BOOTROM
Returning to boot ROM...
Regards,
-Kurt
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由lists.intricate@gmail.com代发】
2019-11-13 18:44 ` Kurt Miller
@ 2019-11-18 3:05 ` Kever Yang
2019-11-18 16:04 ` Kurt Miller
0 siblings, 1 reply; 13+ messages in thread
From: Kever Yang @ 2019-11-18 3:05 UTC (permalink / raw)
To: u-boot
Hi Kurt,
On 2019/11/14 上午2:44, Kurt Miller wrote:
> On Tue, 2019-09-17 at 12:02 -0400, Kurt Miller wrote:
>> On Tue, 2019-09-17 at 10:57 +0800, Kever Yang wrote:
>>> Hi Kurt,
>>>
>>> Could you try with below update:
>>>
>>>
>>> diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> index 4a4414a960..dc9db047cb 100644
>>> --- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
>>> @@ -13,8 +13,8 @@
>>> 0x2
>>> 0x1
>>> 0x0
>>> - 0xf
>>> - 0xf
>>> + 0x10
>>> + 0x10
>>> 1
>>> 0x80241d22
>>> 0x15050f08
>>> @@ -28,8 +28,8 @@
>>> 0x2
>>> 0x1
>>> 0x0
>>> - 0xf
>>> - 0xf
>>> + 0x10
>>> + 0x10
>>> 1
>>> 0x80241d22
>>> 0x15050f08
>>>
>>> Thanks,
>>> - Kever
>> Hi Kever,
>>
>> Yes, that diff does correct the memory size detection
>> for my board:
>>
>> U-Boot TPL 2019.10-rc3-00332-ga314ec1bfd-dirty (Sep 17 2019 - 11:55:26)
>> con reg
>> cru , cic , grf , sgrf , pmucru , pmu
>> Starting SDRAM initialization...
>> sdram_init: data trained for rank 1, ch 0
>> sdram_init: data trained for rank 1, ch 1
>> Channel 0: LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
>> Channel 1: LPDDR4, 50MHz
>> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
>> 256B stride
>> lpddr4_set_ctl: channel 0 training pass
>> lpddr4_set_ctl: channel 1 training pass
>> lpddr4_set_rate: change freq to 400 mhz 0, 1
>> lpddr4_set_ctl: channel 0 training pass
>> lpddr4_set_ctl: channel 1 training pass
>> lpddr4_set_rate: change freq to 800 mhz 1, 0
>> Finish SDRAM initialization...
>> Trying to boot from BOOTROM
>> Returning to boot ROM...
> Hi Kever,
>
> Following up on this issue. I retested 2020.01-rc2 to see if
> memory size detection has been fixed yet. Without your diff above
> applied, 2020.01-rc2 still detects 2G memory instead of 4G:
Could you try with latest u-boot-rockchip?
https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git
Thanks,
- Kever
>
> U-Boot TPL 2020.01-rc2-dirty (Nov 13 2019 - 13:18:40)
> con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
> cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
> Starting SDRAM initialization...
> sdram_init: data trained for rank 1, ch 0
> sdram_init: data trained for rank 1, ch 1
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
> 256B stride
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 400 mhz 0, 1
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 800 mhz 1, 0
> Finish SDRAM initialization...
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> With your diff above applied I get 4G correctly:
>
> U-Boot TPL 2020.01-rc2-dirty (Nov 13 2019 - 13:23:22)
> con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
> cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
> Starting SDRAM initialization...
> sdram_init: data trained for rank 1, ch 0
> sdram_init: data trained for rank 1, ch 1
> Channel 0: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> Channel 1: LPDDR4, 50MHz
> BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> 256B stride
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 400 mhz 0, 1
> lpddr4_set_ctl: channel 0 training pass
> lpddr4_set_ctl: channel 1 training pass
> lpddr4_set_rate: change freq to 800 mhz 1, 0
> Finish SDRAM initialization...
> Trying to boot from BOOTROM
> Returning to boot ROM...
>
> Regards,
> -Kurt
>
^ permalink raw reply [flat|nested] 13+ messages in thread
* [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由lists.intricate@gmail.com代发】
2019-11-18 3:05 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由lists.intricate@gmail.com代发】 Kever Yang
@ 2019-11-18 16:04 ` Kurt Miller
0 siblings, 0 replies; 13+ messages in thread
From: Kurt Miller @ 2019-11-18 16:04 UTC (permalink / raw)
To: u-boot
Hi Kever,
On Mon, 2019-11-18 at 11:05 +0800, Kever Yang wrote:
> Hi Kurt,
>
> On 2019/11/14 上午2:44, Kurt Miller wrote:
> >
> > On Tue, 2019-09-17 at 12:02 -0400, Kurt Miller wrote:
> > >
> > > On Tue, 2019-09-17 at 10:57 +0800, Kever Yang wrote:
> > > >
> > > > Hi Kurt,
> > > >
> > > > Could you try with below update:
> > > >
> > > >
> > > > diff --git a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > > > b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > > > index 4a4414a960..dc9db047cb 100644
> > > > --- a/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > > > +++ b/arch/arm/dts/rk3399-sdram-lpddr4-100.dtsi
> > > > @@ -13,8 +13,8 @@
> > > > 0x2
> > > > 0x1
> > > > 0x0
> > > > - 0xf
> > > > - 0xf
> > > > + 0x10
> > > > + 0x10
> > > > 1
> > > > 0x80241d22
> > > > 0x15050f08
> > > > @@ -28,8 +28,8 @@
> > > > 0x2
> > > > 0x1
> > > > 0x0
> > > > - 0xf
> > > > - 0xf
> > > > + 0x10
> > > > + 0x10
> > > > 1
> > > > 0x80241d22
> > > > 0x15050f08
> > > >
> > > > Thanks,
> > > > - Kever
> > > Hi Kever,
> > >
> > > Yes, that diff does correct the memory size detection
> > > for my board:
> > >
> > > U-Boot TPL 2019.10-rc3-00332-ga314ec1bfd-dirty (Sep 17 2019 - 11:55:26)
> > > con reg
> > > cru , cic , grf , sgrf , pmucru , pmu
> > > Starting SDRAM initialization...
> > > sdram_init: data trained for rank 1, ch 0
> > > sdram_init: data trained for rank 1, ch 1
> > > Channel 0: LPDDR4, 50MHz
> > > BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> > > Channel 1: LPDDR4, 50MHz
> > > BW=32 Col=10 Bk=8 CS0 Row=16 CS=1 Die BW=16 Size=2048MB
> > > 256B stride
> > > lpddr4_set_ctl: channel 0 training pass
> > > lpddr4_set_ctl: channel 1 training pass
> > > lpddr4_set_rate: change freq to 400 mhz 0, 1
> > > lpddr4_set_ctl: channel 0 training pass
> > > lpddr4_set_ctl: channel 1 training pass
> > > lpddr4_set_rate: change freq to 800 mhz 1, 0
> > > Finish SDRAM initialization...
> > > Trying to boot from BOOTROM
> > > Returning to boot ROM...
> > Hi Kever,
> >
> > Following up on this issue. I retested 2020.01-rc2 to see if
> > memory size detection has been fixed yet. Without your diff above
> > applied, 2020.01-rc2 still detects 2G memory instead of 4G:
>
> Could you try with latest u-boot-rockchip?
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip.git
>
The latest u-boot-rockchip does detect the correct memory
size. I'll keep an eye out for the next rockchip pull
to master occurs.
Thank you,
-Kurt
U-Boot TPL 2020.01-rc2-04834-g59b01eb7a1-dirty (Nov 18 2019 - 10:34:14)
con reg ffa80000 ffa80800 ffa82000 ffa84000 ffa88000 ffa88800 ffa8a000 ffa8c000
cru ff760000, cic ff620000, grf ff320000, sgrf ff330000, pmucru ff750000, pmu ff310000
Starting SDRAM initialization...
sdram_init: data trained for rank 1, ch 0
sdram_init: data trained for rank 1, ch 1
Channel 0: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
Channel 1: LPDDR4, 50MHz
BW=32 Col=10 Bk=8 CS0 Row=16/15 CS=1 Die BW=16 Size=2048MB
256B stride
256B stride
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 400000000 mhz 0, 1
lpddr4_set_ctl: channel 0 training pass
lpddr4_set_ctl: channel 1 training pass
lpddr4_set_rate: change freq to 800000000 mhz 1, 0
Finish SDRAM initialization...
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2020.01-rc2-04834-g59b01eb7a1-dirty (Nov 18 2019 - 10:34:14 -0500)
Trying to boot from MMC1
NOTICE: BL31: v2.2(debug):2.2
NOTICE: BL31: Built : 10:33:33, Nov 18 2019
INFO: GICv3 with legacy support detected. ARM GICv3 driver initialized in EL3
INFO: plat_rockchip_pmu_init(1605): pd status 3e
INFO: BL31: Initializing runtime services
INFO: BL31: cortex_a53: CPU workaround for 855873 was applied
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0x200000
INFO: SPSR = 0x3c9
U-Boot 2020.01-rc2-04834-g59b01eb7a1-dirty (Nov 18 2019 - 10:34:14 -0500)
Model: Pine64 RockPro64
DRAM: rk3399_dmc_probe: pmugrf = 00000000ff320000
3.9 GiB
PMIC: RK808
MMC: dwmmc at fe320000: 1, sdhci at fe330000: 0
Loading Environment from MMC... Card did not respond to voltage select!
*** Warning - No block device, using default environment
In: serial at ff1a0000
Out: serial at ff1a0000
Err: serial at ff1a0000
Model: Pine64 RockPro64
rockchip_dnl_key_pressed: adc_channel_single_shot fail!
Net: eth0: ethernet at fe300000
Hit any key to stop autoboot: 0
Card did not respond to voltage select!
switch to partitions #0, OK
mmc1 is current device
Scanning mmc 1:1...
Found EFI removable media binary efi/boot/bootaa64.efi
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
Scanning disk dwmmc at fe320000.blk...
** Unrecognized filesystem type **
Card did not respond to voltage select!
Scanning disk sdhci at fe330000.blk...
Disk sdhci at fe330000.blk not ready
Found 3 disks
BootOrder not defined
EFI boot manager: Cannot load any image
161090 bytes read in 16 ms (9.6 MiB/s)
libfdt fdt_check_header(): FDT_ERR_BADMAGIC
disks: sd0*
>> OpenBSD/arm64 BOOTAA64 0.19
boot>
booting sd0a:/bsd: 7480340+1599872+539984+848776 [621522+109+869160+526938]=0xd3fe68
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2019-11-18 16:04 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-08-28 21:45 [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
2019-09-13 22:02 ` Kurt Miller
2019-09-17 2:57 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected Kever Yang
2019-09-17 16:02 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Kurt Miller
2019-11-13 18:44 ` Kurt Miller
2019-11-18 3:05 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由lists.intricate@gmail.com代发】 Kever Yang
2019-11-18 16:04 ` Kurt Miller
2019-09-17 9:25 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
2019-09-18 3:38 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected【请注意，邮件由u-boot-bounces@lists.denx.de代发】 detected Kever Yang
2019-09-18 5:01 ` Jagan Teki
2019-09-19 5:33 ` Jagan Teki
2019-09-26 12:53 ` Kurt Miller
2019-09-17 9:32 ` [U-Boot] rockchip: rk3399: TPL: rockpro64: Wrong memory size detected Jagan Teki
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