* [Intel-gfx] [PATCH v2 00/10] drm/i915: Cleanups around .crtc_enable/disable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rebased for CI. All reviewed already.
Ville Syrjälä (10):
drm/i915: Change intel_encoders_<hook>() calling convention
drm/i915: Add intel_crtc_vblank_off()
drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
drm/i915: Move crtc_state to tighter scope
drm/i915: Pass intel_crtc to ironlake_fdi_disable()
drm/i915: Change watermark hook calling convention
drm/i915: Pass dev_priv to cpt_verify_modeset()
drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
drm/i915: Change .crtc_enable/disable() calling convention
drivers/gpu/drm/i915/display/intel_display.c | 459 +++++++++----------
drivers/gpu/drm/i915/i915_drv.h | 14 +-
drivers/gpu/drm/i915/intel_pm.c | 63 +--
3 files changed, 271 insertions(+), 265 deletions(-)
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 30+ messages in thread
* [PATCH v2 01/10] drm/i915: Change intel_encoders_<hook>() calling convention
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state and the crtc to intel_encoders_enable() & co.
Make life simpler when you don't have to think which state (old vs. new)
you have to pass in. Also constify the states while at it.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++---------
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 23f00a651738..5d2ab40def8f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6311,11 +6311,12 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
}
}
-static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6331,11 +6332,12 @@ static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_pre_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6351,11 +6353,12 @@ static void intel_encoders_pre_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6372,11 +6375,12 @@ static void intel_encoders_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6393,11 +6397,12 @@ static void intel_encoders_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6413,11 +6418,12 @@ static void intel_encoders_post_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6433,11 +6439,12 @@ static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_update_pipe(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_update_pipe(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6504,7 +6511,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true;
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6537,7 +6544,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
@@ -6621,12 +6628,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6703,7 +6710,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6751,7 +6758,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6763,7 +6770,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (old_crtc_state->has_pch_encoder)
ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6801,7 +6808,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6823,9 +6830,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7056,7 +7063,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (IS_CHERRYVIEW(dev_priv)) {
chv_prepare_pll(intel_crtc, pipe_config);
@@ -7066,7 +7073,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
vlv_enable_pll(intel_crtc, pipe_config);
}
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_pfit_enable(pipe_config);
@@ -7081,7 +7088,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7120,7 +7127,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_enable_pll(intel_crtc, pipe_config);
@@ -7141,7 +7148,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7175,7 +7182,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -7184,7 +7191,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7195,7 +7202,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -14365,7 +14372,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_pre_plane_update(old_crtc_state, new_crtc_state);
if (new_crtc_state->update_pipe)
- intel_encoders_update_pipe(crtc, new_crtc_state, state);
+ intel_encoders_update_pipe(state, crtc);
}
if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 01/10] drm/i915: Change intel_encoders_<hook>() calling convention
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state and the crtc to intel_encoders_enable() & co.
Make life simpler when you don't have to think which state (old vs. new)
you have to pass in. Also constify the states while at it.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 101 ++++++++++---------
1 file changed, 54 insertions(+), 47 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 23f00a651738..5d2ab40def8f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6311,11 +6311,12 @@ static void intel_encoders_update_complete(struct intel_atomic_state *state)
}
}
-static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6331,11 +6332,12 @@ static void intel_encoders_pre_pll_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_pre_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_pre_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6351,11 +6353,12 @@ static void intel_encoders_pre_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_enable(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6372,11 +6375,12 @@ static void intel_encoders_enable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6393,11 +6397,12 @@ static void intel_encoders_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6413,11 +6418,12 @@ static void intel_encoders_post_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
- struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *old_conn_state;
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
+ const struct drm_connector_state *old_conn_state;
struct drm_connector *conn;
int i;
@@ -6433,11 +6439,12 @@ static void intel_encoders_post_pll_disable(struct intel_crtc *crtc,
}
}
-static void intel_encoders_update_pipe(struct intel_crtc *crtc,
- struct intel_crtc_state *crtc_state,
- struct intel_atomic_state *state)
+static void intel_encoders_update_pipe(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct drm_connector_state *conn_state;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct drm_connector_state *conn_state;
struct drm_connector *conn;
int i;
@@ -6504,7 +6511,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc->active = true;
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6537,7 +6544,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev, intel_crtc->pipe);
@@ -6621,12 +6628,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (WARN_ON(intel_crtc->active))
return;
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6703,7 +6710,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6751,7 +6758,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6763,7 +6770,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (old_crtc_state->has_pch_encoder)
ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6801,7 +6808,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -6823,9 +6830,9 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7056,7 +7063,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_pll_enable(state, intel_crtc);
if (IS_CHERRYVIEW(dev_priv)) {
chv_prepare_pll(intel_crtc, pipe_config);
@@ -7066,7 +7073,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
vlv_enable_pll(intel_crtc, pipe_config);
}
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_pfit_enable(pipe_config);
@@ -7081,7 +7088,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7120,7 +7127,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(intel_crtc, pipe_config, state);
+ intel_encoders_pre_enable(state, intel_crtc);
i9xx_enable_pll(intel_crtc, pipe_config);
@@ -7141,7 +7148,7 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(intel_crtc, pipe_config, state);
+ intel_encoders_enable(state, intel_crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7175,7 +7182,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_disable(state, intel_crtc);
drm_crtc_vblank_off(crtc);
assert_vblank_disabled(crtc);
@@ -7184,7 +7191,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_disable(state, intel_crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7195,7 +7202,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(intel_crtc, old_crtc_state, state);
+ intel_encoders_post_pll_disable(state, intel_crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -14365,7 +14372,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
intel_pre_plane_update(old_crtc_state, new_crtc_state);
if (new_crtc_state->update_pipe)
- intel_encoders_update_pipe(crtc, new_crtc_state, state);
+ intel_encoders_update_pipe(state, crtc);
}
if (new_crtc_state->update_pipe && !new_crtc_state->enable_fbc)
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 02/10] drm/i915: Add intel_crtc_vblank_off()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have intel_crtc_vblank_on(). Add a counterpart so we
don't have to inline the disable+assert all over.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5d2ab40def8f..bf7faaf061a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1843,6 +1843,12 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
drm_crtc_vblank_on(&crtc->base);
}
+static void intel_crtc_vblank_off(struct intel_crtc *crtc)
+{
+ drm_crtc_vblank_off(&crtc->base);
+ assert_vblank_disabled(&crtc->base);
+}
+
static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -6760,8 +6766,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
@@ -6810,8 +6815,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -7184,8 +7188,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 02/10] drm/i915: Add intel_crtc_vblank_off()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We already have intel_crtc_vblank_on(). Add a counterpart so we
don't have to inline the disable+assert all over.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 5d2ab40def8f..bf7faaf061a3 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1843,6 +1843,12 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
drm_crtc_vblank_on(&crtc->base);
}
+static void intel_crtc_vblank_off(struct intel_crtc *crtc)
+{
+ drm_crtc_vblank_off(&crtc->base);
+ assert_vblank_disabled(&crtc->base);
+}
+
static void intel_enable_pipe(const struct intel_crtc_state *new_crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
@@ -6760,8 +6766,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
@@ -6810,8 +6815,7 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -7184,8 +7188,7 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_encoders_disable(state, intel_crtc);
- drm_crtc_vblank_off(crtc);
- assert_vblank_disabled(crtc);
+ intel_crtc_vblank_off(intel_crtc);
intel_disable_pipe(old_crtc_state);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 03/10] drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the assert_vblank_disabled() into intel_crtc_vblank_on()
so that we don't have to inline it all over.
This does mean we now assert_vblank_disabled() during readout as well
but that is totally fine as it happens after drm_crtc_vblank_reset().
One can even argue it's what we want to do anyway to make sure
the reset actually happened.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf7faaf061a3..854ccca2bf6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1838,6 +1838,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ assert_vblank_disabled(&crtc->base);
drm_crtc_set_max_vblank_count(&crtc->base,
intel_crtc_max_vblank_count(crtc_state));
drm_crtc_vblank_on(&crtc->base);
@@ -6547,7 +6548,6 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
ironlake_pch_enable(state, pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -6713,7 +6713,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7089,7 +7088,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
dev_priv->display.initial_watermarks(state, pipe_config);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7149,7 +7147,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 03/10] drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the assert_vblank_disabled() into intel_crtc_vblank_on()
so that we don't have to inline it all over.
This does mean we now assert_vblank_disabled() during readout as well
but that is totally fine as it happens after drm_crtc_vblank_reset().
One can even argue it's what we want to do anyway to make sure
the reset actually happened.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bf7faaf061a3..854ccca2bf6e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -1838,6 +1838,7 @@ static void intel_crtc_vblank_on(const struct intel_crtc_state *crtc_state)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ assert_vblank_disabled(&crtc->base);
drm_crtc_set_max_vblank_count(&crtc->base,
intel_crtc_max_vblank_count(crtc_state));
drm_crtc_vblank_on(&crtc->base);
@@ -6547,7 +6548,6 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
ironlake_pch_enable(state, pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -6713,7 +6713,6 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (pipe_config->has_pch_encoder)
lpt_pch_enable(state, pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7089,7 +7088,6 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
dev_priv->display.initial_watermarks(state, pipe_config);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
@@ -7149,7 +7147,6 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
- assert_vblank_disabled(crtc);
intel_crtc_vblank_on(pipe_config);
intel_encoders_enable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 04/10] drm/i915: Move crtc_state to tighter scope
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_modeset_setup_hw_state() doesn't need the crtc_state at the
top level scope. Move it to where it's needed.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 854ccca2bf6e..084f94ec79a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17785,7 +17785,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_state *crtc_state;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
@@ -17818,7 +17817,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
* waits, so we need vblank interrupts restored beforehand.
*/
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
drm_crtc_vblank_reset(&crtc->base);
@@ -17832,7 +17832,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
intel_sanitize_encoder(encoder);
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
intel_sanitize_crtc(crtc, ctx);
intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
}
@@ -17865,9 +17867,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
}
for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
u64 put_domains;
- crtc_state = to_intel_crtc_state(crtc->base.state);
put_domains = modeset_get_crtc_power_domains(crtc_state);
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 04/10] drm/i915: Move crtc_state to tighter scope
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
intel_modeset_setup_hw_state() doesn't need the crtc_state at the
top level scope. Move it to where it's needed.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 11 +++++++----
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 854ccca2bf6e..084f94ec79a4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -17785,7 +17785,6 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
struct drm_modeset_acquire_ctx *ctx)
{
struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc_state *crtc_state;
struct intel_encoder *encoder;
struct intel_crtc *crtc;
intel_wakeref_t wakeref;
@@ -17818,7 +17817,8 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
* waits, so we need vblank interrupts restored beforehand.
*/
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
drm_crtc_vblank_reset(&crtc->base);
@@ -17832,7 +17832,9 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
intel_sanitize_encoder(encoder);
for_each_intel_crtc(&dev_priv->drm, crtc) {
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ struct intel_crtc_state *crtc_state =
+ crtc_state = to_intel_crtc_state(crtc->base.state);
+
intel_sanitize_crtc(crtc, ctx);
intel_dump_pipe_config(crtc_state, NULL, "[setup_hw_state]");
}
@@ -17865,9 +17867,10 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
}
for_each_intel_crtc(dev, crtc) {
+ struct intel_crtc_state *crtc_state =
+ to_intel_crtc_state(crtc->base.state);
u64 put_domains;
- crtc_state = to_intel_crtc_state(crtc->base.state);
put_domains = modeset_get_crtc_power_domains(crtc_state);
if (WARN_ON(put_domains))
modeset_put_power_domains(dev_priv, put_domains);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 05/10] drm/i915: Pass intel_crtc to ironlake_fdi_disable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Switch to intel_crtc from drm_crtc.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 084f94ec79a4..c873c85a69a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5061,12 +5061,10 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
udelay(100);
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_disable(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp;
@@ -6772,7 +6770,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_disable(intel_crtc);
intel_encoders_post_disable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 05/10] drm/i915: Pass intel_crtc to ironlake_fdi_disable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Switch to intel_crtc from drm_crtc.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 084f94ec79a4..c873c85a69a7 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5061,12 +5061,10 @@ static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
udelay(100);
}
-static void ironlake_fdi_disable(struct drm_crtc *crtc)
+static void ironlake_fdi_disable(struct intel_crtc *crtc)
{
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
i915_reg_t reg;
u32 temp;
@@ -6772,7 +6770,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(crtc);
+ ironlake_fdi_disable(intel_crtc);
intel_encoders_post_disable(state, intel_crtc);
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
time for the caller when it doesn't have to think what to pass.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
3 files changed, 53 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c873c85a69a7..68a7e5d467ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6189,9 +6189,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(intel_state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(intel_state, crtc);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc);
}
@@ -6539,8 +6538,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6698,8 +6697,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(intel_crtc);
@@ -7083,7 +7082,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, pipe_config);
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
@@ -7138,9 +7137,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
else
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
@@ -14316,6 +14314,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state);
@@ -14339,8 +14338,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
}
if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state,
- new_crtc_state);
+ dev_priv->display.atomic_update_watermarks(state, crtc);
}
static void intel_update_crtc(struct intel_crtc *crtc,
@@ -14444,8 +14442,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state,
- new_crtc_state);
+ dev_priv->display.initial_watermarks(state, crtc);
}
static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
@@ -14895,8 +14892,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state,
- new_crtc_state);
+ dev_priv->display.optimize_watermarks(state, crtc);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -16851,7 +16847,7 @@ static void sanitize_watermarks(struct drm_device *dev)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc_state);
+ dev_priv->display.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bbf4dfdfa8ba..9b37c0d657de 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
void (*initial_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 287602b1e426..5aad9d49a528 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1528,10 +1528,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
}
static void g4x_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1540,10 +1541,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
}
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -1923,11 +1925,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state;
int sprite0_start, sprite1_start, fifo_size;
@@ -2147,10 +2150,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
}
static void vlv_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2159,10 +2163,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
}
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -5499,11 +5504,12 @@ skl_compute_wm(struct intel_atomic_state *state)
}
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe;
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5513,10 +5519,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
}
static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_values *results = &state->wm_results;
if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5525,7 +5532,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex);
if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc_state);
+ skl_atomic_update_crtc_wm(state, crtc);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
@@ -5581,10 +5588,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
}
static void ilk_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5593,10 +5601,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 06/10] drm/i915: Change watermark hook calling convention
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic_state+crtc to the watermarks hooks. Eeasier
time for the caller when it doesn't have to think what to pass.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 32 +++++-----
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/intel_pm.c | 63 +++++++++++---------
3 files changed, 53 insertions(+), 48 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c873c85a69a7..68a7e5d467ff 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6189,9 +6189,8 @@ static void intel_pre_plane_update(struct intel_crtc_state *old_crtc_state,
* we'll continue to update watermarks the old way, if flags tell
* us to.
*/
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(intel_state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(intel_state, crtc);
else if (pipe_config->update_wm_pre)
intel_update_watermarks(crtc);
}
@@ -6539,8 +6538,8 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6698,8 +6697,8 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state, pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
if (INTEL_GEN(dev_priv) >= 11)
icl_pipe_mbus_enable(intel_crtc);
@@ -7083,7 +7082,7 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, pipe_config);
+ dev_priv->display.initial_watermarks(state, intel_crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
@@ -7138,9 +7137,8 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- if (dev_priv->display.initial_watermarks != NULL)
- dev_priv->display.initial_watermarks(state,
- pipe_config);
+ if (dev_priv->display.initial_watermarks)
+ dev_priv->display.initial_watermarks(state, intel_crtc);
else
intel_update_watermarks(intel_crtc);
intel_enable_pipe(pipe_config);
@@ -14316,6 +14314,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
struct intel_crtc_state *old_crtc_state,
struct intel_crtc_state *new_crtc_state)
{
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
bool modeset = needs_modeset(new_crtc_state);
@@ -14339,8 +14338,7 @@ static void commit_pipe_config(struct intel_atomic_state *state,
}
if (dev_priv->display.atomic_update_watermarks)
- dev_priv->display.atomic_update_watermarks(state,
- new_crtc_state);
+ dev_priv->display.atomic_update_watermarks(state, crtc);
}
static void intel_update_crtc(struct intel_crtc *crtc,
@@ -14444,8 +14442,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
if (!new_crtc_state->hw.active &&
!HAS_GMCH(dev_priv) &&
dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state,
- new_crtc_state);
+ dev_priv->display.initial_watermarks(state, crtc);
}
static void intel_trans_port_sync_modeset_disables(struct intel_atomic_state *state,
@@ -14895,8 +14892,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
*/
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (dev_priv->display.optimize_watermarks)
- dev_priv->display.optimize_watermarks(state,
- new_crtc_state);
+ dev_priv->display.optimize_watermarks(state, crtc);
}
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
@@ -16851,7 +16847,7 @@ static void sanitize_watermarks(struct drm_device *dev)
/* Write calculated watermark values back */
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
crtc_state->wm.need_postvbl_update = true;
- dev_priv->display.optimize_watermarks(intel_state, crtc_state);
+ dev_priv->display.optimize_watermarks(intel_state, crtc);
to_intel_crtc_state(crtc->base.state)->wm = crtc_state->wm;
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bbf4dfdfa8ba..9b37c0d657de 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -273,11 +273,11 @@ struct drm_i915_display_funcs {
int (*compute_pipe_wm)(struct intel_crtc_state *crtc_state);
int (*compute_intermediate_wm)(struct intel_crtc_state *crtc_state);
void (*initial_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*atomic_update_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
void (*optimize_watermarks)(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state);
+ struct intel_crtc *crtc);
int (*compute_global_watermarks)(struct intel_atomic_state *state);
void (*update_wm)(struct intel_crtc *crtc);
int (*modeset_calc_cdclk)(struct intel_atomic_state *state);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 287602b1e426..5aad9d49a528 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -1528,10 +1528,11 @@ static void g4x_program_watermarks(struct drm_i915_private *dev_priv)
}
static void g4x_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate;
@@ -1540,10 +1541,11 @@ static void g4x_initial_watermarks(struct intel_atomic_state *state,
}
static void g4x_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -1923,11 +1925,12 @@ static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state)
(((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_uncore *uncore = &dev_priv->uncore;
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
const struct vlv_fifo_state *fifo_state =
&crtc_state->wm.vlv.fifo_state;
int sprite0_start, sprite1_start, fifo_size;
@@ -2147,10 +2150,11 @@ static void vlv_program_watermarks(struct drm_i915_private *dev_priv)
}
static void vlv_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate;
@@ -2159,10 +2163,11 @@ static void vlv_initial_watermarks(struct intel_atomic_state *state,
}
static void vlv_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
@@ -5499,11 +5504,12 @@ skl_compute_wm(struct intel_atomic_state *state)
}
static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
enum pipe pipe = crtc->pipe;
if ((state->wm_results.dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5513,10 +5519,11 @@ static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
}
static void skl_initial_wm(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct skl_ddb_values *results = &state->wm_results;
if ((results->dirty_pipes & BIT(crtc->pipe)) == 0)
@@ -5525,7 +5532,7 @@ static void skl_initial_wm(struct intel_atomic_state *state,
mutex_lock(&dev_priv->wm.wm_mutex);
if (crtc_state->uapi.active_changed)
- skl_atomic_update_crtc_wm(state, crtc_state);
+ skl_atomic_update_crtc_wm(state, crtc);
mutex_unlock(&dev_priv->wm.wm_mutex);
}
@@ -5581,10 +5588,11 @@ static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
}
static void ilk_initial_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
mutex_lock(&dev_priv->wm.wm_mutex);
crtc->wm.active.ilk = crtc_state->wm.ilk.intermediate;
@@ -5593,10 +5601,11 @@ static void ilk_initial_watermarks(struct intel_atomic_state *state,
}
static void ilk_optimize_watermarks(struct intel_atomic_state *state,
- struct intel_crtc_state *crtc_state)
+ struct intel_crtc *crtc)
{
- struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ const struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
if (!crtc_state->wm.need_postvbl_update)
return;
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 07/10] drm/i915: Pass dev_priv to cpt_verify_modeset()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the last 'dev' usage in ironlake_crtc_enable() by
passing dev_priv to cpt_verify_modeset().
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 68a7e5d467ff..556b31bf2fb0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5474,9 +5474,9 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
-static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
+static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t dslreg = PIPEDSL(pipe);
u32 temp;
@@ -6550,7 +6550,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
- cpt_verify_modeset(dev, intel_crtc->pipe);
+ cpt_verify_modeset(dev_priv, pipe);
/*
* Must wait for vblank to avoid spurious PCH FIFO underruns.
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 07/10] drm/i915: Pass dev_priv to cpt_verify_modeset()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the last 'dev' usage in ironlake_crtc_enable() by
passing dev_priv to cpt_verify_modeset().
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 68a7e5d467ff..556b31bf2fb0 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5474,9 +5474,9 @@ static void lpt_pch_enable(const struct intel_atomic_state *state,
lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
}
-static void cpt_verify_modeset(struct drm_device *dev, enum pipe pipe)
+static void cpt_verify_modeset(struct drm_i915_private *dev_priv,
+ enum pipe pipe)
{
- struct drm_i915_private *dev_priv = to_i915(dev);
i915_reg_t dslreg = PIPEDSL(pipe);
u32 temp;
@@ -6550,7 +6550,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_enable(state, intel_crtc);
if (HAS_PCH_CPT(dev_priv))
- cpt_verify_modeset(dev, intel_crtc->pipe);
+ cpt_verify_modeset(dev_priv, pipe);
/*
* Must wait for vblank to avoid spurious PCH FIFO underruns.
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 08/10] drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the horrible aliasing drm_crtc and intel_crtc variables
in the crtc enable/disable hooks.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++----------
1 file changed, 65 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 556b31bf2fb0..d6ad32179a17 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6475,13 +6475,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
/*
@@ -6513,9 +6511,9 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
ironlake_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6539,7 +6537,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6547,7 +6545,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev_priv, pipe);
@@ -6621,22 +6619,21 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bool psl_clkgate_wa;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6668,7 +6665,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
@@ -6692,16 +6689,16 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (INTEL_GEN(dev_priv) >= 11)
- icl_set_pipe_chicken(intel_crtc);
+ icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
if (INTEL_GEN(dev_priv) >= 11)
- icl_pipe_mbus_enable(intel_crtc);
+ icl_pipe_mbus_enable(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6712,7 +6709,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6746,11 +6743,9 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* Sometimes spurious CPU pipe underruns happen when the
@@ -6760,18 +6755,18 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(intel_crtc);
+ ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6794,7 +6789,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
I915_WRITE(PCH_DPLL_SEL, temp);
}
- ironlake_fdi_pll_disable(intel_crtc);
+ ironlake_fdi_pll_disable(crtc);
}
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6804,14 +6799,13 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6826,13 +6820,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_dsc_disable(old_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_scaler_disable(intel_crtc);
+ skylake_scaler_disable(crtc);
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7037,13 +7031,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
if (intel_crtc_has_dp_encoder(pipe_config))
@@ -7059,21 +7051,21 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(intel_crtc, pipe_config);
- chv_enable_pll(intel_crtc, pipe_config);
+ chv_prepare_pll(crtc, pipe_config);
+ chv_enable_pll(crtc, pipe_config);
} else {
- vlv_prepare_pll(intel_crtc, pipe_config);
- vlv_enable_pll(intel_crtc, pipe_config);
+ vlv_prepare_pll(crtc, pipe_config);
+ vlv_enable_pll(crtc, pipe_config);
}
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
i9xx_pfit_enable(pipe_config);
@@ -7082,12 +7074,12 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7102,13 +7094,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
i9xx_set_pll_dividers(pipe_config);
@@ -7121,14 +7111,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(intel_crtc, pipe_config);
+ i9xx_enable_pll(crtc, pipe_config);
i9xx_pfit_enable(pipe_config);
@@ -7138,14 +7128,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7166,11 +7156,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* On gen2 planes are double buffered but the pipe isn't, so we must
@@ -7179,15 +7167,15 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7198,13 +7186,13 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 08/10] drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Get rid of the horrible aliasing drm_crtc and intel_crtc variables
in the crtc enable/disable hooks.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 142 +++++++++----------
1 file changed, 65 insertions(+), 77 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 556b31bf2fb0..d6ad32179a17 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6475,13 +6475,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
/*
@@ -6513,9 +6511,9 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
ironlake_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (pipe_config->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
@@ -6539,7 +6537,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
if (pipe_config->has_pch_encoder)
@@ -6547,7 +6545,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (HAS_PCH_CPT(dev_priv))
cpt_verify_modeset(dev_priv, pipe);
@@ -6621,22 +6619,21 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe, hsw_workaround_pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
bool psl_clkgate_wa;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (pipe_config->shared_dpll)
intel_enable_shared_dpll(pipe_config);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
if (intel_crtc_has_dp_encoder(pipe_config))
intel_dp_set_m_n(pipe_config, M1_N1);
@@ -6668,7 +6665,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
bdw_set_pipemisc(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
@@ -6692,16 +6689,16 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (INTEL_GEN(dev_priv) >= 11)
- icl_set_pipe_chicken(intel_crtc);
+ icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
intel_ddi_enable_transcoder_func(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
if (INTEL_GEN(dev_priv) >= 11)
- icl_pipe_mbus_enable(intel_crtc);
+ icl_pipe_mbus_enable(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6712,7 +6709,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
if (psl_clkgate_wa) {
intel_wait_for_vblank(dev_priv, pipe);
@@ -6746,11 +6743,9 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* Sometimes spurious CPU pipe underruns happen when the
@@ -6760,18 +6755,18 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
ironlake_pfit_disable(old_crtc_state);
if (old_crtc_state->has_pch_encoder)
- ironlake_fdi_disable(intel_crtc);
+ ironlake_fdi_disable(crtc);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (old_crtc_state->has_pch_encoder) {
ironlake_disable_pch_transcoder(dev_priv, pipe);
@@ -6794,7 +6789,7 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
I915_WRITE(PCH_DPLL_SEL, temp);
}
- ironlake_fdi_pll_disable(intel_crtc);
+ ironlake_fdi_pll_disable(crtc);
}
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
@@ -6804,14 +6799,13 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_i915_private *dev_priv = to_i915(crtc->dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
@@ -6826,13 +6820,13 @@ static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_dsc_disable(old_crtc_state);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_scaler_disable(intel_crtc);
+ skylake_scaler_disable(crtc);
else
ironlake_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
}
static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
@@ -7037,13 +7031,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
if (intel_crtc_has_dp_encoder(pipe_config))
@@ -7059,21 +7051,21 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_pll_enable(state, intel_crtc);
+ intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(intel_crtc, pipe_config);
- chv_enable_pll(intel_crtc, pipe_config);
+ chv_prepare_pll(crtc, pipe_config);
+ chv_enable_pll(crtc, pipe_config);
} else {
- vlv_prepare_pll(intel_crtc, pipe_config);
- vlv_enable_pll(intel_crtc, pipe_config);
+ vlv_prepare_pll(crtc, pipe_config);
+ vlv_enable_pll(crtc, pipe_config);
}
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
i9xx_pfit_enable(pipe_config);
@@ -7082,12 +7074,12 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
/* update DSPCNTR to configure gamma for pipe bottom color */
intel_disable_primary_plane(pipe_config);
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
@@ -7102,13 +7094,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = pipe_config->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
- if (WARN_ON(intel_crtc->active))
+ if (WARN_ON(crtc->active))
return;
i9xx_set_pll_dividers(pipe_config);
@@ -7121,14 +7111,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
i9xx_set_pipeconf(pipe_config);
- intel_crtc->active = true;
+ crtc->active = true;
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
- intel_encoders_pre_enable(state, intel_crtc);
+ intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(intel_crtc, pipe_config);
+ i9xx_enable_pll(crtc, pipe_config);
i9xx_pfit_enable(pipe_config);
@@ -7138,14 +7128,14 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_disable_primary_plane(pipe_config);
if (dev_priv->display.initial_watermarks)
- dev_priv->display.initial_watermarks(state, intel_crtc);
+ dev_priv->display.initial_watermarks(state, crtc);
else
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
intel_enable_pipe(pipe_config);
intel_crtc_vblank_on(pipe_config);
- intel_encoders_enable(state, intel_crtc);
+ intel_encoders_enable(state, crtc);
}
static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
@@ -7166,11 +7156,9 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
struct intel_atomic_state *state)
{
- struct drm_crtc *crtc = old_crtc_state->uapi.crtc;
- struct drm_device *dev = crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
- struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
- enum pipe pipe = intel_crtc->pipe;
+ struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ enum pipe pipe = crtc->pipe;
/*
* On gen2 planes are double buffered but the pipe isn't, so we must
@@ -7179,15 +7167,15 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
if (IS_GEN(dev_priv, 2))
intel_wait_for_vblank(dev_priv, pipe);
- intel_encoders_disable(state, intel_crtc);
+ intel_encoders_disable(state, crtc);
- intel_crtc_vblank_off(intel_crtc);
+ intel_crtc_vblank_off(crtc);
intel_disable_pipe(old_crtc_state);
i9xx_pfit_disable(old_crtc_state);
- intel_encoders_post_disable(state, intel_crtc);
+ intel_encoders_post_disable(state, crtc);
if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
if (IS_CHERRYVIEW(dev_priv))
@@ -7198,13 +7186,13 @@ static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
i9xx_disable_pll(old_crtc_state);
}
- intel_encoders_post_pll_disable(state, intel_crtc);
+ intel_encoders_post_pll_disable(state, crtc);
if (!IS_GEN(dev_priv, 2))
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
if (!dev_priv->display.initial_watermarks)
- intel_update_watermarks(intel_crtc);
+ intel_update_watermarks(crtc);
/* clock the pipe down to 640x480@60 to potentially save power */
if (IS_I830(dev_priv))
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
The 'pipe_config' name is a zombie that we need to finally put down.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 173 +++++++++----------
1 file changed, 85 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d6ad32179a17..27204a499f93 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6472,10 +6472,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
+static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6495,55 +6495,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- if (pipe_config->has_pch_encoder)
- intel_prepare_shared_dpll(pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ intel_prepare_shared_dpll(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
- ironlake_set_pipeconf(pipe_config);
+ ironlake_set_pipeconf(new_crtc_state);
crtc->active = true;
intel_encoders_pre_enable(state, crtc);
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
- ironlake_fdi_pll_enable(pipe_config);
+ ironlake_fdi_pll_enable(new_crtc_state);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
}
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- ironlake_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ ironlake_pch_enable(state, new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6556,7 +6555,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
* some interlaced HDMI modes. Let's do the double wait always
* in case there are more corner cases we don't know about.
*/
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
intel_wait_for_vblank(dev_priv, pipe);
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -6616,13 +6615,13 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
I915_WRITE(reg, val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
+static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
bool psl_clkgate_wa;
if (WARN_ON(crtc->active))
@@ -6630,69 +6629,67 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
- if (pipe_config->shared_dpll)
- intel_enable_shared_dpll(pipe_config);
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
- icl_enable_trans_port_sync(pipe_config);
+ icl_enable_trans_port_sync(new_crtc_state);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_src_size(new_crtc_state);
if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder)) {
+ !transcoder_is_dsi(cpu_transcoder))
I915_WRITE(PIPE_MULT(cpu_transcoder),
- pipe_config->pixel_multiplier - 1);
- }
+ new_crtc_state->pixel_multiplier - 1);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
if (!transcoder_is_dsi(cpu_transcoder)) {
- hsw_set_frame_start_delay(pipe_config);
- haswell_set_pipeconf(pipe_config);
+ hsw_set_frame_start_delay(new_crtc_state);
+ haswell_set_pipeconf(new_crtc_state);
}
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(pipe_config);
+ bdw_set_pipemisc(new_crtc_state);
crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
- pipe_config->pch_pfit.enabled;
+ new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_pfit_enable(pipe_config);
+ skylake_pfit_enable(new_crtc_state);
else
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma/csc for pipe bottom color */
if (INTEL_GEN(dev_priv) < 9)
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_ddi_enable_transcoder_func(pipe_config);
+ intel_ddi_enable_transcoder_func(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
@@ -6702,12 +6699,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- lpt_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ lpt_pch_enable(state, new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6718,7 +6715,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
- hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
+ hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
@@ -7028,28 +7025,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
+static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
I915_WRITE(CHV_CANVAS(pipe), 0);
}
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7058,26 +7055,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(crtc, pipe_config);
- chv_enable_pll(crtc, pipe_config);
+ chv_prepare_pll(crtc, new_crtc_state);
+ chv_enable_pll(crtc, new_crtc_state);
} else {
- vlv_prepare_pll(crtc, pipe_config);
- vlv_enable_pll(crtc, pipe_config);
+ vlv_prepare_pll(crtc, new_crtc_state);
+ vlv_enable_pll(crtc, new_crtc_state);
}
intel_encoders_pre_enable(state, crtc);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
@@ -7091,25 +7088,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
+static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- i9xx_set_pll_dividers(pipe_config);
+ i9xx_set_pll_dividers(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7118,22 +7115,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(crtc, pipe_config);
+ i9xx_enable_pll(crtc, new_crtc_state);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
--
2.23.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 09/10] drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename pipe_config to new_crtc_state in the .crtc_enable() hooks.
The 'pipe_config' name is a zombie that we need to finally put down.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 173 +++++++++----------
1 file changed, 85 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index d6ad32179a17..27204a499f93 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6472,10 +6472,10 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
+static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6495,55 +6495,54 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
- if (pipe_config->has_pch_encoder)
- intel_prepare_shared_dpll(pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ intel_prepare_shared_dpll(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
- ironlake_set_pipeconf(pipe_config);
+ ironlake_set_pipeconf(new_crtc_state);
crtc->active = true;
intel_encoders_pre_enable(state, crtc);
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
/* Note: FDI PLL enabling _must_ be done before we enable the
* cpu pipes, hence this is separate from all the other fdi/pch
* enabling. */
- ironlake_fdi_pll_enable(pipe_config);
+ ironlake_fdi_pll_enable(new_crtc_state);
} else {
assert_fdi_tx_disabled(dev_priv, pipe);
assert_fdi_rx_disabled(dev_priv, pipe);
}
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- ironlake_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ ironlake_pch_enable(state, new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6556,7 +6555,7 @@ static void ironlake_crtc_enable(struct intel_crtc_state *pipe_config,
* some interlaced HDMI modes. Let's do the double wait always
* in case there are more corner cases we don't know about.
*/
- if (pipe_config->has_pch_encoder) {
+ if (new_crtc_state->has_pch_encoder) {
intel_wait_for_vblank(dev_priv, pipe);
intel_wait_for_vblank(dev_priv, pipe);
}
@@ -6616,13 +6615,13 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
I915_WRITE(reg, val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
+static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
- enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
+ enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
bool psl_clkgate_wa;
if (WARN_ON(crtc->active))
@@ -6630,69 +6629,67 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
- if (pipe_config->shared_dpll)
- intel_enable_shared_dpll(pipe_config);
+ if (new_crtc_state->shared_dpll)
+ intel_enable_shared_dpll(new_crtc_state);
intel_encoders_pre_enable(state, crtc);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_set_pipe_timings(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
- icl_enable_trans_port_sync(pipe_config);
+ icl_enable_trans_port_sync(new_crtc_state);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_src_size(new_crtc_state);
if (cpu_transcoder != TRANSCODER_EDP &&
- !transcoder_is_dsi(cpu_transcoder)) {
+ !transcoder_is_dsi(cpu_transcoder))
I915_WRITE(PIPE_MULT(cpu_transcoder),
- pipe_config->pixel_multiplier - 1);
- }
+ new_crtc_state->pixel_multiplier - 1);
- if (pipe_config->has_pch_encoder) {
- intel_cpu_transcoder_set_m_n(pipe_config,
- &pipe_config->fdi_m_n, NULL);
- }
+ if (new_crtc_state->has_pch_encoder)
+ intel_cpu_transcoder_set_m_n(new_crtc_state,
+ &new_crtc_state->fdi_m_n, NULL);
if (!transcoder_is_dsi(cpu_transcoder)) {
- hsw_set_frame_start_delay(pipe_config);
- haswell_set_pipeconf(pipe_config);
+ hsw_set_frame_start_delay(new_crtc_state);
+ haswell_set_pipeconf(new_crtc_state);
}
if (INTEL_GEN(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
- bdw_set_pipemisc(pipe_config);
+ bdw_set_pipemisc(new_crtc_state);
crtc->active = true;
/* Display WA #1180: WaDisableScalarClockGating: glk, cnl */
psl_clkgate_wa = (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
- pipe_config->pch_pfit.enabled;
+ new_crtc_state->pch_pfit.enabled;
if (psl_clkgate_wa)
glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
if (INTEL_GEN(dev_priv) >= 9)
- skylake_pfit_enable(pipe_config);
+ skylake_pfit_enable(new_crtc_state);
else
- ironlake_pfit_enable(pipe_config);
+ ironlake_pfit_enable(new_crtc_state);
/*
* On ILK+ LUT must be loaded before the pipe is running but with
* clocks enabled
*/
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma/csc for pipe bottom color */
if (INTEL_GEN(dev_priv) < 9)
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (INTEL_GEN(dev_priv) >= 11)
icl_set_pipe_chicken(crtc);
if (!transcoder_is_dsi(cpu_transcoder))
- intel_ddi_enable_transcoder_func(pipe_config);
+ intel_ddi_enable_transcoder_func(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
@@ -6702,12 +6699,12 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* XXX: Do the pipe assertions at the right place for BXT DSI. */
if (!transcoder_is_dsi(cpu_transcoder))
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- if (pipe_config->has_pch_encoder)
- lpt_pch_enable(state, pipe_config);
+ if (new_crtc_state->has_pch_encoder)
+ lpt_pch_enable(state, new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
@@ -6718,7 +6715,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
/* If we change the relative order between pipe/planes enabling, we need
* to change the workaround. */
- hsw_workaround_pipe = pipe_config->hsw_workaround_pipe;
+ hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
intel_wait_for_vblank(dev_priv, hsw_workaround_pipe);
@@ -7028,28 +7025,28 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
+static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
I915_WRITE(CHV_BLEND(pipe), CHV_BLEND_LEGACY);
I915_WRITE(CHV_CANVAS(pipe), 0);
}
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7058,26 +7055,26 @@ static void valleyview_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_pll_enable(state, crtc);
if (IS_CHERRYVIEW(dev_priv)) {
- chv_prepare_pll(crtc, pipe_config);
- chv_enable_pll(crtc, pipe_config);
+ chv_prepare_pll(crtc, new_crtc_state);
+ chv_enable_pll(crtc, new_crtc_state);
} else {
- vlv_prepare_pll(crtc, pipe_config);
- vlv_enable_pll(crtc, pipe_config);
+ vlv_prepare_pll(crtc, new_crtc_state);
+ vlv_enable_pll(crtc, new_crtc_state);
}
intel_encoders_pre_enable(state, crtc);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
dev_priv->display.initial_watermarks(state, crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
@@ -7091,25 +7088,25 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
+static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
struct intel_atomic_state *state)
{
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
if (WARN_ON(crtc->active))
return;
- i9xx_set_pll_dividers(pipe_config);
+ i9xx_set_pll_dividers(new_crtc_state);
- if (intel_crtc_has_dp_encoder(pipe_config))
- intel_dp_set_m_n(pipe_config, M1_N1);
+ if (intel_crtc_has_dp_encoder(new_crtc_state))
+ intel_dp_set_m_n(new_crtc_state, M1_N1);
- intel_set_pipe_timings(pipe_config);
- intel_set_pipe_src_size(pipe_config);
+ intel_set_pipe_timings(new_crtc_state);
+ intel_set_pipe_src_size(new_crtc_state);
- i9xx_set_pipeconf(pipe_config);
+ i9xx_set_pipeconf(new_crtc_state);
crtc->active = true;
@@ -7118,22 +7115,22 @@ static void i9xx_crtc_enable(struct intel_crtc_state *pipe_config,
intel_encoders_pre_enable(state, crtc);
- i9xx_enable_pll(crtc, pipe_config);
+ i9xx_enable_pll(crtc, new_crtc_state);
- i9xx_pfit_enable(pipe_config);
+ i9xx_pfit_enable(new_crtc_state);
- intel_color_load_luts(pipe_config);
- intel_color_commit(pipe_config);
+ intel_color_load_luts(new_crtc_state);
+ intel_color_commit(new_crtc_state);
/* update DSPCNTR to configure gamma for pipe bottom color */
- intel_disable_primary_plane(pipe_config);
+ intel_disable_primary_plane(new_crtc_state);
if (dev_priv->display.initial_watermarks)
dev_priv->display.initial_watermarks(state, crtc);
else
intel_update_watermarks(crtc);
- intel_enable_pipe(pipe_config);
+ intel_enable_pipe(new_crtc_state);
- intel_crtc_vblank_on(pipe_config);
+ intel_crtc_vblank_on(new_crtc_state);
intel_encoders_enable(state, crtc);
}
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [PATCH v2 10/10] drm/i915: Change .crtc_enable/disable() calling convention
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state+crtc to the .crtc_enable()
.crtc_disable(). Life is easier when you don't have to think
whether to pass the old or the new crtc state.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 8 +--
2 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27204a499f93..cbe5ceea20fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6472,10 +6472,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6615,10 +6616,11 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
I915_WRITE(reg, val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
@@ -6737,10 +6739,11 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
}
-static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6793,10 +6796,11 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
-static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
@@ -7025,10 +7029,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void valleyview_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7088,10 +7093,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7150,10 +7156,11 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
I915_WRITE(PFIT_CONTROL, 0);
}
-static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7239,7 +7246,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
WARN_ON(IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
+ dev_priv->display.crtc_disable(to_intel_atomic_state(state),
+ intel_crtc);
drm_atomic_state_put(state);
@@ -14340,7 +14348,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
if (modeset) {
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
@@ -14411,7 +14419,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(old_crtc_state, state);
+ dev_priv->display.crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -14526,7 +14534,7 @@ static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
intel_crtc_enable_pipe_crc(crtc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b37c0d657de..fdae5a919bc8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -290,10 +290,10 @@ struct drm_i915_display_funcs {
struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
- void (*crtc_enable)(struct intel_crtc_state *pipe_config,
- struct intel_atomic_state *old_state);
- void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *old_state);
+ void (*crtc_enable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*crtc_disable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
void (*audio_codec_enable)(struct intel_encoder *encoder,
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread* [Intel-gfx] [PATCH v2 10/10] drm/i915: Change .crtc_enable/disable() calling convention
@ 2019-11-18 16:44 ` Ville Syrjala
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjala @ 2019-11-18 16:44 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Just pass the atomic state+crtc to the .crtc_enable()
.crtc_disable(). Life is easier when you don't have to think
whether to pass the old or the new crtc state.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 58 +++++++++++---------
drivers/gpu/drm/i915/i915_drv.h | 8 +--
2 files changed, 37 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 27204a499f93..cbe5ceea20fa 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6472,10 +6472,11 @@ static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_stat
plane->disable_plane(plane, crtc_state);
}
-static void ironlake_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6615,10 +6616,11 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
I915_WRITE(reg, val);
}
-static void haswell_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
@@ -6737,10 +6739,11 @@ static void ironlake_pfit_disable(const struct intel_crtc_state *old_crtc_state)
}
}
-static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void ironlake_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -6793,10 +6796,11 @@ static void ironlake_crtc_disable(struct intel_crtc_state *old_crtc_state,
intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
}
-static void haswell_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void haswell_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
@@ -7025,10 +7029,11 @@ static void modeset_put_power_domains(struct drm_i915_private *dev_priv,
intel_display_power_put_unchecked(dev_priv, domain);
}
-static void valleyview_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void valleyview_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7088,10 +7093,11 @@ static void i9xx_set_pll_dividers(const struct intel_crtc_state *crtc_state)
I915_WRITE(FP1(crtc->pipe), crtc_state->dpll_hw_state.fp1);
}
-static void i9xx_crtc_enable(struct intel_crtc_state *new_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_enable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
+ const struct intel_crtc_state *new_crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7150,10 +7156,11 @@ static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
I915_WRITE(PFIT_CONTROL, 0);
}
-static void i9xx_crtc_disable(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *state)
+static void i9xx_crtc_disable(struct intel_atomic_state *state,
+ struct intel_crtc *crtc)
{
- struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
+ struct intel_crtc_state *old_crtc_state =
+ intel_atomic_get_old_crtc_state(state, crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum pipe pipe = crtc->pipe;
@@ -7239,7 +7246,8 @@ static void intel_crtc_disable_noatomic(struct drm_crtc *crtc,
WARN_ON(IS_ERR(temp_crtc_state) || ret);
- dev_priv->display.crtc_disable(temp_crtc_state, to_intel_atomic_state(state));
+ dev_priv->display.crtc_disable(to_intel_atomic_state(state),
+ intel_crtc);
drm_atomic_state_put(state);
@@ -14340,7 +14348,7 @@ static void intel_update_crtc(struct intel_crtc *crtc,
if (modeset) {
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
/* vblanks work again, re-enable pipe CRC. */
intel_crtc_enable_pipe_crc(crtc);
@@ -14411,7 +14419,7 @@ static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
*/
intel_crtc_disable_pipe_crc(crtc);
- dev_priv->display.crtc_disable(old_crtc_state, state);
+ dev_priv->display.crtc_disable(state, crtc);
crtc->active = false;
intel_fbc_disable(crtc);
intel_disable_shared_dpll(old_crtc_state);
@@ -14526,7 +14534,7 @@ static void intel_crtc_enable_trans_port_sync(struct intel_crtc *crtc,
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
intel_crtc_update_active_timings(new_crtc_state);
- dev_priv->display.crtc_enable(new_crtc_state, state);
+ dev_priv->display.crtc_enable(state, crtc);
intel_crtc_enable_pipe_crc(crtc);
}
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9b37c0d657de..fdae5a919bc8 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -290,10 +290,10 @@ struct drm_i915_display_funcs {
struct intel_initial_plane_config *);
int (*crtc_compute_clock)(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
- void (*crtc_enable)(struct intel_crtc_state *pipe_config,
- struct intel_atomic_state *old_state);
- void (*crtc_disable)(struct intel_crtc_state *old_crtc_state,
- struct intel_atomic_state *old_state);
+ void (*crtc_enable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
+ void (*crtc_disable)(struct intel_atomic_state *state,
+ struct intel_crtc *crtc);
void (*commit_modeset_enables)(struct intel_atomic_state *state);
void (*commit_modeset_disables)(struct intel_atomic_state *state);
void (*audio_codec_enable)(struct intel_encoder *encoder,
--
2.23.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 30+ messages in thread
* ✗ Fi.CI.BAT: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev3)
@ 2019-11-18 20:00 ` Patchwork
0 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2019-11-18 20:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev3)
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7365 -> Patchwork_15318
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15318 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15318, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15318:
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-apl-guc/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_15318 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [DMESG-WARN][2] ([fdo#112261]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick: [INCOMPLETE][4] ([fdo# 111542]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][6] ([fdo#111045] / [fdo#111096]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
[fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298
Participating hosts (50 -> 44)
------------------------------
Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7365 -> Patchwork_15318
CI-20190529: 20190529
CI_DRM_7365: ae28c3736610ca3c242ea9d0af8cbc767a0ddeba @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5292: ea9cd47fdb72c16d5ec84c04a85122c451c30025 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15318: 51722a3c4a400139e36da7dff37d811e43764742 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
51722a3c4a40 drm/i915: Change .crtc_enable/disable() calling convention
994e8c898a9d drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
bdda7ae229b6 drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
b00425fbe162 drm/i915: Pass dev_priv to cpt_verify_modeset()
a6b69213c21d drm/i915: Change watermark hook calling convention
e64f45c936f0 drm/i915: Pass intel_crtc to ironlake_fdi_disable()
3fdf29be4a79 drm/i915: Move crtc_state to tighter scope
23c61ad2eab5 drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
6b1221da3421 drm/i915: Add intel_crtc_vblank_off()
05f430adcdf3 drm/i915: Change intel_encoders_<hook>() calling convention
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev3)
@ 2019-11-18 20:00 ` Patchwork
0 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2019-11-18 20:00 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev3)
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7365 -> Patchwork_15318
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15318 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15318, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15318:
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-apl-guc/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_15318 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [DMESG-WARN][2] ([fdo#112261]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick: [INCOMPLETE][4] ([fdo# 111542]) -> [PASS][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][6] ([fdo#111045] / [fdo#111096]) -> [PASS][7]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7365/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo# 111542]: https://bugs.freedesktop.org/show_bug.cgi?id= 111542
[fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#112261]: https://bugs.freedesktop.org/show_bug.cgi?id=112261
[fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298
Participating hosts (50 -> 44)
------------------------------
Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7365 -> Patchwork_15318
CI-20190529: 20190529
CI_DRM_7365: ae28c3736610ca3c242ea9d0af8cbc767a0ddeba @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5292: ea9cd47fdb72c16d5ec84c04a85122c451c30025 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15318: 51722a3c4a400139e36da7dff37d811e43764742 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
51722a3c4a40 drm/i915: Change .crtc_enable/disable() calling convention
994e8c898a9d drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
bdda7ae229b6 drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
b00425fbe162 drm/i915: Pass dev_priv to cpt_verify_modeset()
a6b69213c21d drm/i915: Change watermark hook calling convention
e64f45c936f0 drm/i915: Pass intel_crtc to ironlake_fdi_disable()
3fdf29be4a79 drm/i915: Move crtc_state to tighter scope
23c61ad2eab5 drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
6b1221da3421 drm/i915: Add intel_crtc_vblank_off()
05f430adcdf3 drm/i915: Change intel_encoders_<hook>() calling convention
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* Re: ✗ Fi.CI.BAT: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev3)
@ 2019-11-19 14:27 ` Ville Syrjälä
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjälä @ 2019-11-19 14:27 UTC (permalink / raw)
To: intel-gfx
On Mon, Nov 18, 2019 at 08:00:07PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Cleanups around .crtc_enable/disable() (rev3)
> URL : https://patchwork.freedesktop.org/series/69352/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7365 -> Patchwork_15318
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_15318 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_15318, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_15318:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@runner@aborted:
> - fi-apl-guc: NOTRUN -> [FAIL][1]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-apl-guc/igt@runner@aborted.html
<3>[ 172.016356] BUG jbd2_journal_head (Tainted: G U ): Redzone overwritten
<3>[ 172.016440] -----------------------------------------------------------------------------
<3>[ 172.016544] INFO: 0x00000000b51300f6-0x00000000b51300f6. First byte 0xbf instead of 0xbb
<3>[ 172.016640] INFO: Allocated in jbd2_journal_add_journal_head+0x93/0x1b0 age=1235 cpu=2 pid=2191
...
<3>[ 172.017564] INFO: Freed in jbd2_journal_put_journal_head+0xef/0x1b9 age=1148 cpu=0 pid=232
Doesn't really match the pattern in
https://bugs.freedesktop.org/show_bug.cgi?id=111863
except by having bit 2 flipped as well.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev3)
@ 2019-11-19 14:27 ` Ville Syrjälä
0 siblings, 0 replies; 30+ messages in thread
From: Ville Syrjälä @ 2019-11-19 14:27 UTC (permalink / raw)
To: intel-gfx
On Mon, Nov 18, 2019 at 08:00:07PM -0000, Patchwork wrote:
> == Series Details ==
>
> Series: drm/i915: Cleanups around .crtc_enable/disable() (rev3)
> URL : https://patchwork.freedesktop.org/series/69352/
> State : failure
>
> == Summary ==
>
> CI Bug Log - changes from CI_DRM_7365 -> Patchwork_15318
> ====================================================
>
> Summary
> -------
>
> **FAILURE**
>
> Serious unknown changes coming with Patchwork_15318 absolutely need to be
> verified manually.
>
> If you think the reported changes have nothing to do with the changes
> introduced in Patchwork_15318, please notify your bug team to allow them
> to document this new failure mode, which will reduce false positives in CI.
>
> External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/index.html
>
> Possible new issues
> -------------------
>
> Here are the unknown changes that may have been introduced in Patchwork_15318:
>
> ### IGT changes ###
>
> #### Possible regressions ####
>
> * igt@runner@aborted:
> - fi-apl-guc: NOTRUN -> [FAIL][1]
> [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15318/fi-apl-guc/igt@runner@aborted.html
<3>[ 172.016356] BUG jbd2_journal_head (Tainted: G U ): Redzone overwritten
<3>[ 172.016440] -----------------------------------------------------------------------------
<3>[ 172.016544] INFO: 0x00000000b51300f6-0x00000000b51300f6. First byte 0xbf instead of 0xbb
<3>[ 172.016640] INFO: Allocated in jbd2_journal_add_journal_head+0x93/0x1b0 age=1235 cpu=2 pid=2191
...
<3>[ 172.017564] INFO: Freed in jbd2_journal_put_journal_head+0xef/0x1b9 age=1148 cpu=0 pid=232
Doesn't really match the pattern in
https://bugs.freedesktop.org/show_bug.cgi?id=111863
except by having bit 2 flipped as well.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Cleanups around .crtc_enable/disable() (rev4)
@ 2019-11-19 15:22 ` Patchwork
0 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2019-11-19 15:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev4)
URL : https://patchwork.freedesktop.org/series/69352/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7371 -> Patchwork_15329
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/index.html
Known issues
------------
Here are the changes found in Patchwork_15329 that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_busy@basic-flip-pipe-a:
- fi-icl-u2: [TIMEOUT][1] ([fdo#111800]) -> [PASS][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/fi-icl-u2/igt@kms_busy@basic-flip-pipe-a.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][3] ([fdo#111407]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111800]: https://bugs.freedesktop.org/show_bug.cgi?id=111800
Participating hosts (50 -> 44)
------------------------------
Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7371 -> Patchwork_15329
CI-20190529: 20190529
CI_DRM_7371: 4a9a6d1fade97c450a0eabbc3436f1dc5518b15e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5295: 9211e4794e40135d797e6d056d6d8d40076acb92 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15329: db4218f02897a41488c48d54b5757b29fbc74c6e @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
db4218f02897 drm/i915: Change .crtc_enable/disable() calling convention
3d8164cfaf48 drm/i915: s/pipe_config/new_crtc_state/ in .crtc_enable()
fb22d42c4ead drm/i915: s/intel_crtc/crtc/ in .crtc_enable() and .crtc_disable()
18eae5a36d19 drm/i915: Pass dev_priv to cpt_verify_modeset()
e654f5ae7ba6 drm/i915: Change watermark hook calling convention
f12e66beeb39 drm/i915: Pass intel_crtc to ironlake_fdi_disable()
3255e30c8634 drm/i915: Move crtc_state to tighter scope
34bc068536a5 drm/i915: Move assert_vblank_disabled() into intel_crtc_vblank_on()
27b52f9c78ba drm/i915: Add intel_crtc_vblank_off()
1cf7018c4c93 drm/i915: Change intel_encoders_<hook>() calling convention
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 30+ messages in thread* ✗ Fi.CI.IGT: failure for drm/i915: Cleanups around .crtc_enable/disable() (rev4)
@ 2019-11-20 0:02 ` Patchwork
0 siblings, 0 replies; 30+ messages in thread
From: Patchwork @ 2019-11-20 0:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Cleanups around .crtc_enable/disable() (rev4)
URL : https://patchwork.freedesktop.org/series/69352/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7371_full -> Patchwork_15329_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15329_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15329_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15329_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-skl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-skl2/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
Known issues
------------
Here are the changes found in Patchwork_15329_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#112080]) +14 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb4/igt@gem_busy@busy-vcs1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb5/igt@gem_busy@busy-vcs1.html
* igt@gem_ctx_isolation@vcs1-s3:
- shard-tglb: [PASS][5] -> [INCOMPLETE][6] ([fdo#111832])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb9/igt@gem_ctx_isolation@vcs1-s3.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb5/igt@gem_ctx_isolation@vcs1-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#109276] / [fdo#112080]) +4 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb6/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_ctx_shared@exec-single-timeline-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#110841])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb8/igt@gem_ctx_shared@exec-single-timeline-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd.html
* igt@gem_eio@reset-stress:
- shard-snb: [PASS][11] -> [FAIL][12] ([fdo#109661])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-snb4/igt@gem_eio@reset-stress.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-snb4/igt@gem_eio@reset-stress.html
* igt@gem_exec_parallel@basic:
- shard-tglb: [PASS][13] -> [INCOMPLETE][14] ([fdo#111887])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb9/igt@gem_exec_parallel@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb6/igt@gem_exec_parallel@basic.html
* igt@gem_exec_parallel@contexts:
- shard-snb: [PASS][15] -> [INCOMPLETE][16] ([fdo#105411])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-snb7/igt@gem_exec_parallel@contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-snb1/igt@gem_exec_parallel@contexts.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#112146]) +12 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb5/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb4/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109276]) +18 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb1/igt@gem_exec_schedule@promotion-bsd1.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb3/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-apl: [PASS][21] -> [TIMEOUT][22] ([fdo#112113])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-apl2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-apl8/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-glk: [PASS][23] -> [DMESG-FAIL][24] ([fdo#112309])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-glk7/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-glk2/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-kbl: [PASS][25] -> [FAIL][26] ([fdo#112037])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-kbl1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-kbl2/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_pipe_control_store_loop@reused-buffer:
- shard-tglb: [PASS][27] -> [INCOMPLETE][28] ([fdo#111998])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb8/igt@gem_pipe_control_store_loop@reused-buffer.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb6/igt@gem_pipe_control_store_loop@reused-buffer.html
* igt@gem_softpin@noreloc-s3:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([fdo#108566]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-kbl3/igt@gem_softpin@noreloc-s3.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-kbl4/igt@gem_softpin@noreloc-s3.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-hsw: [PASS][31] -> [DMESG-WARN][32] ([fdo#111870]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-hsw1/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-hsw6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_userptr_blits@sync-unmap:
- shard-snb: [PASS][33] -> [DMESG-WARN][34] ([fdo#111870])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-snb1/igt@gem_userptr_blits@sync-unmap.html
* igt@i915_pm_dc@dc6-dpms:
- shard-iclb: [PASS][35] -> [FAIL][36] ([fdo#111830 ]) +1 similar issue
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb1/igt@i915_pm_dc@dc6-dpms.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_selftest@live_gt_timelines:
- shard-tglb: [PASS][37] -> [INCOMPLETE][38] ([fdo#111831])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb5/igt@i915_selftest@live_gt_timelines.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb9/igt@i915_selftest@live_gt_timelines.html
* igt@i915_selftest@live_hangcheck:
- shard-hsw: [PASS][39] -> [DMESG-FAIL][40] ([fdo#111991])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-hsw1/igt@i915_selftest@live_hangcheck.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-hsw5/igt@i915_selftest@live_hangcheck.html
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: [PASS][41] -> [FAIL][42] ([fdo#103167]) +6 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [PASS][43] -> [FAIL][44] ([fdo#103167]) +4 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: [PASS][45] -> [DMESG-WARN][46] ([fdo#108566])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: [PASS][47] -> [FAIL][48] ([fdo#108145])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: [PASS][49] -> [FAIL][50] ([fdo#103166])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb4/igt@kms_plane_lowres@pipe-a-tiling-x.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb5/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@no_drrs:
- shard-iclb: [PASS][51] -> [FAIL][52] ([fdo#108341])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb8/igt@kms_psr@no_drrs.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb1/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#109441]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb8/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_psr@suspend:
- shard-tglb: [PASS][55] -> [INCOMPLETE][56] ([fdo#111832] / [fdo#111850]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb5/igt@kms_psr@suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb7/igt@kms_psr@suspend.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][57] -> [FAIL][58] ([fdo#99912])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-apl1/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-apl4/igt@kms_setmode@basic.html
* igt@perf@short-reads:
- shard-hsw: [PASS][59] -> [FAIL][60] ([fdo#103183])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-hsw4/igt@perf@short-reads.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-hsw4/igt@perf@short-reads.html
#### Possible fixes ####
* igt@gem_ctx_persistence@vcs1-hostile-preempt:
- shard-iclb: [SKIP][61] ([fdo#109276] / [fdo#112080]) -> [PASS][62] +3 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb5/igt@gem_ctx_persistence@vcs1-hostile-preempt.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb4/igt@gem_ctx_persistence@vcs1-hostile-preempt.html
* igt@gem_exec_balancer@smoke:
- shard-iclb: [SKIP][63] ([fdo#110854]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb5/igt@gem_exec_balancer@smoke.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb4/igt@gem_exec_balancer@smoke.html
* igt@gem_exec_parallel@vcs1-fds:
- shard-iclb: [SKIP][65] ([fdo#112080]) -> [PASS][66] +20 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb3/igt@gem_exec_parallel@vcs1-fds.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb1/igt@gem_exec_parallel@vcs1-fds.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [SKIP][67] ([fdo#112146]) -> [PASS][68] +3 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb5/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_exec_whisper@normal:
- shard-tglb: [INCOMPLETE][69] ([fdo#111747]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb6/igt@gem_exec_whisper@normal.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb4/igt@gem_exec_whisper@normal.html
* igt@gem_softpin@noreloc-s3:
- shard-tglb: [INCOMPLETE][71] ([fdo#111832]) -> [PASS][72] +1 similar issue
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb8/igt@gem_softpin@noreloc-s3.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb6/igt@gem_softpin@noreloc-s3.html
* igt@gem_sync@basic-all:
- shard-tglb: [INCOMPLETE][73] ([fdo#111880]) -> [PASS][74]
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb6/igt@gem_sync@basic-all.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb3/igt@gem_sync@basic-all.html
* igt@gem_userptr_blits@sync-unmap-after-close:
- shard-hsw: [DMESG-WARN][75] ([fdo#111870]) -> [PASS][76]
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-hsw4/igt@gem_userptr_blits@sync-unmap-after-close.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-tglb: [INCOMPLETE][77] ([fdo#111832] / [fdo#111850]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb1/igt@gem_workarounds@suspend-resume-fd.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb1/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_flip@2x-flip-vs-expired-vblank:
- shard-glk: [FAIL][79] ([fdo#105363]) -> [PASS][80]
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-glk7/igt@kms_flip@2x-flip-vs-expired-vblank.html
* igt@kms_flip@flip-vs-expired-vblank:
- shard-skl: [FAIL][81] ([fdo#105363]) -> [PASS][82] +1 similar issue
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-skl10/igt@kms_flip@flip-vs-expired-vblank.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-skl9/igt@kms_flip@flip-vs-expired-vblank.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt:
- shard-tglb: [FAIL][83] ([fdo#103167]) -> [PASS][84] +1 similar issue
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-msflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [DMESG-WARN][85] ([fdo#108566]) -> [PASS][86] +4 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-apl6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-kbl: [DMESG-WARN][87] ([fdo#108566]) -> [PASS][88] +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [FAIL][89] ([fdo#108145] / [fdo#110403]) -> [PASS][90]
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-skl8/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [SKIP][91] ([fdo#109441]) -> [PASS][92]
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb6/igt@kms_psr@psr2_no_drrs.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-skl: [INCOMPLETE][93] ([fdo#104108]) -> [PASS][94]
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-skl10/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-skl9/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
* igt@prime_busy@hang-bsd2:
- shard-iclb: [SKIP][95] ([fdo#109276]) -> [PASS][96] +29 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-iclb6/igt@prime_busy@hang-bsd2.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-iclb2/igt@prime_busy@hang-bsd2.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs2-dirty-create:
- shard-tglb: [SKIP][97] ([fdo#111912] / [fdo#112080]) -> [SKIP][98] ([fdo#112080])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb3/igt@gem_ctx_isolation@vcs2-dirty-create.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-create.html
* igt@gem_exec_schedule@deep-bsd1:
- shard-tglb: [FAIL][99] ([fdo#111646]) -> [INCOMPLETE][100] ([fdo#111671])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb3/igt@gem_exec_schedule@deep-bsd1.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb4/igt@gem_exec_schedule@deep-bsd1.html
* igt@gem_exec_schedule@deep-bsd2:
- shard-tglb: [INCOMPLETE][101] ([fdo#111671]) -> [FAIL][102] ([fdo#111646])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb6/igt@gem_exec_schedule@deep-bsd2.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb8/igt@gem_exec_schedule@deep-bsd2.html
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-tglb: [SKIP][103] ([fdo#112016 ] / [fdo#112021 ]) -> [SKIP][104] ([fdo#112021 ])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7371/shard-tglb3/igt@kms_atomic_transition@6x-modeset-transitions.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103166]: https://bugs.freedesktop.org/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15329/index.html
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