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* [PATCH] riscv: virt: Allow PCI address 0
@ 2019-11-22 15:27 Bin Meng
  2019-11-22 22:41 ` Palmer Dabbelt
  0 siblings, 1 reply; 5+ messages in thread
From: Bin Meng @ 2019-11-22 15:27 UTC (permalink / raw)
  To: Alistair Francis, Bastian Koppelmann, Palmer Dabbelt,
	Sagar Karandikar, qemu-devel, qemu-riscv

When testing e1000 with the virt machine, e1000's I/O space cannot
be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
written with address 0 plus I/O enable bit, but QEMU's "info pci"
shows that:

  Bus  0, device   1, function 0:
    Ethernet controller: PCI device 8086:100e
  ...
      BAR1: I/O at 0xffffffffffffffff [0x003e].
  ...

It turns out we should set pci_allow_0_address to true to allow 0
PCI address, otherwise pci_bar_address() treats such address as
PCI_BAR_UNMAPPED.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 hw/riscv/virt.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 23f340d..411bef5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -603,6 +603,7 @@ static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
     mc->init = riscv_virt_board_init;
     mc->max_cpus = 8;
     mc->default_cpu_type = VIRT_CPU;
+    mc->pci_allow_0_address = true;
 }
 
 static const TypeInfo riscv_virt_machine_typeinfo = {
-- 
2.7.4



^ permalink raw reply related	[flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: virt: Allow PCI address 0
  2019-11-22 15:27 [PATCH] riscv: virt: Allow PCI address 0 Bin Meng
@ 2019-11-22 22:41 ` Palmer Dabbelt
  2020-02-02 15:41     ` Bin Meng
  0 siblings, 1 reply; 5+ messages in thread
From: Palmer Dabbelt @ 2019-11-22 22:41 UTC (permalink / raw)
  To: bmeng.cn
  Cc: Alistair Francis, Bastian Koppelmann, sagark, qemu-devel, qemu-riscv

On Fri, 22 Nov 2019 07:27:52 PST (-0800), bmeng.cn@gmail.com wrote:
> When testing e1000 with the virt machine, e1000's I/O space cannot
> be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
> written with address 0 plus I/O enable bit, but QEMU's "info pci"
> shows that:
>
>   Bus  0, device   1, function 0:
>     Ethernet controller: PCI device 8086:100e
>   ...
>       BAR1: I/O at 0xffffffffffffffff [0x003e].
>   ...
>
> It turns out we should set pci_allow_0_address to true to allow 0
> PCI address, otherwise pci_bar_address() treats such address as
> PCI_BAR_UNMAPPED.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> ---
>
>  hw/riscv/virt.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> index 23f340d..411bef5 100644
> --- a/hw/riscv/virt.c
> +++ b/hw/riscv/virt.c
> @@ -603,6 +603,7 @@ static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
>      mc->init = riscv_virt_board_init;
>      mc->max_cpus = 8;
>      mc->default_cpu_type = VIRT_CPU;
> +    mc->pci_allow_0_address = true;
>  }
>
>  static const TypeInfo riscv_virt_machine_typeinfo = {

Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>

I've put this on for-next, as I don't think this is 4.2 material.

Thanks!


^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: virt: Allow PCI address 0
  2019-11-22 22:41 ` Palmer Dabbelt
@ 2020-02-02 15:41     ` Bin Meng
  0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2020-02-02 15:41 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: Bastian Koppelmann, Alistair Francis,
	qemu-devel@nongnu.org Developers, Sagar Karandikar,
	open list:RISC-V

Hi Palmer,

On Sat, Nov 23, 2019 at 6:41 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> On Fri, 22 Nov 2019 07:27:52 PST (-0800), bmeng.cn@gmail.com wrote:
> > When testing e1000 with the virt machine, e1000's I/O space cannot
> > be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
> > written with address 0 plus I/O enable bit, but QEMU's "info pci"
> > shows that:
> >
> >   Bus  0, device   1, function 0:
> >     Ethernet controller: PCI device 8086:100e
> >   ...
> >       BAR1: I/O at 0xffffffffffffffff [0x003e].
> >   ...
> >
> > It turns out we should set pci_allow_0_address to true to allow 0
> > PCI address, otherwise pci_bar_address() treats such address as
> > PCI_BAR_UNMAPPED.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> >  hw/riscv/virt.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 23f340d..411bef5 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -603,6 +603,7 @@ static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
> >      mc->init = riscv_virt_board_init;
> >      mc->max_cpus = 8;
> >      mc->default_cpu_type = VIRT_CPU;
> > +    mc->pci_allow_0_address = true;
> >  }
> >
> >  static const TypeInfo riscv_virt_machine_typeinfo = {
>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>
> I've put this on for-next, as I don't think this is 4.2 material.

Looks you missed picking up this one :(

Regards,
Bin


^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: virt: Allow PCI address 0
@ 2020-02-02 15:41     ` Bin Meng
  0 siblings, 0 replies; 5+ messages in thread
From: Bin Meng @ 2020-02-02 15:41 UTC (permalink / raw)
  To: Palmer Dabbelt
  Cc: Alistair Francis, Bastian Koppelmann, Sagar Karandikar,
	qemu-devel@nongnu.org Developers, open list:RISC-V

Hi Palmer,

On Sat, Nov 23, 2019 at 6:41 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>
> On Fri, 22 Nov 2019 07:27:52 PST (-0800), bmeng.cn@gmail.com wrote:
> > When testing e1000 with the virt machine, e1000's I/O space cannot
> > be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
> > written with address 0 plus I/O enable bit, but QEMU's "info pci"
> > shows that:
> >
> >   Bus  0, device   1, function 0:
> >     Ethernet controller: PCI device 8086:100e
> >   ...
> >       BAR1: I/O at 0xffffffffffffffff [0x003e].
> >   ...
> >
> > It turns out we should set pci_allow_0_address to true to allow 0
> > PCI address, otherwise pci_bar_address() treats such address as
> > PCI_BAR_UNMAPPED.
> >
> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> > ---
> >
> >  hw/riscv/virt.c | 1 +
> >  1 file changed, 1 insertion(+)
> >
> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
> > index 23f340d..411bef5 100644
> > --- a/hw/riscv/virt.c
> > +++ b/hw/riscv/virt.c
> > @@ -603,6 +603,7 @@ static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
> >      mc->init = riscv_virt_board_init;
> >      mc->max_cpus = 8;
> >      mc->default_cpu_type = VIRT_CPU;
> > +    mc->pci_allow_0_address = true;
> >  }
> >
> >  static const TypeInfo riscv_virt_machine_typeinfo = {
>
> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>
> I've put this on for-next, as I don't think this is 4.2 material.

Looks you missed picking up this one :(

Regards,
Bin


^ permalink raw reply	[flat|nested] 5+ messages in thread
* Re: [PATCH] riscv: virt: Allow PCI address 0
  2020-02-02 15:41     ` Bin Meng
  (?)
@ 2020-02-18 16:30     ` Palmer Dabbelt
  -1 siblings, 0 replies; 5+ messages in thread
From: Palmer Dabbelt @ 2020-02-18 16:30 UTC (permalink / raw)
  To: bmeng.cn
  Cc: Alistair Francis, Bastian Koppelmann, sagark, qemu-devel, qemu-riscv

On Sun, 02 Feb 2020 07:41:25 PST (-0800), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Sat, Nov 23, 2019 at 6:41 AM Palmer Dabbelt <palmerdabbelt@google.com> wrote:
>>
>> On Fri, 22 Nov 2019 07:27:52 PST (-0800), bmeng.cn@gmail.com wrote:
>> > When testing e1000 with the virt machine, e1000's I/O space cannot
>> > be accessed. Debugging shows that the I/O BAR (BAR1) is correctly
>> > written with address 0 plus I/O enable bit, but QEMU's "info pci"
>> > shows that:
>> >
>> >   Bus  0, device   1, function 0:
>> >     Ethernet controller: PCI device 8086:100e
>> >   ...
>> >       BAR1: I/O at 0xffffffffffffffff [0x003e].
>> >   ...
>> >
>> > It turns out we should set pci_allow_0_address to true to allow 0
>> > PCI address, otherwise pci_bar_address() treats such address as
>> > PCI_BAR_UNMAPPED.
>> >
>> > Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> > ---
>> >
>> >  hw/riscv/virt.c | 1 +
>> >  1 file changed, 1 insertion(+)
>> >
>> > diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
>> > index 23f340d..411bef5 100644
>> > --- a/hw/riscv/virt.c
>> > +++ b/hw/riscv/virt.c
>> > @@ -603,6 +603,7 @@ static void riscv_virt_machine_class_init(ObjectClass *oc, void *data)
>> >      mc->init = riscv_virt_board_init;
>> >      mc->max_cpus = 8;
>> >      mc->default_cpu_type = VIRT_CPU;
>> > +    mc->pci_allow_0_address = true;
>> >  }
>> >
>> >  static const TypeInfo riscv_virt_machine_typeinfo = {
>>
>> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com>
>>
>> I've put this on for-next, as I don't think this is 4.2 material.
>
> Looks you missed picking up this one :(

Sorry about that, it's back on for-master.


^ permalink raw reply	[flat|nested] 5+ messages in thread
end of thread, other threads:[~2020-02-18 16:31 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-22 15:27 [PATCH] riscv: virt: Allow PCI address 0 Bin Meng
2019-11-22 22:41 ` Palmer Dabbelt
2020-02-02 15:41   ` Bin Meng
2020-02-02 15:41     ` Bin Meng
2020-02-18 16:30     ` Palmer Dabbelt

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