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* [PATCH v6 0/3] Dynamic EU configuration of Slice/Sub-slice/EU
@ 2019-11-26  4:51 ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel

This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc. Following are the power savings.

Power savings on GLK-GT1 Bobba platform running on Chrome OS.
-----------------------------------------------|
App /KPI                | % Power Benefit (mW) |
------------------------|----------------------|
Hangout Call- 20 minute |	1.8%           |
Youtube 4K VPB          |       14.13%         |
WebGL Aquarium          |       13.76%         |
Unity3D                 |       6.78%          |
			|		       |
------------------------|----------------------|
Chrome PLT              | BatteryLife Improves |
			| by ~45 minute        |
-----------------------------------------------|

Power savings on KBL-GT3 running on  Android and Ubuntu (Linux).
-----------------------------------------------|
App /KPI              	| % Power Benefit (mW) |
                        |----------------------|
			|  Android |  Ubuntu   |
------------------------|----------|-----------|
3D Mark (Ice storm)     | 2.30%    | N.A.      |
TRex On screen          | 2.49%    | 2.97%     |
Manhattan On screen     | 3.11%    | 4.90%     |
Carchase On Screen	| N.A.     | 5.06%     |
AnTuTu 6.1.4            | 3.42%    | N.A.      |
SynMark2		| N.A.     | 1.7%      |
-----------------------------------------------|

We have also observed GPU core residencies improves by 1.035%.

Technical Insights of the patch:
Current GPU configuration code for i915 does not allow us to change
EU/Slice/Sub-slice configuration dynamically. Its done only once while context
is created.

While particular graphics application is running, if we examine the command
requests from user space, we observe that command density is not consistent.
It means there is scope to change the graphics configuration dynamically even
while context is running actively. This patch series proposes the solution to
find the active pending load for all active context at given time and based on
that, dynamically perform graphics configuration for each context.

We use a hr (high resolution) timer with i915 driver in kernel to get a
callback every few milliseconds (this timer value can be configured through
debugfs, default is '0' indicating timer is in disabled state i.e. original
system without any intervention).In the timer callback, we examine pending
commands for a context in the queue, essentially, we intercept them before
they are executed by GPU and we update context with required number of EUs.

Two questions, how did we arrive at right timer value? and what's the right
number of EUs? For the prior one, empirical data to achieve best performance
in least power was considered. For the later one, we roughly categorized number 
of EUs logically based on platform. Now we compare number of pending commands
with a particular threshold and then set number of EUs accordingly with update
context. That threshold is also based on experiments & findings. If GPU is able
to catch up with CPU, typically there are no pending commands, the EU config
would remain unchanged there. In case there are more pending commands we
reprogram context with higher number of EUs. Please note, here we are changing
EUs even while context is running by examining pending commands every 'x'
milliseconds.

Ankit Navik (3):
  drm/i915: Get active pending request for given context
  drm/i915: set optimum eu/slice/sub-slice configuration based on load
    type
  drm/i915: Predictive governor to control slice/subslice/eu

 drivers/gpu/drm/i915/Makefile                     |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_context.c       |  19 ++++
 drivers/gpu/drm/i915/gem/i915_gem_context.h       |   2 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h |  37 ++++++++
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c    |   2 +
 drivers/gpu/drm/i915/gt/intel_deu.c               | 104 ++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_deu.h               |  31 +++++++
 drivers/gpu/drm/i915/gt/intel_lrc.c               |  45 +++++++++-
 drivers/gpu/drm/i915/i915_drv.h                   |   9 ++
 drivers/gpu/drm/i915/i915_gem.c                   |   4 +
 drivers/gpu/drm/i915/i915_params.c                |   4 +
 drivers/gpu/drm/i915/i915_params.h                |   1 +
 drivers/gpu/drm/i915/intel_device_info.c          |  62 ++++++++++++-
 13 files changed, 317 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v6 0/3] Dynamic EU configuration of Slice/Sub-slice/EU
@ 2019-11-26  4:51 ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

drm/i915: Context aware user agnostic EU/Slice/Sub-slice control within kernel

This patch sets improves GPU power consumption on Linux kernel based OS such as
Chromium OS, Ubuntu, etc. Following are the power savings.

Power savings on GLK-GT1 Bobba platform running on Chrome OS.
-----------------------------------------------|
App /KPI                | % Power Benefit (mW) |
------------------------|----------------------|
Hangout Call- 20 minute |	1.8%           |
Youtube 4K VPB          |       14.13%         |
WebGL Aquarium          |       13.76%         |
Unity3D                 |       6.78%          |
			|		       |
------------------------|----------------------|
Chrome PLT              | BatteryLife Improves |
			| by ~45 minute        |
-----------------------------------------------|

Power savings on KBL-GT3 running on  Android and Ubuntu (Linux).
-----------------------------------------------|
App /KPI              	| % Power Benefit (mW) |
                        |----------------------|
			|  Android |  Ubuntu   |
------------------------|----------|-----------|
3D Mark (Ice storm)     | 2.30%    | N.A.      |
TRex On screen          | 2.49%    | 2.97%     |
Manhattan On screen     | 3.11%    | 4.90%     |
Carchase On Screen	| N.A.     | 5.06%     |
AnTuTu 6.1.4            | 3.42%    | N.A.      |
SynMark2		| N.A.     | 1.7%      |
-----------------------------------------------|

We have also observed GPU core residencies improves by 1.035%.

Technical Insights of the patch:
Current GPU configuration code for i915 does not allow us to change
EU/Slice/Sub-slice configuration dynamically. Its done only once while context
is created.

While particular graphics application is running, if we examine the command
requests from user space, we observe that command density is not consistent.
It means there is scope to change the graphics configuration dynamically even
while context is running actively. This patch series proposes the solution to
find the active pending load for all active context at given time and based on
that, dynamically perform graphics configuration for each context.

We use a hr (high resolution) timer with i915 driver in kernel to get a
callback every few milliseconds (this timer value can be configured through
debugfs, default is '0' indicating timer is in disabled state i.e. original
system without any intervention).In the timer callback, we examine pending
commands for a context in the queue, essentially, we intercept them before
they are executed by GPU and we update context with required number of EUs.

Two questions, how did we arrive at right timer value? and what's the right
number of EUs? For the prior one, empirical data to achieve best performance
in least power was considered. For the later one, we roughly categorized number 
of EUs logically based on platform. Now we compare number of pending commands
with a particular threshold and then set number of EUs accordingly with update
context. That threshold is also based on experiments & findings. If GPU is able
to catch up with CPU, typically there are no pending commands, the EU config
would remain unchanged there. In case there are more pending commands we
reprogram context with higher number of EUs. Please note, here we are changing
EUs even while context is running by examining pending commands every 'x'
milliseconds.

Ankit Navik (3):
  drm/i915: Get active pending request for given context
  drm/i915: set optimum eu/slice/sub-slice configuration based on load
    type
  drm/i915: Predictive governor to control slice/subslice/eu

 drivers/gpu/drm/i915/Makefile                     |   1 +
 drivers/gpu/drm/i915/gem/i915_gem_context.c       |  19 ++++
 drivers/gpu/drm/i915/gem/i915_gem_context.h       |   2 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h |  37 ++++++++
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c    |   2 +
 drivers/gpu/drm/i915/gt/intel_deu.c               | 104 ++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_deu.h               |  31 +++++++
 drivers/gpu/drm/i915/gt/intel_lrc.c               |  45 +++++++++-
 drivers/gpu/drm/i915/i915_drv.h                   |   9 ++
 drivers/gpu/drm/i915/i915_gem.c                   |   4 +
 drivers/gpu/drm/i915/i915_params.c                |   4 +
 drivers/gpu/drm/i915/i915_params.h                |   1 +
 drivers/gpu/drm/i915/intel_device_info.c          |  62 ++++++++++++-
 13 files changed, 317 insertions(+), 4 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h

-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [PATCH v6 1/3] drm/i915: Get active pending request for given context
@ 2019-11-26  4:51   ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

This patch gives us the active pending request count which is yet
to be submitted to the GPU.

V2:
 * Change 64-bit to atomic for request count. (Tvrtko Ursulin)

V3:
 * Remove mutex for request count.
 * Rebase.
 * Fixes hitting underflow for predictive request. (Tvrtko Ursulin)

V4:
 * Rebase.

V5:
 * Rebase.

V6
 * Rebase.

Cc: Vipin Anand <vipin.anand@intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c       | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 5 +++++
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c    | 2 ++
 drivers/gpu/drm/i915/gt/intel_lrc.c               | 3 +++
 4 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c94ac83..8288fb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -712,6 +712,7 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
 	}
 
 	trace_i915_context_create(ctx);
+	atomic_set(&ctx->req_cnt, 0);
 
 	return ctx;
 }
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index c060bc4..3931c06 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -168,6 +168,11 @@ struct i915_gem_context {
 	 */
 	struct radix_tree_root handles_vma;
 
+	/** req_cnt: tracks the pending commands, based on which we decide to
+	 * go for low/medium/high load configuration of the GPU.
+	 */
+	atomic_t req_cnt;
+
 	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
 	 *  Guarded by struct_mutex
 	 */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7a87e82..83f4392 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2700,6 +2700,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	if (eb.batch->private)
 		intel_engine_pool_mark_active(eb.batch->private, eb.request);
 
+	atomic_inc(&eb.gem_context->req_cnt);
+
 	trace_i915_request_queue(eb.request, eb.batch_flags);
 	err = eb_submit(&eb);
 err_request:
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4cd0d46..511d5a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1956,6 +1956,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 
 				submit = true;
 				last = rq;
+
+				if (atomic_read(&rq->gem_context->req_cnt) > 0)
+					atomic_dec(&rq->gem_context->req_cnt);
 			}
 		}
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v6 1/3] drm/i915: Get active pending request for given context
@ 2019-11-26  4:51   ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

This patch gives us the active pending request count which is yet
to be submitted to the GPU.

V2:
 * Change 64-bit to atomic for request count. (Tvrtko Ursulin)

V3:
 * Remove mutex for request count.
 * Rebase.
 * Fixes hitting underflow for predictive request. (Tvrtko Ursulin)

V4:
 * Rebase.

V5:
 * Rebase.

V6
 * Rebase.

Cc: Vipin Anand <vipin.anand@intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c       | 1 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 5 +++++
 drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c    | 2 ++
 drivers/gpu/drm/i915/gt/intel_lrc.c               | 3 +++
 4 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index c94ac83..8288fb9 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -712,6 +712,7 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
 	}
 
 	trace_i915_context_create(ctx);
+	atomic_set(&ctx->req_cnt, 0);
 
 	return ctx;
 }
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index c060bc4..3931c06 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -168,6 +168,11 @@ struct i915_gem_context {
 	 */
 	struct radix_tree_root handles_vma;
 
+	/** req_cnt: tracks the pending commands, based on which we decide to
+	 * go for low/medium/high load configuration of the GPU.
+	 */
+	atomic_t req_cnt;
+
 	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
 	 *  Guarded by struct_mutex
 	 */
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
index 7a87e82..83f4392 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
@@ -2700,6 +2700,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
 	if (eb.batch->private)
 		intel_engine_pool_mark_active(eb.batch->private, eb.request);
 
+	atomic_inc(&eb.gem_context->req_cnt);
+
 	trace_i915_request_queue(eb.request, eb.batch_flags);
 	err = eb_submit(&eb);
 err_request:
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 4cd0d46..511d5a1 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1956,6 +1956,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
 
 				submit = true;
 				last = rq;
+
+				if (atomic_read(&rq->gem_context->req_cnt) > 0)
+					atomic_dec(&rq->gem_context->req_cnt);
 			}
 		}
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
@ 2019-11-26  4:51   ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select optimum configuration from
pre-defined optimum configuration table(opt_config).

It also introduce flag update_render_config which can set by any governor.

v2:
 * Move static optimum_config to device init time.
 * Rename function to appropriate name, fix data types and patch ordering.
 * Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)

v3:
 * Add safe guard check in i915_gem_context_set_load_type.
 * Rename struct from optimum_config to i915_sseu_optimum_config to
   avoid namespace clashes.
 * Reduces memcpy for space efficient.
 * Rebase.
 * Improved commit message. (Tvrtko Ursulin)

v4:
 * Move optimum config table to file scope. (Tvrtko Ursulin)

v5:
 * Adds optimal table of slice/sub-slice/EU for Gen 9 GT1.
 * Rebase.

v6:
 * Rebase.
 * Fix warnings.

Cc: Vipin Anand <vipin.anand@intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c       | 18 +++++++
 drivers/gpu/drm/i915/gem/i915_gem_context.h       |  2 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 32 ++++++++++++
 drivers/gpu/drm/i915/gt/intel_lrc.c               | 42 ++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h                   |  5 ++
 drivers/gpu/drm/i915/intel_device_info.c          | 62 ++++++++++++++++++++++-
 6 files changed, 157 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 8288fb9..ac94f92 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -713,10 +713,28 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
 
 	trace_i915_context_create(ctx);
 	atomic_set(&ctx->req_cnt, 0);
+	ctx->slice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.slice_mask);
+	ctx->subslice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.subslice_mask[0]);
+	ctx->eu_cnt = RUNTIME_INFO(i915)->sseu.eu_per_subslice;
 
 	return ctx;
 }
 
+void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
+				    enum gem_load_type type)
+{
+	struct drm_i915_private *dev_priv = ctx->i915;
+
+	if (GEM_WARN_ON(type > LOAD_TYPE_LAST))
+		return;
+
+	/* Call opt_config to get correct configuration for eu,slice,subslice */
+	ctx->slice_cnt = dev_priv->opt_config[type].slice;
+	ctx->subslice_cnt = dev_priv->opt_config[type].subslice;
+	ctx->eu_cnt = dev_priv->opt_config[type].eu;
+	ctx->pending_load_type = type;
+}
+
 static void
 destroy_kernel_context(struct i915_gem_context **ctxp)
 {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 18e50a7..8677427 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -177,6 +177,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
 				    struct drm_file *file_priv);
 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
 				       struct drm_file *file);
+void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
+				enum gem_load_type type);
 
 struct i915_gem_context *
 i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 3931c06..6847d49 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -40,6 +40,19 @@ struct i915_gem_engines_iter {
 	const struct i915_gem_engines *engines;
 };
 
+enum gem_load_type {
+	LOAD_TYPE_LOW,
+	LOAD_TYPE_MEDIUM,
+	LOAD_TYPE_HIGH,
+	LOAD_TYPE_LAST
+};
+
+struct i915_sseu_optimum_config {
+	u8 slice;
+	u8 subslice;
+	u8 eu;
+};
+
 /**
  * struct i915_gem_context - client state
  *
@@ -173,6 +186,25 @@ struct i915_gem_context {
 	 */
 	atomic_t req_cnt;
 
+	/** slice_cnt: used to set the # of slices to be enabled. */
+	u8 slice_cnt;
+
+	/** subslice_cnt: used to set the # of subslices to be enabled. */
+	u8 subslice_cnt;
+
+	/** eu_cnt: used to set the # of eu to be enabled. */
+	u8 eu_cnt;
+
+	/** load_type: The designated load_type (high/medium/low) for a given
+	 * number of pending commands in the command queue.
+	 */
+	enum gem_load_type load_type;
+
+	/** pending_load_type: The earlier load type that the GPU was configured
+	 * for (high/medium/low).
+	 */
+	enum gem_load_type pending_load_type;
+
 	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
 	 *  Guarded by struct_mutex
 	 */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 511d5a1..c3f279e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2436,6 +2436,36 @@ static void execlists_context_unpin(struct intel_context *ce)
 	intel_ring_reset(ce->ring, ce->ring->tail);
 }
 
+static u32
+get_context_rpcs_config(struct i915_gem_context *ctx)
+{
+	u32 rpcs = 0;
+	struct drm_i915_private *dev_priv = ctx->i915;
+
+	if (INTEL_GEN(dev_priv) < 8)
+		return 0;
+
+	if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) {
+		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
+		rpcs |= ctx->slice_cnt << GEN8_RPCS_S_CNT_SHIFT;
+		rpcs |= GEN8_RPCS_ENABLE;
+	}
+
+	if (RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg) {
+		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
+		rpcs |= ctx->subslice_cnt << GEN8_RPCS_SS_CNT_SHIFT;
+		rpcs |= GEN8_RPCS_ENABLE;
+	}
+
+	if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) {
+		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MIN_SHIFT;
+		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MAX_SHIFT;
+		rpcs |= GEN8_RPCS_ENABLE;
+	}
+
+	return rpcs;
+}
+
 static void
 __execlists_update_reg_state(const struct intel_context *ce,
 			     const struct intel_engine_cs *engine)
@@ -2452,8 +2482,13 @@ __execlists_update_reg_state(const struct intel_context *ce,
 
 	/* RPCS */
 	if (engine->class == RENDER_CLASS) {
-		regs[CTX_R_PWR_CLK_STATE] =
-			intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+		if (engine->i915->predictive_load_enable) {
+			regs[CTX_R_PWR_CLK_STATE] =
+				get_context_rpcs_config(ce->gem_context);
+		} else {
+			regs[CTX_R_PWR_CLK_STATE] =
+				intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+		}
 
 		i915_oa_init_reg_state(ce, engine);
 	}
@@ -2485,6 +2520,9 @@ __execlists_context_pin(struct intel_context *ce,
 	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
 	__execlists_update_reg_state(ce, engine);
 
+	if (ce->gem_context->load_type != ce->gem_context->pending_load_type)
+		ce->gem_context->load_type = ce->gem_context->pending_load_type;
+
 	return 0;
 
 unpin_active:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdae5a9..3064ddf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -999,6 +999,11 @@ struct drm_i915_private {
 	/* protects panel power sequencer state */
 	struct mutex pps_mutex;
 
+	/* optimal slice/subslice/EU configration state */
+	struct i915_sseu_optimum_config *opt_config;
+
+	int predictive_load_enable;
+
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_preferred_vco_freq;
 	unsigned int max_cdclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a5b5713..b3c2f92 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -873,6 +873,34 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 }
 
+/* static table of slice/subslice/EU for Cherryview */
+static const struct i915_sseu_optimum_config chv_config[LOAD_TYPE_LAST] = {
+	{1, 1, 4},	/* Low */
+	{1, 1, 6},	/* Medium */
+	{1, 2, 6}	/* High */
+};
+
+/* static table of slice/subslice/EU for GLK GT1 */
+static const struct i915_sseu_optimum_config glk_gt1_config[LOAD_TYPE_LAST] = {
+	{1, 2, 2},	/* Low */
+	{1, 2, 3},	/* Medium */
+	{1, 2, 6}	/* High */
+};
+
+/* static table of slice/subslice/EU for KBL GT2 */
+static const struct i915_sseu_optimum_config kbl_gt2_config[LOAD_TYPE_LAST] = {
+	{1, 3, 2},	/* Low */
+	{1, 3, 4},	/* Medium */
+	{1, 3, 8}	/* High */
+};
+
+/* static table of slice/subslice/EU for KBL GT3 */
+static const struct i915_sseu_optimum_config kbl_gt3_config[LOAD_TYPE_LAST] = {
+	{2, 3, 4},	/* Low */
+	{2, 3, 6},	/* Medium */
+	{2, 3, 8}	/* High */
+};
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
@@ -894,6 +922,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
+	struct i915_sseu_optimum_config *opt_config = NULL;
 
 	if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
@@ -999,12 +1028,38 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	/* Initialize slice/subslice/EU info */
 	if (IS_HASWELL(dev_priv))
 		haswell_sseu_info_init(dev_priv);
-	else if (IS_CHERRYVIEW(dev_priv))
+	else if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_sseu_info_init(dev_priv);
+		opt_config = (struct i915_sseu_optimum_config *)chv_config;
+		BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
+	}
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (IS_GEN(dev_priv, 9))
+	else if (IS_GEN(dev_priv, 9)) {
 		gen9_sseu_info_init(dev_priv);
+
+		switch (info->gt) {
+		default: /* fall through */
+		case 1:
+			opt_config = (struct i915_sseu_optimum_config *)
+						glk_gt1_config;
+			BUILD_BUG_ON(ARRAY_SIZE(glk_gt1_config)
+						!= LOAD_TYPE_LAST);
+		break;
+		case 2:
+			opt_config = (struct i915_sseu_optimum_config *)
+						kbl_gt2_config;
+			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config)
+						!= LOAD_TYPE_LAST);
+		break;
+		case 3:
+			opt_config = (struct i915_sseu_optimum_config *)
+						kbl_gt3_config;
+			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config)
+						!= LOAD_TYPE_LAST);
+		break;
+		}
+	}
 	else if (IS_GEN(dev_priv, 10))
 		gen10_sseu_info_init(dev_priv);
 	else if (IS_GEN(dev_priv, 11))
@@ -1017,6 +1072,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		info->ppgtt_type = INTEL_PPGTT_NONE;
 	}
 
+	if (opt_config)
+		dev_priv->opt_config = opt_config;
+
 	/* Initialize command stream timestamp frequency */
 	runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
@ 2019-11-26  4:51   ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

This patch will select optimum eu/slice/sub-slice configuration based on
type of load (low, medium, high) as input.
Based on our readings and experiments we have predefined set of optimum
configuration for each platform(CHT, KBL).
i915_gem_context_set_load_type will select optimum configuration from
pre-defined optimum configuration table(opt_config).

It also introduce flag update_render_config which can set by any governor.

v2:
 * Move static optimum_config to device init time.
 * Rename function to appropriate name, fix data types and patch ordering.
 * Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)

v3:
 * Add safe guard check in i915_gem_context_set_load_type.
 * Rename struct from optimum_config to i915_sseu_optimum_config to
   avoid namespace clashes.
 * Reduces memcpy for space efficient.
 * Rebase.
 * Improved commit message. (Tvrtko Ursulin)

v4:
 * Move optimum config table to file scope. (Tvrtko Ursulin)

v5:
 * Adds optimal table of slice/sub-slice/EU for Gen 9 GT1.
 * Rebase.

v6:
 * Rebase.
 * Fix warnings.

Cc: Vipin Anand <vipin.anand@intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
---
 drivers/gpu/drm/i915/gem/i915_gem_context.c       | 18 +++++++
 drivers/gpu/drm/i915/gem/i915_gem_context.h       |  2 +
 drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 32 ++++++++++++
 drivers/gpu/drm/i915/gt/intel_lrc.c               | 42 ++++++++++++++-
 drivers/gpu/drm/i915/i915_drv.h                   |  5 ++
 drivers/gpu/drm/i915/intel_device_info.c          | 62 ++++++++++++++++++++++-
 6 files changed, 157 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
index 8288fb9..ac94f92 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
@@ -713,10 +713,28 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
 
 	trace_i915_context_create(ctx);
 	atomic_set(&ctx->req_cnt, 0);
+	ctx->slice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.slice_mask);
+	ctx->subslice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.subslice_mask[0]);
+	ctx->eu_cnt = RUNTIME_INFO(i915)->sseu.eu_per_subslice;
 
 	return ctx;
 }
 
+void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
+				    enum gem_load_type type)
+{
+	struct drm_i915_private *dev_priv = ctx->i915;
+
+	if (GEM_WARN_ON(type > LOAD_TYPE_LAST))
+		return;
+
+	/* Call opt_config to get correct configuration for eu,slice,subslice */
+	ctx->slice_cnt = dev_priv->opt_config[type].slice;
+	ctx->subslice_cnt = dev_priv->opt_config[type].subslice;
+	ctx->eu_cnt = dev_priv->opt_config[type].eu;
+	ctx->pending_load_type = type;
+}
+
 static void
 destroy_kernel_context(struct i915_gem_context **ctxp)
 {
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
index 18e50a7..8677427 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
@@ -177,6 +177,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
 				    struct drm_file *file_priv);
 int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
 				       struct drm_file *file);
+void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
+				enum gem_load_type type);
 
 struct i915_gem_context *
 i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio);
diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
index 3931c06..6847d49 100644
--- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
+++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
@@ -40,6 +40,19 @@ struct i915_gem_engines_iter {
 	const struct i915_gem_engines *engines;
 };
 
+enum gem_load_type {
+	LOAD_TYPE_LOW,
+	LOAD_TYPE_MEDIUM,
+	LOAD_TYPE_HIGH,
+	LOAD_TYPE_LAST
+};
+
+struct i915_sseu_optimum_config {
+	u8 slice;
+	u8 subslice;
+	u8 eu;
+};
+
 /**
  * struct i915_gem_context - client state
  *
@@ -173,6 +186,25 @@ struct i915_gem_context {
 	 */
 	atomic_t req_cnt;
 
+	/** slice_cnt: used to set the # of slices to be enabled. */
+	u8 slice_cnt;
+
+	/** subslice_cnt: used to set the # of subslices to be enabled. */
+	u8 subslice_cnt;
+
+	/** eu_cnt: used to set the # of eu to be enabled. */
+	u8 eu_cnt;
+
+	/** load_type: The designated load_type (high/medium/low) for a given
+	 * number of pending commands in the command queue.
+	 */
+	enum gem_load_type load_type;
+
+	/** pending_load_type: The earlier load type that the GPU was configured
+	 * for (high/medium/low).
+	 */
+	enum gem_load_type pending_load_type;
+
 	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
 	 *  Guarded by struct_mutex
 	 */
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 511d5a1..c3f279e 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -2436,6 +2436,36 @@ static void execlists_context_unpin(struct intel_context *ce)
 	intel_ring_reset(ce->ring, ce->ring->tail);
 }
 
+static u32
+get_context_rpcs_config(struct i915_gem_context *ctx)
+{
+	u32 rpcs = 0;
+	struct drm_i915_private *dev_priv = ctx->i915;
+
+	if (INTEL_GEN(dev_priv) < 8)
+		return 0;
+
+	if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) {
+		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
+		rpcs |= ctx->slice_cnt << GEN8_RPCS_S_CNT_SHIFT;
+		rpcs |= GEN8_RPCS_ENABLE;
+	}
+
+	if (RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg) {
+		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
+		rpcs |= ctx->subslice_cnt << GEN8_RPCS_SS_CNT_SHIFT;
+		rpcs |= GEN8_RPCS_ENABLE;
+	}
+
+	if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) {
+		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MIN_SHIFT;
+		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MAX_SHIFT;
+		rpcs |= GEN8_RPCS_ENABLE;
+	}
+
+	return rpcs;
+}
+
 static void
 __execlists_update_reg_state(const struct intel_context *ce,
 			     const struct intel_engine_cs *engine)
@@ -2452,8 +2482,13 @@ __execlists_update_reg_state(const struct intel_context *ce,
 
 	/* RPCS */
 	if (engine->class == RENDER_CLASS) {
-		regs[CTX_R_PWR_CLK_STATE] =
-			intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+		if (engine->i915->predictive_load_enable) {
+			regs[CTX_R_PWR_CLK_STATE] =
+				get_context_rpcs_config(ce->gem_context);
+		} else {
+			regs[CTX_R_PWR_CLK_STATE] =
+				intel_sseu_make_rpcs(engine->i915, &ce->sseu);
+		}
 
 		i915_oa_init_reg_state(ce, engine);
 	}
@@ -2485,6 +2520,9 @@ __execlists_context_pin(struct intel_context *ce,
 	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
 	__execlists_update_reg_state(ce, engine);
 
+	if (ce->gem_context->load_type != ce->gem_context->pending_load_type)
+		ce->gem_context->load_type = ce->gem_context->pending_load_type;
+
 	return 0;
 
 unpin_active:
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdae5a9..3064ddf 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -999,6 +999,11 @@ struct drm_i915_private {
 	/* protects panel power sequencer state */
 	struct mutex pps_mutex;
 
+	/* optimal slice/subslice/EU configration state */
+	struct i915_sseu_optimum_config *opt_config;
+
+	int predictive_load_enable;
+
 	unsigned int fsb_freq, mem_freq, is_ddr3;
 	unsigned int skl_preferred_vco_freq;
 	unsigned int max_cdclk_freq;
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index a5b5713..b3c2f92 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -873,6 +873,34 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 }
 
+/* static table of slice/subslice/EU for Cherryview */
+static const struct i915_sseu_optimum_config chv_config[LOAD_TYPE_LAST] = {
+	{1, 1, 4},	/* Low */
+	{1, 1, 6},	/* Medium */
+	{1, 2, 6}	/* High */
+};
+
+/* static table of slice/subslice/EU for GLK GT1 */
+static const struct i915_sseu_optimum_config glk_gt1_config[LOAD_TYPE_LAST] = {
+	{1, 2, 2},	/* Low */
+	{1, 2, 3},	/* Medium */
+	{1, 2, 6}	/* High */
+};
+
+/* static table of slice/subslice/EU for KBL GT2 */
+static const struct i915_sseu_optimum_config kbl_gt2_config[LOAD_TYPE_LAST] = {
+	{1, 3, 2},	/* Low */
+	{1, 3, 4},	/* Medium */
+	{1, 3, 8}	/* High */
+};
+
+/* static table of slice/subslice/EU for KBL GT3 */
+static const struct i915_sseu_optimum_config kbl_gt3_config[LOAD_TYPE_LAST] = {
+	{2, 3, 4},	/* Low */
+	{2, 3, 6},	/* Medium */
+	{2, 3, 8}	/* High */
+};
+
 /**
  * intel_device_info_runtime_init - initialize runtime info
  * @dev_priv: the i915 device
@@ -894,6 +922,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	struct intel_device_info *info = mkwrite_device_info(dev_priv);
 	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 	enum pipe pipe;
+	struct i915_sseu_optimum_config *opt_config = NULL;
 
 	if (INTEL_GEN(dev_priv) >= 10) {
 		for_each_pipe(dev_priv, pipe)
@@ -999,12 +1028,38 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 	/* Initialize slice/subslice/EU info */
 	if (IS_HASWELL(dev_priv))
 		haswell_sseu_info_init(dev_priv);
-	else if (IS_CHERRYVIEW(dev_priv))
+	else if (IS_CHERRYVIEW(dev_priv)) {
 		cherryview_sseu_info_init(dev_priv);
+		opt_config = (struct i915_sseu_optimum_config *)chv_config;
+		BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
+	}
 	else if (IS_BROADWELL(dev_priv))
 		broadwell_sseu_info_init(dev_priv);
-	else if (IS_GEN(dev_priv, 9))
+	else if (IS_GEN(dev_priv, 9)) {
 		gen9_sseu_info_init(dev_priv);
+
+		switch (info->gt) {
+		default: /* fall through */
+		case 1:
+			opt_config = (struct i915_sseu_optimum_config *)
+						glk_gt1_config;
+			BUILD_BUG_ON(ARRAY_SIZE(glk_gt1_config)
+						!= LOAD_TYPE_LAST);
+		break;
+		case 2:
+			opt_config = (struct i915_sseu_optimum_config *)
+						kbl_gt2_config;
+			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config)
+						!= LOAD_TYPE_LAST);
+		break;
+		case 3:
+			opt_config = (struct i915_sseu_optimum_config *)
+						kbl_gt3_config;
+			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config)
+						!= LOAD_TYPE_LAST);
+		break;
+		}
+	}
 	else if (IS_GEN(dev_priv, 10))
 		gen10_sseu_info_init(dev_priv);
 	else if (IS_GEN(dev_priv, 11))
@@ -1017,6 +1072,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 		info->ppgtt_type = INTEL_PPGTT_NONE;
 	}
 
+	if (opt_config)
+		dev_priv->opt_config = opt_config;
+
 	/* Initialize command stream timestamp frequency */
 	runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
 }
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26  4:51   ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

High resolution timer is used for predictive governor to control
eu/slice/subslice based on workloads.

param is provided to enable/disable/update timer configuration

V2:
 * Fix code style.
 * Move predictive_load_timer into a drm_i915_private
   structure.
 * Make generic function to set optimum config. (Tvrtko Ursulin)

V3:
 * Rebase.
 * Fix race condition for predictive load set.
 * Add slack to start hrtimer for more power efficient. (Tvrtko Ursulin)

V4:
 * Fix data type and initialization of mutex to protect predictive load
   state.
 * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
 * Move debugfs to kernel parameter.

V5:
 * Rebase.
 * Remove mutex for pred_timer

V6:
 * Rebase.
 * Fix warnings.

Cc: Vipin Anand <vipin.anand@intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
---
 drivers/gpu/drm/i915/Makefile       |   1 +
 drivers/gpu/drm/i915/gt/intel_deu.c | 104 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
 drivers/gpu/drm/i915/i915_drv.h     |   4 ++
 drivers/gpu/drm/i915/i915_gem.c     |   4 ++
 drivers/gpu/drm/i915/i915_params.c  |   4 ++
 drivers/gpu/drm/i915/i915_params.h  |   1 +
 7 files changed, 149 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e0fd10c..c1a98f3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ obj-y += gt/
 gt-y += \
 	gt/intel_breadcrumbs.o \
 	gt/intel_context.o \
+	gt/intel_deu.o \
 	gt/intel_engine_cs.o \
 	gt/intel_engine_heartbeat.o \
 	gt/intel_engine_pm.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c b/drivers/gpu/drm/i915/gt/intel_deu.c
new file mode 100644
index 0000000..6c5b01c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_deu.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Ankit Navik <ankit.p.navik@intel.com>
+ */
+
+/**
+ * DOC: Dynamic EU Control (DEU)
+ *
+ * DEU tries to re-configure EU allocation during runtime by predictive load
+ * calculation of command queue to gain power saving.
+ * It is transparent to user space and completely handled in the kernel.
+ */
+
+#include "intel_deu.h"
+#include "i915_drv.h"
+#include "gem/i915_gem_context.h"
+
+/*
+ * Anything above threshold is considered as HIGH load, less is considered
+ * as LOW load and equal is considered as MEDIUM load.
+ *
+ * The threshold value of three active requests pending.
+ */
+#define PENDING_THRESHOLD_MEDIUM 3
+
+#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
+
+enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer)
+{
+	struct drm_i915_private *dev_priv =
+			container_of(hrtimer, typeof(*dev_priv), pred_timer);
+	struct i915_gem_context *ctx;
+	enum gem_load_type load_type;
+	unsigned int req_pending;
+
+	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
+		req_pending = atomic_read(&ctx->req_cnt);
+
+		/*
+		 * Transitioning to low state whenever pending request is zero
+		 * would cause vacillation between low and high state.
+		 */
+		if (req_pending == 0)
+			continue;
+
+		if (req_pending > PENDING_THRESHOLD_MEDIUM)
+			load_type = LOAD_TYPE_HIGH;
+		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
+			load_type = LOAD_TYPE_MEDIUM;
+		else
+			load_type = LOAD_TYPE_LOW;
+
+		i915_gem_context_set_load_type(ctx, load_type);
+	}
+
+	hrtimer_forward_now(hrtimer,
+			    ms_to_ktime(dev_priv->predictive_load_enable));
+
+	return HRTIMER_RESTART;
+}
+
+/**
+ * intel_deu_init - Initialize dynamic EU
+ * @dev_priv: i915 device instance
+ *
+ * This function is called at driver load
+ */
+void intel_deu_init(struct drm_i915_private *dev_priv)
+{
+	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
+	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	dev_priv->pred_timer.function = predictive_load_cb;
+
+	if (dev_priv->predictive_load_enable) {
+		if (!hrtimer_active(&dev_priv->pred_timer))
+			hrtimer_start_range_ns(&dev_priv->pred_timer,
+			ms_to_ktime(dev_priv->predictive_load_enable),
+			SLACK_TIMER_NSEC,
+			HRTIMER_MODE_REL_PINNED);
+	} else {
+		hrtimer_cancel(&dev_priv->pred_timer);
+	}
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h b/drivers/gpu/drm/i915/gt/intel_deu.h
new file mode 100644
index 0000000..3b4b16f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_deu.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __INTEL_DEU_H__
+#define __INTEL_DEU_H__
+
+struct drm_i915_private;
+
+void intel_deu_init(struct drm_i915_private *dev_priv);
+
+#endif /* __INTEL_DEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3064ddf..5553537 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1002,6 +1002,8 @@ struct drm_i915_private {
 	/* optimal slice/subslice/EU configration state */
 	struct i915_sseu_optimum_config *opt_config;
 
+	/* protects predictive load state */
+	struct hrtimer pred_timer;
 	int predictive_load_enable;
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
@@ -1768,6 +1770,8 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
 #endif
 extern const struct dev_pm_ops i915_pm_ops;
 
+extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);
+
 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 void i915_driver_remove(struct drm_i915_private *i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61395b0..ee711ce 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -45,6 +45,7 @@
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_ioctls.h"
 #include "gem/i915_gem_pm.h"
+#include "gt/intel_deu.h"
 #include "gt/intel_context.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gt.h"
@@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
 	i915_gem_init__mm(dev_priv);
 
 	spin_lock_init(&dev_priv->fb_tracking.lock);
+
+	/* Dynamic EU timer initialization for predictive load */
+	intel_deu_init(dev_priv);
 }
 
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1dd1f36..a5a3a6e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
 
 i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
 
+i915_param_named_unsafe(deu_enable, int, 0600,
+	"Enable dynamic EU control for power savings "
+	"(0=disable deu predictive timer [default], 150=optimal deu predictive timer)");
+
 i915_param_named(fastboot, int, 0600,
 	"Try to skip unnecessary mode sets at boot time "
 	"(0=disabled, 1=enabled) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 31b88f2..cf0903b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,6 +54,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
+	param(int, deu_enable, 0) \
 	param(int, enable_guc, 0) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26  4:51   ` Ankit Navik
  0 siblings, 0 replies; 37+ messages in thread
From: Ankit Navik @ 2019-11-26  4:51 UTC (permalink / raw)
  To: intel-gfx; +Cc: ankit.p.navik, vipin.anand

High resolution timer is used for predictive governor to control
eu/slice/subslice based on workloads.

param is provided to enable/disable/update timer configuration

V2:
 * Fix code style.
 * Move predictive_load_timer into a drm_i915_private
   structure.
 * Make generic function to set optimum config. (Tvrtko Ursulin)

V3:
 * Rebase.
 * Fix race condition for predictive load set.
 * Add slack to start hrtimer for more power efficient. (Tvrtko Ursulin)

V4:
 * Fix data type and initialization of mutex to protect predictive load
   state.
 * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
 * Move debugfs to kernel parameter.

V5:
 * Rebase.
 * Remove mutex for pred_timer

V6:
 * Rebase.
 * Fix warnings.

Cc: Vipin Anand <vipin.anand@intel.com>
Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
---
 drivers/gpu/drm/i915/Makefile       |   1 +
 drivers/gpu/drm/i915/gt/intel_deu.c | 104 ++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
 drivers/gpu/drm/i915/i915_drv.h     |   4 ++
 drivers/gpu/drm/i915/i915_gem.c     |   4 ++
 drivers/gpu/drm/i915/i915_params.c  |   4 ++
 drivers/gpu/drm/i915/i915_params.h  |   1 +
 7 files changed, 149 insertions(+)
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
 create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e0fd10c..c1a98f3 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -77,6 +77,7 @@ obj-y += gt/
 gt-y += \
 	gt/intel_breadcrumbs.o \
 	gt/intel_context.o \
+	gt/intel_deu.o \
 	gt/intel_engine_cs.o \
 	gt/intel_engine_heartbeat.o \
 	gt/intel_engine_pm.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c b/drivers/gpu/drm/i915/gt/intel_deu.c
new file mode 100644
index 0000000..6c5b01c
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_deu.c
@@ -0,0 +1,104 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Ankit Navik <ankit.p.navik@intel.com>
+ */
+
+/**
+ * DOC: Dynamic EU Control (DEU)
+ *
+ * DEU tries to re-configure EU allocation during runtime by predictive load
+ * calculation of command queue to gain power saving.
+ * It is transparent to user space and completely handled in the kernel.
+ */
+
+#include "intel_deu.h"
+#include "i915_drv.h"
+#include "gem/i915_gem_context.h"
+
+/*
+ * Anything above threshold is considered as HIGH load, less is considered
+ * as LOW load and equal is considered as MEDIUM load.
+ *
+ * The threshold value of three active requests pending.
+ */
+#define PENDING_THRESHOLD_MEDIUM 3
+
+#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
+
+enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer)
+{
+	struct drm_i915_private *dev_priv =
+			container_of(hrtimer, typeof(*dev_priv), pred_timer);
+	struct i915_gem_context *ctx;
+	enum gem_load_type load_type;
+	unsigned int req_pending;
+
+	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
+		req_pending = atomic_read(&ctx->req_cnt);
+
+		/*
+		 * Transitioning to low state whenever pending request is zero
+		 * would cause vacillation between low and high state.
+		 */
+		if (req_pending == 0)
+			continue;
+
+		if (req_pending > PENDING_THRESHOLD_MEDIUM)
+			load_type = LOAD_TYPE_HIGH;
+		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
+			load_type = LOAD_TYPE_MEDIUM;
+		else
+			load_type = LOAD_TYPE_LOW;
+
+		i915_gem_context_set_load_type(ctx, load_type);
+	}
+
+	hrtimer_forward_now(hrtimer,
+			    ms_to_ktime(dev_priv->predictive_load_enable));
+
+	return HRTIMER_RESTART;
+}
+
+/**
+ * intel_deu_init - Initialize dynamic EU
+ * @dev_priv: i915 device instance
+ *
+ * This function is called at driver load
+ */
+void intel_deu_init(struct drm_i915_private *dev_priv)
+{
+	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
+	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
+	dev_priv->pred_timer.function = predictive_load_cb;
+
+	if (dev_priv->predictive_load_enable) {
+		if (!hrtimer_active(&dev_priv->pred_timer))
+			hrtimer_start_range_ns(&dev_priv->pred_timer,
+			ms_to_ktime(dev_priv->predictive_load_enable),
+			SLACK_TIMER_NSEC,
+			HRTIMER_MODE_REL_PINNED);
+	} else {
+		hrtimer_cancel(&dev_priv->pred_timer);
+	}
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h b/drivers/gpu/drm/i915/gt/intel_deu.h
new file mode 100644
index 0000000..3b4b16f
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_deu.h
@@ -0,0 +1,31 @@
+/*
+ * Copyright © 2019 Intel Corporation
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ */
+
+#ifndef __INTEL_DEU_H__
+#define __INTEL_DEU_H__
+
+struct drm_i915_private;
+
+void intel_deu_init(struct drm_i915_private *dev_priv);
+
+#endif /* __INTEL_DEU_H__ */
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 3064ddf..5553537 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1002,6 +1002,8 @@ struct drm_i915_private {
 	/* optimal slice/subslice/EU configration state */
 	struct i915_sseu_optimum_config *opt_config;
 
+	/* protects predictive load state */
+	struct hrtimer pred_timer;
 	int predictive_load_enable;
 
 	unsigned int fsb_freq, mem_freq, is_ddr3;
@@ -1768,6 +1770,8 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
 #endif
 extern const struct dev_pm_ops i915_pm_ops;
 
+extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);
+
 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
 void i915_driver_remove(struct drm_i915_private *i915);
 
diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 61395b0..ee711ce 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -45,6 +45,7 @@
 #include "gem/i915_gem_context.h"
 #include "gem/i915_gem_ioctls.h"
 #include "gem/i915_gem_pm.h"
+#include "gt/intel_deu.h"
 #include "gt/intel_context.h"
 #include "gt/intel_engine_user.h"
 #include "gt/intel_gt.h"
@@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
 	i915_gem_init__mm(dev_priv);
 
 	spin_lock_init(&dev_priv->fb_tracking.lock);
+
+	/* Dynamic EU timer initialization for predictive load */
+	intel_deu_init(dev_priv);
 }
 
 void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
index 1dd1f36..a5a3a6e 100644
--- a/drivers/gpu/drm/i915/i915_params.c
+++ b/drivers/gpu/drm/i915/i915_params.c
@@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
 
 i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
 
+i915_param_named_unsafe(deu_enable, int, 0600,
+	"Enable dynamic EU control for power savings "
+	"(0=disable deu predictive timer [default], 150=optimal deu predictive timer)");
+
 i915_param_named(fastboot, int, 0600,
 	"Try to skip unnecessary mode sets at boot time "
 	"(0=disabled, 1=enabled) "
diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
index 31b88f2..cf0903b 100644
--- a/drivers/gpu/drm/i915/i915_params.h
+++ b/drivers/gpu/drm/i915/i915_params.h
@@ -54,6 +54,7 @@ struct drm_printer;
 	param(int, disable_power_well, -1) \
 	param(int, enable_ips, 1) \
 	param(int, invert_brightness, 0) \
+	param(int, deu_enable, 0) \
 	param(int, enable_guc, 0) \
 	param(int, guc_log_level, -1) \
 	param(char *, guc_firmware_path, NULL) \
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 37+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
@ 2019-11-26  5:01   ` Patchwork
  0 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2019-11-26  5:01 UTC (permalink / raw)
  To: Ankit Navik; +Cc: intel-gfx

== Series Details ==

Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
URL   : https://patchwork.freedesktop.org/series/69980/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
529f5590d903 drm/i915: Get active pending request for given context
ccb5ba29f346 drm/i915: set optimum eu/slice/sub-slice configuration based on load type
-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.h:181:
+void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
+				enum gem_load_type type);

total: 0 errors, 0 warnings, 1 checks, 241 lines checked
6de2093b5fba drm/i915: Predictive governor to control slice/subslice/eu
-:52: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#52: 
new file mode 100644

-:57: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#57: FILE: drivers/gpu/drm/i915/gt/intel_deu.c:1:
+/*

-:154: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#154: FILE: drivers/gpu/drm/i915/gt/intel_deu.c:98:
+			hrtimer_start_range_ns(&dev_priv->pred_timer,
+			ms_to_ktime(dev_priv->predictive_load_enable),

-:167: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#167: FILE: drivers/gpu/drm/i915/gt/intel_deu.h:1:
+/*

-:215: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#215: FILE: drivers/gpu/drm/i915/i915_drv.h:1773:
+extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);

-:251: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#251: FILE: drivers/gpu/drm/i915/i915_params.c:105:
+i915_param_named_unsafe(deu_enable, int, 0600,
+	"Enable dynamic EU control for power savings "

total: 0 errors, 3 warnings, 3 checks, 191 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
@ 2019-11-26  5:01   ` Patchwork
  0 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2019-11-26  5:01 UTC (permalink / raw)
  To: Ankit Navik; +Cc: intel-gfx

== Series Details ==

Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
URL   : https://patchwork.freedesktop.org/series/69980/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
529f5590d903 drm/i915: Get active pending request for given context
ccb5ba29f346 drm/i915: set optimum eu/slice/sub-slice configuration based on load type
-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/gem/i915_gem_context.h:181:
+void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
+				enum gem_load_type type);

total: 0 errors, 0 warnings, 1 checks, 241 lines checked
6de2093b5fba drm/i915: Predictive governor to control slice/subslice/eu
-:52: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#52: 
new file mode 100644

-:57: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#57: FILE: drivers/gpu/drm/i915/gt/intel_deu.c:1:
+/*

-:154: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#154: FILE: drivers/gpu/drm/i915/gt/intel_deu.c:98:
+			hrtimer_start_range_ns(&dev_priv->pred_timer,
+			ms_to_ktime(dev_priv->predictive_load_enable),

-:167: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#167: FILE: drivers/gpu/drm/i915/gt/intel_deu.h:1:
+/*

-:215: CHECK:AVOID_EXTERNS: extern prototypes should be avoided in .h files
#215: FILE: drivers/gpu/drm/i915/i915_drv.h:1773:
+extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);

-:251: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#251: FILE: drivers/gpu/drm/i915/i915_params.c:105:
+i915_param_named_unsafe(deu_enable, int, 0600,
+	"Enable dynamic EU control for power savings "

total: 0 errors, 3 warnings, 3 checks, 191 lines checked

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* ✓ Fi.CI.BAT: success for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
@ 2019-11-26  5:24   ` Patchwork
  0 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2019-11-26  5:24 UTC (permalink / raw)
  To: Ankit Navik; +Cc: intel-gfx

== Series Details ==

Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
URL   : https://patchwork.freedesktop.org/series/69980/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15433
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/index.html

Known issues
------------

  Here are the changes found in Patchwork_15433 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-icl-dsi:         [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108840])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][3] ([fdo#108511]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [FAIL][5] ([fdo#109635 ] / [fdo#110387]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#109483]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [FAIL][9] ([fdo#112223]) -> [SKIP][10] ([fdo#109271])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][12] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][14] ([fdo#103558] / [fdo#105602]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#112223]: https://bugs.freedesktop.org/show_bug.cgi?id=112223
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7420 -> Patchwork_15433

  CI-20190529: 20190529
  CI_DRM_7420: a876581f0065620f1519cfb9852fe5bd364db7c8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5305: eafaa79dfb71f7251126f1c000e0cbe94425c95a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15433: 6de2093b5fbadcb7b3c57138bb2052007f32c293 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6de2093b5fba drm/i915: Predictive governor to control slice/subslice/eu
ccb5ba29f346 drm/i915: set optimum eu/slice/sub-slice configuration based on load type
529f5590d903 drm/i915: Get active pending request for given context

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
@ 2019-11-26  5:24   ` Patchwork
  0 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2019-11-26  5:24 UTC (permalink / raw)
  To: Ankit Navik; +Cc: intel-gfx

== Series Details ==

Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
URL   : https://patchwork.freedesktop.org/series/69980/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_7420 -> Patchwork_15433
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/index.html

Known issues
------------

  Here are the changes found in Patchwork_15433 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_pm_rpm@basic-pci-d3-state:
    - fi-icl-dsi:         [PASS][1] -> [INCOMPLETE][2] ([fdo#107713] / [fdo#108840])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-icl-dsi/igt@i915_pm_rpm@basic-pci-d3-state.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][3] ([fdo#108511]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-icl-u2:          [FAIL][5] ([fdo#109635 ] / [fdo#110387]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-icl-u2/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#109483]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [FAIL][9] ([fdo#112223]) -> [SKIP][10] ([fdo#109271])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  * igt@kms_flip@basic-flip-vs-modeset:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][12] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +8 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][14] ([fdo#103558] / [fdo#105602]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/fi-kbl-x1275/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
  [fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
  [fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
  [fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
  [fdo#108511]: https://bugs.freedesktop.org/show_bug.cgi?id=108511
  [fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109483]: https://bugs.freedesktop.org/show_bug.cgi?id=109483
  [fdo#109635 ]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 
  [fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
  [fdo#110387]: https://bugs.freedesktop.org/show_bug.cgi?id=110387
  [fdo#112223]: https://bugs.freedesktop.org/show_bug.cgi?id=112223
  [fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298


Participating hosts (51 -> 45)
------------------------------

  Missing    (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7420 -> Patchwork_15433

  CI-20190529: 20190529
  CI_DRM_7420: a876581f0065620f1519cfb9852fe5bd364db7c8 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5305: eafaa79dfb71f7251126f1c000e0cbe94425c95a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_15433: 6de2093b5fbadcb7b3c57138bb2052007f32c293 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6de2093b5fba drm/i915: Predictive governor to control slice/subslice/eu
ccb5ba29f346 drm/i915: set optimum eu/slice/sub-slice configuration based on load type
529f5590d903 drm/i915: Get active pending request for given context

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 1/3] drm/i915: Get active pending request for given context
@ 2019-11-26 10:26     ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 10:26 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> This patch gives us the active pending request count which is yet
> to be submitted to the GPU.
> 
> V2:
>   * Change 64-bit to atomic for request count. (Tvrtko Ursulin)
> 
> V3:
>   * Remove mutex for request count.
>   * Rebase.
>   * Fixes hitting underflow for predictive request. (Tvrtko Ursulin)
> 
> V4:
>   * Rebase.
> 
> V5:
>   * Rebase.
> 
> V6
>   * Rebase.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_context.c       | 1 +
>   drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 5 +++++
>   drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c    | 2 ++
>   drivers/gpu/drm/i915/gt/intel_lrc.c               | 3 +++
>   4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c94ac83..8288fb9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -712,6 +712,7 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
>   	}
>   
>   	trace_i915_context_create(ctx);
> +	atomic_set(&ctx->req_cnt, 0);
>   
>   	return ctx;
>   }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index c060bc4..3931c06 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -168,6 +168,11 @@ struct i915_gem_context {
>   	 */
>   	struct radix_tree_root handles_vma;
>   
> +	/** req_cnt: tracks the pending commands, based on which we decide to
> +	 * go for low/medium/high load configuration of the GPU.
> +	 */
> +	atomic_t req_cnt;
> +
>   	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
>   	 *  Guarded by struct_mutex
>   	 */
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 7a87e82..83f4392 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2700,6 +2700,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
>   	if (eb.batch->private)
>   		intel_engine_pool_mark_active(eb.batch->private, eb.request);
>   
> +	atomic_inc(&eb.gem_context->req_cnt);
> +
>   	trace_i915_request_queue(eb.request, eb.batch_flags);
>   	err = eb_submit(&eb);
>   err_request:
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 4cd0d46..511d5a1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1956,6 +1956,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   
>   				submit = true;
>   				last = rq;
> +
> +				if (atomic_read(&rq->gem_context->req_cnt) > 0)

If you need this check (underflow is real) we need to understand when it 
can happen and solve it properly. Until then the code is telling me that 
in some unexplained circumstances feature will not work for this context.

Perhaps put a GEM_BUG_ON there and send it to CI so we see if it's real 
or not. :)

On the overall it is still an interesting question what request states 
should be looked at by the heuristics. Submitted or submitted + 
runnable. Long time ago I had patches which implement these counters 
correctly so that needs to be dug out and rebased on drm-tip. Then you 
can read and add the counts you want.

Regards,

Tvrtko

> +					atomic_dec(&rq->gem_context->req_cnt);
>   			}
>   		}
>   
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 1/3] drm/i915: Get active pending request for given context
@ 2019-11-26 10:26     ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 10:26 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> This patch gives us the active pending request count which is yet
> to be submitted to the GPU.
> 
> V2:
>   * Change 64-bit to atomic for request count. (Tvrtko Ursulin)
> 
> V3:
>   * Remove mutex for request count.
>   * Rebase.
>   * Fixes hitting underflow for predictive request. (Tvrtko Ursulin)
> 
> V4:
>   * Rebase.
> 
> V5:
>   * Rebase.
> 
> V6
>   * Rebase.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_context.c       | 1 +
>   drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 5 +++++
>   drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c    | 2 ++
>   drivers/gpu/drm/i915/gt/intel_lrc.c               | 3 +++
>   4 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index c94ac83..8288fb9 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -712,6 +712,7 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
>   	}
>   
>   	trace_i915_context_create(ctx);
> +	atomic_set(&ctx->req_cnt, 0);
>   
>   	return ctx;
>   }
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index c060bc4..3931c06 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -168,6 +168,11 @@ struct i915_gem_context {
>   	 */
>   	struct radix_tree_root handles_vma;
>   
> +	/** req_cnt: tracks the pending commands, based on which we decide to
> +	 * go for low/medium/high load configuration of the GPU.
> +	 */
> +	atomic_t req_cnt;
> +
>   	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
>   	 *  Guarded by struct_mutex
>   	 */
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> index 7a87e82..83f4392 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_execbuffer.c
> @@ -2700,6 +2700,8 @@ i915_gem_do_execbuffer(struct drm_device *dev,
>   	if (eb.batch->private)
>   		intel_engine_pool_mark_active(eb.batch->private, eb.request);
>   
> +	atomic_inc(&eb.gem_context->req_cnt);
> +
>   	trace_i915_request_queue(eb.request, eb.batch_flags);
>   	err = eb_submit(&eb);
>   err_request:
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 4cd0d46..511d5a1 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1956,6 +1956,9 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>   
>   				submit = true;
>   				last = rq;
> +
> +				if (atomic_read(&rq->gem_context->req_cnt) > 0)

If you need this check (underflow is real) we need to understand when it 
can happen and solve it properly. Until then the code is telling me that 
in some unexplained circumstances feature will not work for this context.

Perhaps put a GEM_BUG_ON there and send it to CI so we see if it's real 
or not. :)

On the overall it is still an interesting question what request states 
should be looked at by the heuristics. Submitted or submitted + 
runnable. Long time ago I had patches which implement these counters 
correctly so that needs to be dug out and rebased on drm-tip. Then you 
can read and add the counts you want.

Regards,

Tvrtko

> +					atomic_dec(&rq->gem_context->req_cnt);
>   			}
>   		}
>   
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
@ 2019-11-26 10:41     ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 10:41 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> This patch will select optimum eu/slice/sub-slice configuration based on
> type of load (low, medium, high) as input.
> Based on our readings and experiments we have predefined set of optimum
> configuration for each platform(CHT, KBL).
> i915_gem_context_set_load_type will select optimum configuration from
> pre-defined optimum configuration table(opt_config).
> 
> It also introduce flag update_render_config which can set by any governor.
> 
> v2:
>   * Move static optimum_config to device init time.
>   * Rename function to appropriate name, fix data types and patch ordering.
>   * Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)
> 
> v3:
>   * Add safe guard check in i915_gem_context_set_load_type.
>   * Rename struct from optimum_config to i915_sseu_optimum_config to
>     avoid namespace clashes.
>   * Reduces memcpy for space efficient.
>   * Rebase.
>   * Improved commit message. (Tvrtko Ursulin)
> 
> v4:
>   * Move optimum config table to file scope. (Tvrtko Ursulin)
> 
> v5:
>   * Adds optimal table of slice/sub-slice/EU for Gen 9 GT1.
>   * Rebase.
> 
> v6:
>   * Rebase.
>   * Fix warnings.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_context.c       | 18 +++++++
>   drivers/gpu/drm/i915/gem/i915_gem_context.h       |  2 +
>   drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 32 ++++++++++++
>   drivers/gpu/drm/i915/gt/intel_lrc.c               | 42 ++++++++++++++-
>   drivers/gpu/drm/i915/i915_drv.h                   |  5 ++
>   drivers/gpu/drm/i915/intel_device_info.c          | 62 ++++++++++++++++++++++-
>   6 files changed, 157 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 8288fb9..ac94f92 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -713,10 +713,28 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
>   
>   	trace_i915_context_create(ctx);
>   	atomic_set(&ctx->req_cnt, 0);
> +	ctx->slice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.slice_mask);
> +	ctx->subslice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.subslice_mask[0]);
> +	ctx->eu_cnt = RUNTIME_INFO(i915)->sseu.eu_per_subslice;

I wanted to say that you need to wrap this into a named structure from 
which it will be clear these members are about Dynamic EU but let me 
finish the read, there might be a better way.

>   
>   	return ctx;
>   }
>   
> +void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
> +				    enum gem_load_type type)
> +{
> +	struct drm_i915_private *dev_priv = ctx->i915;
> +
> +	if (GEM_WARN_ON(type > LOAD_TYPE_LAST))
> +		return;

 >= I think, or bad things can happen.

> +
> +	/* Call opt_config to get correct configuration for eu,slice,subslice */
> +	ctx->slice_cnt = dev_priv->opt_config[type].slice;
> +	ctx->subslice_cnt = dev_priv->opt_config[type].subslice;
> +	ctx->eu_cnt = dev_priv->opt_config[type].eu;
> +	ctx->pending_load_type = type;
> +}
> +
>   static void
>   destroy_kernel_context(struct i915_gem_context **ctxp)
>   {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index 18e50a7..8677427 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -177,6 +177,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
>   				    struct drm_file *file_priv);
>   int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
>   				       struct drm_file *file);
> +void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
> +				enum gem_load_type type);
>   
>   struct i915_gem_context *
>   i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 3931c06..6847d49 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -40,6 +40,19 @@ struct i915_gem_engines_iter {
>   	const struct i915_gem_engines *engines;
>   };
>   
> +enum gem_load_type {
> +	LOAD_TYPE_LOW,
> +	LOAD_TYPE_MEDIUM,
> +	LOAD_TYPE_HIGH,
> +	LOAD_TYPE_LAST
> +};
> +
> +struct i915_sseu_optimum_config {
> +	u8 slice;
> +	u8 subslice;
> +	u8 eu;
> +};
> +
>   /**
>    * struct i915_gem_context - client state
>    *
> @@ -173,6 +186,25 @@ struct i915_gem_context {
>   	 */
>   	atomic_t req_cnt;
>   
> +	/** slice_cnt: used to set the # of slices to be enabled. */
> +	u8 slice_cnt;
> +
> +	/** subslice_cnt: used to set the # of subslices to be enabled. */
> +	u8 subslice_cnt;
> +
> +	/** eu_cnt: used to set the # of eu to be enabled. */
> +	u8 eu_cnt;
> +
> +	/** load_type: The designated load_type (high/medium/low) for a given
> +	 * number of pending commands in the command queue.
> +	 */
> +	enum gem_load_type load_type;
> +
> +	/** pending_load_type: The earlier load type that the GPU was configured
> +	 * for (high/medium/low).
> +	 */
> +	enum gem_load_type pending_load_type;
> +
>   	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
>   	 *  Guarded by struct_mutex
>   	 */
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 511d5a1..c3f279e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2436,6 +2436,36 @@ static void execlists_context_unpin(struct intel_context *ce)
>   	intel_ring_reset(ce->ring, ce->ring->tail);
>   }
>   
> +static u32
> +get_context_rpcs_config(struct i915_gem_context *ctx)
> +{
> +	u32 rpcs = 0;
> +	struct drm_i915_private *dev_priv = ctx->i915;
> +
> +	if (INTEL_GEN(dev_priv) < 8)
> +		return 0;
> +
> +	if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) {
> +		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> +		rpcs |= ctx->slice_cnt << GEN8_RPCS_S_CNT_SHIFT;
> +		rpcs |= GEN8_RPCS_ENABLE;
> +	}
> +
> +	if (RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg) {
> +		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> +		rpcs |= ctx->subslice_cnt << GEN8_RPCS_SS_CNT_SHIFT;
> +		rpcs |= GEN8_RPCS_ENABLE;
> +	}
> +
> +	if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) {
> +		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MIN_SHIFT;
> +		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MAX_SHIFT;
> +		rpcs |= GEN8_RPCS_ENABLE;
> +	}
> +
> +	return rpcs;
> +}
> +
>   static void
>   __execlists_update_reg_state(const struct intel_context *ce,
>   			     const struct intel_engine_cs *engine)
> @@ -2452,8 +2482,13 @@ __execlists_update_reg_state(const struct intel_context *ce,
>   
>   	/* RPCS */
>   	if (engine->class == RENDER_CLASS) {
> -		regs[CTX_R_PWR_CLK_STATE] =
> -			intel_sseu_make_rpcs(engine->i915, &ce->sseu);
> +		if (engine->i915->predictive_load_enable) {
> +			regs[CTX_R_PWR_CLK_STATE] =
> +				get_context_rpcs_config(ce->gem_context);

You cannot do it like this because you break OA and Gen11 user 
configured SSEU.

You need to have intel_sseu_make_rpcs below be the central decision 
maker on what is the correct SSEU config to apply.

Order of precedence should be:

1. OA compatible configuration
2. User requested configuration (via context set param
3. Dynamic SSEU suggested configuration
4. Defaults

Perhaps we need a marker on ce saying that user configuration has been 
set and then this code can remain as it were, just when you are applying 
Dynamic SSEU settings you do something like:

   if (!ce->user_sseu_set)
	  ce->sseu = make_dynamic_sseu(your optimal config);

I'll explain in the next patch what I am thinking in more detail.

Regards,

Tvrtko

> +		} else {
> +			regs[CTX_R_PWR_CLK_STATE] =
> +				intel_sseu_make_rpcs(engine->i915, &ce->sseu);
> +		}
>   
>   		i915_oa_init_reg_state(ce, engine);
>   	}
> @@ -2485,6 +2520,9 @@ __execlists_context_pin(struct intel_context *ce,
>   	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
>   	__execlists_update_reg_state(ce, engine);
>   
> +	if (ce->gem_context->load_type != ce->gem_context->pending_load_type)
> +		ce->gem_context->load_type = ce->gem_context->pending_load_type;
> +
>   	return 0;
>   
>   unpin_active:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fdae5a9..3064ddf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -999,6 +999,11 @@ struct drm_i915_private {
>   	/* protects panel power sequencer state */
>   	struct mutex pps_mutex;
>   
> +	/* optimal slice/subslice/EU configration state */
> +	struct i915_sseu_optimum_config *opt_config;
> +
> +	int predictive_load_enable;
> +
>   	unsigned int fsb_freq, mem_freq, is_ddr3;
>   	unsigned int skl_preferred_vco_freq;
>   	unsigned int max_cdclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a5b5713..b3c2f92 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -873,6 +873,34 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>   	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
>   }
>   
> +/* static table of slice/subslice/EU for Cherryview */
> +static const struct i915_sseu_optimum_config chv_config[LOAD_TYPE_LAST] = {
> +	{1, 1, 4},	/* Low */
> +	{1, 1, 6},	/* Medium */
> +	{1, 2, 6}	/* High */
> +};
> +
> +/* static table of slice/subslice/EU for GLK GT1 */
> +static const struct i915_sseu_optimum_config glk_gt1_config[LOAD_TYPE_LAST] = {
> +	{1, 2, 2},	/* Low */
> +	{1, 2, 3},	/* Medium */
> +	{1, 2, 6}	/* High */
> +};
> +
> +/* static table of slice/subslice/EU for KBL GT2 */
> +static const struct i915_sseu_optimum_config kbl_gt2_config[LOAD_TYPE_LAST] = {
> +	{1, 3, 2},	/* Low */
> +	{1, 3, 4},	/* Medium */
> +	{1, 3, 8}	/* High */
> +};
> +
> +/* static table of slice/subslice/EU for KBL GT3 */
> +static const struct i915_sseu_optimum_config kbl_gt3_config[LOAD_TYPE_LAST] = {
> +	{2, 3, 4},	/* Low */
> +	{2, 3, 6},	/* Medium */
> +	{2, 3, 8}	/* High */
> +};
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @dev_priv: the i915 device
> @@ -894,6 +922,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	struct intel_device_info *info = mkwrite_device_info(dev_priv);
>   	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>   	enum pipe pipe;
> +	struct i915_sseu_optimum_config *opt_config = NULL;
>   
>   	if (INTEL_GEN(dev_priv) >= 10) {
>   		for_each_pipe(dev_priv, pipe)
> @@ -999,12 +1028,38 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	/* Initialize slice/subslice/EU info */
>   	if (IS_HASWELL(dev_priv))
>   		haswell_sseu_info_init(dev_priv);
> -	else if (IS_CHERRYVIEW(dev_priv))
> +	else if (IS_CHERRYVIEW(dev_priv)) {
>   		cherryview_sseu_info_init(dev_priv);
> +		opt_config = (struct i915_sseu_optimum_config *)chv_config;
> +		BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
> +	}
>   	else if (IS_BROADWELL(dev_priv))
>   		broadwell_sseu_info_init(dev_priv);
> -	else if (IS_GEN(dev_priv, 9))
> +	else if (IS_GEN(dev_priv, 9)) {
>   		gen9_sseu_info_init(dev_priv);
> +
> +		switch (info->gt) {
> +		default: /* fall through */
> +		case 1:
> +			opt_config = (struct i915_sseu_optimum_config *)
> +						glk_gt1_config;
> +			BUILD_BUG_ON(ARRAY_SIZE(glk_gt1_config)
> +						!= LOAD_TYPE_LAST);
> +		break;
> +		case 2:
> +			opt_config = (struct i915_sseu_optimum_config *)
> +						kbl_gt2_config;
> +			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config)
> +						!= LOAD_TYPE_LAST);
> +		break;
> +		case 3:
> +			opt_config = (struct i915_sseu_optimum_config *)
> +						kbl_gt3_config;
> +			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config)
> +						!= LOAD_TYPE_LAST);
> +		break;
> +		}
> +	}
>   	else if (IS_GEN(dev_priv, 10))
>   		gen10_sseu_info_init(dev_priv);
>   	else if (IS_GEN(dev_priv, 11))
> @@ -1017,6 +1072,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		info->ppgtt_type = INTEL_PPGTT_NONE;
>   	}
>   
> +	if (opt_config)
> +		dev_priv->opt_config = opt_config;
> +
>   	/* Initialize command stream timestamp frequency */
>   	runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>   }
> 
_______________________________________________
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^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type
@ 2019-11-26 10:41     ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 10:41 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> This patch will select optimum eu/slice/sub-slice configuration based on
> type of load (low, medium, high) as input.
> Based on our readings and experiments we have predefined set of optimum
> configuration for each platform(CHT, KBL).
> i915_gem_context_set_load_type will select optimum configuration from
> pre-defined optimum configuration table(opt_config).
> 
> It also introduce flag update_render_config which can set by any governor.
> 
> v2:
>   * Move static optimum_config to device init time.
>   * Rename function to appropriate name, fix data types and patch ordering.
>   * Rename prev_load_type to pending_load_type. (Tvrtko Ursulin)
> 
> v3:
>   * Add safe guard check in i915_gem_context_set_load_type.
>   * Rename struct from optimum_config to i915_sseu_optimum_config to
>     avoid namespace clashes.
>   * Reduces memcpy for space efficient.
>   * Rebase.
>   * Improved commit message. (Tvrtko Ursulin)
> 
> v4:
>   * Move optimum config table to file scope. (Tvrtko Ursulin)
> 
> v5:
>   * Adds optimal table of slice/sub-slice/EU for Gen 9 GT1.
>   * Rebase.
> 
> v6:
>   * Rebase.
>   * Fix warnings.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/gem/i915_gem_context.c       | 18 +++++++
>   drivers/gpu/drm/i915/gem/i915_gem_context.h       |  2 +
>   drivers/gpu/drm/i915/gem/i915_gem_context_types.h | 32 ++++++++++++
>   drivers/gpu/drm/i915/gt/intel_lrc.c               | 42 ++++++++++++++-
>   drivers/gpu/drm/i915/i915_drv.h                   |  5 ++
>   drivers/gpu/drm/i915/intel_device_info.c          | 62 ++++++++++++++++++++++-
>   6 files changed, 157 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.c b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> index 8288fb9..ac94f92 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.c
> @@ -713,10 +713,28 @@ i915_gem_create_context(struct drm_i915_private *i915, unsigned int flags)
>   
>   	trace_i915_context_create(ctx);
>   	atomic_set(&ctx->req_cnt, 0);
> +	ctx->slice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.slice_mask);
> +	ctx->subslice_cnt = hweight8(RUNTIME_INFO(i915)->sseu.subslice_mask[0]);
> +	ctx->eu_cnt = RUNTIME_INFO(i915)->sseu.eu_per_subslice;

I wanted to say that you need to wrap this into a named structure from 
which it will be clear these members are about Dynamic EU but let me 
finish the read, there might be a better way.

>   
>   	return ctx;
>   }
>   
> +void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
> +				    enum gem_load_type type)
> +{
> +	struct drm_i915_private *dev_priv = ctx->i915;
> +
> +	if (GEM_WARN_ON(type > LOAD_TYPE_LAST))
> +		return;

 >= I think, or bad things can happen.

> +
> +	/* Call opt_config to get correct configuration for eu,slice,subslice */
> +	ctx->slice_cnt = dev_priv->opt_config[type].slice;
> +	ctx->subslice_cnt = dev_priv->opt_config[type].subslice;
> +	ctx->eu_cnt = dev_priv->opt_config[type].eu;
> +	ctx->pending_load_type = type;
> +}
> +
>   static void
>   destroy_kernel_context(struct i915_gem_context **ctxp)
>   {
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context.h b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> index 18e50a7..8677427 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context.h
> @@ -177,6 +177,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data,
>   				    struct drm_file *file_priv);
>   int i915_gem_context_reset_stats_ioctl(struct drm_device *dev, void *data,
>   				       struct drm_file *file);
> +void i915_gem_context_set_load_type(struct i915_gem_context *ctx,
> +				enum gem_load_type type);
>   
>   struct i915_gem_context *
>   i915_gem_context_create_kernel(struct drm_i915_private *i915, int prio);
> diff --git a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> index 3931c06..6847d49 100644
> --- a/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> +++ b/drivers/gpu/drm/i915/gem/i915_gem_context_types.h
> @@ -40,6 +40,19 @@ struct i915_gem_engines_iter {
>   	const struct i915_gem_engines *engines;
>   };
>   
> +enum gem_load_type {
> +	LOAD_TYPE_LOW,
> +	LOAD_TYPE_MEDIUM,
> +	LOAD_TYPE_HIGH,
> +	LOAD_TYPE_LAST
> +};
> +
> +struct i915_sseu_optimum_config {
> +	u8 slice;
> +	u8 subslice;
> +	u8 eu;
> +};
> +
>   /**
>    * struct i915_gem_context - client state
>    *
> @@ -173,6 +186,25 @@ struct i915_gem_context {
>   	 */
>   	atomic_t req_cnt;
>   
> +	/** slice_cnt: used to set the # of slices to be enabled. */
> +	u8 slice_cnt;
> +
> +	/** subslice_cnt: used to set the # of subslices to be enabled. */
> +	u8 subslice_cnt;
> +
> +	/** eu_cnt: used to set the # of eu to be enabled. */
> +	u8 eu_cnt;
> +
> +	/** load_type: The designated load_type (high/medium/low) for a given
> +	 * number of pending commands in the command queue.
> +	 */
> +	enum gem_load_type load_type;
> +
> +	/** pending_load_type: The earlier load type that the GPU was configured
> +	 * for (high/medium/low).
> +	 */
> +	enum gem_load_type pending_load_type;
> +
>   	/** jump_whitelist: Bit array for tracking cmds during cmdparsing
>   	 *  Guarded by struct_mutex
>   	 */
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index 511d5a1..c3f279e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -2436,6 +2436,36 @@ static void execlists_context_unpin(struct intel_context *ce)
>   	intel_ring_reset(ce->ring, ce->ring->tail);
>   }
>   
> +static u32
> +get_context_rpcs_config(struct i915_gem_context *ctx)
> +{
> +	u32 rpcs = 0;
> +	struct drm_i915_private *dev_priv = ctx->i915;
> +
> +	if (INTEL_GEN(dev_priv) < 8)
> +		return 0;
> +
> +	if (RUNTIME_INFO(dev_priv)->sseu.has_slice_pg) {
> +		rpcs |= GEN8_RPCS_S_CNT_ENABLE;
> +		rpcs |= ctx->slice_cnt << GEN8_RPCS_S_CNT_SHIFT;
> +		rpcs |= GEN8_RPCS_ENABLE;
> +	}
> +
> +	if (RUNTIME_INFO(dev_priv)->sseu.has_subslice_pg) {
> +		rpcs |= GEN8_RPCS_SS_CNT_ENABLE;
> +		rpcs |= ctx->subslice_cnt << GEN8_RPCS_SS_CNT_SHIFT;
> +		rpcs |= GEN8_RPCS_ENABLE;
> +	}
> +
> +	if (RUNTIME_INFO(dev_priv)->sseu.has_eu_pg) {
> +		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MIN_SHIFT;
> +		rpcs |= ctx->eu_cnt << GEN8_RPCS_EU_MAX_SHIFT;
> +		rpcs |= GEN8_RPCS_ENABLE;
> +	}
> +
> +	return rpcs;
> +}
> +
>   static void
>   __execlists_update_reg_state(const struct intel_context *ce,
>   			     const struct intel_engine_cs *engine)
> @@ -2452,8 +2482,13 @@ __execlists_update_reg_state(const struct intel_context *ce,
>   
>   	/* RPCS */
>   	if (engine->class == RENDER_CLASS) {
> -		regs[CTX_R_PWR_CLK_STATE] =
> -			intel_sseu_make_rpcs(engine->i915, &ce->sseu);
> +		if (engine->i915->predictive_load_enable) {
> +			regs[CTX_R_PWR_CLK_STATE] =
> +				get_context_rpcs_config(ce->gem_context);

You cannot do it like this because you break OA and Gen11 user 
configured SSEU.

You need to have intel_sseu_make_rpcs below be the central decision 
maker on what is the correct SSEU config to apply.

Order of precedence should be:

1. OA compatible configuration
2. User requested configuration (via context set param
3. Dynamic SSEU suggested configuration
4. Defaults

Perhaps we need a marker on ce saying that user configuration has been 
set and then this code can remain as it were, just when you are applying 
Dynamic SSEU settings you do something like:

   if (!ce->user_sseu_set)
	  ce->sseu = make_dynamic_sseu(your optimal config);

I'll explain in the next patch what I am thinking in more detail.

Regards,

Tvrtko

> +		} else {
> +			regs[CTX_R_PWR_CLK_STATE] =
> +				intel_sseu_make_rpcs(engine->i915, &ce->sseu);
> +		}
>   
>   		i915_oa_init_reg_state(ce, engine);
>   	}
> @@ -2485,6 +2520,9 @@ __execlists_context_pin(struct intel_context *ce,
>   	ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE;
>   	__execlists_update_reg_state(ce, engine);
>   
> +	if (ce->gem_context->load_type != ce->gem_context->pending_load_type)
> +		ce->gem_context->load_type = ce->gem_context->pending_load_type;
> +
>   	return 0;
>   
>   unpin_active:
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index fdae5a9..3064ddf 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -999,6 +999,11 @@ struct drm_i915_private {
>   	/* protects panel power sequencer state */
>   	struct mutex pps_mutex;
>   
> +	/* optimal slice/subslice/EU configration state */
> +	struct i915_sseu_optimum_config *opt_config;
> +
> +	int predictive_load_enable;
> +
>   	unsigned int fsb_freq, mem_freq, is_ddr3;
>   	unsigned int skl_preferred_vco_freq;
>   	unsigned int max_cdclk_freq;
> diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
> index a5b5713..b3c2f92 100644
> --- a/drivers/gpu/drm/i915/intel_device_info.c
> +++ b/drivers/gpu/drm/i915/intel_device_info.c
> @@ -873,6 +873,34 @@ void intel_device_info_subplatform_init(struct drm_i915_private *i915)
>   	RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
>   }
>   
> +/* static table of slice/subslice/EU for Cherryview */
> +static const struct i915_sseu_optimum_config chv_config[LOAD_TYPE_LAST] = {
> +	{1, 1, 4},	/* Low */
> +	{1, 1, 6},	/* Medium */
> +	{1, 2, 6}	/* High */
> +};
> +
> +/* static table of slice/subslice/EU for GLK GT1 */
> +static const struct i915_sseu_optimum_config glk_gt1_config[LOAD_TYPE_LAST] = {
> +	{1, 2, 2},	/* Low */
> +	{1, 2, 3},	/* Medium */
> +	{1, 2, 6}	/* High */
> +};
> +
> +/* static table of slice/subslice/EU for KBL GT2 */
> +static const struct i915_sseu_optimum_config kbl_gt2_config[LOAD_TYPE_LAST] = {
> +	{1, 3, 2},	/* Low */
> +	{1, 3, 4},	/* Medium */
> +	{1, 3, 8}	/* High */
> +};
> +
> +/* static table of slice/subslice/EU for KBL GT3 */
> +static const struct i915_sseu_optimum_config kbl_gt3_config[LOAD_TYPE_LAST] = {
> +	{2, 3, 4},	/* Low */
> +	{2, 3, 6},	/* Medium */
> +	{2, 3, 8}	/* High */
> +};
> +
>   /**
>    * intel_device_info_runtime_init - initialize runtime info
>    * @dev_priv: the i915 device
> @@ -894,6 +922,7 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	struct intel_device_info *info = mkwrite_device_info(dev_priv);
>   	struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
>   	enum pipe pipe;
> +	struct i915_sseu_optimum_config *opt_config = NULL;
>   
>   	if (INTEL_GEN(dev_priv) >= 10) {
>   		for_each_pipe(dev_priv, pipe)
> @@ -999,12 +1028,38 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   	/* Initialize slice/subslice/EU info */
>   	if (IS_HASWELL(dev_priv))
>   		haswell_sseu_info_init(dev_priv);
> -	else if (IS_CHERRYVIEW(dev_priv))
> +	else if (IS_CHERRYVIEW(dev_priv)) {
>   		cherryview_sseu_info_init(dev_priv);
> +		opt_config = (struct i915_sseu_optimum_config *)chv_config;
> +		BUILD_BUG_ON(ARRAY_SIZE(chv_config) != LOAD_TYPE_LAST);
> +	}
>   	else if (IS_BROADWELL(dev_priv))
>   		broadwell_sseu_info_init(dev_priv);
> -	else if (IS_GEN(dev_priv, 9))
> +	else if (IS_GEN(dev_priv, 9)) {
>   		gen9_sseu_info_init(dev_priv);
> +
> +		switch (info->gt) {
> +		default: /* fall through */
> +		case 1:
> +			opt_config = (struct i915_sseu_optimum_config *)
> +						glk_gt1_config;
> +			BUILD_BUG_ON(ARRAY_SIZE(glk_gt1_config)
> +						!= LOAD_TYPE_LAST);
> +		break;
> +		case 2:
> +			opt_config = (struct i915_sseu_optimum_config *)
> +						kbl_gt2_config;
> +			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt2_config)
> +						!= LOAD_TYPE_LAST);
> +		break;
> +		case 3:
> +			opt_config = (struct i915_sseu_optimum_config *)
> +						kbl_gt3_config;
> +			BUILD_BUG_ON(ARRAY_SIZE(kbl_gt3_config)
> +						!= LOAD_TYPE_LAST);
> +		break;
> +		}
> +	}
>   	else if (IS_GEN(dev_priv, 10))
>   		gen10_sseu_info_init(dev_priv);
>   	else if (IS_GEN(dev_priv, 11))
> @@ -1017,6 +1072,9 @@ void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
>   		info->ppgtt_type = INTEL_PPGTT_NONE;
>   	}
>   
> +	if (opt_config)
> +		dev_priv->opt_config = opt_config;
> +
>   	/* Initialize command stream timestamp frequency */
>   	runtime->cs_timestamp_frequency_khz = read_timestamp_frequency(dev_priv);
>   }
> 
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^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 10:51     ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 10:51 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> High resolution timer is used for predictive governor to control
> eu/slice/subslice based on workloads.
> 
> param is provided to enable/disable/update timer configuration
> 
> V2:
>   * Fix code style.
>   * Move predictive_load_timer into a drm_i915_private
>     structure.
>   * Make generic function to set optimum config. (Tvrtko Ursulin)
> 
> V3:
>   * Rebase.
>   * Fix race condition for predictive load set.
>   * Add slack to start hrtimer for more power efficient. (Tvrtko Ursulin)
> 
> V4:
>   * Fix data type and initialization of mutex to protect predictive load
>     state.
>   * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
>   * Move debugfs to kernel parameter.
> 
> V5:
>   * Rebase.
>   * Remove mutex for pred_timer
> 
> V6:
>   * Rebase.
>   * Fix warnings.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile       |   1 +
>   drivers/gpu/drm/i915/gt/intel_deu.c | 104 ++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
>   drivers/gpu/drm/i915/i915_drv.h     |   4 ++
>   drivers/gpu/drm/i915/i915_gem.c     |   4 ++
>   drivers/gpu/drm/i915/i915_params.c  |   4 ++
>   drivers/gpu/drm/i915/i915_params.h  |   1 +
>   7 files changed, 149 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
>   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e0fd10c..c1a98f3 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -77,6 +77,7 @@ obj-y += gt/
>   gt-y += \
>   	gt/intel_breadcrumbs.o \
>   	gt/intel_context.o \
> +	gt/intel_deu.o \
>   	gt/intel_engine_cs.o \
>   	gt/intel_engine_heartbeat.o \
>   	gt/intel_engine_pm.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c b/drivers/gpu/drm/i915/gt/intel_deu.c
> new file mode 100644
> index 0000000..6c5b01c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_deu.c
> @@ -0,0 +1,104 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *    Ankit Navik <ankit.p.navik@intel.com>
> + */
> +
> +/**
> + * DOC: Dynamic EU Control (DEU)
> + *
> + * DEU tries to re-configure EU allocation during runtime by predictive load
> + * calculation of command queue to gain power saving.
> + * It is transparent to user space and completely handled in the kernel.
> + */
> +
> +#include "intel_deu.h"
> +#include "i915_drv.h"
> +#include "gem/i915_gem_context.h"
> +
> +/*
> + * Anything above threshold is considered as HIGH load, less is considered
> + * as LOW load and equal is considered as MEDIUM load.
> + *
> + * The threshold value of three active requests pending.
> + */
> +#define PENDING_THRESHOLD_MEDIUM 3
> +
> +#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
> +
> +enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer)
> +{
> +	struct drm_i915_private *dev_priv =
> +			container_of(hrtimer, typeof(*dev_priv), pred_timer);
> +	struct i915_gem_context *ctx;
> +	enum gem_load_type load_type;
> +	unsigned int req_pending;
> +
> +	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
> +		req_pending = atomic_read(&ctx->req_cnt);
> +
> +		/*
> +		 * Transitioning to low state whenever pending request is zero
> +		 * would cause vacillation between low and high state.
> +		 */
> +		if (req_pending == 0)
> +			continue;
> +
> +		if (req_pending > PENDING_THRESHOLD_MEDIUM)
> +			load_type = LOAD_TYPE_HIGH;
> +		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
> +			load_type = LOAD_TYPE_MEDIUM;
> +		else
> +			load_type = LOAD_TYPE_LOW;
> +
> +		i915_gem_context_set_load_type(ctx, load_type);
> +	}

Now ideally we don't want to iterate contexts from a timer for more than 
one reason. Most interesting one is that the configuration you are 
setting here is not actually applied until __execlists_update_reg_state. 
Which runs only when contexts is getting pinned (or re-pinned).

You mentioned you did some experiment where you did something on context 
pinning and that it did not work so well. I don't know what that was 
though. I don't think that was ever posted?

What I am thinking is this: You drop the timer altogether. Instead in 
__execlists_update_reg_state you look at your gem_context->req_cnt and 
implement your logic there.

You convert your selected configuration to struct intel_sseu (so counts 
to bitmasks) and pass it to intel_sseu_make_rpcs which does the right thing.

> +
> +	hrtimer_forward_now(hrtimer,
> +			    ms_to_ktime(dev_priv->predictive_load_enable));
> +
> +	return HRTIMER_RESTART;
> +}
> +
> +/**
> + * intel_deu_init - Initialize dynamic EU
> + * @dev_priv: i915 device instance
> + *
> + * This function is called at driver load
> + */
> +void intel_deu_init(struct drm_i915_private *dev_priv)
> +{
> +	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
> +	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> +	dev_priv->pred_timer.function = predictive_load_cb;
> +
> +	if (dev_priv->predictive_load_enable) {
> +		if (!hrtimer_active(&dev_priv->pred_timer))
> +			hrtimer_start_range_ns(&dev_priv->pred_timer,
> +			ms_to_ktime(dev_priv->predictive_load_enable),
> +			SLACK_TIMER_NSEC,
> +			HRTIMER_MODE_REL_PINNED);
> +	} else {
> +		hrtimer_cancel(&dev_priv->pred_timer);

Why do you need to stop something which hasn't been started?

And more importantly, who stops the timer on driver unload?

> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h b/drivers/gpu/drm/i915/gt/intel_deu.h
> new file mode 100644
> index 0000000..3b4b16f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_deu.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __INTEL_DEU_H__
> +#define __INTEL_DEU_H__
> +
> +struct drm_i915_private;
> +
> +void intel_deu_init(struct drm_i915_private *dev_priv);
> +
> +#endif /* __INTEL_DEU_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3064ddf..5553537 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1002,6 +1002,8 @@ struct drm_i915_private {
>   	/* optimal slice/subslice/EU configration state */
>   	struct i915_sseu_optimum_config *opt_config;
>   
> +	/* protects predictive load state */
> +	struct hrtimer pred_timer;
>   	int predictive_load_enable;
>   
>   	unsigned int fsb_freq, mem_freq, is_ddr3;
> @@ -1768,6 +1770,8 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
>   #endif
>   extern const struct dev_pm_ops i915_pm_ops;
>   
> +extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);
> +
>   int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
>   void i915_driver_remove(struct drm_i915_private *i915);
>   
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 61395b0..ee711ce 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -45,6 +45,7 @@
>   #include "gem/i915_gem_context.h"
>   #include "gem/i915_gem_ioctls.h"
>   #include "gem/i915_gem_pm.h"
> +#include "gt/intel_deu.h"
>   #include "gt/intel_context.h"
>   #include "gt/intel_engine_user.h"
>   #include "gt/intel_gt.h"
> @@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
>   	i915_gem_init__mm(dev_priv);
>   
>   	spin_lock_init(&dev_priv->fb_tracking.lock);
> +
> +	/* Dynamic EU timer initialization for predictive load */
> +	intel_deu_init(dev_priv);
>   }
>   
>   void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 1dd1f36..a5a3a6e 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
>   
>   i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
>   
> +i915_param_named_unsafe(deu_enable, int, 0600,
> +	"Enable dynamic EU control for power savings "
> +	"(0=disable deu predictive timer [default], 150=optimal deu predictive timer)"); > +
>   i915_param_named(fastboot, int, 0600,
>   	"Try to skip unnecessary mode sets at boot time "
>   	"(0=disabled, 1=enabled) "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 31b88f2..cf0903b 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -54,6 +54,7 @@ struct drm_printer;
>   	param(int, disable_power_well, -1) \
>   	param(int, enable_ips, 1) \
>   	param(int, invert_brightness, 0) \
> +	param(int, deu_enable, 0) \
>   	param(int, enable_guc, 0) \
>   	param(int, guc_log_level, -1) \
>   	param(char *, guc_firmware_path, NULL) \
> 

Regards,

Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 10:51     ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 10:51 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> High resolution timer is used for predictive governor to control
> eu/slice/subslice based on workloads.
> 
> param is provided to enable/disable/update timer configuration
> 
> V2:
>   * Fix code style.
>   * Move predictive_load_timer into a drm_i915_private
>     structure.
>   * Make generic function to set optimum config. (Tvrtko Ursulin)
> 
> V3:
>   * Rebase.
>   * Fix race condition for predictive load set.
>   * Add slack to start hrtimer for more power efficient. (Tvrtko Ursulin)
> 
> V4:
>   * Fix data type and initialization of mutex to protect predictive load
>     state.
>   * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
>   * Move debugfs to kernel parameter.
> 
> V5:
>   * Rebase.
>   * Remove mutex for pred_timer
> 
> V6:
>   * Rebase.
>   * Fix warnings.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile       |   1 +
>   drivers/gpu/drm/i915/gt/intel_deu.c | 104 ++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
>   drivers/gpu/drm/i915/i915_drv.h     |   4 ++
>   drivers/gpu/drm/i915/i915_gem.c     |   4 ++
>   drivers/gpu/drm/i915/i915_params.c  |   4 ++
>   drivers/gpu/drm/i915/i915_params.h  |   1 +
>   7 files changed, 149 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
>   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e0fd10c..c1a98f3 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -77,6 +77,7 @@ obj-y += gt/
>   gt-y += \
>   	gt/intel_breadcrumbs.o \
>   	gt/intel_context.o \
> +	gt/intel_deu.o \
>   	gt/intel_engine_cs.o \
>   	gt/intel_engine_heartbeat.o \
>   	gt/intel_engine_pm.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c b/drivers/gpu/drm/i915/gt/intel_deu.c
> new file mode 100644
> index 0000000..6c5b01c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_deu.c
> @@ -0,0 +1,104 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *    Ankit Navik <ankit.p.navik@intel.com>
> + */
> +
> +/**
> + * DOC: Dynamic EU Control (DEU)
> + *
> + * DEU tries to re-configure EU allocation during runtime by predictive load
> + * calculation of command queue to gain power saving.
> + * It is transparent to user space and completely handled in the kernel.
> + */
> +
> +#include "intel_deu.h"
> +#include "i915_drv.h"
> +#include "gem/i915_gem_context.h"
> +
> +/*
> + * Anything above threshold is considered as HIGH load, less is considered
> + * as LOW load and equal is considered as MEDIUM load.
> + *
> + * The threshold value of three active requests pending.
> + */
> +#define PENDING_THRESHOLD_MEDIUM 3
> +
> +#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
> +
> +enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer)
> +{
> +	struct drm_i915_private *dev_priv =
> +			container_of(hrtimer, typeof(*dev_priv), pred_timer);
> +	struct i915_gem_context *ctx;
> +	enum gem_load_type load_type;
> +	unsigned int req_pending;
> +
> +	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
> +		req_pending = atomic_read(&ctx->req_cnt);
> +
> +		/*
> +		 * Transitioning to low state whenever pending request is zero
> +		 * would cause vacillation between low and high state.
> +		 */
> +		if (req_pending == 0)
> +			continue;
> +
> +		if (req_pending > PENDING_THRESHOLD_MEDIUM)
> +			load_type = LOAD_TYPE_HIGH;
> +		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
> +			load_type = LOAD_TYPE_MEDIUM;
> +		else
> +			load_type = LOAD_TYPE_LOW;
> +
> +		i915_gem_context_set_load_type(ctx, load_type);
> +	}

Now ideally we don't want to iterate contexts from a timer for more than 
one reason. Most interesting one is that the configuration you are 
setting here is not actually applied until __execlists_update_reg_state. 
Which runs only when contexts is getting pinned (or re-pinned).

You mentioned you did some experiment where you did something on context 
pinning and that it did not work so well. I don't know what that was 
though. I don't think that was ever posted?

What I am thinking is this: You drop the timer altogether. Instead in 
__execlists_update_reg_state you look at your gem_context->req_cnt and 
implement your logic there.

You convert your selected configuration to struct intel_sseu (so counts 
to bitmasks) and pass it to intel_sseu_make_rpcs which does the right thing.

> +
> +	hrtimer_forward_now(hrtimer,
> +			    ms_to_ktime(dev_priv->predictive_load_enable));
> +
> +	return HRTIMER_RESTART;
> +}
> +
> +/**
> + * intel_deu_init - Initialize dynamic EU
> + * @dev_priv: i915 device instance
> + *
> + * This function is called at driver load
> + */
> +void intel_deu_init(struct drm_i915_private *dev_priv)
> +{
> +	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
> +	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> +	dev_priv->pred_timer.function = predictive_load_cb;
> +
> +	if (dev_priv->predictive_load_enable) {
> +		if (!hrtimer_active(&dev_priv->pred_timer))
> +			hrtimer_start_range_ns(&dev_priv->pred_timer,
> +			ms_to_ktime(dev_priv->predictive_load_enable),
> +			SLACK_TIMER_NSEC,
> +			HRTIMER_MODE_REL_PINNED);
> +	} else {
> +		hrtimer_cancel(&dev_priv->pred_timer);

Why do you need to stop something which hasn't been started?

And more importantly, who stops the timer on driver unload?

> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h b/drivers/gpu/drm/i915/gt/intel_deu.h
> new file mode 100644
> index 0000000..3b4b16f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_deu.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __INTEL_DEU_H__
> +#define __INTEL_DEU_H__
> +
> +struct drm_i915_private;
> +
> +void intel_deu_init(struct drm_i915_private *dev_priv);
> +
> +#endif /* __INTEL_DEU_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3064ddf..5553537 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1002,6 +1002,8 @@ struct drm_i915_private {
>   	/* optimal slice/subslice/EU configration state */
>   	struct i915_sseu_optimum_config *opt_config;
>   
> +	/* protects predictive load state */
> +	struct hrtimer pred_timer;
>   	int predictive_load_enable;
>   
>   	unsigned int fsb_freq, mem_freq, is_ddr3;
> @@ -1768,6 +1770,8 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
>   #endif
>   extern const struct dev_pm_ops i915_pm_ops;
>   
> +extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);
> +
>   int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
>   void i915_driver_remove(struct drm_i915_private *i915);
>   
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 61395b0..ee711ce 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -45,6 +45,7 @@
>   #include "gem/i915_gem_context.h"
>   #include "gem/i915_gem_ioctls.h"
>   #include "gem/i915_gem_pm.h"
> +#include "gt/intel_deu.h"
>   #include "gt/intel_context.h"
>   #include "gt/intel_engine_user.h"
>   #include "gt/intel_gt.h"
> @@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
>   	i915_gem_init__mm(dev_priv);
>   
>   	spin_lock_init(&dev_priv->fb_tracking.lock);
> +
> +	/* Dynamic EU timer initialization for predictive load */
> +	intel_deu_init(dev_priv);
>   }
>   
>   void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 1dd1f36..a5a3a6e 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
>   
>   i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
>   
> +i915_param_named_unsafe(deu_enable, int, 0600,
> +	"Enable dynamic EU control for power savings "
> +	"(0=disable deu predictive timer [default], 150=optimal deu predictive timer)"); > +
>   i915_param_named(fastboot, int, 0600,
>   	"Try to skip unnecessary mode sets at boot time "
>   	"(0=disabled, 1=enabled) "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 31b88f2..cf0903b 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -54,6 +54,7 @@ struct drm_printer;
>   	param(int, disable_power_well, -1) \
>   	param(int, enable_ips, 1) \
>   	param(int, invert_brightness, 0) \
> +	param(int, deu_enable, 0) \
>   	param(int, enable_guc, 0) \
>   	param(int, guc_log_level, -1) \
>   	param(char *, guc_firmware_path, NULL) \
> 

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 11:09       ` Chris Wilson
  0 siblings, 0 replies; 37+ messages in thread
From: Chris Wilson @ 2019-11-26 11:09 UTC (permalink / raw)
  To: Ankit Navik, Tvrtko Ursulin, intel-gfx; +Cc: vipin.anand

Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
> You mentioned you did some experiment where you did something on context 
> pinning and that it did not work so well. I don't know what that was 
> though. I don't think that was ever posted?
> 
> What I am thinking is this: You drop the timer altogether. Instead in 
> __execlists_update_reg_state you look at your gem_context->req_cnt and 
> implement your logic there.

I noticed the same non-sequitur. Except I would push that either the
entire measurement and hence patch series is bogus (beyond the patches
themselves being trivially broken, tested much?), or that it really
should be done from a timer and also adjust pinned contexts ala
reconfigure_sseu.

A bunch of selftests and igt proving that different sseu setups do
consume different power (i.e. that we can adjust sseu correctly),
along with demonstrating good workloads where autotuning produces
beneficial results is a must.

Also given Tvrtko's stats, this could all be done from userspace with an
extended CONTEXT_PARAM_SSEU, so why would we not do it that way?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 11:09       ` Chris Wilson
  0 siblings, 0 replies; 37+ messages in thread
From: Chris Wilson @ 2019-11-26 11:09 UTC (permalink / raw)
  To: Ankit Navik, Tvrtko Ursulin, intel-gfx; +Cc: vipin.anand

Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
> You mentioned you did some experiment where you did something on context 
> pinning and that it did not work so well. I don't know what that was 
> though. I don't think that was ever posted?
> 
> What I am thinking is this: You drop the timer altogether. Instead in 
> __execlists_update_reg_state you look at your gem_context->req_cnt and 
> implement your logic there.

I noticed the same non-sequitur. Except I would push that either the
entire measurement and hence patch series is bogus (beyond the patches
themselves being trivially broken, tested much?), or that it really
should be done from a timer and also adjust pinned contexts ala
reconfigure_sseu.

A bunch of selftests and igt proving that different sseu setups do
consume different power (i.e. that we can adjust sseu correctly),
along with demonstrating good workloads where autotuning produces
beneficial results is a must.

Also given Tvrtko's stats, this could all be done from userspace with an
extended CONTEXT_PARAM_SSEU, so why would we not do it that way?
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 11:31         ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 11:31 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 11:09, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
>> You mentioned you did some experiment where you did something on context
>> pinning and that it did not work so well. I don't know what that was
>> though. I don't think that was ever posted?
>>
>> What I am thinking is this: You drop the timer altogether. Instead in
>> __execlists_update_reg_state you look at your gem_context->req_cnt and
>> implement your logic there.
> 
> I noticed the same non-sequitur. Except I would push that either the
> entire measurement and hence patch series is bogus (beyond the patches
> themselves being trivially broken, tested much?), or that it really
> should be done from a timer and also adjust pinned contexts ala
> reconfigure_sseu.

Yeah, if doing it at pin time would not show the power benefit that 
would mean looking at req_cnt at pin time does not work, while looking 
at it half a timer period ago, on average, works. Which would be very 
intriguing. We'd probably want nice graphs in this case overlaying 
power, request counts, selected EU config, etc.

> A bunch of selftests and igt proving that different sseu setups do
> consume different power (i.e. that we can adjust sseu correctly),
> along with demonstrating good workloads where autotuning produces
> beneficial results is a must.
> 
> Also given Tvrtko's stats, this could all be done from userspace with an
> extended CONTEXT_PARAM_SSEU, so why would we not do it that way?

You mean patching and recompiling userspace? I don't think that would 
work for them.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 11:31         ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 11:31 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 11:09, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
>> You mentioned you did some experiment where you did something on context
>> pinning and that it did not work so well. I don't know what that was
>> though. I don't think that was ever posted?
>>
>> What I am thinking is this: You drop the timer altogether. Instead in
>> __execlists_update_reg_state you look at your gem_context->req_cnt and
>> implement your logic there.
> 
> I noticed the same non-sequitur. Except I would push that either the
> entire measurement and hence patch series is bogus (beyond the patches
> themselves being trivially broken, tested much?), or that it really
> should be done from a timer and also adjust pinned contexts ala
> reconfigure_sseu.

Yeah, if doing it at pin time would not show the power benefit that 
would mean looking at req_cnt at pin time does not work, while looking 
at it half a timer period ago, on average, works. Which would be very 
intriguing. We'd probably want nice graphs in this case overlaying 
power, request counts, selected EU config, etc.

> A bunch of selftests and igt proving that different sseu setups do
> consume different power (i.e. that we can adjust sseu correctly),
> along with demonstrating good workloads where autotuning produces
> beneficial results is a must.
> 
> Also given Tvrtko's stats, this could all be done from userspace with an
> extended CONTEXT_PARAM_SSEU, so why would we not do it that way?

You mean patching and recompiling userspace? I don't think that would 
work for them.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* ✗ Fi.CI.IGT: failure for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
@ 2019-11-26 11:42   ` Patchwork
  0 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2019-11-26 11:42 UTC (permalink / raw)
  To: Ankit Navik; +Cc: intel-gfx

== Series Details ==

Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
URL   : https://patchwork.freedesktop.org/series/69980/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7420_full -> Patchwork_15433_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15433_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15433_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15433_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl10/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl2/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb1/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         NOTRUN -> [INCOMPLETE][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  
Known issues
------------

  Here are the changes found in Patchwork_15433_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [PASS][6] -> [INCOMPLETE][7] ([fdo#111832]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@gem_ctx_isolation@vcs0-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb4/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-clean:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb1/igt@gem_ctx_isolation@vcs1-clean.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb8/igt@gem_ctx_isolation@vcs1-clean.html

  * igt@gem_ctx_shared@single-timeline:
    - shard-skl:          [PASS][10] -> [FAIL][11] ([fdo#112390])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@gem_ctx_shared@single-timeline.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl6/igt@gem_ctx_shared@single-timeline.html
    - shard-glk:          [PASS][12] -> [FAIL][13] ([fdo#112390])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-glk9/igt@gem_ctx_shared@single-timeline.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-glk2/igt@gem_ctx_shared@single-timeline.html
    - shard-apl:          [PASS][14] -> [FAIL][15] ([fdo#112390])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl4/igt@gem_ctx_shared@single-timeline.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl8/igt@gem_ctx_shared@single-timeline.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [PASS][16] -> [SKIP][17] ([fdo#112146])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_exec_async@concurrent-writes-bsd.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][18] -> [SKIP][19] ([fdo#109276]) +11 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-snb:          [PASS][20] -> [FAIL][21] ([fdo#112037])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-snb4/igt@gem_persistent_relocs@forked-thrashing.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-snb2/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_sync@basic-store-all:
    - shard-tglb:         [PASS][22] -> [INCOMPLETE][23] ([fdo#111880]) +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb7/igt@gem_sync@basic-store-all.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb3/igt@gem_sync@basic-store-all.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [PASS][24] -> [DMESG-WARN][25] ([fdo#111870])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-tglb:         [PASS][26] -> [INCOMPLETE][27] ([fdo#111747] / [fdo#111850])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb3/igt@i915_pm_rpm@system-suspend.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb3/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][28] -> [DMESG-FAIL][29] ([fdo#111991])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-hsw1/igt@i915_selftest@live_hangcheck.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-hsw6/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-tglb:         [PASS][30] -> [INCOMPLETE][31] ([fdo#111832] / [fdo#111850]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb6/igt@i915_suspend@fence-restore-untiled.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb5/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [PASS][32] -> [INCOMPLETE][33] ([fdo#111850])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][34] -> [DMESG-WARN][35] ([fdo#108566]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][36] -> [INCOMPLETE][37] ([fdo#107713])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][38] -> [FAIL][39] ([fdo#103167]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - shard-tglb:         [PASS][40] -> [FAIL][41] ([fdo#103167]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-skl:          [PASS][42] -> [INCOMPLETE][43] ([fdo#112347])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][44] -> [DMESG-WARN][45] ([fdo#108566]) +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][46] -> [FAIL][47] ([fdo#108145])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][48] -> [FAIL][49] ([fdo#108145] / [fdo#110403])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][50] -> [SKIP][51] ([fdo#109441])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][52] -> [DMESG-WARN][53] ([fdo#103313])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@perf@oa-exponents:
    - shard-apl:          [PASS][54] -> [TIMEOUT][55] ([fdo#111732 ])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl2/igt@perf@oa-exponents.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl4/igt@perf@oa-exponents.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][56] -> [SKIP][57] ([fdo#112080]) +6 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb1/igt@perf_pmu@busy-vcs1.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb8/igt@perf_pmu@busy-vcs1.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][58] ([fdo#112080]) -> [PASS][59] +4 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_busy@busy-vcs1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [DMESG-WARN][60] ([fdo#108566]) -> [PASS][61] +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
    - shard-tglb:         [INCOMPLETE][62] ([fdo#111832]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb2/igt@gem_ctx_isolation@bcs0-s3.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb6/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [SKIP][64] ([fdo#109276] / [fdo#112080]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][66] ([fdo#109276]) -> [PASS][67] +6 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][68] ([fdo#112146]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-kbl:          [FAIL][70] ([fdo#112392]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][72] ([fdo#111870]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-hsw4/igt@gem_userptr_blits@sync-unmap.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-hsw4/igt@gem_userptr_blits@sync-unmap.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-apl:          [INCOMPLETE][74] ([fdo#103927]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl8/igt@gem_userptr_blits@sync-unmap-after-close.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-skl:          [INCOMPLETE][76] ([fdo#104108] / [fdo#112347]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl8/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180:
    - shard-iclb:         [INCOMPLETE][78] ([fdo#107713]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_ccs@pipe-b-crc-primary-rotation-180.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@kms_ccs@pipe-b-crc-primary-rotation-180.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-tglb:         [FAIL][80] ([fdo#103167]) -> [PASS][81] +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
    - shard-iclb:         [FAIL][82] ([fdo#103167]) -> [PASS][83] +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-tglb:         [INCOMPLETE][84] ([fdo#112393]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-skl:          [INCOMPLETE][86] ([fdo#106978]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl6/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl8/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [DMESG-WARN][88] ([fdo#108566]) -> [PASS][89] +3 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][90] ([fdo#109441]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-tglb:         [INCOMPLETE][92] ([fdo#111832] / [fdo#111850]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@perf@disabled-read-error:
    - shard-iclb:         [DMESG-WARN][94] ([fdo#112394]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@perf@disabled-read-error.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@perf@disabled-read-error.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][96] ([fdo#111329]) -> [SKIP][97] ([fdo#109276] / [fdo#112080])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][98] ([fdo#103167]) -> [INCOMPLETE][99] ([fdo#111747] / [fdo#111884])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@perf@oa-exponents:
    - shard-skl:          [TIMEOUT][100] ([fdo#111732 ]) -> [INCOMPLETE][101] ([fdo#104108])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@perf@oa-exponents.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl9/igt@perf@oa-exponents.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106978]: https://bugs.freedesktop.org/sho

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
@ 2019-11-26 11:42   ` Patchwork
  0 siblings, 0 replies; 37+ messages in thread
From: Patchwork @ 2019-11-26 11:42 UTC (permalink / raw)
  To: Ankit Navik; +Cc: intel-gfx

== Series Details ==

Series: Dynamic EU configuration of Slice/Sub-slice/EU (rev4)
URL   : https://patchwork.freedesktop.org/series/69980/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7420_full -> Patchwork_15433_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_15433_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_15433_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_15433_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_big_fb@y-tiled-32bpp-rotate-180:
    - shard-skl:          [PASS][1] -> [INCOMPLETE][2] +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl10/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl2/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html

  * igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
    - shard-tglb:         [PASS][3] -> [INCOMPLETE][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb8/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb1/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move:
    - shard-tglb:         NOTRUN -> [INCOMPLETE][5]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-move.html

  
Known issues
------------

  Here are the changes found in Patchwork_15433_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_isolation@vcs0-s3:
    - shard-tglb:         [PASS][6] -> [INCOMPLETE][7] ([fdo#111832]) +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@gem_ctx_isolation@vcs0-s3.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb4/igt@gem_ctx_isolation@vcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-clean:
    - shard-iclb:         [PASS][8] -> [SKIP][9] ([fdo#109276] / [fdo#112080]) +2 similar issues
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb1/igt@gem_ctx_isolation@vcs1-clean.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb8/igt@gem_ctx_isolation@vcs1-clean.html

  * igt@gem_ctx_shared@single-timeline:
    - shard-skl:          [PASS][10] -> [FAIL][11] ([fdo#112390])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@gem_ctx_shared@single-timeline.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl6/igt@gem_ctx_shared@single-timeline.html
    - shard-glk:          [PASS][12] -> [FAIL][13] ([fdo#112390])
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-glk9/igt@gem_ctx_shared@single-timeline.html
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-glk2/igt@gem_ctx_shared@single-timeline.html
    - shard-apl:          [PASS][14] -> [FAIL][15] ([fdo#112390])
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl4/igt@gem_ctx_shared@single-timeline.html
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl8/igt@gem_ctx_shared@single-timeline.html

  * igt@gem_exec_async@concurrent-writes-bsd:
    - shard-iclb:         [PASS][16] -> [SKIP][17] ([fdo#112146])
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_exec_async@concurrent-writes-bsd.html
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@gem_exec_async@concurrent-writes-bsd.html

  * igt@gem_exec_schedule@preempt-queue-bsd1:
    - shard-iclb:         [PASS][18] -> [SKIP][19] ([fdo#109276]) +11 similar issues
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb6/igt@gem_exec_schedule@preempt-queue-bsd1.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-snb:          [PASS][20] -> [FAIL][21] ([fdo#112037])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-snb4/igt@gem_persistent_relocs@forked-thrashing.html
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-snb2/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_sync@basic-store-all:
    - shard-tglb:         [PASS][22] -> [INCOMPLETE][23] ([fdo#111880]) +1 similar issue
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb7/igt@gem_sync@basic-store-all.html
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb3/igt@gem_sync@basic-store-all.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-snb:          [PASS][24] -> [DMESG-WARN][25] ([fdo#111870])
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@i915_pm_rpm@system-suspend:
    - shard-tglb:         [PASS][26] -> [INCOMPLETE][27] ([fdo#111747] / [fdo#111850])
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb3/igt@i915_pm_rpm@system-suspend.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb3/igt@i915_pm_rpm@system-suspend.html

  * igt@i915_selftest@live_hangcheck:
    - shard-hsw:          [PASS][28] -> [DMESG-FAIL][29] ([fdo#111991])
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-hsw1/igt@i915_selftest@live_hangcheck.html
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-hsw6/igt@i915_selftest@live_hangcheck.html

  * igt@i915_suspend@fence-restore-untiled:
    - shard-tglb:         [PASS][30] -> [INCOMPLETE][31] ([fdo#111832] / [fdo#111850]) +1 similar issue
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb6/igt@i915_suspend@fence-restore-untiled.html
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb5/igt@i915_suspend@fence-restore-untiled.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [PASS][32] -> [INCOMPLETE][33] ([fdo#111850])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb4/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][34] -> [DMESG-WARN][35] ([fdo#108566]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][36] -> [INCOMPLETE][37] ([fdo#107713])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb7/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
    - shard-iclb:         [PASS][38] -> [FAIL][39] ([fdo#103167]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff:
    - shard-tglb:         [PASS][40] -> [FAIL][41] ([fdo#103167]) +1 similar issue
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-onoff.html

  * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
    - shard-skl:          [PASS][42] -> [INCOMPLETE][43] ([fdo#112347])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl9/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][44] -> [DMESG-WARN][45] ([fdo#108566]) +3 similar issues
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][46] -> [FAIL][47] ([fdo#108145])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
    - shard-skl:          [PASS][48] -> [FAIL][49] ([fdo#108145] / [fdo#110403])
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html

  * igt@kms_psr@psr2_sprite_blt:
    - shard-iclb:         [PASS][50] -> [SKIP][51] ([fdo#109441])
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb2/igt@kms_psr@psr2_sprite_blt.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb5/igt@kms_psr@psr2_sprite_blt.html

  * igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
    - shard-kbl:          [PASS][52] -> [DMESG-WARN][53] ([fdo#103313])
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl7/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl3/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html

  * igt@perf@oa-exponents:
    - shard-apl:          [PASS][54] -> [TIMEOUT][55] ([fdo#111732 ])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl2/igt@perf@oa-exponents.html
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl4/igt@perf@oa-exponents.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][56] -> [SKIP][57] ([fdo#112080]) +6 similar issues
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb1/igt@perf_pmu@busy-vcs1.html
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb8/igt@perf_pmu@busy-vcs1.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][58] ([fdo#112080]) -> [PASS][59] +4 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_busy@busy-vcs1.html
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@gem_busy@busy-vcs1.html

  * igt@gem_ctx_isolation@bcs0-s3:
    - shard-apl:          [DMESG-WARN][60] ([fdo#108566]) -> [PASS][61] +2 similar issues
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl6/igt@gem_ctx_isolation@bcs0-s3.html
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
    - shard-tglb:         [INCOMPLETE][62] ([fdo#111832]) -> [PASS][63]
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb2/igt@gem_ctx_isolation@bcs0-s3.html
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb6/igt@gem_ctx_isolation@bcs0-s3.html

  * igt@gem_ctx_isolation@vcs1-dirty-create:
    - shard-iclb:         [SKIP][64] ([fdo#109276] / [fdo#112080]) -> [PASS][65]
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_ctx_isolation@vcs1-dirty-create.html
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html

  * igt@gem_exec_schedule@preempt-contexts-bsd2:
    - shard-iclb:         [SKIP][66] ([fdo#109276]) -> [PASS][67] +6 similar issues
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@gem_exec_schedule@preempt-contexts-bsd2.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@gem_exec_schedule@preempt-contexts-bsd2.html

  * igt@gem_exec_schedule@preemptive-hang-bsd:
    - shard-iclb:         [SKIP][68] ([fdo#112146]) -> [PASS][69]
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb2/igt@gem_exec_schedule@preemptive-hang-bsd.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb5/igt@gem_exec_schedule@preemptive-hang-bsd.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-kbl:          [FAIL][70] ([fdo#112392]) -> [PASS][71]
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl3/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@gem_userptr_blits@sync-unmap:
    - shard-hsw:          [DMESG-WARN][72] ([fdo#111870]) -> [PASS][73]
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-hsw4/igt@gem_userptr_blits@sync-unmap.html
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-hsw4/igt@gem_userptr_blits@sync-unmap.html

  * igt@gem_userptr_blits@sync-unmap-after-close:
    - shard-apl:          [INCOMPLETE][74] ([fdo#103927]) -> [PASS][75]
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-apl8/igt@gem_userptr_blits@sync-unmap-after-close.html
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-apl6/igt@gem_userptr_blits@sync-unmap-after-close.html

  * igt@kms_big_fb@y-tiled-32bpp-rotate-0:
    - shard-skl:          [INCOMPLETE][76] ([fdo#104108] / [fdo#112347]) -> [PASS][77]
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl8/igt@kms_big_fb@y-tiled-32bpp-rotate-0.html

  * igt@kms_ccs@pipe-b-crc-primary-rotation-180:
    - shard-iclb:         [INCOMPLETE][78] ([fdo#107713]) -> [PASS][79]
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_ccs@pipe-b-crc-primary-rotation-180.html
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@kms_ccs@pipe-b-crc-primary-rotation-180.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-tglb:         [FAIL][80] ([fdo#103167]) -> [PASS][81] +1 similar issue
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render:
    - shard-iclb:         [FAIL][82] ([fdo#103167]) -> [PASS][83] +2 similar issues
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb2/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render:
    - shard-tglb:         [INCOMPLETE][84] ([fdo#112393]) -> [PASS][85]
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary:
    - shard-skl:          [INCOMPLETE][86] ([fdo#106978]) -> [PASS][87]
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl6/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl8/igt@kms_frontbuffer_tracking@psr-shrfb-scaledprimary.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-kbl:          [DMESG-WARN][88] ([fdo#108566]) -> [PASS][89] +3 similar issues
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-kbl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [SKIP][90] ([fdo#109441]) -> [PASS][91]
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@kms_psr@psr2_cursor_plane_onoff.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_vblank@pipe-b-ts-continuation-suspend:
    - shard-tglb:         [INCOMPLETE][92] ([fdo#111832] / [fdo#111850]) -> [PASS][93]
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb3/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb7/igt@kms_vblank@pipe-b-ts-continuation-suspend.html

  * igt@perf@disabled-read-error:
    - shard-iclb:         [DMESG-WARN][94] ([fdo#112394]) -> [PASS][95]
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb3/igt@perf@disabled-read-error.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb1/igt@perf@disabled-read-error.html

  
#### Warnings ####

  * igt@gem_ctx_isolation@vcs1-nonpriv:
    - shard-iclb:         [FAIL][96] ([fdo#111329]) -> [SKIP][97] ([fdo#109276] / [fdo#112080])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-iclb4/igt@gem_ctx_isolation@vcs1-nonpriv.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-iclb6/igt@gem_ctx_isolation@vcs1-nonpriv.html

  * igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw:
    - shard-tglb:         [FAIL][98] ([fdo#103167]) -> [INCOMPLETE][99] ([fdo#111747] / [fdo#111884])
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-tglb7/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-pri-indfb-multidraw.html

  * igt@perf@oa-exponents:
    - shard-skl:          [TIMEOUT][100] ([fdo#111732 ]) -> [INCOMPLETE][101] ([fdo#104108])
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7420/shard-skl5/igt@perf@oa-exponents.html
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/shard-skl9/igt@perf@oa-exponents.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103313]: https://bugs.freedesktop.org/show_bug.cgi?id=103313
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#106978]: https://bugs.freedesktop.org/sho

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15433/index.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 13:16           ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 13:16 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 11:31, Tvrtko Ursulin wrote:
> On 26/11/2019 11:09, Chris Wilson wrote:
>> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
>>> You mentioned you did some experiment where you did something on context
>>> pinning and that it did not work so well. I don't know what that was
>>> though. I don't think that was ever posted?
>>>
>>> What I am thinking is this: You drop the timer altogether. Instead in
>>> __execlists_update_reg_state you look at your gem_context->req_cnt and
>>> implement your logic there.
>>
>> I noticed the same non-sequitur. Except I would push that either the
>> entire measurement and hence patch series is bogus (beyond the patches
>> themselves being trivially broken, tested much?), or that it really
>> should be done from a timer and also adjust pinned contexts ala
>> reconfigure_sseu.
> 
> Yeah, if doing it at pin time would not show the power benefit that 
> would mean looking at req_cnt at pin time does not work, while looking 
> at it half a timer period ago, on average, works. Which would be very 
> intriguing. We'd probably want nice graphs in this case overlaying 
> power, request counts, selected EU config, etc.

Another thing to try, if simple bucketing of req_cnt to load level at 
pin time will not work, could be a time-weighted moving average of the 
same count, but also driven from context pinning.

Regards,

Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 13:16           ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 13:16 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 11:31, Tvrtko Ursulin wrote:
> On 26/11/2019 11:09, Chris Wilson wrote:
>> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
>>> You mentioned you did some experiment where you did something on context
>>> pinning and that it did not work so well. I don't know what that was
>>> though. I don't think that was ever posted?
>>>
>>> What I am thinking is this: You drop the timer altogether. Instead in
>>> __execlists_update_reg_state you look at your gem_context->req_cnt and
>>> implement your logic there.
>>
>> I noticed the same non-sequitur. Except I would push that either the
>> entire measurement and hence patch series is bogus (beyond the patches
>> themselves being trivially broken, tested much?), or that it really
>> should be done from a timer and also adjust pinned contexts ala
>> reconfigure_sseu.
> 
> Yeah, if doing it at pin time would not show the power benefit that 
> would mean looking at req_cnt at pin time does not work, while looking 
> at it half a timer period ago, on average, works. Which would be very 
> intriguing. We'd probably want nice graphs in this case overlaying 
> power, request counts, selected EU config, etc.

Another thing to try, if simple bucketing of req_cnt to load level at 
pin time will not work, could be a time-weighted moving average of the 
same count, but also driven from context pinning.

Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 13:21           ` Chris Wilson
  0 siblings, 0 replies; 37+ messages in thread
From: Chris Wilson @ 2019-11-26 13:21 UTC (permalink / raw)
  To: Ankit Navik, Tvrtko Ursulin, intel-gfx; +Cc: vipin.anand

Quoting Tvrtko Ursulin (2019-11-26 11:31:14)
> 
> On 26/11/2019 11:09, Chris Wilson wrote:
> > Also given Tvrtko's stats, this could all be done from userspace with an
> > extended CONTEXT_PARAM_SSEU, so why would we not do it that way?
> 
> You mean patching and recompiling userspace? I don't think that would 
> work for them.

No. I was thinking about some proof-of-concept userspace daemon using
per-context stats and tuning each context from a timer. Almost exactly
as proposed here, but it would be very nice validation that our kernel
API are not getting in the way of userspace creativity. :)

But who am I to talk, I think C is a scripting language ;)
-Chris
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 13:21           ` Chris Wilson
  0 siblings, 0 replies; 37+ messages in thread
From: Chris Wilson @ 2019-11-26 13:21 UTC (permalink / raw)
  To: Ankit Navik, Tvrtko Ursulin, intel-gfx; +Cc: vipin.anand

Quoting Tvrtko Ursulin (2019-11-26 11:31:14)
> 
> On 26/11/2019 11:09, Chris Wilson wrote:
> > Also given Tvrtko's stats, this could all be done from userspace with an
> > extended CONTEXT_PARAM_SSEU, so why would we not do it that way?
> 
> You mean patching and recompiling userspace? I don't think that would 
> work for them.

No. I was thinking about some proof-of-concept userspace daemon using
per-context stats and tuning each context from a timer. Almost exactly
as proposed here, but it would be very nice validation that our kernel
API are not getting in the way of userspace creativity. :)

But who am I to talk, I think C is a scripting language ;)
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 13:39             ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 13:39 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 13:21, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-26 11:31:14)
>>
>> On 26/11/2019 11:09, Chris Wilson wrote:
>>> Also given Tvrtko's stats, this could all be done from userspace with an
>>> extended CONTEXT_PARAM_SSEU, so why would we not do it that way?
>>
>> You mean patching and recompiling userspace? I don't think that would
>> work for them.
> 
> No. I was thinking about some proof-of-concept userspace daemon using
> per-context stats and tuning each context from a timer. Almost exactly
> as proposed here, but it would be very nice validation that our kernel
> API are not getting in the way of userspace creativity. :)
> 
> But who am I to talk, I think C is a scripting language ;)

Ah, I overlooked you wrote _extended_ CONTEXT_PARAM_SSEU.

Regards,

Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-26 13:39             ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-26 13:39 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 13:21, Chris Wilson wrote:
> Quoting Tvrtko Ursulin (2019-11-26 11:31:14)
>>
>> On 26/11/2019 11:09, Chris Wilson wrote:
>>> Also given Tvrtko's stats, this could all be done from userspace with an
>>> extended CONTEXT_PARAM_SSEU, so why would we not do it that way?
>>
>> You mean patching and recompiling userspace? I don't think that would
>> work for them.
> 
> No. I was thinking about some proof-of-concept userspace daemon using
> per-context stats and tuning each context from a timer. Almost exactly
> as proposed here, but it would be very nice validation that our kernel
> API are not getting in the way of userspace creativity. :)
> 
> But who am I to talk, I think C is a scripting language ;)

Ah, I overlooked you wrote _extended_ CONTEXT_PARAM_SSEU.

Regards,

Tvrtko
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-27 11:06         ` Navik, Ankit P
  0 siblings, 0 replies; 37+ messages in thread
From: Navik, Ankit P @ 2019-11-27 11:06 UTC (permalink / raw)
  To: Chris Wilson, Tvrtko Ursulin, intel-gfx; +Cc: Anand, Vipin

Hi Chris, 

Thank you for your feedback.

> On 26/11/2019 10:52, Charis Wilson wrote:
> 
> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
> > You mentioned you did some experiment where you did something on
> > context pinning and that it did not work so well. I don't know what
> > that was though. I don't think that was ever posted?
> >
> > What I am thinking is this: You drop the timer altogether. Instead in
> > __execlists_update_reg_state you look at your gem_context->req_cnt and
> > implement your logic there.
> 
> I noticed the same non-sequitur. Except I would push that either the entire
> measurement and hence patch series is bogus (beyond the patches themselves
> being trivially broken, tested much?), or that it really should be done from a
> timer and also adjust pinned contexts ala reconfigure_sseu.
> 
> A bunch of selftests and igt proving that different sseu setups do consume
> different power (i.e. that we can adjust sseu correctly), along with
> demonstrating good workloads where autotuning produces beneficial results is
> a must.
> 
> Also given Tvrtko's stats, this could all be done from userspace with an extended
> CONTEXT_PARAM_SSEU, so why would we not do it that way?
> -Chris

We have verified this patch series on KBL, GLK & CML platforms with well
known standard benchmarks as mentioned in the cover letters.
Power savings are verified with various tools (RAPL counters, Moonsoon
power monitor and socwatch).
We have also verified Battery Life use cases which shows significant power
savings. So I hope you will understand the we have taken proper measurements
before pushing the patch series. 

Thanks & Regards, 
Ankit
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-27 11:06         ` Navik, Ankit P
  0 siblings, 0 replies; 37+ messages in thread
From: Navik, Ankit P @ 2019-11-27 11:06 UTC (permalink / raw)
  To: Chris Wilson, Tvrtko Ursulin, intel-gfx; +Cc: Anand, Vipin

Hi Chris, 

Thank you for your feedback.

> On 26/11/2019 10:52, Charis Wilson wrote:
> 
> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
> > You mentioned you did some experiment where you did something on
> > context pinning and that it did not work so well. I don't know what
> > that was though. I don't think that was ever posted?
> >
> > What I am thinking is this: You drop the timer altogether. Instead in
> > __execlists_update_reg_state you look at your gem_context->req_cnt and
> > implement your logic there.
> 
> I noticed the same non-sequitur. Except I would push that either the entire
> measurement and hence patch series is bogus (beyond the patches themselves
> being trivially broken, tested much?), or that it really should be done from a
> timer and also adjust pinned contexts ala reconfigure_sseu.
> 
> A bunch of selftests and igt proving that different sseu setups do consume
> different power (i.e. that we can adjust sseu correctly), along with
> demonstrating good workloads where autotuning produces beneficial results is
> a must.
> 
> Also given Tvrtko's stats, this could all be done from userspace with an extended
> CONTEXT_PARAM_SSEU, so why would we not do it that way?
> -Chris

We have verified this patch series on KBL, GLK & CML platforms with well
known standard benchmarks as mentioned in the cover letters.
Power savings are verified with various tools (RAPL counters, Moonsoon
power monitor and socwatch).
We have also verified Battery Life use cases which shows significant power
savings. So I hope you will understand the we have taken proper measurements
before pushing the patch series. 

Thanks & Regards, 
Ankit
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-27 11:53       ` Navik, Ankit P
  0 siblings, 0 replies; 37+ messages in thread
From: Navik, Ankit P @ 2019-11-27 11:53 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx; +Cc: Anand, Vipin

> On 26/11/2019 04:21, Tvrtko Ursulin wrote:
> 
> On 26/11/2019 04:51, Ankit Navik wrote:
> > High resolution timer is used for predictive governor to control
> > eu/slice/subslice based on workloads.
> >
> > param is provided to enable/disable/update timer configuration
> >
> > V2:
> >   * Fix code style.
> >   * Move predictive_load_timer into a drm_i915_private
> >     structure.
> >   * Make generic function to set optimum config. (Tvrtko Ursulin)
> >
> > V3:
> >   * Rebase.
> >   * Fix race condition for predictive load set.
> >   * Add slack to start hrtimer for more power efficient. (Tvrtko
> > Ursulin)
> >
> > V4:
> >   * Fix data type and initialization of mutex to protect predictive load
> >     state.
> >   * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
> >   * Move debugfs to kernel parameter.
> >
> > V5:
> >   * Rebase.
> >   * Remove mutex for pred_timer
> >
> > V6:
> >   * Rebase.
> >   * Fix warnings.
> >
> > Cc: Vipin Anand <vipin.anand@intel.com>
> > Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> > ---
> >   drivers/gpu/drm/i915/Makefile       |   1 +
> >   drivers/gpu/drm/i915/gt/intel_deu.c | 104
> ++++++++++++++++++++++++++++++++++++
> >   drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
> >   drivers/gpu/drm/i915/i915_drv.h     |   4 ++
> >   drivers/gpu/drm/i915/i915_gem.c     |   4 ++
> >   drivers/gpu/drm/i915/i915_params.c  |   4 ++
> >   drivers/gpu/drm/i915/i915_params.h  |   1 +
> >   7 files changed, 149 insertions(+)
> >   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
> >   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index e0fd10c..c1a98f3 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -77,6 +77,7 @@ obj-y += gt/
> >   gt-y += \
> >   	gt/intel_breadcrumbs.o \
> >   	gt/intel_context.o \
> > +	gt/intel_deu.o \
> >   	gt/intel_engine_cs.o \
> >   	gt/intel_engine_heartbeat.o \
> >   	gt/intel_engine_pm.o \
> > diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c
> > b/drivers/gpu/drm/i915/gt/intel_deu.c
> > new file mode 100644
> > index 0000000..6c5b01c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/intel_deu.c
> > @@ -0,0 +1,104 @@
> > +/*
> > + * Copyright © 2019 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors:
> > + *    Ankit Navik <ankit.p.navik@intel.com>
> > + */
> > +
> > +/**
> > + * DOC: Dynamic EU Control (DEU)
> > + *
> > + * DEU tries to re-configure EU allocation during runtime by
> > +predictive load
> > + * calculation of command queue to gain power saving.
> > + * It is transparent to user space and completely handled in the kernel.
> > + */
> > +
> > +#include "intel_deu.h"
> > +#include "i915_drv.h"
> > +#include "gem/i915_gem_context.h"
> > +
> > +/*
> > + * Anything above threshold is considered as HIGH load, less is
> > +considered
> > + * as LOW load and equal is considered as MEDIUM load.
> > + *
> > + * The threshold value of three active requests pending.
> > + */
> > +#define PENDING_THRESHOLD_MEDIUM 3
> > +
> > +#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
> > +
> > +enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer) {
> > +	struct drm_i915_private *dev_priv =
> > +			container_of(hrtimer, typeof(*dev_priv), pred_timer);
> > +	struct i915_gem_context *ctx;
> > +	enum gem_load_type load_type;
> > +	unsigned int req_pending;
> > +
> > +	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
> > +		req_pending = atomic_read(&ctx->req_cnt);
> > +
> > +		/*
> > +		 * Transitioning to low state whenever pending request is zero
> > +		 * would cause vacillation between low and high state.
> > +		 */
> > +		if (req_pending == 0)
> > +			continue;
> > +
> > +		if (req_pending > PENDING_THRESHOLD_MEDIUM)
> > +			load_type = LOAD_TYPE_HIGH;
> > +		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
> > +			load_type = LOAD_TYPE_MEDIUM;
> > +		else
> > +			load_type = LOAD_TYPE_LOW;
> > +
> > +		i915_gem_context_set_load_type(ctx, load_type);
> > +	}
> 
> Now ideally we don't want to iterate contexts from a timer for more than one
> reason. Most interesting one is that the configuration you are setting here is not
> actually applied until __execlists_update_reg_state.
> Which runs only when contexts is getting pinned (or re-pinned).
> 
> You mentioned you did some experiment where you did something on context
> pinning and that it did not work so well. I don't know what that was though. I
> don't think that was ever posted?
> 
> What I am thinking is this: You drop the timer altogether. Instead in
> __execlists_update_reg_state you look at your gem_context->req_cnt and
> implement your logic there.
> 
> You convert your selected configuration to struct intel_sseu (so counts to
> bitmasks) and pass it to intel_sseu_make_rpcs which does the right thing.

Ok, we will drop the timer and verify the results with the suggestion. 

Thanks & Regards, 
Ankit
> 
> > +
> > +	hrtimer_forward_now(hrtimer,
> > +			    ms_to_ktime(dev_priv->predictive_load_enable));
> > +
> > +	return HRTIMER_RESTART;
> > +}
> > +
> > +/**
> > + * intel_deu_init - Initialize dynamic EU
> > + * @dev_priv: i915 device instance
> > + *
> > + * This function is called at driver load  */ void
> > +intel_deu_init(struct drm_i915_private *dev_priv) {
> > +	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
> > +	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC,
> HRTIMER_MODE_REL);
> > +	dev_priv->pred_timer.function = predictive_load_cb;
> > +
> > +	if (dev_priv->predictive_load_enable) {
> > +		if (!hrtimer_active(&dev_priv->pred_timer))
> > +			hrtimer_start_range_ns(&dev_priv->pred_timer,
> > +			ms_to_ktime(dev_priv->predictive_load_enable),
> > +			SLACK_TIMER_NSEC,
> > +			HRTIMER_MODE_REL_PINNED);
> > +	} else {
> > +		hrtimer_cancel(&dev_priv->pred_timer);
> 
> Why do you need to stop something which hasn't been started?
> 
> And more importantly, who stops the timer on driver unload?
> 
> > +	}
> > +}
> > diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h
> > b/drivers/gpu/drm/i915/gt/intel_deu.h
> > new file mode 100644
> > index 0000000..3b4b16f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/intel_deu.h
> > @@ -0,0 +1,31 @@
> > +/*
> > + * Copyright © 2019 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#ifndef __INTEL_DEU_H__
> > +#define __INTEL_DEU_H__
> > +
> > +struct drm_i915_private;
> > +
> > +void intel_deu_init(struct drm_i915_private *dev_priv);
> > +
> > +#endif /* __INTEL_DEU_H__ */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 3064ddf..5553537 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1002,6 +1002,8 @@ struct drm_i915_private {
> >   	/* optimal slice/subslice/EU configration state */
> >   	struct i915_sseu_optimum_config *opt_config;
> >
> > +	/* protects predictive load state */
> > +	struct hrtimer pred_timer;
> >   	int predictive_load_enable;
> >
> >   	unsigned int fsb_freq, mem_freq, is_ddr3; @@ -1768,6 +1770,8 @@
> > long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
> >   #endif
> >   extern const struct dev_pm_ops i915_pm_ops;
> >
> > +extern enum hrtimer_restart predictive_load_cb(struct hrtimer
> > +*hrtimer);
> > +
> >   int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
> >   void i915_driver_remove(struct drm_i915_private *i915);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c index 61395b0..ee711ce 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -45,6 +45,7 @@
> >   #include "gem/i915_gem_context.h"
> >   #include "gem/i915_gem_ioctls.h"
> >   #include "gem/i915_gem_pm.h"
> > +#include "gt/intel_deu.h"
> >   #include "gt/intel_context.h"
> >   #include "gt/intel_engine_user.h"
> >   #include "gt/intel_gt.h"
> > @@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private
> *dev_priv)
> >   	i915_gem_init__mm(dev_priv);
> >
> >   	spin_lock_init(&dev_priv->fb_tracking.lock);
> > +
> > +	/* Dynamic EU timer initialization for predictive load */
> > +	intel_deu_init(dev_priv);
> >   }
> >
> >   void i915_gem_cleanup_early(struct drm_i915_private *dev_priv) diff
> > --git a/drivers/gpu/drm/i915/i915_params.c
> > b/drivers/gpu/drm/i915/i915_params.c
> > index 1dd1f36..a5a3a6e 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int,
> > 0400,
> >
> >   i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default:
> > true)");
> >
> > +i915_param_named_unsafe(deu_enable, int, 0600,
> > +	"Enable dynamic EU control for power savings "
> > +	"(0=disable deu predictive timer [default], 150=optimal deu
> > +predictive timer)"); > +
> >   i915_param_named(fastboot, int, 0600,
> >   	"Try to skip unnecessary mode sets at boot time "
> >   	"(0=disabled, 1=enabled) "
> > diff --git a/drivers/gpu/drm/i915/i915_params.h
> > b/drivers/gpu/drm/i915/i915_params.h
> > index 31b88f2..cf0903b 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -54,6 +54,7 @@ struct drm_printer;
> >   	param(int, disable_power_well, -1) \
> >   	param(int, enable_ips, 1) \
> >   	param(int, invert_brightness, 0) \
> > +	param(int, deu_enable, 0) \
> >   	param(int, enable_guc, 0) \
> >   	param(int, guc_log_level, -1) \
> >   	param(char *, guc_firmware_path, NULL) \
> >
> 
> Regards,
> 
> Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-27 11:53       ` Navik, Ankit P
  0 siblings, 0 replies; 37+ messages in thread
From: Navik, Ankit P @ 2019-11-27 11:53 UTC (permalink / raw)
  To: Tvrtko Ursulin, intel-gfx; +Cc: Anand, Vipin

> On 26/11/2019 04:21, Tvrtko Ursulin wrote:
> 
> On 26/11/2019 04:51, Ankit Navik wrote:
> > High resolution timer is used for predictive governor to control
> > eu/slice/subslice based on workloads.
> >
> > param is provided to enable/disable/update timer configuration
> >
> > V2:
> >   * Fix code style.
> >   * Move predictive_load_timer into a drm_i915_private
> >     structure.
> >   * Make generic function to set optimum config. (Tvrtko Ursulin)
> >
> > V3:
> >   * Rebase.
> >   * Fix race condition for predictive load set.
> >   * Add slack to start hrtimer for more power efficient. (Tvrtko
> > Ursulin)
> >
> > V4:
> >   * Fix data type and initialization of mutex to protect predictive load
> >     state.
> >   * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
> >   * Move debugfs to kernel parameter.
> >
> > V5:
> >   * Rebase.
> >   * Remove mutex for pred_timer
> >
> > V6:
> >   * Rebase.
> >   * Fix warnings.
> >
> > Cc: Vipin Anand <vipin.anand@intel.com>
> > Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> > ---
> >   drivers/gpu/drm/i915/Makefile       |   1 +
> >   drivers/gpu/drm/i915/gt/intel_deu.c | 104
> ++++++++++++++++++++++++++++++++++++
> >   drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
> >   drivers/gpu/drm/i915/i915_drv.h     |   4 ++
> >   drivers/gpu/drm/i915/i915_gem.c     |   4 ++
> >   drivers/gpu/drm/i915/i915_params.c  |   4 ++
> >   drivers/gpu/drm/i915/i915_params.h  |   1 +
> >   7 files changed, 149 insertions(+)
> >   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
> >   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h
> >
> > diff --git a/drivers/gpu/drm/i915/Makefile
> > b/drivers/gpu/drm/i915/Makefile index e0fd10c..c1a98f3 100644
> > --- a/drivers/gpu/drm/i915/Makefile
> > +++ b/drivers/gpu/drm/i915/Makefile
> > @@ -77,6 +77,7 @@ obj-y += gt/
> >   gt-y += \
> >   	gt/intel_breadcrumbs.o \
> >   	gt/intel_context.o \
> > +	gt/intel_deu.o \
> >   	gt/intel_engine_cs.o \
> >   	gt/intel_engine_heartbeat.o \
> >   	gt/intel_engine_pm.o \
> > diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c
> > b/drivers/gpu/drm/i915/gt/intel_deu.c
> > new file mode 100644
> > index 0000000..6c5b01c
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/intel_deu.c
> > @@ -0,0 +1,104 @@
> > +/*
> > + * Copyright © 2019 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + *
> > + * Authors:
> > + *    Ankit Navik <ankit.p.navik@intel.com>
> > + */
> > +
> > +/**
> > + * DOC: Dynamic EU Control (DEU)
> > + *
> > + * DEU tries to re-configure EU allocation during runtime by
> > +predictive load
> > + * calculation of command queue to gain power saving.
> > + * It is transparent to user space and completely handled in the kernel.
> > + */
> > +
> > +#include "intel_deu.h"
> > +#include "i915_drv.h"
> > +#include "gem/i915_gem_context.h"
> > +
> > +/*
> > + * Anything above threshold is considered as HIGH load, less is
> > +considered
> > + * as LOW load and equal is considered as MEDIUM load.
> > + *
> > + * The threshold value of three active requests pending.
> > + */
> > +#define PENDING_THRESHOLD_MEDIUM 3
> > +
> > +#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
> > +
> > +enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer) {
> > +	struct drm_i915_private *dev_priv =
> > +			container_of(hrtimer, typeof(*dev_priv), pred_timer);
> > +	struct i915_gem_context *ctx;
> > +	enum gem_load_type load_type;
> > +	unsigned int req_pending;
> > +
> > +	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
> > +		req_pending = atomic_read(&ctx->req_cnt);
> > +
> > +		/*
> > +		 * Transitioning to low state whenever pending request is zero
> > +		 * would cause vacillation between low and high state.
> > +		 */
> > +		if (req_pending == 0)
> > +			continue;
> > +
> > +		if (req_pending > PENDING_THRESHOLD_MEDIUM)
> > +			load_type = LOAD_TYPE_HIGH;
> > +		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
> > +			load_type = LOAD_TYPE_MEDIUM;
> > +		else
> > +			load_type = LOAD_TYPE_LOW;
> > +
> > +		i915_gem_context_set_load_type(ctx, load_type);
> > +	}
> 
> Now ideally we don't want to iterate contexts from a timer for more than one
> reason. Most interesting one is that the configuration you are setting here is not
> actually applied until __execlists_update_reg_state.
> Which runs only when contexts is getting pinned (or re-pinned).
> 
> You mentioned you did some experiment where you did something on context
> pinning and that it did not work so well. I don't know what that was though. I
> don't think that was ever posted?
> 
> What I am thinking is this: You drop the timer altogether. Instead in
> __execlists_update_reg_state you look at your gem_context->req_cnt and
> implement your logic there.
> 
> You convert your selected configuration to struct intel_sseu (so counts to
> bitmasks) and pass it to intel_sseu_make_rpcs which does the right thing.

Ok, we will drop the timer and verify the results with the suggestion. 

Thanks & Regards, 
Ankit
> 
> > +
> > +	hrtimer_forward_now(hrtimer,
> > +			    ms_to_ktime(dev_priv->predictive_load_enable));
> > +
> > +	return HRTIMER_RESTART;
> > +}
> > +
> > +/**
> > + * intel_deu_init - Initialize dynamic EU
> > + * @dev_priv: i915 device instance
> > + *
> > + * This function is called at driver load  */ void
> > +intel_deu_init(struct drm_i915_private *dev_priv) {
> > +	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
> > +	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC,
> HRTIMER_MODE_REL);
> > +	dev_priv->pred_timer.function = predictive_load_cb;
> > +
> > +	if (dev_priv->predictive_load_enable) {
> > +		if (!hrtimer_active(&dev_priv->pred_timer))
> > +			hrtimer_start_range_ns(&dev_priv->pred_timer,
> > +			ms_to_ktime(dev_priv->predictive_load_enable),
> > +			SLACK_TIMER_NSEC,
> > +			HRTIMER_MODE_REL_PINNED);
> > +	} else {
> > +		hrtimer_cancel(&dev_priv->pred_timer);
> 
> Why do you need to stop something which hasn't been started?
> 
> And more importantly, who stops the timer on driver unload?
> 
> > +	}
> > +}
> > diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h
> > b/drivers/gpu/drm/i915/gt/intel_deu.h
> > new file mode 100644
> > index 0000000..3b4b16f
> > --- /dev/null
> > +++ b/drivers/gpu/drm/i915/gt/intel_deu.h
> > @@ -0,0 +1,31 @@
> > +/*
> > + * Copyright © 2019 Intel Corporation
> > + *
> > + * Permission is hereby granted, free of charge, to any person
> > +obtaining a
> > + * copy of this software and associated documentation files (the
> > +"Software"),
> > + * to deal in the Software without restriction, including without
> > +limitation
> > + * the rights to use, copy, modify, merge, publish, distribute,
> > +sublicense,
> > + * and/or sell copies of the Software, and to permit persons to whom
> > +the
> > + * Software is furnished to do so, subject to the following conditions:
> > + *
> > + * The above copyright notice and this permission notice (including
> > +the next
> > + * paragraph) shall be included in all copies or substantial portions
> > +of the
> > + * Software.
> > + *
> > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> > +EXPRESS OR
> > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> > +MERCHANTABILITY,
> > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO
> EVENT
> > +SHALL
> > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
> DAMAGES
> > +OR OTHER
> > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
> > +ARISING
> > + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
> > +OTHER
> > + * DEALINGS IN THE SOFTWARE.
> > + */
> > +
> > +#ifndef __INTEL_DEU_H__
> > +#define __INTEL_DEU_H__
> > +
> > +struct drm_i915_private;
> > +
> > +void intel_deu_init(struct drm_i915_private *dev_priv);
> > +
> > +#endif /* __INTEL_DEU_H__ */
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > b/drivers/gpu/drm/i915/i915_drv.h index 3064ddf..5553537 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1002,6 +1002,8 @@ struct drm_i915_private {
> >   	/* optimal slice/subslice/EU configration state */
> >   	struct i915_sseu_optimum_config *opt_config;
> >
> > +	/* protects predictive load state */
> > +	struct hrtimer pred_timer;
> >   	int predictive_load_enable;
> >
> >   	unsigned int fsb_freq, mem_freq, is_ddr3; @@ -1768,6 +1770,8 @@
> > long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
> >   #endif
> >   extern const struct dev_pm_ops i915_pm_ops;
> >
> > +extern enum hrtimer_restart predictive_load_cb(struct hrtimer
> > +*hrtimer);
> > +
> >   int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
> >   void i915_driver_remove(struct drm_i915_private *i915);
> >
> > diff --git a/drivers/gpu/drm/i915/i915_gem.c
> > b/drivers/gpu/drm/i915/i915_gem.c index 61395b0..ee711ce 100644
> > --- a/drivers/gpu/drm/i915/i915_gem.c
> > +++ b/drivers/gpu/drm/i915/i915_gem.c
> > @@ -45,6 +45,7 @@
> >   #include "gem/i915_gem_context.h"
> >   #include "gem/i915_gem_ioctls.h"
> >   #include "gem/i915_gem_pm.h"
> > +#include "gt/intel_deu.h"
> >   #include "gt/intel_context.h"
> >   #include "gt/intel_engine_user.h"
> >   #include "gt/intel_gt.h"
> > @@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private
> *dev_priv)
> >   	i915_gem_init__mm(dev_priv);
> >
> >   	spin_lock_init(&dev_priv->fb_tracking.lock);
> > +
> > +	/* Dynamic EU timer initialization for predictive load */
> > +	intel_deu_init(dev_priv);
> >   }
> >
> >   void i915_gem_cleanup_early(struct drm_i915_private *dev_priv) diff
> > --git a/drivers/gpu/drm/i915/i915_params.c
> > b/drivers/gpu/drm/i915/i915_params.c
> > index 1dd1f36..a5a3a6e 100644
> > --- a/drivers/gpu/drm/i915/i915_params.c
> > +++ b/drivers/gpu/drm/i915/i915_params.c
> > @@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int,
> > 0400,
> >
> >   i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default:
> > true)");
> >
> > +i915_param_named_unsafe(deu_enable, int, 0600,
> > +	"Enable dynamic EU control for power savings "
> > +	"(0=disable deu predictive timer [default], 150=optimal deu
> > +predictive timer)"); > +
> >   i915_param_named(fastboot, int, 0600,
> >   	"Try to skip unnecessary mode sets at boot time "
> >   	"(0=disabled, 1=enabled) "
> > diff --git a/drivers/gpu/drm/i915/i915_params.h
> > b/drivers/gpu/drm/i915/i915_params.h
> > index 31b88f2..cf0903b 100644
> > --- a/drivers/gpu/drm/i915/i915_params.h
> > +++ b/drivers/gpu/drm/i915/i915_params.h
> > @@ -54,6 +54,7 @@ struct drm_printer;
> >   	param(int, disable_power_well, -1) \
> >   	param(int, enable_ips, 1) \
> >   	param(int, invert_brightness, 0) \
> > +	param(int, deu_enable, 0) \
> >   	param(int, enable_guc, 0) \
> >   	param(int, guc_log_level, -1) \
> >   	param(char *, guc_firmware_path, NULL) \
> >
> 
> Regards,
> 
> Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-28 10:27             ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-28 10:27 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 13:16, Tvrtko Ursulin wrote:
> 
> On 26/11/2019 11:31, Tvrtko Ursulin wrote:
>> On 26/11/2019 11:09, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
>>>> You mentioned you did some experiment where you did something on 
>>>> context
>>>> pinning and that it did not work so well. I don't know what that was
>>>> though. I don't think that was ever posted?
>>>>
>>>> What I am thinking is this: You drop the timer altogether. Instead in
>>>> __execlists_update_reg_state you look at your gem_context->req_cnt and
>>>> implement your logic there.
>>>
>>> I noticed the same non-sequitur. Except I would push that either the
>>> entire measurement and hence patch series is bogus (beyond the patches
>>> themselves being trivially broken, tested much?), or that it really
>>> should be done from a timer and also adjust pinned contexts ala
>>> reconfigure_sseu.
>>
>> Yeah, if doing it at pin time would not show the power benefit that 
>> would mean looking at req_cnt at pin time does not work, while looking 
>> at it half a timer period ago, on average, works. Which would be very 
>> intriguing. We'd probably want nice graphs in this case overlaying 
>> power, request counts, selected EU config, etc.
> 
> Another thing to try, if simple bucketing of req_cnt to load level at 
> pin time will not work, could be a time-weighted moving average of the 
> same count, but also driven from context pinning.

Yet another interesting experiment would be to try context busyness 
instead of request counts. Crudely, look at context's GPU busy time (I 
have patches for this) per evaluation period and configure accordingly.

This should be able to track better in theory I think, but probably has 
it's own problems. Hard to say without trying and comparing.

Implementation wise, a kthread periodically reconfiguring contexts would 
work I think. Like:

every second
   per context
     query context engine busyness
       calculate relative busyness
         re-configure sseu
		
Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
@ 2019-11-28 10:27             ` Tvrtko Ursulin
  0 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-11-28 10:27 UTC (permalink / raw)
  To: Chris Wilson, Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 13:16, Tvrtko Ursulin wrote:
> 
> On 26/11/2019 11:31, Tvrtko Ursulin wrote:
>> On 26/11/2019 11:09, Chris Wilson wrote:
>>> Quoting Tvrtko Ursulin (2019-11-26 10:51:22)
>>>> You mentioned you did some experiment where you did something on 
>>>> context
>>>> pinning and that it did not work so well. I don't know what that was
>>>> though. I don't think that was ever posted?
>>>>
>>>> What I am thinking is this: You drop the timer altogether. Instead in
>>>> __execlists_update_reg_state you look at your gem_context->req_cnt and
>>>> implement your logic there.
>>>
>>> I noticed the same non-sequitur. Except I would push that either the
>>> entire measurement and hence patch series is bogus (beyond the patches
>>> themselves being trivially broken, tested much?), or that it really
>>> should be done from a timer and also adjust pinned contexts ala
>>> reconfigure_sseu.
>>
>> Yeah, if doing it at pin time would not show the power benefit that 
>> would mean looking at req_cnt at pin time does not work, while looking 
>> at it half a timer period ago, on average, works. Which would be very 
>> intriguing. We'd probably want nice graphs in this case overlaying 
>> power, request counts, selected EU config, etc.
> 
> Another thing to try, if simple bucketing of req_cnt to load level at 
> pin time will not work, could be a time-weighted moving average of the 
> same count, but also driven from context pinning.

Yet another interesting experiment would be to try context busyness 
instead of request counts. Crudely, look at context's GPU busy time (I 
have patches for this) per evaluation period and configure accordingly.

This should be able to track better in theory I think, but probably has 
it's own problems. Hard to say without trying and comparing.

Implementation wise, a kthread periodically reconfiguring contexts would 
work I think. Like:

every second
   per context
     query context engine busyness
       calculate relative busyness
         re-configure sseu
		
Regards,

Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
* Re: [Intel-gfx] [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu
  2019-11-26  4:51   ` [Intel-gfx] " Ankit Navik
  (?)
  (?)
@ 2019-12-20 14:50   ` Tvrtko Ursulin
  -1 siblings, 0 replies; 37+ messages in thread
From: Tvrtko Ursulin @ 2019-12-20 14:50 UTC (permalink / raw)
  To: Ankit Navik, intel-gfx; +Cc: vipin.anand


On 26/11/2019 04:51, Ankit Navik wrote:
> High resolution timer is used for predictive governor to control
> eu/slice/subslice based on workloads.
> 
> param is provided to enable/disable/update timer configuration
> 
> V2:
>   * Fix code style.
>   * Move predictive_load_timer into a drm_i915_private
>     structure.
>   * Make generic function to set optimum config. (Tvrtko Ursulin)
> 
> V3:
>   * Rebase.
>   * Fix race condition for predictive load set.
>   * Add slack to start hrtimer for more power efficient. (Tvrtko Ursulin)
> 
> V4:
>   * Fix data type and initialization of mutex to protect predictive load
>     state.
>   * Move predictive timer init to i915_gem_init_early. (Tvrtko Ursulin)
>   * Move debugfs to kernel parameter.
> 
> V5:
>   * Rebase.
>   * Remove mutex for pred_timer
> 
> V6:
>   * Rebase.
>   * Fix warnings.
> 
> Cc: Vipin Anand <vipin.anand@intel.com>
> Signed-off-by: Ankit Navik <ankit.p.navik@intel.com>
> ---
>   drivers/gpu/drm/i915/Makefile       |   1 +
>   drivers/gpu/drm/i915/gt/intel_deu.c | 104 ++++++++++++++++++++++++++++++++++++
>   drivers/gpu/drm/i915/gt/intel_deu.h |  31 +++++++++++
>   drivers/gpu/drm/i915/i915_drv.h     |   4 ++
>   drivers/gpu/drm/i915/i915_gem.c     |   4 ++
>   drivers/gpu/drm/i915/i915_params.c  |   4 ++
>   drivers/gpu/drm/i915/i915_params.h  |   1 +
>   7 files changed, 149 insertions(+)
>   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.c
>   create mode 100644 drivers/gpu/drm/i915/gt/intel_deu.h
> 
> diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
> index e0fd10c..c1a98f3 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -77,6 +77,7 @@ obj-y += gt/
>   gt-y += \
>   	gt/intel_breadcrumbs.o \
>   	gt/intel_context.o \
> +	gt/intel_deu.o \
>   	gt/intel_engine_cs.o \
>   	gt/intel_engine_heartbeat.o \
>   	gt/intel_engine_pm.o \
> diff --git a/drivers/gpu/drm/i915/gt/intel_deu.c b/drivers/gpu/drm/i915/gt/intel_deu.c
> new file mode 100644
> index 0000000..6c5b01c
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_deu.c
> @@ -0,0 +1,104 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + *
> + * Authors:
> + *    Ankit Navik <ankit.p.navik@intel.com>
> + */
> +
> +/**
> + * DOC: Dynamic EU Control (DEU)
> + *
> + * DEU tries to re-configure EU allocation during runtime by predictive load
> + * calculation of command queue to gain power saving.
> + * It is transparent to user space and completely handled in the kernel.
> + */
> +
> +#include "intel_deu.h"
> +#include "i915_drv.h"
> +#include "gem/i915_gem_context.h"
> +
> +/*
> + * Anything above threshold is considered as HIGH load, less is considered
> + * as LOW load and equal is considered as MEDIUM load.
> + *
> + * The threshold value of three active requests pending.
> + */
> +#define PENDING_THRESHOLD_MEDIUM 3
> +
> +#define SLACK_TIMER_NSEC 1000000 /* Timer range in nano second */
> +
> +enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer)
> +{
> +	struct drm_i915_private *dev_priv =
> +			container_of(hrtimer, typeof(*dev_priv), pred_timer);
> +	struct i915_gem_context *ctx;
> +	enum gem_load_type load_type;
> +	unsigned int req_pending;
> +
> +	list_for_each_entry(ctx, &dev_priv->gem.contexts.list, link) {
> +		req_pending = atomic_read(&ctx->req_cnt);
> +

Another thought here. SSEU configuration is a shared resource affecting 
some engines with some commands. For instance number of requests 
targeting the blitter engine sounds completely irrelevant to this 
decision. Requests targeting video engines may or may not be relevant, 
depends if they are using media fixed function or non-fixed function 
pipeline (I think at least they can do this.). Render is always relevant.

I had some patches which count per engine, but in a world of virtual 
engines that does not work so well. Maybe solution is to track per 
struct intel_context. That should solve the virtual engine problem, but 
I am unsure how to deal with the media angle.

I can sketch out the intel_context request tracking after the holiday 
break as a starting point.

Regards,

Tvrtko

> +		/*
> +		 * Transitioning to low state whenever pending request is zero
> +		 * would cause vacillation between low and high state.
> +		 */
> +		if (req_pending == 0)
> +			continue;
> +
> +		if (req_pending > PENDING_THRESHOLD_MEDIUM)
> +			load_type = LOAD_TYPE_HIGH;
> +		else if (req_pending == PENDING_THRESHOLD_MEDIUM)
> +			load_type = LOAD_TYPE_MEDIUM;
> +		else
> +			load_type = LOAD_TYPE_LOW;
> +
> +		i915_gem_context_set_load_type(ctx, load_type);
> +	}
> +
> +	hrtimer_forward_now(hrtimer,
> +			    ms_to_ktime(dev_priv->predictive_load_enable));
> +
> +	return HRTIMER_RESTART;
> +}
> +
> +/**
> + * intel_deu_init - Initialize dynamic EU
> + * @dev_priv: i915 device instance
> + *
> + * This function is called at driver load
> + */
> +void intel_deu_init(struct drm_i915_private *dev_priv)
> +{
> +	dev_priv->predictive_load_enable = i915_modparams.deu_enable;
> +	hrtimer_init(&dev_priv->pred_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
> +	dev_priv->pred_timer.function = predictive_load_cb;
> +
> +	if (dev_priv->predictive_load_enable) {
> +		if (!hrtimer_active(&dev_priv->pred_timer))
> +			hrtimer_start_range_ns(&dev_priv->pred_timer,
> +			ms_to_ktime(dev_priv->predictive_load_enable),
> +			SLACK_TIMER_NSEC,
> +			HRTIMER_MODE_REL_PINNED);
> +	} else {
> +		hrtimer_cancel(&dev_priv->pred_timer);
> +	}
> +}
> diff --git a/drivers/gpu/drm/i915/gt/intel_deu.h b/drivers/gpu/drm/i915/gt/intel_deu.h
> new file mode 100644
> index 0000000..3b4b16f
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/gt/intel_deu.h
> @@ -0,0 +1,31 @@
> +/*
> + * Copyright © 2019 Intel Corporation
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the "Software"),
> + * to deal in the Software without restriction, including without limitation
> + * the rights to use, copy, modify, merge, publish, distribute, sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom the
> + * Software is furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice (including the next
> + * paragraph) shall be included in all copies or substantial portions of the
> + * Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
> + * DEALINGS IN THE SOFTWARE.
> + */
> +
> +#ifndef __INTEL_DEU_H__
> +#define __INTEL_DEU_H__
> +
> +struct drm_i915_private;
> +
> +void intel_deu_init(struct drm_i915_private *dev_priv);
> +
> +#endif /* __INTEL_DEU_H__ */
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 3064ddf..5553537 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1002,6 +1002,8 @@ struct drm_i915_private {
>   	/* optimal slice/subslice/EU configration state */
>   	struct i915_sseu_optimum_config *opt_config;
>   
> +	/* protects predictive load state */
> +	struct hrtimer pred_timer;
>   	int predictive_load_enable;
>   
>   	unsigned int fsb_freq, mem_freq, is_ddr3;
> @@ -1768,6 +1770,8 @@ long i915_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg);
>   #endif
>   extern const struct dev_pm_ops i915_pm_ops;
>   
> +extern enum hrtimer_restart predictive_load_cb(struct hrtimer *hrtimer);
> +
>   int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent);
>   void i915_driver_remove(struct drm_i915_private *i915);
>   
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 61395b0..ee711ce 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -45,6 +45,7 @@
>   #include "gem/i915_gem_context.h"
>   #include "gem/i915_gem_ioctls.h"
>   #include "gem/i915_gem_pm.h"
> +#include "gt/intel_deu.h"
>   #include "gt/intel_context.h"
>   #include "gt/intel_engine_user.h"
>   #include "gt/intel_gt.h"
> @@ -1416,6 +1417,9 @@ void i915_gem_init_early(struct drm_i915_private *dev_priv)
>   	i915_gem_init__mm(dev_priv);
>   
>   	spin_lock_init(&dev_priv->fb_tracking.lock);
> +
> +	/* Dynamic EU timer initialization for predictive load */
> +	intel_deu_init(dev_priv);
>   }
>   
>   void i915_gem_cleanup_early(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/i915_params.c b/drivers/gpu/drm/i915/i915_params.c
> index 1dd1f36..a5a3a6e 100644
> --- a/drivers/gpu/drm/i915/i915_params.c
> +++ b/drivers/gpu/drm/i915/i915_params.c
> @@ -101,6 +101,10 @@ i915_param_named_unsafe(disable_power_well, int, 0400,
>   
>   i915_param_named_unsafe(enable_ips, int, 0600, "Enable IPS (default: true)");
>   
> +i915_param_named_unsafe(deu_enable, int, 0600,
> +	"Enable dynamic EU control for power savings "
> +	"(0=disable deu predictive timer [default], 150=optimal deu predictive timer)");
> +
>   i915_param_named(fastboot, int, 0600,
>   	"Try to skip unnecessary mode sets at boot time "
>   	"(0=disabled, 1=enabled) "
> diff --git a/drivers/gpu/drm/i915/i915_params.h b/drivers/gpu/drm/i915/i915_params.h
> index 31b88f2..cf0903b 100644
> --- a/drivers/gpu/drm/i915/i915_params.h
> +++ b/drivers/gpu/drm/i915/i915_params.h
> @@ -54,6 +54,7 @@ struct drm_printer;
>   	param(int, disable_power_well, -1) \
>   	param(int, enable_ips, 1) \
>   	param(int, invert_brightness, 0) \
> +	param(int, deu_enable, 0) \
>   	param(int, enable_guc, 0) \
>   	param(int, guc_log_level, -1) \
>   	param(char *, guc_firmware_path, NULL) \
> 
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 37+ messages in thread
end of thread, other threads:[~2019-12-20 14:50 UTC | newest]

Thread overview: 37+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-26  4:51 [PATCH v6 0/3] Dynamic EU configuration of Slice/Sub-slice/EU Ankit Navik
2019-11-26  4:51 ` [Intel-gfx] " Ankit Navik
2019-11-26  4:51 ` [PATCH v6 1/3] drm/i915: Get active pending request for given context Ankit Navik
2019-11-26  4:51   ` [Intel-gfx] " Ankit Navik
2019-11-26 10:26   ` Tvrtko Ursulin
2019-11-26 10:26     ` [Intel-gfx] " Tvrtko Ursulin
2019-11-26  4:51 ` [PATCH v6 2/3] drm/i915: set optimum eu/slice/sub-slice configuration based on load type Ankit Navik
2019-11-26  4:51   ` [Intel-gfx] " Ankit Navik
2019-11-26 10:41   ` Tvrtko Ursulin
2019-11-26 10:41     ` [Intel-gfx] " Tvrtko Ursulin
2019-11-26  4:51 ` [PATCH v6 3/3] drm/i915: Predictive governor to control slice/subslice/eu Ankit Navik
2019-11-26  4:51   ` [Intel-gfx] " Ankit Navik
2019-11-26 10:51   ` Tvrtko Ursulin
2019-11-26 10:51     ` [Intel-gfx] " Tvrtko Ursulin
2019-11-26 11:09     ` Chris Wilson
2019-11-26 11:09       ` [Intel-gfx] " Chris Wilson
2019-11-26 11:31       ` Tvrtko Ursulin
2019-11-26 11:31         ` [Intel-gfx] " Tvrtko Ursulin
2019-11-26 13:16         ` Tvrtko Ursulin
2019-11-26 13:16           ` [Intel-gfx] " Tvrtko Ursulin
2019-11-28 10:27           ` Tvrtko Ursulin
2019-11-28 10:27             ` [Intel-gfx] " Tvrtko Ursulin
2019-11-26 13:21         ` Chris Wilson
2019-11-26 13:21           ` [Intel-gfx] " Chris Wilson
2019-11-26 13:39           ` Tvrtko Ursulin
2019-11-26 13:39             ` [Intel-gfx] " Tvrtko Ursulin
2019-11-27 11:06       ` Navik, Ankit P
2019-11-27 11:06         ` [Intel-gfx] " Navik, Ankit P
2019-11-27 11:53     ` Navik, Ankit P
2019-11-27 11:53       ` [Intel-gfx] " Navik, Ankit P
2019-12-20 14:50   ` Tvrtko Ursulin
2019-11-26  5:01 ` ✗ Fi.CI.CHECKPATCH: warning for Dynamic EU configuration of Slice/Sub-slice/EU (rev4) Patchwork
2019-11-26  5:01   ` [Intel-gfx] " Patchwork
2019-11-26  5:24 ` ✓ Fi.CI.BAT: success " Patchwork
2019-11-26  5:24   ` [Intel-gfx] " Patchwork
2019-11-26 11:42 ` ✗ Fi.CI.IGT: failure " Patchwork
2019-11-26 11:42   ` [Intel-gfx] " Patchwork

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