* [PATCH v5 0/4] Enable second DBuf slice for ICL and TGL
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Those patch series, do some initial preparation DBuf manipulating code
cleanups, i.e remove redundant structures/code, switch to mask
based DBuf manupulation, get into use DBuf assignment according to
BSpec rules.
Stanislav Lisovskiy (4):
drm/i915: Remove skl_ddl_allocation struct
drm/i915: Move dbuf slice update to proper place
drm/i915: Manipulate DBuf slices properly
drm/i915: Correctly map DBUF slices to pipes
drivers/gpu/drm/i915/display/intel_display.c | 47 ++-
.../drm/i915/display/intel_display_power.c | 100 +++---
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 296 +++++++++++++++---
drivers/gpu/drm/i915/intel_pm.h | 4 +-
8 files changed, 342 insertions(+), 123 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v5 0/4] Enable second DBuf slice for ICL and TGL
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Those patch series, do some initial preparation DBuf manipulating code
cleanups, i.e remove redundant structures/code, switch to mask
based DBuf manupulation, get into use DBuf assignment according to
BSpec rules.
Stanislav Lisovskiy (4):
drm/i915: Remove skl_ddl_allocation struct
drm/i915: Move dbuf slice update to proper place
drm/i915: Manipulate DBuf slices properly
drm/i915: Correctly map DBUF slices to pipes
drivers/gpu/drm/i915/display/intel_display.c | 47 ++-
.../drm/i915/display/intel_display_power.c | 100 +++---
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_drv.h | 6 +-
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 296 +++++++++++++++---
drivers/gpu/drm/i915/intel_pm.h | 4 +-
8 files changed, 342 insertions(+), 123 deletions(-)
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH v5 1/4] drm/i915: Remove skl_ddl_allocation struct
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Current consensus that it is redundant as
we already have skl_ddb_values struct out there,
also this struct contains only single member
which makes it unnecessary.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
.../gpu/drm/i915/display/intel_display_power.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 6 +-----
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++--------
drivers/gpu/drm/i915/intel_pm.h | 4 ++--
5 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..530832067113 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13393,10 +13393,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
struct skl_hw_state {
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
- struct skl_ddb_allocation ddb;
+ struct skl_ddb_values ddb;
struct skl_pipe_wm wm;
} *hw;
- struct skl_ddb_allocation *sw_ddb;
+ struct skl_ddb_values *sw_ddb;
struct skl_pipe_wm *sw_wm;
struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
const enum pipe pipe = crtc->pipe;
@@ -13415,7 +13415,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
skl_ddb_get_hw_state(dev_priv, &hw->ddb);
- sw_ddb = &dev_priv->wm.skl_hw.ddb;
+ sw_ddb = &dev_priv->wm.skl_hw;
if (INTEL_GEN(dev_priv) >= 11 &&
hw->ddb.enabled_slices != sw_ddb->enabled_slices)
@@ -14647,8 +14647,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
- u8 required_slices = state->wm_results.ddb.enabled_slices;
+ u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+ u8 required_slices = state->wm_results.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce1b64f4dd44..75198da13479 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ const u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
bool ret;
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
@@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
if (ret)
- dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ dev_priv->wm.skl_hw.enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
@@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that we only have 1 slice, see
* intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->wm.skl_hw.enabled_slices = 1;
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that the first slice is always
* enabled, see intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->wm.skl_hw.enabled_slices = 1;
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdae5a919bc8..6457f8e557a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -798,13 +798,9 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
return false;
}
-struct skl_ddb_allocation {
- u8 enabled_slices; /* GEN11 has configurable 2 slices */
-};
-
struct skl_ddb_values {
unsigned dirty_pipes;
- struct skl_ddb_allocation ddb;
+ u8 enabled_slices; /* GEN11 has configurable 2 slices */
};
struct skl_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5aad9d49a528..3857ec3d2bd6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3823,7 +3823,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
const int num_active,
- struct skl_ddb_allocation *ddb)
+ struct skl_ddb_values *ddb)
{
const struct drm_display_mode *adjusted_mode;
u64 total_data_bw;
@@ -3859,7 +3859,7 @@ static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- struct skl_ddb_allocation *ddb,
+ struct skl_ddb_values *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -4047,7 +4047,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
}
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */)
+ struct skl_ddb_values *ddb /* out */)
{
ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
}
@@ -4227,7 +4227,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
- struct skl_ddb_allocation *ddb /* out */)
+ struct skl_ddb_values *ddb /* out */)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_crtc *crtc = crtc_state->uapi.crtc;
@@ -5184,13 +5184,13 @@ static int
skl_compute_ddb(struct intel_atomic_state *state)
{
const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ struct skl_ddb_values *ddb = &state->wm_results;
struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int ret, i;
- memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
+ memcpy(ddb, &dev_priv->wm.skl_hw, sizeof(*ddb));
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -5666,11 +5666,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
- struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- skl_ddb_get_hw_state(dev_priv, ddb);
+ skl_ddb_get_hw_state(dev_priv, hw);
for_each_intel_crtc(&dev_priv->drm, crtc) {
crtc_state = to_intel_crtc_state(crtc->base.state);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..1d03732ff22e 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -17,8 +17,8 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
-struct skl_ddb_allocation;
struct skl_ddb_entry;
+struct skl_ddb_values;
struct skl_pipe_wm;
struct skl_wm_level;
@@ -37,7 +37,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */);
+ struct skl_ddb_values *ddb /* out */);
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v5 1/4] drm/i915: Remove skl_ddl_allocation struct
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Current consensus that it is redundant as
we already have skl_ddb_values struct out there,
also this struct contains only single member
which makes it unnecessary.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 10 +++++-----
.../gpu/drm/i915/display/intel_display_power.c | 8 ++++----
drivers/gpu/drm/i915/i915_drv.h | 6 +-----
drivers/gpu/drm/i915/intel_pm.c | 15 +++++++--------
drivers/gpu/drm/i915/intel_pm.h | 4 ++--
5 files changed, 19 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 53dc310a5f6d..530832067113 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13393,10 +13393,10 @@ static void verify_wm_state(struct intel_crtc *crtc,
struct skl_hw_state {
struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
struct skl_ddb_entry ddb_uv[I915_MAX_PLANES];
- struct skl_ddb_allocation ddb;
+ struct skl_ddb_values ddb;
struct skl_pipe_wm wm;
} *hw;
- struct skl_ddb_allocation *sw_ddb;
+ struct skl_ddb_values *sw_ddb;
struct skl_pipe_wm *sw_wm;
struct skl_ddb_entry *hw_ddb_entry, *sw_ddb_entry;
const enum pipe pipe = crtc->pipe;
@@ -13415,7 +13415,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
skl_pipe_ddb_get_hw_state(crtc, hw->ddb_y, hw->ddb_uv);
skl_ddb_get_hw_state(dev_priv, &hw->ddb);
- sw_ddb = &dev_priv->wm.skl_hw.ddb;
+ sw_ddb = &dev_priv->wm.skl_hw;
if (INTEL_GEN(dev_priv) >= 11 &&
hw->ddb.enabled_slices != sw_ddb->enabled_slices)
@@ -14647,8 +14647,8 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
- u8 required_slices = state->wm_results.ddb.enabled_slices;
+ u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+ u8 required_slices = state->wm_results.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ce1b64f4dd44..75198da13479 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4264,7 +4264,7 @@ static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.ddb.enabled_slices;
+ const u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
bool ret;
if (req_slices > intel_dbuf_max_slices(dev_priv)) {
@@ -4281,7 +4281,7 @@ void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
if (ret)
- dev_priv->wm.skl_hw.ddb.enabled_slices = req_slices;
+ dev_priv->wm.skl_hw.enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
@@ -4300,7 +4300,7 @@ static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that we only have 1 slice, see
* intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->wm.skl_hw.enabled_slices = 1;
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
@@ -4319,7 +4319,7 @@ static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
* FIXME: for now pretend that the first slice is always
* enabled, see intel_enabled_dbuf_slices_num().
*/
- dev_priv->wm.skl_hw.ddb.enabled_slices = 1;
+ dev_priv->wm.skl_hw.enabled_slices = 1;
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index fdae5a919bc8..6457f8e557a2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -798,13 +798,9 @@ static inline bool skl_ddb_entry_equal(const struct skl_ddb_entry *e1,
return false;
}
-struct skl_ddb_allocation {
- u8 enabled_slices; /* GEN11 has configurable 2 slices */
-};
-
struct skl_ddb_values {
unsigned dirty_pipes;
- struct skl_ddb_allocation ddb;
+ u8 enabled_slices; /* GEN11 has configurable 2 slices */
};
struct skl_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 5aad9d49a528..3857ec3d2bd6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3823,7 +3823,7 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
const int num_active,
- struct skl_ddb_allocation *ddb)
+ struct skl_ddb_values *ddb)
{
const struct drm_display_mode *adjusted_mode;
u64 total_data_bw;
@@ -3859,7 +3859,7 @@ static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
- struct skl_ddb_allocation *ddb,
+ struct skl_ddb_values *ddb,
struct skl_ddb_entry *alloc, /* out */
int *num_active /* out */)
{
@@ -4047,7 +4047,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
}
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */)
+ struct skl_ddb_values *ddb /* out */)
{
ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
}
@@ -4227,7 +4227,7 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state,
- struct skl_ddb_allocation *ddb /* out */)
+ struct skl_ddb_values *ddb /* out */)
{
struct drm_atomic_state *state = crtc_state->uapi.state;
struct drm_crtc *crtc = crtc_state->uapi.crtc;
@@ -5184,13 +5184,13 @@ static int
skl_compute_ddb(struct intel_atomic_state *state)
{
const struct drm_i915_private *dev_priv = to_i915(state->base.dev);
- struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
+ struct skl_ddb_values *ddb = &state->wm_results;
struct intel_crtc_state *old_crtc_state;
struct intel_crtc_state *new_crtc_state;
struct intel_crtc *crtc;
int ret, i;
- memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
+ memcpy(ddb, &dev_priv->wm.skl_hw, sizeof(*ddb));
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
@@ -5666,11 +5666,10 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
void skl_wm_get_hw_state(struct drm_i915_private *dev_priv)
{
struct skl_ddb_values *hw = &dev_priv->wm.skl_hw;
- struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
struct intel_crtc *crtc;
struct intel_crtc_state *crtc_state;
- skl_ddb_get_hw_state(dev_priv, ddb);
+ skl_ddb_get_hw_state(dev_priv, hw);
for_each_intel_crtc(&dev_priv->drm, crtc) {
crtc_state = to_intel_crtc_state(crtc->base.state);
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index b579c724b915..1d03732ff22e 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -17,8 +17,8 @@ struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_plane;
-struct skl_ddb_allocation;
struct skl_ddb_entry;
+struct skl_ddb_values;
struct skl_pipe_wm;
struct skl_wm_level;
@@ -37,7 +37,7 @@ void skl_pipe_ddb_get_hw_state(struct intel_crtc *crtc,
struct skl_ddb_entry *ddb_y,
struct skl_ddb_entry *ddb_uv);
void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
- struct skl_ddb_allocation *ddb /* out */);
+ struct skl_ddb_values *ddb /* out */);
void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v5 2/4] drm/i915: Move dbuf slice update to proper place
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Current DBuf slices update wasn't done in proper
plane, especially its "post" part, which should
disable those only once vblank had passed and
all other changes are committed.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 36 +++++++++++++++-----
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 530832067113..0d53bf82b2df 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14639,6 +14639,28 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
state);
}
+static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+ u8 required_slices = state->wm_results.enabled_slices;
+
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
+static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+ u8 required_slices = state->wm_results.enabled_slices;
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14656,10 +14678,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if (new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
- /* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
-
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -14716,10 +14734,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
progress = true;
}
} while (progress);
-
- /* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
@@ -14849,6 +14863,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_encoders_update_prepare(state);
+ /* Enable all new slices, we might need */
+ icl_dbuf_slice_pre_update(state);
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -14908,6 +14925,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
+ /* Disable all slices, we don't need */
+ icl_dbuf_slice_post_update(state);
+
drm_atomic_helper_commit_hw_done(&state->base);
if (state->modeset) {
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v5 2/4] drm/i915: Move dbuf slice update to proper place
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Current DBuf slices update wasn't done in proper
plane, especially its "post" part, which should
disable those only once vblank had passed and
all other changes are committed.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 36 +++++++++++++++-----
1 file changed, 28 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 530832067113..0d53bf82b2df 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -14639,6 +14639,28 @@ static void intel_update_trans_port_sync_crtcs(struct intel_crtc *crtc,
state);
}
+static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+ u8 required_slices = state->wm_results.enabled_slices;
+
+ /* If 2nd DBuf slice required, enable it here */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
+static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+ u8 required_slices = state->wm_results.enabled_slices;
+
+ /* If 2nd DBuf slice is no more required disable it */
+ if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
+ icl_dbuf_slices_update(dev_priv, required_slices);
+}
+
static void skl_commit_modeset_enables(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
@@ -14656,10 +14678,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
if (new_crtc_state->hw.active)
entries[i] = old_crtc_state->wm.skl.ddb;
- /* If 2nd DBuf slice required, enable it here */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
-
/*
* Whenever the number of active pipes changes, we need to make sure we
* update the pipes in the right order so that their ddb allocations
@@ -14716,10 +14734,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
progress = true;
}
} while (progress);
-
- /* If 2nd DBuf slice is no more required disable it */
- if (INTEL_GEN(dev_priv) >= 11 && required_slices < hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
}
static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
@@ -14849,6 +14863,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset)
intel_encoders_update_prepare(state);
+ /* Enable all new slices, we might need */
+ icl_dbuf_slice_pre_update(state);
+
/* Now enable the clocks, plane, pipe, and connectors that we set up. */
dev_priv->display.commit_modeset_enables(state);
@@ -14908,6 +14925,9 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
if (state->modeset && intel_can_enable_sagv(state))
intel_enable_sagv(dev_priv);
+ /* Disable all slices, we don't need */
+ icl_dbuf_slice_post_update(state);
+
drm_atomic_helper_commit_hw_done(&state->base);
if (state->modeset) {
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v5 3/4] drm/i915: Manipulate DBuf slices properly
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.
Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
we still need some value which should
reflect how much DBuf slices are supported
by the platform, now device info contains
num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
manipulating slices in a more proper way.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +-
.../drm/i915/display/intel_display_power.c | 100 ++++++++----------
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 43 +++-----
6 files changed, 72 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0d53bf82b2df..134d20992671 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13419,7 +13419,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) >= 11 &&
hw->ddb.enabled_slices != sw_ddb->enabled_slices)
- DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+ DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
sw_ddb->enabled_slices,
hw->ddb.enabled_slices);
@@ -14644,10 +14644,11 @@ static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
u8 required_slices = state->wm_results.enabled_slices;
+ u8 slices_union = hw_enabled_slices | required_slices;
/* If 2nd DBuf slice required, enable it here */
if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
+ icl_dbuf_slices_update(dev_priv, slices_union);
}
static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
@@ -14669,8 +14670,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
- u8 required_slices = state->wm_results.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 75198da13479..340fc2d3147d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1031,15 +1031,6 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
-static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
-{
- u32 tmp = I915_READ(DBUF_CTL);
-
- WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
- (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
- "Unexpected DBuf power power state (0x%08x)\n", tmp);
-}
-
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
@@ -1055,8 +1046,6 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
- gen9_assert_dbuf_enabled(dev_priv);
-
if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
@@ -4254,72 +4243,71 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
}
-static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) < 11)
- return 1;
- return 2;
+ return INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+}
+
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv)
+{
+ const u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+
+ icl_dbuf_slices_update(dev_priv, hw_enabled_slices);
}
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
- bool ret;
+ int i;
+ int max_slices = intel_dbuf_max_slices(dev_priv);
- if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+ if (hweight8(req_slices) > intel_dbuf_max_slices(dev_priv)) {
DRM_ERROR("Invalid number of dbuf slices requested\n");
return;
}
- if (req_slices == hw_enabled_slices || req_slices == 0)
- return;
+ DRM_DEBUG_KMS("Updating dbuf slices to %x\n", req_slices);
- if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
- else
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+ for (i = 0; i < max_slices; i++) {
+ int slice_bit = BIT(i);
+ bool slice_set = (slice_bit & req_slices) != 0;
+
+ switch (slice_bit) {
+ case DBUF_S1_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S1,
+ slice_set);
+ break;
+ case DBUF_S2_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S2,
+ slice_set);
+ break;
+ default:
+ MISSING_CASE(slice_bit);
+ }
+ }
- if (ret)
- dev_priv->wm.skl_hw.enabled_slices = req_slices;
+ dev_priv->wm.skl_hw.enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power enable timeout\n");
- else
- /*
- * FIXME: for now pretend that we only have 1 slice, see
- * intel_enabled_dbuf_slices_num().
- */
- dev_priv->wm.skl_hw.enabled_slices = 1;
+ /*
+ * Just power up 1 slice, we will
+ * figure out later which slices we have and what we need.
+ */
+ dev_priv->wm.skl_hw.enabled_slices = DBUF_S1_BIT;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power disable timeout!\n");
- else
- /*
- * FIXME: for now pretend that the first slice is always
- * enabled, see intel_enabled_dbuf_slices_num().
- */
- dev_priv->wm.skl_hw.enabled_slices = 1;
+ /*
+ * Disable all slices
+ */
+ dev_priv->wm.skl_hw.enabled_slices = 0;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1da04f3e0fb3..0d9f87607eac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -311,8 +311,13 @@ intel_display_power_put_async(struct drm_i915_private *i915,
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
+#define DBUF_S1_BIT BIT(0)
+#define DBUF_S2_BIT BIT(1)
+
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv);
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da3e9b5752ac..a050222240e4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -614,7 +614,8 @@ static const struct intel_device_info intel_cherryview_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896
+ .ddb_size = 896, \
+ .num_supported_dbuf_slices = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -649,6 +650,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
+ .num_supported_dbuf_slices = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -737,6 +739,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
GEN9_FEATURES, \
GEN(10), \
.ddb_size = 1024, \
+ .num_supported_dbuf_slices = 1, \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
@@ -773,6 +776,7 @@ static const struct intel_device_info intel_cannonlake_info = {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .num_supported_dbuf_slices = 2, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4bdf8a6cfb47..4a9f54a900be 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u8 num_supported_dbuf_slices; /* number of DBuf slices */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3857ec3d2bd6..4c30dddb943a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3601,22 +3601,18 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
{
- u8 enabled_slices;
-
- /* Slice 1 will always be enabled */
- enabled_slices = 1;
+ u8 enabled_slices = 0;
/* Gen prior to GEN11 have only one DBuf slice */
if (INTEL_GEN(dev_priv) < 11)
- return enabled_slices;
+ return DBUF_S1_BIT;
- /*
- * FIXME: for now we'll only ever use 1 slice; pretend that we have
- * only that 1 slice enabled until we have a proper way for on-demand
- * toggling of the second slice.
- */
- if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
- enabled_slices++;
+ /* Check if second DBuf slice is enabled */
+ if (I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S1_BIT;
+
+ if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S2_BIT;
return enabled_slices;
}
@@ -3825,8 +3821,6 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const int num_active,
struct skl_ddb_values *ddb)
{
- const struct drm_display_mode *adjusted_mode;
- u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
@@ -3834,23 +3828,14 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &crtc_state->hw.adjusted_mode;
- total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
-
/*
- * 12GB/s is maximum BW supported by single DBuf slice.
- *
- * FIXME dbuf slice code is broken:
- * - must wait for planes to stop using the slice before powering it off
- * - plane straddling both slices is illegal in multi-pipe scenarios
- * - should validate we stay within the hw bandwidth limits
+ * FIXME: Enabled slices should be only
+ * in according to BSpec and be determined
+ * by num active pipes(BSpec 12716 and 49255).
+ * For now set mask for 1st slice only.
*/
- if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- ddb->enabled_slices = 2;
- } else {
- ddb->enabled_slices = 1;
- ddb_size /= 2;
- }
+ ddb->enabled_slices = DBUF_S1_BIT;
+ ddb_size /= 2;
return ddb_size;
}
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v5 3/4] drm/i915: Manipulate DBuf slices properly
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Start manipulating DBuf slices as a mask,
but not as a total number, as current approach
doesn't give us full control on all combinations
of slices, which we might need(like enabling S2
only can't enabled by setting enabled_slices=1).
Removed wrong code from intel_get_ddb_size as
it doesn't match to BSpec. For now still just
use DBuf slice until proper algorithm is implemented.
Other minor code refactoring to get prepared
for major DBuf assignment changes landed:
- As now enabled slices contain a mask
we still need some value which should
reflect how much DBuf slices are supported
by the platform, now device info contains
num_supported_dbuf_slices.
- Removed unneeded assertion as we are now
manipulating slices in a more proper way.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 7 +-
.../drm/i915/display/intel_display_power.c | 100 ++++++++----------
.../drm/i915/display/intel_display_power.h | 5 +
drivers/gpu/drm/i915/i915_pci.c | 6 +-
drivers/gpu/drm/i915/intel_device_info.h | 1 +
drivers/gpu/drm/i915/intel_pm.c | 43 +++-----
6 files changed, 72 insertions(+), 90 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 0d53bf82b2df..134d20992671 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13419,7 +13419,7 @@ static void verify_wm_state(struct intel_crtc *crtc,
if (INTEL_GEN(dev_priv) >= 11 &&
hw->ddb.enabled_slices != sw_ddb->enabled_slices)
- DRM_ERROR("mismatch in DBUF Slices (expected %u, got %u)\n",
+ DRM_ERROR("mismatch in DBUF Slices (expected %x, got %x)\n",
sw_ddb->enabled_slices,
hw->ddb.enabled_slices);
@@ -14644,10 +14644,11 @@ static void icl_dbuf_slice_pre_update(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
u8 required_slices = state->wm_results.enabled_slices;
+ u8 slices_union = hw_enabled_slices | required_slices;
/* If 2nd DBuf slice required, enable it here */
if (INTEL_GEN(dev_priv) >= 11 && required_slices > hw_enabled_slices)
- icl_dbuf_slices_update(dev_priv, required_slices);
+ icl_dbuf_slices_update(dev_priv, slices_union);
}
static void icl_dbuf_slice_post_update(struct intel_atomic_state *state)
@@ -14669,8 +14670,6 @@ static void skl_commit_modeset_enables(struct intel_atomic_state *state)
unsigned int updated = 0;
bool progress;
int i;
- u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
- u8 required_slices = state->wm_results.enabled_slices;
struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 75198da13479..340fc2d3147d 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1031,15 +1031,6 @@ static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
}
-static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
-{
- u32 tmp = I915_READ(DBUF_CTL);
-
- WARN((tmp & (DBUF_POWER_STATE | DBUF_POWER_REQUEST)) !=
- (DBUF_POWER_STATE | DBUF_POWER_REQUEST),
- "Unexpected DBuf power power state (0x%08x)\n", tmp);
-}
-
static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
{
struct intel_cdclk_state cdclk_state = {};
@@ -1055,8 +1046,6 @@ static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
/* Can't read out voltage_level so can't use intel_cdclk_changed() */
WARN_ON(intel_cdclk_needs_modeset(&dev_priv->cdclk.hw, &cdclk_state));
- gen9_assert_dbuf_enabled(dev_priv);
-
if (IS_GEN9_LP(dev_priv))
bxt_verify_ddi_phy_power_wells(dev_priv);
@@ -4254,72 +4243,71 @@ static void gen9_dbuf_disable(struct drm_i915_private *dev_priv)
intel_dbuf_slice_set(dev_priv, DBUF_CTL, false);
}
-static u8 intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv)
{
- if (INTEL_GEN(dev_priv) < 11)
- return 1;
- return 2;
+ return INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+}
+
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv)
+{
+ const u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
+
+ icl_dbuf_slices_update(dev_priv, hw_enabled_slices);
}
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices)
{
- const u8 hw_enabled_slices = dev_priv->wm.skl_hw.enabled_slices;
- bool ret;
+ int i;
+ int max_slices = intel_dbuf_max_slices(dev_priv);
- if (req_slices > intel_dbuf_max_slices(dev_priv)) {
+ if (hweight8(req_slices) > intel_dbuf_max_slices(dev_priv)) {
DRM_ERROR("Invalid number of dbuf slices requested\n");
return;
}
- if (req_slices == hw_enabled_slices || req_slices == 0)
- return;
+ DRM_DEBUG_KMS("Updating dbuf slices to %x\n", req_slices);
- if (req_slices > hw_enabled_slices)
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, true);
- else
- ret = intel_dbuf_slice_set(dev_priv, DBUF_CTL_S2, false);
+ for (i = 0; i < max_slices; i++) {
+ int slice_bit = BIT(i);
+ bool slice_set = (slice_bit & req_slices) != 0;
+
+ switch (slice_bit) {
+ case DBUF_S1_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S1,
+ slice_set);
+ break;
+ case DBUF_S2_BIT:
+ intel_dbuf_slice_set(dev_priv,
+ DBUF_CTL_S2,
+ slice_set);
+ break;
+ default:
+ MISSING_CASE(slice_bit);
+ }
+ }
- if (ret)
- dev_priv->wm.skl_hw.enabled_slices = req_slices;
+ dev_priv->wm.skl_hw.enabled_slices = req_slices;
}
static void icl_dbuf_enable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) | DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) | DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if (!(I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- !(I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power enable timeout\n");
- else
- /*
- * FIXME: for now pretend that we only have 1 slice, see
- * intel_enabled_dbuf_slices_num().
- */
- dev_priv->wm.skl_hw.enabled_slices = 1;
+ /*
+ * Just power up 1 slice, we will
+ * figure out later which slices we have and what we need.
+ */
+ dev_priv->wm.skl_hw.enabled_slices = DBUF_S1_BIT;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_dbuf_disable(struct drm_i915_private *dev_priv)
{
- I915_WRITE(DBUF_CTL_S1, I915_READ(DBUF_CTL_S1) & ~DBUF_POWER_REQUEST);
- I915_WRITE(DBUF_CTL_S2, I915_READ(DBUF_CTL_S2) & ~DBUF_POWER_REQUEST);
- POSTING_READ(DBUF_CTL_S2);
-
- udelay(10);
-
- if ((I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE) ||
- (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE))
- DRM_ERROR("DBuf power disable timeout!\n");
- else
- /*
- * FIXME: for now pretend that the first slice is always
- * enabled, see intel_enabled_dbuf_slices_num().
- */
- dev_priv->wm.skl_hw.enabled_slices = 1;
+ /*
+ * Disable all slices
+ */
+ dev_priv->wm.skl_hw.enabled_slices = 0;
+ icl_program_dbuf_slices(dev_priv);
}
static void icl_mbus_init(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 1da04f3e0fb3..0d9f87607eac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -311,8 +311,13 @@ intel_display_power_put_async(struct drm_i915_private *i915,
for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
+#define DBUF_S1_BIT BIT(0)
+#define DBUF_S2_BIT BIT(1)
+
void icl_dbuf_slices_update(struct drm_i915_private *dev_priv,
u8 req_slices);
+void icl_program_dbuf_slices(struct drm_i915_private *dev_priv);
+int intel_dbuf_max_slices(struct drm_i915_private *dev_priv);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index da3e9b5752ac..a050222240e4 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -614,7 +614,8 @@ static const struct intel_device_info intel_cherryview_info = {
.has_gt_uc = 1, \
.display.has_hdcp = 1, \
.display.has_ipc = 1, \
- .ddb_size = 896
+ .ddb_size = 896, \
+ .num_supported_dbuf_slices = 1
#define SKL_PLATFORM \
GEN9_FEATURES, \
@@ -649,6 +650,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
#define GEN9_LP_FEATURES \
GEN(9), \
.is_lp = 1, \
+ .num_supported_dbuf_slices = 1, \
.display.has_hotplug = 1, \
.engine_mask = BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0), \
.pipe_mask = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C), \
@@ -737,6 +739,7 @@ static const struct intel_device_info intel_coffeelake_gt3_info = {
GEN9_FEATURES, \
GEN(10), \
.ddb_size = 1024, \
+ .num_supported_dbuf_slices = 1, \
.display.has_dsc = 1, \
.has_coherent_ggtt = false, \
GLK_COLORS
@@ -773,6 +776,7 @@ static const struct intel_device_info intel_cannonlake_info = {
}, \
GEN(11), \
.ddb_size = 2048, \
+ .num_supported_dbuf_slices = 2, \
.has_logical_ring_elsq = 1, \
.color = { .degamma_lut_size = 33, .gamma_lut_size = 262145 }
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 4bdf8a6cfb47..4a9f54a900be 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -180,6 +180,7 @@ struct intel_device_info {
} display;
u16 ddb_size; /* in blocks */
+ u8 num_supported_dbuf_slices; /* number of DBuf slices */
/* Register offsets for the various display pipes and transcoders */
int pipe_offsets[I915_MAX_TRANSCODERS];
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 3857ec3d2bd6..4c30dddb943a 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3601,22 +3601,18 @@ bool ilk_disable_lp_wm(struct drm_device *dev)
static u8 intel_enabled_dbuf_slices_num(struct drm_i915_private *dev_priv)
{
- u8 enabled_slices;
-
- /* Slice 1 will always be enabled */
- enabled_slices = 1;
+ u8 enabled_slices = 0;
/* Gen prior to GEN11 have only one DBuf slice */
if (INTEL_GEN(dev_priv) < 11)
- return enabled_slices;
+ return DBUF_S1_BIT;
- /*
- * FIXME: for now we'll only ever use 1 slice; pretend that we have
- * only that 1 slice enabled until we have a proper way for on-demand
- * toggling of the second slice.
- */
- if (0 && I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
- enabled_slices++;
+ /* Check if second DBuf slice is enabled */
+ if (I915_READ(DBUF_CTL_S1) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S1_BIT;
+
+ if (I915_READ(DBUF_CTL_S2) & DBUF_POWER_STATE)
+ enabled_slices |= DBUF_S2_BIT;
return enabled_slices;
}
@@ -3825,8 +3821,6 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const int num_active,
struct skl_ddb_values *ddb)
{
- const struct drm_display_mode *adjusted_mode;
- u64 total_data_bw;
u16 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
WARN_ON(ddb_size == 0);
@@ -3834,23 +3828,14 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- adjusted_mode = &crtc_state->hw.adjusted_mode;
- total_data_bw = total_data_rate * drm_mode_vrefresh(adjusted_mode);
-
/*
- * 12GB/s is maximum BW supported by single DBuf slice.
- *
- * FIXME dbuf slice code is broken:
- * - must wait for planes to stop using the slice before powering it off
- * - plane straddling both slices is illegal in multi-pipe scenarios
- * - should validate we stay within the hw bandwidth limits
+ * FIXME: Enabled slices should be only
+ * in according to BSpec and be determined
+ * by num active pipes(BSpec 12716 and 49255).
+ * For now set mask for 1st slice only.
*/
- if (0 && (num_active > 1 || total_data_bw >= GBps(12))) {
- ddb->enabled_slices = 2;
- } else {
- ddb->enabled_slices = 1;
- ddb_size /= 2;
- }
+ ddb->enabled_slices = DBUF_S1_BIT;
+ ddb_size /= 2;
return ddb_size;
}
--
2.17.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH v5 4/4] drm/i915: Correctly map DBUF slices to pipes
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 250 ++++++++++++++++++++++++++++++--
1 file changed, 236 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c30dddb943a..66657a207ed4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3815,6 +3815,25 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
return true;
}
+/*
+ * Calculate initial DBuf slice offset, based on slice size
+ * and mask(i.e if slice size is 1024 and second slice is enabled
+ * offset would be 1024)
+ */
+static u32 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
+ u32 slice_size, u32 ddb_size)
+{
+ u32 offset = 0;
+
+ if (!dbuf_slice_mask)
+ return 0;
+
+ offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
+
+ WARN_ON(offset >= ddb_size);
+ return offset;
+}
+
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
@@ -3828,18 +3847,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- /*
- * FIXME: Enabled slices should be only
- * in according to BSpec and be determined
- * by num active pipes(BSpec 12716 and 49255).
- * For now set mask for 1st slice only.
- */
- ddb->enabled_slices = DBUF_S1_BIT;
- ddb_size /= 2;
-
return ddb_size;
}
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state);
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
@@ -3855,7 +3869,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
+ u32 ddb_range_size;
u32 i;
+ u32 dbuf_slice_mask;
+ u32 active_pipes;
+ u32 offset;
+ u32 slice_size;
+ u32 total_slice_mask;
+ u32 start, end;
if (WARN_ON(!state) || !crtc_state->hw.active) {
alloc->start = 0;
@@ -3864,14 +3885,23 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
- if (intel_state->active_pipe_changes)
+ if (intel_state->active_pipe_changes) {
*num_active = hweight8(intel_state->active_pipes);
- else
+ active_pipes = intel_state->active_pipes;
+ } else {
*num_active = hweight8(dev_priv->active_pipes);
+ active_pipes = dev_priv->active_pipes;
+ }
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
*num_active, ddb);
+ DRM_DEBUG_KMS("Got total ddb size %d\n", ddb_size);
+
+ slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+
+ DRM_DEBUG_KMS("Got DBuf slice size %d\n", slice_size);
+
/*
* If the state doesn't change the active CRTC's or there is no
* modeset request, then there's no need to recalculate;
@@ -3889,18 +3919,68 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
+ /*
+ * Get allowed DBuf slices for correspondent pipe and platform.
+ */
+ dbuf_slice_mask = i915_possible_dbuf_slices(dev_priv, for_pipe,
+ active_pipes, crtc_state);
+
+ DRM_DEBUG_KMS("DBuf slice mask %x pipe %d active pipes %x\n",
+ dbuf_slice_mask,
+ for_pipe, active_pipes);
+
+ /*
+ * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
+ * and slice size is 1024, the offset would be 1024
+ */
+ offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
+ slice_size, ddb_size);
+
+ /*
+ * Figure out total size of allowed DBuf slices, which is basically
+ * a number of allowed slices for that pipe multiplied by slice size.
+ * Inside of this
+ * range ddb entries are still allocated in proportion to display width.
+ */
+ ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
+
/*
* Watermark/ddb requirement highly depends upon width of the
* framebuffer, So instead of allocating DDB equally among pipes
* distribute DDB based on resolution/width of the display.
*/
+ total_slice_mask = dbuf_slice_mask;
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
+ u32 pipe_dbuf_slice_mask =
+ i915_possible_dbuf_slices(dev_priv,
+ pipe,
+ active_pipes,
+ crtc_state);
- if (!crtc_state->hw.enable)
+ if (!crtc_state->hw.active)
+ continue;
+
+ /*
+ * According to BSpec pipe can share one dbuf slice with another
+ * pipes or pipe can use multiple dbufs, in both cases we
+ * account for other pipes only if they have exactly same mask.
+ * However we need to account how many slices we should enable
+ * in total.
+ */
+ total_slice_mask |= pipe_dbuf_slice_mask;
+
+ /*
+ * Do not account pipes using other slice sets
+ * luckily as of current BSpec slice sets do not partially
+ * intersect(pipes share either same one slice or same slice set
+ * i.e no partial intersection), so it is enough to check for
+ * equality for now.
+ */
+ if (dbuf_slice_mask != pipe_dbuf_slice_mask)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3912,8 +3992,19 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
pipe_width = hdisplay;
}
- alloc->start = ddb_size * width_before_pipe / total_width;
- alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
+ ddb->enabled_slices = total_slice_mask;
+
+ start = ddb_range_size * width_before_pipe / total_width;
+ end = ddb_range_size * (width_before_pipe + pipe_width) / total_width;
+
+ alloc->start = offset + start;
+ alloc->end = offset + end;
+
+ DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe,
+ alloc->start, alloc->end);
+ DRM_DEBUG_KMS("Enabled ddb slices mask %x num supported %d\n",
+ ddb->enabled_slices,
+ INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
}
static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
@@ -4035,6 +4126,7 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_values *ddb /* out */)
{
ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ DRM_DEBUG_KMS("Got hw dbuf slices mask %x\n", ddb->enabled_slices);
}
/*
@@ -4084,6 +4176,136 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
+
+struct dbuf_slice_conf_entry {
+ u32 active_pipes;
+ u32 dbuf_mask[I915_MAX_PIPES];
+};
+
+
+#define DBUF_TO_4_PIPES_MAP(active_pipes, dbuf1, dbuf2, dbuf3, dbuf4) \
+ { active_pipes, { dbuf1, dbuf2, dbuf3, dbuf4 } }
+
+/*
+ * Table taken from Bspec 12716
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry icl_allowed_dbufs[] = {
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A), DBUF_S1_BIT, 0, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B), 0, DBUF_S1_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C), 0, 0, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S1_BIT, DBUF_S2_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C), 0,
+ DBUF_S1_BIT, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0)
+};
+
+/*
+ * Table taken from Bspec 49255
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = {
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A), DBUF_S1_BIT | DBUF_S2_BIT, 0, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B), 0, DBUF_S1_BIT | DBUF_S2_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C), 0, 0, DBUF_S1_BIT | DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C), 0, 0, 0, DBUF_S1_BIT | DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S2_BIT, DBUF_S1_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, 0, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, 0, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT)
+};
+
+static u32 i915_find_pipe_conf(int pipe,
+ u32 active_pipes,
+ const struct dbuf_slice_conf_entry *dbuf_slices,
+ int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++) {
+ if (dbuf_slices[i].active_pipes == active_pipes) {
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
+ }
+ return 0;
+}
+
+/*
+ * This function finds an entry with same enabled pipe configuration and
+ * returns correspondent DBuf slice mask as stated in BSpec for particular
+ * platform.
+ */
+static u32 icl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ icl_allowed_dbufs,
+ ARRAY_SIZE(icl_allowed_dbufs));
+}
+
+static u32 tgl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ tgl_allowed_dbufs,
+ ARRAY_SIZE(tgl_allowed_dbufs));
+}
+
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (IS_GEN(dev_priv, 11))
+ return icl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ else if (IS_GEN(dev_priv, 12))
+ return tgl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ /*
+ * For anything else just return one slice yet.
+ * Should be extended for other platforms.
+ */
+ return DBUF_S1_BIT;
+}
+
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v5 4/4] drm/i915: Correctly map DBUF slices to pipes
@ 2019-11-26 16:28 ` Stanislav Lisovskiy
0 siblings, 0 replies; 16+ messages in thread
From: Stanislav Lisovskiy @ 2019-11-26 16:28 UTC (permalink / raw)
To: intel-gfx
Added proper DBuf slice mapping to correspondent
pipes, depending on pipe configuration as stated
in BSpec.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 250 ++++++++++++++++++++++++++++++--
1 file changed, 236 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 4c30dddb943a..66657a207ed4 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3815,6 +3815,25 @@ bool intel_can_enable_sagv(struct intel_atomic_state *state)
return true;
}
+/*
+ * Calculate initial DBuf slice offset, based on slice size
+ * and mask(i.e if slice size is 1024 and second slice is enabled
+ * offset would be 1024)
+ */
+static u32 icl_get_first_dbuf_slice_offset(u32 dbuf_slice_mask,
+ u32 slice_size, u32 ddb_size)
+{
+ u32 offset = 0;
+
+ if (!dbuf_slice_mask)
+ return 0;
+
+ offset = (ffs(dbuf_slice_mask) - 1) * slice_size;
+
+ WARN_ON(offset >= ddb_size);
+ return offset;
+}
+
static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
const u64 total_data_rate,
@@ -3828,18 +3847,13 @@ static u16 intel_get_ddb_size(struct drm_i915_private *dev_priv,
if (INTEL_GEN(dev_priv) < 11)
return ddb_size - 4; /* 4 blocks for bypass path allocation */
- /*
- * FIXME: Enabled slices should be only
- * in according to BSpec and be determined
- * by num active pipes(BSpec 12716 and 49255).
- * For now set mask for 1st slice only.
- */
- ddb->enabled_slices = DBUF_S1_BIT;
- ddb_size /= 2;
-
return ddb_size;
}
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state);
+
static void
skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
const struct intel_crtc_state *crtc_state,
@@ -3855,7 +3869,14 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
u32 pipe_width = 0, total_width = 0, width_before_pipe = 0;
enum pipe for_pipe = to_intel_crtc(for_crtc)->pipe;
u16 ddb_size;
+ u32 ddb_range_size;
u32 i;
+ u32 dbuf_slice_mask;
+ u32 active_pipes;
+ u32 offset;
+ u32 slice_size;
+ u32 total_slice_mask;
+ u32 start, end;
if (WARN_ON(!state) || !crtc_state->hw.active) {
alloc->start = 0;
@@ -3864,14 +3885,23 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
- if (intel_state->active_pipe_changes)
+ if (intel_state->active_pipe_changes) {
*num_active = hweight8(intel_state->active_pipes);
- else
+ active_pipes = intel_state->active_pipes;
+ } else {
*num_active = hweight8(dev_priv->active_pipes);
+ active_pipes = dev_priv->active_pipes;
+ }
ddb_size = intel_get_ddb_size(dev_priv, crtc_state, total_data_rate,
*num_active, ddb);
+ DRM_DEBUG_KMS("Got total ddb size %d\n", ddb_size);
+
+ slice_size = ddb_size / INTEL_INFO(dev_priv)->num_supported_dbuf_slices;
+
+ DRM_DEBUG_KMS("Got DBuf slice size %d\n", slice_size);
+
/*
* If the state doesn't change the active CRTC's or there is no
* modeset request, then there's no need to recalculate;
@@ -3889,18 +3919,68 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
return;
}
+ /*
+ * Get allowed DBuf slices for correspondent pipe and platform.
+ */
+ dbuf_slice_mask = i915_possible_dbuf_slices(dev_priv, for_pipe,
+ active_pipes, crtc_state);
+
+ DRM_DEBUG_KMS("DBuf slice mask %x pipe %d active pipes %x\n",
+ dbuf_slice_mask,
+ for_pipe, active_pipes);
+
+ /*
+ * Figure out at which DBuf slice we start, i.e if we start at Dbuf S2
+ * and slice size is 1024, the offset would be 1024
+ */
+ offset = icl_get_first_dbuf_slice_offset(dbuf_slice_mask,
+ slice_size, ddb_size);
+
+ /*
+ * Figure out total size of allowed DBuf slices, which is basically
+ * a number of allowed slices for that pipe multiplied by slice size.
+ * Inside of this
+ * range ddb entries are still allocated in proportion to display width.
+ */
+ ddb_range_size = hweight8(dbuf_slice_mask) * slice_size;
+
/*
* Watermark/ddb requirement highly depends upon width of the
* framebuffer, So instead of allocating DDB equally among pipes
* distribute DDB based on resolution/width of the display.
*/
+ total_slice_mask = dbuf_slice_mask;
for_each_new_intel_crtc_in_state(intel_state, crtc, crtc_state, i) {
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
enum pipe pipe = crtc->pipe;
int hdisplay, vdisplay;
+ u32 pipe_dbuf_slice_mask =
+ i915_possible_dbuf_slices(dev_priv,
+ pipe,
+ active_pipes,
+ crtc_state);
- if (!crtc_state->hw.enable)
+ if (!crtc_state->hw.active)
+ continue;
+
+ /*
+ * According to BSpec pipe can share one dbuf slice with another
+ * pipes or pipe can use multiple dbufs, in both cases we
+ * account for other pipes only if they have exactly same mask.
+ * However we need to account how many slices we should enable
+ * in total.
+ */
+ total_slice_mask |= pipe_dbuf_slice_mask;
+
+ /*
+ * Do not account pipes using other slice sets
+ * luckily as of current BSpec slice sets do not partially
+ * intersect(pipes share either same one slice or same slice set
+ * i.e no partial intersection), so it is enough to check for
+ * equality for now.
+ */
+ if (dbuf_slice_mask != pipe_dbuf_slice_mask)
continue;
drm_mode_get_hv_timing(adjusted_mode, &hdisplay, &vdisplay);
@@ -3912,8 +3992,19 @@ skl_ddb_get_pipe_allocation_limits(struct drm_i915_private *dev_priv,
pipe_width = hdisplay;
}
- alloc->start = ddb_size * width_before_pipe / total_width;
- alloc->end = ddb_size * (width_before_pipe + pipe_width) / total_width;
+ ddb->enabled_slices = total_slice_mask;
+
+ start = ddb_range_size * width_before_pipe / total_width;
+ end = ddb_range_size * (width_before_pipe + pipe_width) / total_width;
+
+ alloc->start = offset + start;
+ alloc->end = offset + end;
+
+ DRM_DEBUG_KMS("Pipe %d ddb %d-%d\n", for_pipe,
+ alloc->start, alloc->end);
+ DRM_DEBUG_KMS("Enabled ddb slices mask %x num supported %d\n",
+ ddb->enabled_slices,
+ INTEL_INFO(dev_priv)->num_supported_dbuf_slices);
}
static int skl_compute_wm_params(const struct intel_crtc_state *crtc_state,
@@ -4035,6 +4126,7 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
struct skl_ddb_values *ddb /* out */)
{
ddb->enabled_slices = intel_enabled_dbuf_slices_num(dev_priv);
+ DRM_DEBUG_KMS("Got hw dbuf slices mask %x\n", ddb->enabled_slices);
}
/*
@@ -4084,6 +4176,136 @@ skl_plane_downscale_amount(const struct intel_crtc_state *crtc_state,
return mul_fixed16(downscale_w, downscale_h);
}
+
+struct dbuf_slice_conf_entry {
+ u32 active_pipes;
+ u32 dbuf_mask[I915_MAX_PIPES];
+};
+
+
+#define DBUF_TO_4_PIPES_MAP(active_pipes, dbuf1, dbuf2, dbuf3, dbuf4) \
+ { active_pipes, { dbuf1, dbuf2, dbuf3, dbuf4 } }
+
+/*
+ * Table taken from Bspec 12716
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry icl_allowed_dbufs[] = {
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A), DBUF_S1_BIT, 0, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B), 0, DBUF_S1_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C), 0, 0, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S1_BIT, DBUF_S2_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C), 0,
+ DBUF_S1_BIT, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0)
+};
+
+/*
+ * Table taken from Bspec 49255
+ * Pipes do have some preferred DBuf slice affinity,
+ * plus there are some hardcoded requirements on how
+ * those should be distributed for multipipe scenarios.
+ * For more DBuf slices algorithm can get even more messy
+ * and less readable, so decided to use a table almost
+ * as is from BSpec itself - that way it is at least easier
+ * to compare, change and check.
+ */
+static struct dbuf_slice_conf_entry tgl_allowed_dbufs[] = {
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A), DBUF_S1_BIT | DBUF_S2_BIT, 0, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B), 0, DBUF_S1_BIT | DBUF_S2_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C), 0, 0, DBUF_S1_BIT | DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C), 0, 0, 0, DBUF_S1_BIT | DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S2_BIT, DBUF_S1_BIT, 0, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, 0, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, 0, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT),
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT)
+};
+
+static u32 i915_find_pipe_conf(int pipe,
+ u32 active_pipes,
+ const struct dbuf_slice_conf_entry *dbuf_slices,
+ int size)
+{
+ int i;
+
+ for (i = 0; i < size; i++) {
+ if (dbuf_slices[i].active_pipes == active_pipes) {
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
+ }
+ return 0;
+}
+
+/*
+ * This function finds an entry with same enabled pipe configuration and
+ * returns correspondent DBuf slice mask as stated in BSpec for particular
+ * platform.
+ */
+static u32 icl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ icl_allowed_dbufs,
+ ARRAY_SIZE(icl_allowed_dbufs));
+}
+
+static u32 tgl_possible_dbuf_slices(int pipe,
+ u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ return i915_find_pipe_conf(pipe, active_pipes,
+ tgl_allowed_dbufs,
+ ARRAY_SIZE(tgl_allowed_dbufs));
+}
+
+u32 i915_possible_dbuf_slices(struct drm_i915_private *dev_priv,
+ int pipe, u32 active_pipes,
+ const struct intel_crtc_state *crtc_state)
+{
+ if (IS_GEN(dev_priv, 11))
+ return icl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ else if (IS_GEN(dev_priv, 12))
+ return tgl_possible_dbuf_slices(pipe,
+ active_pipes,
+ crtc_state);
+ /*
+ * For anything else just return one slice yet.
+ * Should be extended for other platforms.
+ */
+ return DBUF_S1_BIT;
+}
+
static u64
skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state,
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for Enable second DBuf slice for ICL and TGL
@ 2019-11-26 20:12 ` Patchwork
0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-26 20:12 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f1c5115b93c7 drm/i915: Remove skl_ddl_allocation struct
03280b410f87 drm/i915: Move dbuf slice update to proper place
a778a20b2642 drm/i915: Manipulate DBuf slices properly
f799788524b4 drm/i915: Correctly map DBUF slices to pipes
-:210: CHECK:LINE_SPACING: Please don't use multiple blank lines
#210: FILE: drivers/gpu/drm/i915/intel_pm.c:4179:
+
-:216: CHECK:LINE_SPACING: Please don't use multiple blank lines
#216: FILE: drivers/gpu/drm/i915/intel_pm.c:4185:
+
+
-:235: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#235: FILE: drivers/gpu/drm/i915/intel_pm.c:4204:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S1_BIT, DBUF_S2_BIT, 0, 0),
-:237: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#237: FILE: drivers/gpu/drm/i915/intel_pm.c:4206:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
-:239: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#239: FILE: drivers/gpu/drm/i915/intel_pm.c:4208:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C), 0,
+ DBUF_S1_BIT, DBUF_S2_BIT, 0),
-:241: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#241: FILE: drivers/gpu/drm/i915/intel_pm.c:4210:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0)
-:260: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#260: FILE: drivers/gpu/drm/i915/intel_pm.c:4229:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S2_BIT, DBUF_S1_BIT, 0, 0),
-:262: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#262: FILE: drivers/gpu/drm/i915/intel_pm.c:4231:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
-:264: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#264: FILE: drivers/gpu/drm/i915/intel_pm.c:4233:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, 0, DBUF_S2_BIT),
-:266: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#266: FILE: drivers/gpu/drm/i915/intel_pm.c:4235:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, 0),
-:268: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#268: FILE: drivers/gpu/drm/i915/intel_pm.c:4237:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, 0, DBUF_S2_BIT),
-:270: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#270: FILE: drivers/gpu/drm/i915/intel_pm.c:4239:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
-:272: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#272: FILE: drivers/gpu/drm/i915/intel_pm.c:4241:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
-:274: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#274: FILE: drivers/gpu/drm/i915/intel_pm.c:4243:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0),
-:276: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#276: FILE: drivers/gpu/drm/i915/intel_pm.c:4245:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT),
-:278: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#278: FILE: drivers/gpu/drm/i915/intel_pm.c:4247:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT),
-:280: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#280: FILE: drivers/gpu/drm/i915/intel_pm.c:4249:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT)
-:291: WARNING:BRACES: braces {} are not necessary for single statement blocks
#291: FILE: drivers/gpu/drm/i915/intel_pm.c:4260:
+ if (dbuf_slices[i].active_pipes == active_pipes) {
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
total: 0 errors, 1 warnings, 17 checks, 319 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Enable second DBuf slice for ICL and TGL
@ 2019-11-26 20:12 ` Patchwork
0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-26 20:12 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f1c5115b93c7 drm/i915: Remove skl_ddl_allocation struct
03280b410f87 drm/i915: Move dbuf slice update to proper place
a778a20b2642 drm/i915: Manipulate DBuf slices properly
f799788524b4 drm/i915: Correctly map DBUF slices to pipes
-:210: CHECK:LINE_SPACING: Please don't use multiple blank lines
#210: FILE: drivers/gpu/drm/i915/intel_pm.c:4179:
+
-:216: CHECK:LINE_SPACING: Please don't use multiple blank lines
#216: FILE: drivers/gpu/drm/i915/intel_pm.c:4185:
+
+
-:235: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#235: FILE: drivers/gpu/drm/i915/intel_pm.c:4204:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S1_BIT, DBUF_S2_BIT, 0, 0),
-:237: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#237: FILE: drivers/gpu/drm/i915/intel_pm.c:4206:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
-:239: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#239: FILE: drivers/gpu/drm/i915/intel_pm.c:4208:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C), 0,
+ DBUF_S1_BIT, DBUF_S2_BIT, 0),
-:241: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#241: FILE: drivers/gpu/drm/i915/intel_pm.c:4210:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0)
-:260: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#260: FILE: drivers/gpu/drm/i915/intel_pm.c:4229:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B),
+ DBUF_S2_BIT, DBUF_S1_BIT, 0, 0),
-:262: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#262: FILE: drivers/gpu/drm/i915/intel_pm.c:4231:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, 0),
-:264: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#264: FILE: drivers/gpu/drm/i915/intel_pm.c:4233:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, 0, DBUF_S2_BIT),
-:266: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#266: FILE: drivers/gpu/drm/i915/intel_pm.c:4235:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, 0),
-:268: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#268: FILE: drivers/gpu/drm/i915/intel_pm.c:4237:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, 0, DBUF_S2_BIT),
-:270: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#270: FILE: drivers/gpu/drm/i915/intel_pm.c:4239:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
-:272: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#272: FILE: drivers/gpu/drm/i915/intel_pm.c:4241:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_C) | BIT(PIPE_D),
+ 0, 0, DBUF_S1_BIT, DBUF_S2_BIT),
-:274: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#274: FILE: drivers/gpu/drm/i915/intel_pm.c:4243:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C),
+ DBUF_S1_BIT, DBUF_S1_BIT, DBUF_S2_BIT, 0),
-:276: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#276: FILE: drivers/gpu/drm/i915/intel_pm.c:4245:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_D),
+ DBUF_S1_BIT, DBUF_S1_BIT, 0, DBUF_S2_BIT),
-:278: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#278: FILE: drivers/gpu/drm/i915/intel_pm.c:4247:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_A) | BIT(PIPE_C) | BIT(PIPE_D),
+ DBUF_S1_BIT, 0, DBUF_S2_BIT, DBUF_S2_BIT),
-:280: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#280: FILE: drivers/gpu/drm/i915/intel_pm.c:4249:
+ DBUF_TO_4_PIPES_MAP(BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D),
+ 0, DBUF_S1_BIT, DBUF_S2_BIT, DBUF_S2_BIT)
-:291: WARNING:BRACES: braces {} are not necessary for single statement blocks
#291: FILE: drivers/gpu/drm/i915/intel_pm.c:4260:
+ if (dbuf_slices[i].active_pipes == active_pipes) {
+ return dbuf_slices[i].dbuf_mask[pipe];
+ }
total: 0 errors, 1 warnings, 17 checks, 319 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.SPARSE: warning for Enable second DBuf slice for ICL and TGL
@ 2019-11-26 20:14 ` Patchwork
0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-26 20:14 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Remove skl_ddl_allocation struct
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Enable second DBuf slice for ICL and TGL
@ 2019-11-26 20:14 ` Patchwork
0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-26 20:14 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.6.0
Commit: drm/i915: Remove skl_ddl_allocation struct
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL
@ 2019-11-26 20:36 ` Patchwork
0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-26 20:36 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15441
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15441 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15441, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15441:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_execlists:
- fi-kbl-r: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-r/igt@i915_selftest@live_execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-r/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-6770hq: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-7500u: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
* igt@runner@aborted:
- fi-kbl-r: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-r/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_15441 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-hsw-peppy: [PASS][8] -> [DMESG-FAIL][9] ([fdo#112147])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-hsw-peppy/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111407])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][12] ([fdo#111735]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-tgl-u/igt@gem_ctx_create@basic-files.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-tgl-u/igt@gem_ctx_create@basic-files.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [INCOMPLETE][14] ([fdo#109964] / [fdo#112298]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][16] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][17] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +4 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][18] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][19] ([fdo#103558] / [fdo#105602]) +10 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
[fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298
Participating hosts (49 -> 44)
------------------------------
Additional (1): fi-whl-u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7426 -> Patchwork_15441
CI-20190529: 20190529
CI_DRM_7426: b204d72d3485a148456e2077683974739b675b21 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5310: d1ea62b3f759f10ff6860561ba82e5c4902511d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15441: f799788524b4cb3c48d1c4a99b81e9702b7e4f58 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f799788524b4 drm/i915: Correctly map DBUF slices to pipes
a778a20b2642 drm/i915: Manipulate DBuf slices properly
03280b410f87 drm/i915: Move dbuf slice update to proper place
f1c5115b93c7 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for Enable second DBuf slice for ICL and TGL
@ 2019-11-26 20:36 ` Patchwork
0 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2019-11-26 20:36 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: Enable second DBuf slice for ICL and TGL
URL : https://patchwork.freedesktop.org/series/70059/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7426 -> Patchwork_15441
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_15441 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_15441, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15441:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_execlists:
- fi-kbl-r: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-r/igt@i915_selftest@live_execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-r/igt@i915_selftest@live_execlists.html
* igt@i915_selftest@live_gem_contexts:
- fi-skl-6770hq: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-skl-6770hq/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-7500u: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
* igt@runner@aborted:
- fi-kbl-r: NOTRUN -> [FAIL][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-r/igt@runner@aborted.html
Known issues
------------
Here are the changes found in Patchwork_15441 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-hsw-peppy: [PASS][8] -> [DMESG-FAIL][9] ([fdo#112147])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-hsw-peppy/igt@i915_selftest@live_blt.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-hsw-peppy/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [PASS][10] -> [FAIL][11] ([fdo#111407])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-u}: [INCOMPLETE][12] ([fdo#111735]) -> [PASS][13]
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-tgl-u/igt@gem_ctx_create@basic-files.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-tgl-u/igt@gem_ctx_create@basic-files.html
* igt@i915_module_load@reload-with-fault-injection:
- {fi-kbl-7560u}: [INCOMPLETE][14] ([fdo#109964] / [fdo#112298]) -> [PASS][15]
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-7560u/igt@i915_module_load@reload-with-fault-injection.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s0:
- fi-kbl-x1275: [DMESG-WARN][16] ([fdo#103558] / [fdo#105602]) -> [DMESG-WARN][17] ([fdo#103558] / [fdo#105602] / [fdo#105763]) +4 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-x1275/igt@gem_exec_suspend@basic-s0.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-kbl-x1275: [DMESG-WARN][18] ([fdo#103558] / [fdo#105602] / [fdo#105763]) -> [DMESG-WARN][19] ([fdo#103558] / [fdo#105602]) +10 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7426/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103558]: https://bugs.freedesktop.org/show_bug.cgi?id=103558
[fdo#105602]: https://bugs.freedesktop.org/show_bug.cgi?id=105602
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#109964]: https://bugs.freedesktop.org/show_bug.cgi?id=109964
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#112147]: https://bugs.freedesktop.org/show_bug.cgi?id=112147
[fdo#112298]: https://bugs.freedesktop.org/show_bug.cgi?id=112298
Participating hosts (49 -> 44)
------------------------------
Additional (1): fi-whl-u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7426 -> Patchwork_15441
CI-20190529: 20190529
CI_DRM_7426: b204d72d3485a148456e2077683974739b675b21 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5310: d1ea62b3f759f10ff6860561ba82e5c4902511d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15441: f799788524b4cb3c48d1c4a99b81e9702b7e4f58 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f799788524b4 drm/i915: Correctly map DBUF slices to pipes
a778a20b2642 drm/i915: Manipulate DBuf slices properly
03280b410f87 drm/i915: Move dbuf slice update to proper place
f1c5115b93c7 drm/i915: Remove skl_ddl_allocation struct
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15441/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2019-11-26 20:36 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-11-26 16:28 [PATCH v5 0/4] Enable second DBuf slice for ICL and TGL Stanislav Lisovskiy
2019-11-26 16:28 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-26 16:28 ` [PATCH v5 1/4] drm/i915: Remove skl_ddl_allocation struct Stanislav Lisovskiy
2019-11-26 16:28 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-26 16:28 ` [PATCH v5 2/4] drm/i915: Move dbuf slice update to proper place Stanislav Lisovskiy
2019-11-26 16:28 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-26 16:28 ` [PATCH v5 3/4] drm/i915: Manipulate DBuf slices properly Stanislav Lisovskiy
2019-11-26 16:28 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-26 16:28 ` [PATCH v5 4/4] drm/i915: Correctly map DBUF slices to pipes Stanislav Lisovskiy
2019-11-26 16:28 ` [Intel-gfx] " Stanislav Lisovskiy
2019-11-26 20:12 ` ✗ Fi.CI.CHECKPATCH: warning for Enable second DBuf slice for ICL and TGL Patchwork
2019-11-26 20:12 ` [Intel-gfx] " Patchwork
2019-11-26 20:14 ` ✗ Fi.CI.SPARSE: " Patchwork
2019-11-26 20:14 ` [Intel-gfx] " Patchwork
2019-11-26 20:36 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-11-26 20:36 ` [Intel-gfx] " Patchwork
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