* [Intel-gfx] [PATCH 0/2] Some debugfs enhancements
@ 2019-12-09 22:35 Andi Shyti
2019-12-09 22:35 ` [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers Andi Shyti
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Andi Shyti @ 2019-12-09 22:35 UTC (permalink / raw)
To: Intel GFX
From: Andi Shyti <andi.shyti@intel.com>
Hi,
this two patches are few debugfs improvements. The first adds
some helpers for reading the GT frequency, while the second patch
moves all the power management debufs functions into gt/
Thanks,
Andi
Andi Shyti (2):
drm/i915/rps: Add frequency translation helpers
drm/i915/gt: Move power management debugfs files into gt
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 593 +++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 14 +
drivers/gpu/drm/i915/gt/intel_rps.c | 22 +
drivers/gpu/drm/i915/gt/intel_rps.h | 2 +
drivers/gpu/drm/i915/i915_debugfs.c | 596 +-----------------
drivers/gpu/drm/i915/i915_debugfs.h | 9 +
drivers/gpu/drm/i915/i915_sysfs.c | 14 +-
8 files changed, 652 insertions(+), 599 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
--
2.24.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers
2019-12-09 22:35 [Intel-gfx] [PATCH 0/2] Some debugfs enhancements Andi Shyti
@ 2019-12-09 22:35 ` Andi Shyti
2019-12-09 23:25 ` Chris Wilson
2019-12-09 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt Andi Shyti
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Andi Shyti @ 2019-12-09 22:35 UTC (permalink / raw)
To: Intel GFX
From: Andi Shyti <andi.shyti@intel.com>
Add two helpers that for reading the actual GT's frequency. The
two helpers are:
- intel_cagf_read: reads the frequency and returns it not
normalized
- intel_cagf_freq_read: provides the frequency in Hz.
Use the above helpers in sysfs and debugfs.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
drivers/gpu/drm/i915/gt/intel_rps.c | 22 ++++++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++----------------
drivers/gpu/drm/i915/i915_sysfs.c | 14 ++------------
4 files changed, 31 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 08a38a3b90b0..72c3dd976e32 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -1682,6 +1682,28 @@ u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat)
return cagf;
}
+u32 intel_cagf_read(struct intel_rps *rps)
+{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
+ u32 freq;
+
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ vlv_punit_get(i915);
+ freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(i915);
+
+ return (freq >> 8) & 0xff;
+ }
+
+ return intel_get_cagf(rps, intel_uncore_read(rps_to_gt(rps)->uncore,
+ GEN6_RPSTAT1));
+}
+
+u32 intel_cagf_freq_read(struct intel_rps *rps)
+{
+ return intel_gpu_freq(rps, intel_cagf_read(rps));
+}
+
/* External interface for intel_ips.ko */
static struct drm_i915_private __rcu *ips_mchdev;
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.h b/drivers/gpu/drm/i915/gt/intel_rps.h
index 9518c66c9792..338f8924cd0f 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.h
+++ b/drivers/gpu/drm/i915/gt/intel_rps.h
@@ -30,6 +30,8 @@ void intel_rps_mark_interactive(struct intel_rps *rps, bool interactive);
int intel_gpu_freq(struct intel_rps *rps, int val);
int intel_freq_opcode(struct intel_rps *rps, int val);
u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat1);
+u32 intel_cagf_read(struct intel_rps *rps);
+u32 intel_cagf_freq_read(struct intel_rps *rps);
void gen5_rps_irq_handler(struct intel_rps *rps);
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir);
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 6cb149ba1905..396c8427c156 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -881,7 +881,7 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
- cagf = intel_gpu_freq(rps, intel_get_cagf(rps, rpstat));
+ cagf = intel_cagf_freq_read(rps);
intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
@@ -1623,21 +1623,11 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
struct intel_rps *rps = &dev_priv->gt.rps;
- u32 act_freq = rps->cur_freq;
+ u32 act_freq;
intel_wakeref_t wakeref;
- with_intel_runtime_pm_if_in_use(&dev_priv->runtime_pm, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_punit_get(dev_priv);
- act_freq = vlv_punit_read(dev_priv,
- PUNIT_REG_GPU_FREQ_STS);
- vlv_punit_put(dev_priv);
- act_freq = (act_freq >> 8) & 0xff;
- } else {
- act_freq = intel_get_cagf(rps,
- I915_READ(GEN6_RPSTAT1));
- }
- }
+ with_intel_runtime_pm_if_in_use(&dev_priv->runtime_pm, wakeref)
+ act_freq = intel_cagf_freq_read(rps);
seq_printf(m, "RPS enabled? %d\n", rps->enabled);
seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
@@ -1645,8 +1635,7 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
atomic_read(&rps->num_waiters));
seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
seq_printf(m, "Frequency requested %d, actual %d\n",
- intel_gpu_freq(rps, rps->cur_freq),
- intel_gpu_freq(rps, act_freq));
+ intel_gpu_freq(rps, rps->cur_freq), act_freq);
seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
intel_gpu_freq(rps, rps->min_freq),
intel_gpu_freq(rps, rps->min_freq_softlimit),
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 65476909d1bf..176cdb139f0b 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -265,20 +265,10 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
u32 freq;
wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
-
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- vlv_punit_get(dev_priv);
- freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- vlv_punit_put(dev_priv);
-
- freq = (freq >> 8) & 0xff;
- } else {
- freq = intel_get_cagf(rps, I915_READ(GEN6_RPSTAT1));
- }
-
+ freq = intel_cagf_freq_read(rps);
intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
- return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(rps, freq));
+ return snprintf(buf, PAGE_SIZE, "%d\n", freq);
}
static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
--
2.24.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt
2019-12-09 22:35 [Intel-gfx] [PATCH 0/2] Some debugfs enhancements Andi Shyti
2019-12-09 22:35 ` [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers Andi Shyti
@ 2019-12-09 22:35 ` Andi Shyti
2019-12-09 22:47 ` Chris Wilson
2019-12-09 23:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some debugfs enhancements Patchwork
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Andi Shyti @ 2019-12-09 22:35 UTC (permalink / raw)
To: Intel GFX
From: Andi Shyti <andi.shyti@intel.com>
rc6, rps and llc debugfs files are gt related, move them into the
gt directory.
Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
drivers/gpu/drm/i915/Makefile | 1 +
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c | 593 ++++++++++++++++++
drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h | 14 +
drivers/gpu/drm/i915/i915_debugfs.c | 585 +----------------
drivers/gpu/drm/i915/i915_debugfs.h | 9 +
5 files changed, 626 insertions(+), 576 deletions(-)
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
create mode 100644 drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index e0fd10c0cfb8..6d5306e8312c 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -85,6 +85,7 @@ gt-y += \
gt/intel_gt.o \
gt/intel_gt_irq.o \
gt/intel_gt_pm.o \
+ gt/intel_gt_pm_debugfs.o \
gt/intel_gt_pm_irq.o \
gt/intel_gt_requests.o \
gt/intel_llc.o \
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
new file mode 100644
index 000000000000..112a0e777d0e
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c
@@ -0,0 +1,593 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#include "i915_debugfs.h"
+#include "i915_trace.h"
+#include "intel_gt_pm_debugfs.h"
+#include "intel_rc6.h"
+#include "intel_rps.h"
+#include "intel_sideband.h"
+
+static int i915_frequency_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct intel_rps *rps = &i915->gt.rps;
+ intel_wakeref_t wakeref;
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+
+ if (IS_GEN(i915, 5)) {
+ u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
+ u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
+
+ seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
+ seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
+ seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
+ MEMSTAT_VID_SHIFT);
+ seq_printf(m, "Current P-state: %d\n",
+ (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
+ } else if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
+ u32 rpmodectl, freq_sts;
+
+ rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
+ seq_printf(m, "Video Turbo Mode: %s\n",
+ yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
+ seq_printf(m, "HW control enabled: %s\n",
+ yesno(rpmodectl & GEN6_RP_ENABLE));
+ seq_printf(m, "SW control enabled: %s\n",
+ yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
+ GEN6_RP_MEDIA_SW_MODE));
+
+ vlv_punit_get(i915);
+ freq_sts = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(i915);
+
+ seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
+ seq_printf(m, "DDR freq: %d MHz\n", i915->mem_freq);
+
+ seq_printf(m, "actual GPU freq: %d MHz\n",
+ intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
+
+ seq_printf(m, "current GPU freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->cur_freq));
+
+ seq_printf(m, "max GPU freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+
+ seq_printf(m, "min GPU freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->min_freq));
+
+ seq_printf(m, "idle GPU freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->idle_freq));
+
+ seq_printf(m, "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(rps, rps->efficient_freq));
+ } else if (INTEL_GEN(i915) >= 6) {
+ u32 rp_state_limits;
+ u32 gt_perf_status;
+ u32 rp_state_cap;
+ u32 rpmodectl, rpinclimit, rpdeclimit;
+ u32 rpstat, cagf, reqf;
+ u32 rpupei, rpcurup, rpprevup;
+ u32 rpdownei, rpcurdown, rpprevdown;
+ u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
+ int max_freq;
+
+ rp_state_limits = intel_uncore_read(uncore, GEN6_RP_STATE_LIMITS);
+ if (IS_GEN9_LP(i915)) {
+ rp_state_cap = intel_uncore_read(uncore, BXT_RP_STATE_CAP);
+ gt_perf_status = intel_uncore_read(uncore, BXT_GT_PERF_STATUS);
+ } else {
+ rp_state_cap = intel_uncore_read(uncore, GEN6_RP_STATE_CAP);
+ gt_perf_status = intel_uncore_read(uncore, GEN6_GT_PERF_STATUS);
+ }
+
+ /* RPSTAT1 is in the GT power well */
+ intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
+
+ reqf = intel_uncore_read(uncore, GEN6_RPNSWREQ);
+ if (INTEL_GEN(i915) >= 9)
+ reqf >>= 23;
+ else {
+ reqf &= ~GEN6_TURBO_DISABLE;
+ if (IS_HASWELL(i915) || IS_BROADWELL(i915))
+ reqf >>= 24;
+ else
+ reqf >>= 25;
+ }
+ reqf = intel_gpu_freq(rps, reqf);
+
+ rpmodectl = intel_uncore_read(uncore, GEN6_RP_CONTROL);
+ rpinclimit = intel_uncore_read(uncore, GEN6_RP_UP_THRESHOLD);
+ rpdeclimit = intel_uncore_read(uncore, GEN6_RP_DOWN_THRESHOLD);
+
+ rpstat = intel_uncore_read(uncore, GEN6_RPSTAT1);
+ rpupei = intel_uncore_read(uncore, GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
+ rpcurup = intel_uncore_read(uncore, GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
+ rpprevup = intel_uncore_read(uncore, GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
+ rpdownei = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
+ rpcurdown = intel_uncore_read(uncore, GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
+ rpprevdown = intel_uncore_read(uncore, GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
+ cagf = intel_cagf_freq_read(rps);
+
+ intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
+
+ if (INTEL_GEN(i915) >= 11) {
+ pm_ier = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_ENABLE);
+ pm_imr = intel_uncore_read(uncore, GEN11_GPM_WGBOXPERF_INTR_MASK);
+ /*
+ * The equivalent to the PM ISR & IIR cannot be read
+ * without affecting the current state of the system
+ */
+ pm_isr = 0;
+ pm_iir = 0;
+ } else if (INTEL_GEN(i915) >= 8) {
+ pm_ier = intel_uncore_read(uncore, GEN8_GT_IER(2));
+ pm_imr = intel_uncore_read(uncore, GEN8_GT_IMR(2));
+ pm_isr = intel_uncore_read(uncore, GEN8_GT_ISR(2));
+ pm_iir = intel_uncore_read(uncore, GEN8_GT_IIR(2));
+ } else {
+ pm_ier = intel_uncore_read(uncore, GEN6_PMIER);
+ pm_imr = intel_uncore_read(uncore, GEN6_PMIMR);
+ pm_isr = intel_uncore_read(uncore, GEN6_PMISR);
+ pm_iir = intel_uncore_read(uncore, GEN6_PMIIR);
+ }
+ pm_mask = intel_uncore_read(uncore, GEN6_PMINTRMSK);
+
+ seq_printf(m, "Video Turbo Mode: %s\n",
+ yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
+ seq_printf(m, "HW control enabled: %s\n",
+ yesno(rpmodectl & GEN6_RP_ENABLE));
+ seq_printf(m, "SW control enabled: %s\n",
+ yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
+ GEN6_RP_MEDIA_SW_MODE));
+
+ seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
+ pm_ier, pm_imr, pm_mask);
+ if (INTEL_GEN(i915) <= 10)
+ seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
+ pm_isr, pm_iir);
+ seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
+ rps->pm_intrmsk_mbz);
+ seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
+ seq_printf(m, "Render p-state ratio: %d\n",
+ (gt_perf_status & (INTEL_GEN(i915) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
+ seq_printf(m, "Render p-state VID: %d\n",
+ gt_perf_status & 0xff);
+ seq_printf(m, "Render p-state limit: %d\n",
+ rp_state_limits & 0xff);
+ seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
+ seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
+ seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
+ seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
+ seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
+ seq_printf(m, "CAGF: %dMHz\n", cagf);
+ seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
+ rpupei, GT_PM_INTERVAL_TO_US(i915, rpupei));
+ seq_printf(m, "RP CUR UP: %d (%dus)\n",
+ rpcurup, GT_PM_INTERVAL_TO_US(i915, rpcurup));
+ seq_printf(m, "RP PREV UP: %d (%dus)\n",
+ rpprevup, GT_PM_INTERVAL_TO_US(i915, rpprevup));
+ seq_printf(m, "Up threshold: %d%%\n",
+ rps->power.up_threshold);
+
+ seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
+ rpdownei, GT_PM_INTERVAL_TO_US(i915, rpdownei));
+ seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
+ rpcurdown, GT_PM_INTERVAL_TO_US(i915, rpcurdown));
+ seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
+ rpprevdown, GT_PM_INTERVAL_TO_US(i915, rpprevdown));
+ seq_printf(m, "Down threshold: %d%%\n",
+ rps->power.down_threshold);
+
+ max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 0 :
+ rp_state_cap >> 16) & 0xff;
+ max_freq *= (IS_GEN9_BC(i915) ||
+ INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+ seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
+ intel_gpu_freq(rps, max_freq));
+
+ max_freq = (rp_state_cap & 0xff00) >> 8;
+ max_freq *= (IS_GEN9_BC(i915) ||
+ INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+ seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
+ intel_gpu_freq(rps, max_freq));
+
+ max_freq = (IS_GEN9_LP(i915) ? rp_state_cap >> 16 :
+ rp_state_cap >> 0) & 0xff;
+ max_freq *= (IS_GEN9_BC(i915) ||
+ INTEL_GEN(i915) >= 10 ? GEN9_FREQ_SCALER : 1);
+ seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
+ intel_gpu_freq(rps, max_freq));
+ seq_printf(m, "Max overclocked frequency: %dMHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+
+ seq_printf(m, "Current freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->cur_freq));
+ seq_printf(m, "Actual freq: %d MHz\n", cagf);
+ seq_printf(m, "Idle freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->idle_freq));
+ seq_printf(m, "Min freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->min_freq));
+ seq_printf(m, "Boost freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->boost_freq));
+ seq_printf(m, "Max freq: %d MHz\n",
+ intel_gpu_freq(rps, rps->max_freq));
+ seq_printf(m,
+ "efficient (RPe) frequency: %d MHz\n",
+ intel_gpu_freq(rps, rps->efficient_freq));
+ } else {
+ seq_puts(m, "no P-state info available\n");
+ }
+
+ seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->cdclk.hw.cdclk);
+ seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->max_cdclk_freq);
+ seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
+
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return 0;
+}
+
+static int i915_ring_freq_table(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_rps *rps = &i915->gt.rps;
+ unsigned int max_gpu_freq, min_gpu_freq;
+ intel_wakeref_t wakeref;
+ int gpu_freq, ia_freq;
+
+ if (!HAS_LLC(i915))
+ return -ENODEV;
+
+ min_gpu_freq = rps->min_freq;
+ max_gpu_freq = rps->max_freq;
+ if (IS_GEN9_BC(i915) || INTEL_GEN(i915) >= 10) {
+ /* Convert GT frequency to 50 HZ units */
+ min_gpu_freq /= GEN9_FREQ_SCALER;
+ max_gpu_freq /= GEN9_FREQ_SCALER;
+ }
+
+ seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
+
+ wakeref = intel_runtime_pm_get(&i915->runtime_pm);
+ for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
+ ia_freq = gpu_freq;
+ sandybridge_pcode_read(i915,
+ GEN6_PCODE_READ_MIN_FREQ_TABLE,
+ &ia_freq, NULL);
+ seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
+ intel_gpu_freq(rps,
+ (gpu_freq *
+ (IS_GEN9_BC(i915) ||
+ INTEL_GEN(i915) >= 10 ?
+ GEN9_FREQ_SCALER : 1))),
+ ((ia_freq >> 0) & 0xff) * 100,
+ ((ia_freq >> 8) & 0xff) * 100);
+ }
+ intel_runtime_pm_put(&i915->runtime_pm, wakeref);
+
+ return 0;
+}
+
+static const char *rps_power_to_str(unsigned int power)
+{
+ static const char * const strings[] = {
+ [LOW_POWER] = "low power",
+ [BETWEEN] = "mixed",
+ [HIGH_POWER] = "high power",
+ };
+
+ if (power >= ARRAY_SIZE(strings) || !strings[power])
+ return "unknown";
+
+ return strings[power];
+}
+
+static int i915_rps_boost_info(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct intel_rps *rps = &i915->gt.rps;
+ u32 act_freq;
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm_if_in_use(&i915->runtime_pm, wakeref)
+ act_freq = intel_cagf_freq_read(rps);
+
+ seq_printf(m, "RPS enabled? %d\n", rps->enabled);
+ seq_printf(m, "GPU busy? %s\n", yesno(i915->gt.awake));
+ seq_printf(m, "Boosts outstanding? %d\n",
+ atomic_read(&rps->num_waiters));
+ seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
+ seq_printf(m, "Frequency requested %d, actual %d\n",
+ intel_gpu_freq(rps, rps->cur_freq), act_freq);
+ seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
+ intel_gpu_freq(rps, rps->min_freq),
+ intel_gpu_freq(rps, rps->min_freq_softlimit),
+ intel_gpu_freq(rps, rps->max_freq_softlimit),
+ intel_gpu_freq(rps, rps->max_freq));
+ seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
+ intel_gpu_freq(rps, rps->idle_freq),
+ intel_gpu_freq(rps, rps->efficient_freq),
+ intel_gpu_freq(rps, rps->boost_freq));
+
+ seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));
+
+ if (INTEL_GEN(i915) >= 6 && rps->enabled && i915->gt.awake) {
+ u32 rpup, rpupei;
+ u32 rpdown, rpdownei;
+
+ intel_uncore_forcewake_get(&i915->uncore, FORCEWAKE_ALL);
+ rpup = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
+ rpupei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
+ rpdown = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
+ rpdownei = intel_uncore_read_fw(uncore, GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
+ intel_uncore_forcewake_put(&i915->uncore, FORCEWAKE_ALL);
+
+ seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
+ rps_power_to_str(rps->power.mode));
+ seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
+ rpup && rpupei ? 100 * rpup / rpupei : 0,
+ rps->power.up_threshold);
+ seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
+ rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
+ rps->power.down_threshold);
+ } else {
+ seq_puts(m, "\nRPS Autotuning inactive\n");
+ }
+
+ return 0;
+}
+
+static int i915_forcewake_domains(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
+ struct intel_uncore_forcewake_domain *fw_domain;
+ unsigned int tmp;
+
+ seq_printf(m, "user.bypass_count = %u\n",
+ uncore->user_forcewake_count);
+
+ for_each_fw_domain(fw_domain, uncore, tmp)
+ seq_printf(m, "%s.wake_count = %u\n",
+ intel_uncore_forcewake_domain_to_str(fw_domain->id),
+ READ_ONCE(fw_domain->wake_count));
+
+ return 0;
+}
+
+static void print_rc6_res(struct seq_file *m,
+ const char *title,
+ const i915_reg_t reg)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ intel_wakeref_t wakeref;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref)
+ seq_printf(m, "%s %u (%llu us)\n", title,
+ intel_uncore_read(&i915->uncore, reg),
+ intel_rc6_residency_us(&i915->gt.rc6, reg));
+}
+
+static int vlv_drpc_info(struct seq_file *m)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 rcctl1, pw_status;
+
+ pw_status = intel_uncore_read(uncore, VLV_GTLC_PW_STATUS);
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+
+ seq_printf(m, "RC6 Enabled: %s\n",
+ yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
+ GEN6_RC_CTL_EI_MODE(1))));
+ seq_printf(m, "Render Power Well: %s\n",
+ (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
+ seq_printf(m, "Media Power Well: %s\n",
+ (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
+
+ print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
+ print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
+
+ return i915_forcewake_domains(m, NULL);
+}
+
+static int gen6_drpc_info(struct seq_file *m)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 gt_core_status, rcctl1, rc6vids = 0;
+ u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
+
+ gt_core_status = intel_uncore_read_fw(uncore, GEN6_GT_CORE_STATUS);
+ trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
+
+ rcctl1 = intel_uncore_read(uncore, GEN6_RC_CONTROL);
+ if (INTEL_GEN(i915) >= 9) {
+ gen9_powergate_enable = intel_uncore_read(uncore,
+ GEN9_PG_ENABLE);
+ gen9_powergate_status = intel_uncore_read(uncore,
+ GEN9_PWRGT_DOMAIN_STATUS);
+ }
+
+ if (INTEL_GEN(i915) <= 7)
+ sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
+ &rc6vids, NULL);
+
+ seq_printf(m, "RC1e Enabled: %s\n",
+ yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
+ seq_printf(m, "RC6 Enabled: %s\n",
+ yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
+ if (INTEL_GEN(i915) >= 9) {
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
+ }
+ seq_printf(m, "Deep RC6 Enabled: %s\n",
+ yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
+ seq_printf(m, "Deepest RC6 Enabled: %s\n",
+ yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
+ seq_puts(m, "Current RC state: ");
+ switch (gt_core_status & GEN6_RCn_MASK) {
+ case GEN6_RC0:
+ if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
+ seq_puts(m, "Core Power Down\n");
+ else
+ seq_puts(m, "on\n");
+ break;
+ case GEN6_RC3:
+ seq_puts(m, "RC3\n");
+ break;
+ case GEN6_RC6:
+ seq_puts(m, "RC6\n");
+ break;
+ case GEN6_RC7:
+ seq_puts(m, "RC7\n");
+ break;
+ default:
+ seq_puts(m, "Unknown\n");
+ break;
+ }
+
+ seq_printf(m, "Core Power Down: %s\n",
+ yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
+ if (INTEL_GEN(i915) >= 9) {
+ seq_printf(m, "Render Power Well: %s\n",
+ (gen9_powergate_status &
+ GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
+ seq_printf(m, "Media Power Well: %s\n",
+ (gen9_powergate_status &
+ GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
+ }
+
+ /* Not exactly sure what this is */
+ print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
+ GEN6_GT_GFX_RC6_LOCKED);
+ print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
+ print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
+ print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
+
+ if (INTEL_GEN(i915) <= 7) {
+ seq_printf(m, "RC6 voltage: %dmV\n",
+ GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
+ seq_printf(m, "RC6+ voltage: %dmV\n",
+ GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
+ seq_printf(m, "RC6++ voltage: %dmV\n",
+ GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
+ }
+
+ return i915_forcewake_domains(m, NULL);
+}
+
+static int ironlake_drpc_info(struct seq_file *m)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 rgvmodectl, rstdbyctl;
+ u16 crstandvid;
+
+ rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
+ rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);
+ crstandvid = intel_uncore_read16(uncore, CRSTANDVID);
+
+ seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
+ seq_printf(m, "Boost freq: %d\n",
+ (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
+ MEMMODE_BOOST_FREQ_SHIFT);
+ seq_printf(m, "HW control enabled: %s\n",
+ yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
+ seq_printf(m, "SW control enabled: %s\n",
+ yesno(rgvmodectl & MEMMODE_SWMODE_EN));
+ seq_printf(m, "Gated voltage change: %s\n",
+ yesno(rgvmodectl & MEMMODE_RCLK_GATE));
+ seq_printf(m, "Starting frequency: P%d\n",
+ (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
+ seq_printf(m, "Max P-state: P%d\n",
+ (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
+ seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
+ seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
+ seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
+ seq_printf(m, "Render standby enabled: %s\n",
+ yesno(!(rstdbyctl & RCX_SW_EXIT)));
+ seq_puts(m, "Current RS state: ");
+ switch (rstdbyctl & RSX_STATUS_MASK) {
+ case RSX_STATUS_ON:
+ seq_puts(m, "on\n");
+ break;
+ case RSX_STATUS_RC1:
+ seq_puts(m, "RC1\n");
+ break;
+ case RSX_STATUS_RC1E:
+ seq_puts(m, "RC1E\n");
+ break;
+ case RSX_STATUS_RS1:
+ seq_puts(m, "RS1\n");
+ break;
+ case RSX_STATUS_RS2:
+ seq_puts(m, "RS2 (RC6)\n");
+ break;
+ case RSX_STATUS_RS3:
+ seq_puts(m, "RC3 (RC6+)\n");
+ break;
+ default:
+ seq_puts(m, "unknown\n");
+ break;
+ }
+
+ return 0;
+}
+
+static int i915_drpc_info(struct seq_file *m, void *unused)
+{
+ struct drm_i915_private *i915 = node_to_i915(m->private);
+ intel_wakeref_t wakeref;
+ int err = -ENODEV;
+
+ with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
+ if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
+ err = vlv_drpc_info(m);
+ else if (INTEL_GEN(i915) >= 6)
+ err = gen6_drpc_info(m);
+ else
+ err = ironlake_drpc_info(m);
+ }
+
+ return err;
+}
+
+static int i915_llc(struct seq_file *m, void *data)
+{
+ struct drm_i915_private *dev_priv = node_to_i915(m->private);
+ const bool edram = INTEL_GEN(dev_priv) > 8;
+
+ seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
+ seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
+ dev_priv->edram_size_mb);
+
+ return 0;
+}
+
+static const struct drm_info_list i915_gt_pm_debugfs_list[] = {
+ {"i915_frequency_info", i915_frequency_info, 0},
+ {"i915_ring_freq_table", i915_ring_freq_table, 0},
+ {"i915_rps_boost_info", i915_rps_boost_info, 0},
+ {"i915_forcewake_domains", i915_forcewake_domains, 0},
+ {"i915_drpc_info", i915_drpc_info, 0},
+ {"i915_llc", i915_llc, 0},
+};
+
+int intel_gt_pm_debugfs_register(struct intel_gt *gt)
+{
+ struct drm_minor *minor = gt->i915->drm.primary;
+
+ return drm_debugfs_create_files(i915_gt_pm_debugfs_list,
+ ARRAY_SIZE(i915_gt_pm_debugfs_list),
+ minor->debugfs_root, minor);
+}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
new file mode 100644
index 000000000000..49187e777421
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h
@@ -0,0 +1,14 @@
+/*
+ * SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2019 Intel Corporation
+ */
+
+#ifndef INTEL_RPS_DEBUG_H
+#define INTEL_RPS_DEBUG_H
+
+#include <linux/seq_file.h>
+
+int intel_gt_pm_debugfs_register(struct intel_gt *gt);
+
+#endif /* INTEL_RPS_DEBUG_H */
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 396c8427c156..ef3ae2255346 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -29,7 +29,6 @@
#include <linux/sched/mm.h>
#include <linux/sort.h>
-#include <drm/drm_debugfs.h>
#include <drm/drm_fourcc.h>
#include "display/intel_display_types.h"
@@ -41,10 +40,9 @@
#include "gem/i915_gem_context.h"
#include "gt/intel_gt_pm.h"
+#include "gt/intel_gt_pm_debugfs.h"
#include "gt/intel_gt_requests.h"
#include "gt/intel_reset.h"
-#include "gt/intel_rc6.h"
-#include "gt/intel_rps.h"
#include "gt/uc/intel_guc_submission.h"
#include "i915_debugfs.h"
@@ -54,11 +52,6 @@
#include "intel_pm.h"
#include "intel_sideband.h"
-static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
-{
- return to_i915(node->minor->dev);
-}
-
static int i915_capabilities(struct seq_file *m, void *data)
{
struct drm_i915_private *i915 = node_to_i915(m->private);
@@ -778,443 +771,6 @@ static const struct file_operations i915_error_state_fops = {
};
#endif
-static int i915_frequency_info(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_uncore *uncore = &dev_priv->uncore;
- struct intel_rps *rps = &dev_priv->gt.rps;
- intel_wakeref_t wakeref;
- int ret = 0;
-
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
-
- if (IS_GEN(dev_priv, 5)) {
- u16 rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
- u16 rgvstat = intel_uncore_read16(uncore, MEMSTAT_ILK);
-
- seq_printf(m, "Requested P-state: %d\n", (rgvswctl >> 8) & 0xf);
- seq_printf(m, "Requested VID: %d\n", rgvswctl & 0x3f);
- seq_printf(m, "Current VID: %d\n", (rgvstat & MEMSTAT_VID_MASK) >>
- MEMSTAT_VID_SHIFT);
- seq_printf(m, "Current P-state: %d\n",
- (rgvstat & MEMSTAT_PSTATE_MASK) >> MEMSTAT_PSTATE_SHIFT);
- } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- u32 rpmodectl, freq_sts;
-
- rpmodectl = I915_READ(GEN6_RP_CONTROL);
- seq_printf(m, "Video Turbo Mode: %s\n",
- yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
- seq_printf(m, "HW control enabled: %s\n",
- yesno(rpmodectl & GEN6_RP_ENABLE));
- seq_printf(m, "SW control enabled: %s\n",
- yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
- GEN6_RP_MEDIA_SW_MODE));
-
- vlv_punit_get(dev_priv);
- freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- vlv_punit_put(dev_priv);
-
- seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
- seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
-
- seq_printf(m, "actual GPU freq: %d MHz\n",
- intel_gpu_freq(rps, (freq_sts >> 8) & 0xff));
-
- seq_printf(m, "current GPU freq: %d MHz\n",
- intel_gpu_freq(rps, rps->cur_freq));
-
- seq_printf(m, "max GPU freq: %d MHz\n",
- intel_gpu_freq(rps, rps->max_freq));
-
- seq_printf(m, "min GPU freq: %d MHz\n",
- intel_gpu_freq(rps, rps->min_freq));
-
- seq_printf(m, "idle GPU freq: %d MHz\n",
- intel_gpu_freq(rps, rps->idle_freq));
-
- seq_printf(m,
- "efficient (RPe) frequency: %d MHz\n",
- intel_gpu_freq(rps, rps->efficient_freq));
- } else if (INTEL_GEN(dev_priv) >= 6) {
- u32 rp_state_limits;
- u32 gt_perf_status;
- u32 rp_state_cap;
- u32 rpmodectl, rpinclimit, rpdeclimit;
- u32 rpstat, cagf, reqf;
- u32 rpupei, rpcurup, rpprevup;
- u32 rpdownei, rpcurdown, rpprevdown;
- u32 pm_ier, pm_imr, pm_isr, pm_iir, pm_mask;
- int max_freq;
-
- rp_state_limits = I915_READ(GEN6_RP_STATE_LIMITS);
- if (IS_GEN9_LP(dev_priv)) {
- rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
- gt_perf_status = I915_READ(BXT_GT_PERF_STATUS);
- } else {
- rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
- gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
- }
-
- /* RPSTAT1 is in the GT power well */
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
-
- reqf = I915_READ(GEN6_RPNSWREQ);
- if (INTEL_GEN(dev_priv) >= 9)
- reqf >>= 23;
- else {
- reqf &= ~GEN6_TURBO_DISABLE;
- if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
- reqf >>= 24;
- else
- reqf >>= 25;
- }
- reqf = intel_gpu_freq(rps, reqf);
-
- rpmodectl = I915_READ(GEN6_RP_CONTROL);
- rpinclimit = I915_READ(GEN6_RP_UP_THRESHOLD);
- rpdeclimit = I915_READ(GEN6_RP_DOWN_THRESHOLD);
-
- rpstat = I915_READ(GEN6_RPSTAT1);
- rpupei = I915_READ(GEN6_RP_CUR_UP_EI) & GEN6_CURICONT_MASK;
- rpcurup = I915_READ(GEN6_RP_CUR_UP) & GEN6_CURBSYTAVG_MASK;
- rpprevup = I915_READ(GEN6_RP_PREV_UP) & GEN6_CURBSYTAVG_MASK;
- rpdownei = I915_READ(GEN6_RP_CUR_DOWN_EI) & GEN6_CURIAVG_MASK;
- rpcurdown = I915_READ(GEN6_RP_CUR_DOWN) & GEN6_CURBSYTAVG_MASK;
- rpprevdown = I915_READ(GEN6_RP_PREV_DOWN) & GEN6_CURBSYTAVG_MASK;
- cagf = intel_cagf_freq_read(rps);
-
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
-
- if (INTEL_GEN(dev_priv) >= 11) {
- pm_ier = I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE);
- pm_imr = I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK);
- /*
- * The equivalent to the PM ISR & IIR cannot be read
- * without affecting the current state of the system
- */
- pm_isr = 0;
- pm_iir = 0;
- } else if (INTEL_GEN(dev_priv) >= 8) {
- pm_ier = I915_READ(GEN8_GT_IER(2));
- pm_imr = I915_READ(GEN8_GT_IMR(2));
- pm_isr = I915_READ(GEN8_GT_ISR(2));
- pm_iir = I915_READ(GEN8_GT_IIR(2));
- } else {
- pm_ier = I915_READ(GEN6_PMIER);
- pm_imr = I915_READ(GEN6_PMIMR);
- pm_isr = I915_READ(GEN6_PMISR);
- pm_iir = I915_READ(GEN6_PMIIR);
- }
- pm_mask = I915_READ(GEN6_PMINTRMSK);
-
- seq_printf(m, "Video Turbo Mode: %s\n",
- yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
- seq_printf(m, "HW control enabled: %s\n",
- yesno(rpmodectl & GEN6_RP_ENABLE));
- seq_printf(m, "SW control enabled: %s\n",
- yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
- GEN6_RP_MEDIA_SW_MODE));
-
- seq_printf(m, "PM IER=0x%08x IMR=0x%08x, MASK=0x%08x\n",
- pm_ier, pm_imr, pm_mask);
- if (INTEL_GEN(dev_priv) <= 10)
- seq_printf(m, "PM ISR=0x%08x IIR=0x%08x\n",
- pm_isr, pm_iir);
- seq_printf(m, "pm_intrmsk_mbz: 0x%08x\n",
- rps->pm_intrmsk_mbz);
- seq_printf(m, "GT_PERF_STATUS: 0x%08x\n", gt_perf_status);
- seq_printf(m, "Render p-state ratio: %d\n",
- (gt_perf_status & (INTEL_GEN(dev_priv) >= 9 ? 0x1ff00 : 0xff00)) >> 8);
- seq_printf(m, "Render p-state VID: %d\n",
- gt_perf_status & 0xff);
- seq_printf(m, "Render p-state limit: %d\n",
- rp_state_limits & 0xff);
- seq_printf(m, "RPSTAT1: 0x%08x\n", rpstat);
- seq_printf(m, "RPMODECTL: 0x%08x\n", rpmodectl);
- seq_printf(m, "RPINCLIMIT: 0x%08x\n", rpinclimit);
- seq_printf(m, "RPDECLIMIT: 0x%08x\n", rpdeclimit);
- seq_printf(m, "RPNSWREQ: %dMHz\n", reqf);
- seq_printf(m, "CAGF: %dMHz\n", cagf);
- seq_printf(m, "RP CUR UP EI: %d (%dus)\n",
- rpupei, GT_PM_INTERVAL_TO_US(dev_priv, rpupei));
- seq_printf(m, "RP CUR UP: %d (%dus)\n",
- rpcurup, GT_PM_INTERVAL_TO_US(dev_priv, rpcurup));
- seq_printf(m, "RP PREV UP: %d (%dus)\n",
- rpprevup, GT_PM_INTERVAL_TO_US(dev_priv, rpprevup));
- seq_printf(m, "Up threshold: %d%%\n",
- rps->power.up_threshold);
-
- seq_printf(m, "RP CUR DOWN EI: %d (%dus)\n",
- rpdownei, GT_PM_INTERVAL_TO_US(dev_priv, rpdownei));
- seq_printf(m, "RP CUR DOWN: %d (%dus)\n",
- rpcurdown, GT_PM_INTERVAL_TO_US(dev_priv, rpcurdown));
- seq_printf(m, "RP PREV DOWN: %d (%dus)\n",
- rpprevdown, GT_PM_INTERVAL_TO_US(dev_priv, rpprevdown));
- seq_printf(m, "Down threshold: %d%%\n",
- rps->power.down_threshold);
-
- max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 0 :
- rp_state_cap >> 16) & 0xff;
- max_freq *= (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
- seq_printf(m, "Lowest (RPN) frequency: %dMHz\n",
- intel_gpu_freq(rps, max_freq));
-
- max_freq = (rp_state_cap & 0xff00) >> 8;
- max_freq *= (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
- seq_printf(m, "Nominal (RP1) frequency: %dMHz\n",
- intel_gpu_freq(rps, max_freq));
-
- max_freq = (IS_GEN9_LP(dev_priv) ? rp_state_cap >> 16 :
- rp_state_cap >> 0) & 0xff;
- max_freq *= (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ? GEN9_FREQ_SCALER : 1);
- seq_printf(m, "Max non-overclocked (RP0) frequency: %dMHz\n",
- intel_gpu_freq(rps, max_freq));
- seq_printf(m, "Max overclocked frequency: %dMHz\n",
- intel_gpu_freq(rps, rps->max_freq));
-
- seq_printf(m, "Current freq: %d MHz\n",
- intel_gpu_freq(rps, rps->cur_freq));
- seq_printf(m, "Actual freq: %d MHz\n", cagf);
- seq_printf(m, "Idle freq: %d MHz\n",
- intel_gpu_freq(rps, rps->idle_freq));
- seq_printf(m, "Min freq: %d MHz\n",
- intel_gpu_freq(rps, rps->min_freq));
- seq_printf(m, "Boost freq: %d MHz\n",
- intel_gpu_freq(rps, rps->boost_freq));
- seq_printf(m, "Max freq: %d MHz\n",
- intel_gpu_freq(rps, rps->max_freq));
- seq_printf(m,
- "efficient (RPe) frequency: %d MHz\n",
- intel_gpu_freq(rps, rps->efficient_freq));
- } else {
- seq_puts(m, "no P-state info available\n");
- }
-
- seq_printf(m, "Current CD clock frequency: %d kHz\n", dev_priv->cdclk.hw.cdclk);
- seq_printf(m, "Max CD clock frequency: %d kHz\n", dev_priv->max_cdclk_freq);
- seq_printf(m, "Max pixel clock frequency: %d kHz\n", dev_priv->max_dotclk_freq);
-
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
- return ret;
-}
-
-static int ironlake_drpc_info(struct seq_file *m)
-{
- struct drm_i915_private *i915 = node_to_i915(m->private);
- struct intel_uncore *uncore = &i915->uncore;
- u32 rgvmodectl, rstdbyctl;
- u16 crstandvid;
-
- rgvmodectl = intel_uncore_read(uncore, MEMMODECTL);
- rstdbyctl = intel_uncore_read(uncore, RSTDBYCTL);
- crstandvid = intel_uncore_read16(uncore, CRSTANDVID);
-
- seq_printf(m, "HD boost: %s\n", yesno(rgvmodectl & MEMMODE_BOOST_EN));
- seq_printf(m, "Boost freq: %d\n",
- (rgvmodectl & MEMMODE_BOOST_FREQ_MASK) >>
- MEMMODE_BOOST_FREQ_SHIFT);
- seq_printf(m, "HW control enabled: %s\n",
- yesno(rgvmodectl & MEMMODE_HWIDLE_EN));
- seq_printf(m, "SW control enabled: %s\n",
- yesno(rgvmodectl & MEMMODE_SWMODE_EN));
- seq_printf(m, "Gated voltage change: %s\n",
- yesno(rgvmodectl & MEMMODE_RCLK_GATE));
- seq_printf(m, "Starting frequency: P%d\n",
- (rgvmodectl & MEMMODE_FSTART_MASK) >> MEMMODE_FSTART_SHIFT);
- seq_printf(m, "Max P-state: P%d\n",
- (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT);
- seq_printf(m, "Min P-state: P%d\n", (rgvmodectl & MEMMODE_FMIN_MASK));
- seq_printf(m, "RS1 VID: %d\n", (crstandvid & 0x3f));
- seq_printf(m, "RS2 VID: %d\n", ((crstandvid >> 8) & 0x3f));
- seq_printf(m, "Render standby enabled: %s\n",
- yesno(!(rstdbyctl & RCX_SW_EXIT)));
- seq_puts(m, "Current RS state: ");
- switch (rstdbyctl & RSX_STATUS_MASK) {
- case RSX_STATUS_ON:
- seq_puts(m, "on\n");
- break;
- case RSX_STATUS_RC1:
- seq_puts(m, "RC1\n");
- break;
- case RSX_STATUS_RC1E:
- seq_puts(m, "RC1E\n");
- break;
- case RSX_STATUS_RS1:
- seq_puts(m, "RS1\n");
- break;
- case RSX_STATUS_RS2:
- seq_puts(m, "RS2 (RC6)\n");
- break;
- case RSX_STATUS_RS3:
- seq_puts(m, "RC3 (RC6+)\n");
- break;
- default:
- seq_puts(m, "unknown\n");
- break;
- }
-
- return 0;
-}
-
-static int i915_forcewake_domains(struct seq_file *m, void *data)
-{
- struct drm_i915_private *i915 = node_to_i915(m->private);
- struct intel_uncore *uncore = &i915->uncore;
- struct intel_uncore_forcewake_domain *fw_domain;
- unsigned int tmp;
-
- seq_printf(m, "user.bypass_count = %u\n",
- uncore->user_forcewake_count);
-
- for_each_fw_domain(fw_domain, uncore, tmp)
- seq_printf(m, "%s.wake_count = %u\n",
- intel_uncore_forcewake_domain_to_str(fw_domain->id),
- READ_ONCE(fw_domain->wake_count));
-
- return 0;
-}
-
-static void print_rc6_res(struct seq_file *m,
- const char *title,
- const i915_reg_t reg)
-{
- struct drm_i915_private *i915 = node_to_i915(m->private);
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm(&i915->runtime_pm, wakeref)
- seq_printf(m, "%s %u (%llu us)\n", title,
- intel_uncore_read(&i915->uncore, reg),
- intel_rc6_residency_us(&i915->gt.rc6, reg));
-}
-
-static int vlv_drpc_info(struct seq_file *m)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- u32 rcctl1, pw_status;
-
- pw_status = I915_READ(VLV_GTLC_PW_STATUS);
- rcctl1 = I915_READ(GEN6_RC_CONTROL);
-
- seq_printf(m, "RC6 Enabled: %s\n",
- yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
- GEN6_RC_CTL_EI_MODE(1))));
- seq_printf(m, "Render Power Well: %s\n",
- (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
- seq_printf(m, "Media Power Well: %s\n",
- (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
-
- print_rc6_res(m, "Render RC6 residency since boot:", VLV_GT_RENDER_RC6);
- print_rc6_res(m, "Media RC6 residency since boot:", VLV_GT_MEDIA_RC6);
-
- return i915_forcewake_domains(m, NULL);
-}
-
-static int gen6_drpc_info(struct seq_file *m)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- u32 gt_core_status, rcctl1, rc6vids = 0;
- u32 gen9_powergate_enable = 0, gen9_powergate_status = 0;
-
- gt_core_status = I915_READ_FW(GEN6_GT_CORE_STATUS);
- trace_i915_reg_rw(false, GEN6_GT_CORE_STATUS, gt_core_status, 4, true);
-
- rcctl1 = I915_READ(GEN6_RC_CONTROL);
- if (INTEL_GEN(dev_priv) >= 9) {
- gen9_powergate_enable = I915_READ(GEN9_PG_ENABLE);
- gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
- }
-
- if (INTEL_GEN(dev_priv) <= 7)
- sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
- &rc6vids, NULL);
-
- seq_printf(m, "RC1e Enabled: %s\n",
- yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
- seq_printf(m, "RC6 Enabled: %s\n",
- yesno(rcctl1 & GEN6_RC_CTL_RC6_ENABLE));
- if (INTEL_GEN(dev_priv) >= 9) {
- seq_printf(m, "Render Well Gating Enabled: %s\n",
- yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
- seq_printf(m, "Media Well Gating Enabled: %s\n",
- yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
- }
- seq_printf(m, "Deep RC6 Enabled: %s\n",
- yesno(rcctl1 & GEN6_RC_CTL_RC6p_ENABLE));
- seq_printf(m, "Deepest RC6 Enabled: %s\n",
- yesno(rcctl1 & GEN6_RC_CTL_RC6pp_ENABLE));
- seq_puts(m, "Current RC state: ");
- switch (gt_core_status & GEN6_RCn_MASK) {
- case GEN6_RC0:
- if (gt_core_status & GEN6_CORE_CPD_STATE_MASK)
- seq_puts(m, "Core Power Down\n");
- else
- seq_puts(m, "on\n");
- break;
- case GEN6_RC3:
- seq_puts(m, "RC3\n");
- break;
- case GEN6_RC6:
- seq_puts(m, "RC6\n");
- break;
- case GEN6_RC7:
- seq_puts(m, "RC7\n");
- break;
- default:
- seq_puts(m, "Unknown\n");
- break;
- }
-
- seq_printf(m, "Core Power Down: %s\n",
- yesno(gt_core_status & GEN6_CORE_CPD_STATE_MASK));
- if (INTEL_GEN(dev_priv) >= 9) {
- seq_printf(m, "Render Power Well: %s\n",
- (gen9_powergate_status &
- GEN9_PWRGT_RENDER_STATUS_MASK) ? "Up" : "Down");
- seq_printf(m, "Media Power Well: %s\n",
- (gen9_powergate_status &
- GEN9_PWRGT_MEDIA_STATUS_MASK) ? "Up" : "Down");
- }
-
- /* Not exactly sure what this is */
- print_rc6_res(m, "RC6 \"Locked to RPn\" residency since boot:",
- GEN6_GT_GFX_RC6_LOCKED);
- print_rc6_res(m, "RC6 residency since boot:", GEN6_GT_GFX_RC6);
- print_rc6_res(m, "RC6+ residency since boot:", GEN6_GT_GFX_RC6p);
- print_rc6_res(m, "RC6++ residency since boot:", GEN6_GT_GFX_RC6pp);
-
- if (INTEL_GEN(dev_priv) <= 7) {
- seq_printf(m, "RC6 voltage: %dmV\n",
- GEN6_DECODE_RC6_VID(((rc6vids >> 0) & 0xff)));
- seq_printf(m, "RC6+ voltage: %dmV\n",
- GEN6_DECODE_RC6_VID(((rc6vids >> 8) & 0xff)));
- seq_printf(m, "RC6++ voltage: %dmV\n",
- GEN6_DECODE_RC6_VID(((rc6vids >> 16) & 0xff)));
- }
-
- return i915_forcewake_domains(m, NULL);
-}
-
-static int i915_drpc_info(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- intel_wakeref_t wakeref;
- int err = -ENODEV;
-
- with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
- if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
- err = vlv_drpc_info(m);
- else if (INTEL_GEN(dev_priv) >= 6)
- err = gen6_drpc_info(m);
- else
- err = ironlake_drpc_info(m);
- }
-
- return err;
-}
-
static int i915_frontbuffer_tracking(struct seq_file *m, void *unused)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -1362,47 +918,6 @@ static int i915_sr_status(struct seq_file *m, void *unused)
return 0;
}
-static int i915_ring_freq_table(struct seq_file *m, void *unused)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_rps *rps = &dev_priv->gt.rps;
- unsigned int max_gpu_freq, min_gpu_freq;
- intel_wakeref_t wakeref;
- int gpu_freq, ia_freq;
-
- if (!HAS_LLC(dev_priv))
- return -ENODEV;
-
- min_gpu_freq = rps->min_freq;
- max_gpu_freq = rps->max_freq;
- if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
- /* Convert GT frequency to 50 HZ units */
- min_gpu_freq /= GEN9_FREQ_SCALER;
- max_gpu_freq /= GEN9_FREQ_SCALER;
- }
-
- seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
-
- wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
- for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
- ia_freq = gpu_freq;
- sandybridge_pcode_read(dev_priv,
- GEN6_PCODE_READ_MIN_FREQ_TABLE,
- &ia_freq, NULL);
- seq_printf(m, "%d\t\t%d\t\t\t\t%d\n",
- intel_gpu_freq(rps,
- (gpu_freq *
- (IS_GEN9_BC(dev_priv) ||
- INTEL_GEN(dev_priv) >= 10 ?
- GEN9_FREQ_SCALER : 1))),
- ((ia_freq >> 0) & 0xff) * 100,
- ((ia_freq >> 8) & 0xff) * 100);
- }
- intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
-
- return 0;
-}
-
static int i915_opregion(struct seq_file *m, void *unused)
{
struct intel_opregion *opregion = &node_to_i915(m->private)->opregion;
@@ -1605,87 +1120,6 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
return 0;
}
-static const char *rps_power_to_str(unsigned int power)
-{
- static const char * const strings[] = {
- [LOW_POWER] = "low power",
- [BETWEEN] = "mixed",
- [HIGH_POWER] = "high power",
- };
-
- if (power >= ARRAY_SIZE(strings) || !strings[power])
- return "unknown";
-
- return strings[power];
-}
-
-static int i915_rps_boost_info(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- struct intel_rps *rps = &dev_priv->gt.rps;
- u32 act_freq;
- intel_wakeref_t wakeref;
-
- with_intel_runtime_pm_if_in_use(&dev_priv->runtime_pm, wakeref)
- act_freq = intel_cagf_freq_read(rps);
-
- seq_printf(m, "RPS enabled? %d\n", rps->enabled);
- seq_printf(m, "GPU busy? %s\n", yesno(dev_priv->gt.awake));
- seq_printf(m, "Boosts outstanding? %d\n",
- atomic_read(&rps->num_waiters));
- seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
- seq_printf(m, "Frequency requested %d, actual %d\n",
- intel_gpu_freq(rps, rps->cur_freq), act_freq);
- seq_printf(m, " min hard:%d, soft:%d; max soft:%d, hard:%d\n",
- intel_gpu_freq(rps, rps->min_freq),
- intel_gpu_freq(rps, rps->min_freq_softlimit),
- intel_gpu_freq(rps, rps->max_freq_softlimit),
- intel_gpu_freq(rps, rps->max_freq));
- seq_printf(m, " idle:%d, efficient:%d, boost:%d\n",
- intel_gpu_freq(rps, rps->idle_freq),
- intel_gpu_freq(rps, rps->efficient_freq),
- intel_gpu_freq(rps, rps->boost_freq));
-
- seq_printf(m, "Wait boosts: %d\n", atomic_read(&rps->boosts));
-
- if (INTEL_GEN(dev_priv) >= 6 && rps->enabled && dev_priv->gt.awake) {
- u32 rpup, rpupei;
- u32 rpdown, rpdownei;
-
- intel_uncore_forcewake_get(&dev_priv->uncore, FORCEWAKE_ALL);
- rpup = I915_READ_FW(GEN6_RP_CUR_UP) & GEN6_RP_EI_MASK;
- rpupei = I915_READ_FW(GEN6_RP_CUR_UP_EI) & GEN6_RP_EI_MASK;
- rpdown = I915_READ_FW(GEN6_RP_CUR_DOWN) & GEN6_RP_EI_MASK;
- rpdownei = I915_READ_FW(GEN6_RP_CUR_DOWN_EI) & GEN6_RP_EI_MASK;
- intel_uncore_forcewake_put(&dev_priv->uncore, FORCEWAKE_ALL);
-
- seq_printf(m, "\nRPS Autotuning (current \"%s\" window):\n",
- rps_power_to_str(rps->power.mode));
- seq_printf(m, " Avg. up: %d%% [above threshold? %d%%]\n",
- rpup && rpupei ? 100 * rpup / rpupei : 0,
- rps->power.up_threshold);
- seq_printf(m, " Avg. down: %d%% [below threshold? %d%%]\n",
- rpdown && rpdownei ? 100 * rpdown / rpdownei : 0,
- rps->power.down_threshold);
- } else {
- seq_puts(m, "\nRPS Autotuning inactive\n");
- }
-
- return 0;
-}
-
-static int i915_llc(struct seq_file *m, void *data)
-{
- struct drm_i915_private *dev_priv = node_to_i915(m->private);
- const bool edram = INTEL_GEN(dev_priv) > 8;
-
- seq_printf(m, "LLC: %s\n", yesno(HAS_LLC(dev_priv)));
- seq_printf(m, "%s: %uMB\n", edram ? "eDRAM" : "eLLC",
- dev_priv->edram_size_mb);
-
- return 0;
-}
-
static int i915_huc_load_status_info(struct seq_file *m, void *data)
{
struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -4246,9 +3680,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_guc_load_err_log_dump", i915_guc_log_dump, 0, (void *)1},
{"i915_guc_stage_pool", i915_guc_stage_pool, 0},
{"i915_huc_load_status", i915_huc_load_status_info, 0},
- {"i915_frequency_info", i915_frequency_info, 0},
- {"i915_drpc_info", i915_drpc_info, 0},
- {"i915_ring_freq_table", i915_ring_freq_table, 0},
{"i915_frontbuffer_tracking", i915_frontbuffer_tracking, 0},
{"i915_fbc_status", i915_fbc_status, 0},
{"i915_ips_status", i915_ips_status, 0},
@@ -4257,9 +3688,7 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_vbt", i915_vbt, 0},
{"i915_gem_framebuffer", i915_gem_framebuffer_info, 0},
{"i915_context_status", i915_context_status, 0},
- {"i915_forcewake_domains", i915_forcewake_domains, 0},
{"i915_swizzle_info", i915_swizzle_info, 0},
- {"i915_llc", i915_llc, 0},
{"i915_edp_psr_status", i915_edp_psr_status, 0},
{"i915_energy_uJ", i915_energy_uJ, 0},
{"i915_runtime_pm_status", i915_runtime_pm_status, 0},
@@ -4275,7 +3704,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
{"i915_ddb_info", i915_ddb_info, 0},
{"i915_sseu_status", i915_sseu_status, 0},
{"i915_drrs_status", i915_drrs_status, 0},
- {"i915_rps_boost_info", i915_rps_boost_info, 0},
};
#define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
@@ -4311,6 +3739,7 @@ static const struct i915_debugfs_files {
int i915_debugfs_register(struct drm_i915_private *dev_priv)
{
struct drm_minor *minor = dev_priv->drm.primary;
+ int err;
int i;
debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
@@ -4324,9 +3753,13 @@ int i915_debugfs_register(struct drm_i915_private *dev_priv)
i915_debugfs_files[i].fops);
}
- return drm_debugfs_create_files(i915_debugfs_list,
- I915_DEBUGFS_ENTRIES,
- minor->debugfs_root, minor);
+ err = drm_debugfs_create_files(i915_debugfs_list,
+ I915_DEBUGFS_ENTRIES,
+ minor->debugfs_root, minor);
+ if (err)
+ return err;
+
+ return intel_gt_pm_debugfs_register(&dev_priv->gt);
}
struct dpcd_block {
diff --git a/drivers/gpu/drm/i915/i915_debugfs.h b/drivers/gpu/drm/i915/i915_debugfs.h
index c0cd22eb916d..56bd7d14bb22 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.h
+++ b/drivers/gpu/drm/i915/i915_debugfs.h
@@ -6,6 +6,10 @@
#ifndef __I915_DEBUGFS_H__
#define __I915_DEBUGFS_H__
+#include <drm/drm_debugfs.h>
+
+#include "i915_drv.h"
+
struct drm_i915_private;
struct drm_connector;
@@ -17,4 +21,9 @@ static inline int i915_debugfs_register(struct drm_i915_private *dev_priv) { ret
static inline int i915_debugfs_connector_add(struct drm_connector *connector) { return 0; }
#endif
+static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
+{
+ return to_i915(node->minor->dev);
+}
+
#endif /* __I915_DEBUGFS_H__ */
--
2.24.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt
2019-12-09 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt Andi Shyti
@ 2019-12-09 22:47 ` Chris Wilson
2019-12-09 23:39 ` Andi Shyti
0 siblings, 1 reply; 9+ messages in thread
From: Chris Wilson @ 2019-12-09 22:47 UTC (permalink / raw)
To: Andi Shyti, Intel GFX
Quoting Andi Shyti (2019-12-09 22:35:56)
> +int intel_gt_pm_debugfs_register(struct intel_gt *gt)
> +{
> + struct drm_minor *minor = gt->i915->drm.primary;
> +
> + return drm_debugfs_create_files(i915_gt_pm_debugfs_list,
> + ARRAY_SIZE(i915_gt_pm_debugfs_list),
> + minor->debugfs_root, minor);
You missed a vital trick to pass the gt as our private. Hint don't use
drm_debugfs_create_files() per se.
-Chris
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers
2019-12-09 22:35 ` [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers Andi Shyti
@ 2019-12-09 23:25 ` Chris Wilson
0 siblings, 0 replies; 9+ messages in thread
From: Chris Wilson @ 2019-12-09 23:25 UTC (permalink / raw)
To: Andi Shyti, Intel GFX
Quoting Andi Shyti (2019-12-09 22:35:55)
> From: Andi Shyti <andi.shyti@intel.com>
>
> Add two helpers that for reading the actual GT's frequency. The
> two helpers are:
>
> - intel_cagf_read: reads the frequency and returns it not
> normalized
>
> - intel_cagf_freq_read: provides the frequency in Hz.
>
> Use the above helpers in sysfs and debugfs.
>
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_rps.c | 22 ++++++++++++++++++++++
> drivers/gpu/drm/i915/gt/intel_rps.h | 2 ++
> drivers/gpu/drm/i915/i915_debugfs.c | 21 +++++----------------
> drivers/gpu/drm/i915/i915_sysfs.c | 14 ++------------
> 4 files changed, 31 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
> index 08a38a3b90b0..72c3dd976e32 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rps.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rps.c
> @@ -1682,6 +1682,28 @@ u32 intel_get_cagf(struct intel_rps *rps, u32 rpstat)
> return cagf;
> }
>
> +u32 intel_cagf_read(struct intel_rps *rps)
> +{
> + struct drm_i915_private *i915 = rps_to_i915(rps);
> + u32 freq;
> +
> + if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
> + vlv_punit_get(i915);
> + freq = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
> + vlv_punit_put(i915);
> +
> + return (freq >> 8) & 0xff;
> + }
> +
> + return intel_get_cagf(rps, intel_uncore_read(rps_to_gt(rps)->uncore,
> + GEN6_RPSTAT1));
> +}
> +
> +u32 intel_cagf_freq_read(struct intel_rps *rps)
> +{
> + return intel_gpu_freq(rps, intel_cagf_read(rps));
Thinking about this far too much, this should be something along the
lines of
intel_rps_read_actual_frequency(struct intel_rps *rps)
since it operates on the intel_rps object and
intel_rps_read_cagf()
-Chris
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some debugfs enhancements
2019-12-09 22:35 [Intel-gfx] [PATCH 0/2] Some debugfs enhancements Andi Shyti
2019-12-09 22:35 ` [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers Andi Shyti
2019-12-09 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt Andi Shyti
@ 2019-12-09 23:33 ` Patchwork
2019-12-10 0:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2019-12-10 5:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-12-09 23:33 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: Some debugfs enhancements
URL : https://patchwork.freedesktop.org/series/70658/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
112b55276b89 drm/i915/rps: Add frequency translation helpers
77e7a15ebe7b drm/i915/gt: Move power management debugfs files into gt
-:24: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#24:
new file mode 100644
-:29: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#29: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:1:
+/*
-:30: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#30: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:2:
+ * SPDX-License-Identifier: MIT
-:121: CHECK:BRACES: braces {} should be used on all arms of this statement
#121: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:93:
+ if (INTEL_GEN(i915) >= 9)
[...]
+ else {
[...]
-:123: CHECK:BRACES: Unbalanced braces around else statement
#123: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:95:
+ else {
-:442: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#442: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:414:
+ gen9_powergate_enable = intel_uncore_read(uncore,
+ GEN9_PG_ENABLE);
-:444: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#444: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:416:
+ gen9_powergate_status = intel_uncore_read(uncore,
+ GEN9_PWRGT_DOMAIN_STATUS);
-:457: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#457: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:429:
+ seq_printf(m, "Render Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & GEN9_RENDER_PG_ENABLE));
-:459: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#459: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:431:
+ seq_printf(m, "Media Well Gating Enabled: %s\n",
+ yesno(gen9_powergate_enable & GEN9_MEDIA_PG_ENABLE));
-:466: CHECK:CAMELCASE: Avoid CamelCase: <GEN6_RCn_MASK>
#466: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:438:
+ switch (gt_core_status & GEN6_RCn_MASK) {
-:491: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#491: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:463:
+ seq_printf(m, "Render Power Well: %s\n",
+ (gen9_powergate_status &
-:494: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#494: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.c:466:
+ seq_printf(m, "Media Power Well: %s\n",
+ (gen9_powergate_status &
-:628: WARNING:SPDX_LICENSE_TAG: Missing or malformed SPDX-License-Identifier tag in line 1
#628: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h:1:
+/*
-:629: WARNING:SPDX_LICENSE_TAG: Misplaced SPDX-License-Identifier tag - use line 1 instead
#629: FILE: drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h:2:
+ * SPDX-License-Identifier: MIT
total: 0 errors, 5 warnings, 9 checks, 1287 lines checked
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt
2019-12-09 22:47 ` Chris Wilson
@ 2019-12-09 23:39 ` Andi Shyti
0 siblings, 0 replies; 9+ messages in thread
From: Andi Shyti @ 2019-12-09 23:39 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel GFX
> > +int intel_gt_pm_debugfs_register(struct intel_gt *gt)
> > +{
> > + struct drm_minor *minor = gt->i915->drm.primary;
> > +
> > + return drm_debugfs_create_files(i915_gt_pm_debugfs_list,
> > + ARRAY_SIZE(i915_gt_pm_debugfs_list),
> > + minor->debugfs_root, minor);
>
> You missed a vital trick to pass the gt as our private. Hint don't use
> drm_debugfs_create_files() per se.
I knew this comment would come, but, after some thoughts, it felt
like this was the less drastic approach (because at the end
nothing really changes :) ).
I will improve it in v2, along with the renaming in patch 1.
Thanks Chris,
Andi
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^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Some debugfs enhancements
2019-12-09 22:35 [Intel-gfx] [PATCH 0/2] Some debugfs enhancements Andi Shyti
` (2 preceding siblings ...)
2019-12-09 23:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some debugfs enhancements Patchwork
@ 2019-12-10 0:14 ` Patchwork
2019-12-10 5:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-12-10 0:14 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: Some debugfs enhancements
URL : https://patchwork.freedesktop.org/series/70658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7523 -> Patchwork_15661
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/index.html
Known issues
------------
Here are the changes found in Patchwork_15661 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][1] -> [DMESG-FAIL][2] ([i915#730])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [PASS][3] -> [INCOMPLETE][4] ([i915#694])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
- fi-byt-n2820: [PASS][5] -> [INCOMPLETE][6] ([i915#45])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@gem_ctx_create@basic-files:
- {fi-tgl-guc}: [INCOMPLETE][7] ([fdo#111735]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-tgl-guc/igt@gem_ctx_create@basic-files.html
* igt@i915_pm_rpm@module-reload:
- fi-skl-lmem: [DMESG-WARN][9] ([i915#592]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [DMESG-FAIL][11] ([i915#725]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-ivb-3770/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [DMESG-FAIL][13] -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-hsw-4770/igt@i915_selftest@live_blt.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111096] / [i915#323]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
#### Warnings ####
* igt@gem_exec_suspend@basic-s3:
- fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][18] ([i915#62] / [i915#92]) +6 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html
* igt@kms_flip@basic-flip-vs-modeset:
- fi-kbl-x1275: [DMESG-WARN][19] ([i915#62] / [i915#92]) -> [DMESG-WARN][20] ([i915#62] / [i915#92] / [i915#95]) +4 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#730]: https://gitlab.freedesktop.org/drm/intel/issues/730
[i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (52 -> 46)
------------------------------
Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-kbl-7560u fi-byt-clapper
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7523 -> Patchwork_15661
CI-20190529: 20190529
CI_DRM_7523: bbcf5f94e2ae795beec14cba06533ff3a9971cc0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5341: 5fe683cdebde2d77d16ffc42c9fdf29a9f95bb82 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15661: 77e7a15ebe7b411500d202075ef23f08948992a4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
77e7a15ebe7b drm/i915/gt: Move power management debugfs files into gt
112b55276b89 drm/i915/rps: Add frequency translation helpers
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Some debugfs enhancements
2019-12-09 22:35 [Intel-gfx] [PATCH 0/2] Some debugfs enhancements Andi Shyti
` (3 preceding siblings ...)
2019-12-10 0:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2019-12-10 5:46 ` Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2019-12-10 5:46 UTC (permalink / raw)
To: Andi Shyti; +Cc: intel-gfx
== Series Details ==
Series: Some debugfs enhancements
URL : https://patchwork.freedesktop.org/series/70658/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7523_full -> Patchwork_15661_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_15661_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs}:
- shard-iclb: NOTRUN -> [SKIP][1] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb3/igt@gem_render_copy@y-tiled-mc-ccs-to-yf-tiled-ccs.html
Known issues
------------
Here are the changes found in Patchwork_15661_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_isolation@bcs0-s3:
- shard-apl: [PASS][2] -> [DMESG-WARN][3] ([i915#180]) +4 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-apl7/igt@gem_ctx_isolation@bcs0-s3.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-apl1/igt@gem_ctx_isolation@bcs0-s3.html
* igt@gem_ctx_shared@q-smoketest-bsd1:
- shard-tglb: [PASS][4] -> [INCOMPLETE][5] ([fdo#111735])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb4/igt@gem_ctx_shared@q-smoketest-bsd1.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb4/igt@gem_ctx_shared@q-smoketest-bsd1.html
* igt@gem_eio@kms:
- shard-snb: [PASS][6] -> [INCOMPLETE][7] ([i915#82])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-snb2/igt@gem_eio@kms.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-snb2/igt@gem_eio@kms.html
* igt@gem_exec_parse_blt@allowed-all:
- shard-kbl: [PASS][8] -> [DMESG-WARN][9] ([i915#716])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-kbl4/igt@gem_exec_parse_blt@allowed-all.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-kbl6/igt@gem_exec_parse_blt@allowed-all.html
* igt@gem_exec_schedule@preempt-queue-vebox:
- shard-tglb: [PASS][10] -> [INCOMPLETE][11] ([fdo#111677])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb4/igt@gem_exec_schedule@preempt-queue-vebox.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb6/igt@gem_exec_schedule@preempt-queue-vebox.html
* igt@gem_exec_schedule@smoketest-bsd2:
- shard-tglb: [PASS][12] -> [INCOMPLETE][13] ([i915#707])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb8/igt@gem_exec_schedule@smoketest-bsd2.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb6/igt@gem_exec_schedule@smoketest-bsd2.html
* igt@gem_exec_whisper@normal:
- shard-tglb: [PASS][14] -> [INCOMPLETE][15] ([i915#435])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb1/igt@gem_exec_whisper@normal.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb3/igt@gem_exec_whisper@normal.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-apl: [PASS][16] -> [FAIL][17] ([i915#520])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-apl6/igt@gem_persistent_relocs@forked-thrashing.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-apl4/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-tglb: [PASS][18] -> [INCOMPLETE][19] ([i915#470] / [i915#475])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb6/igt@gem_ppgtt@blt-vs-render-ctxn.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb6/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_sync@basic-store-all:
- shard-tglb: [PASS][20] -> [INCOMPLETE][21] ([i915#472])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb2/igt@gem_sync@basic-store-all.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb6/igt@gem_sync@basic-store-all.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
- shard-snb: [PASS][22] -> [DMESG-WARN][23] ([fdo#111870])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [PASS][24] -> [FAIL][25] ([i915#447])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-iclb6/igt@i915_pm_dc@dc5-dpms.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
* igt@kms_color@pipe-a-ctm-red-to-blue:
- shard-skl: [PASS][26] -> [DMESG-WARN][27] ([i915#109])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl8/igt@kms_color@pipe-a-ctm-red-to-blue.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl4/igt@kms_color@pipe-a-ctm-red-to-blue.html
* igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding:
- shard-skl: [PASS][28] -> [FAIL][29] ([i915#54])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl10/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl5/igt@kms_cursor_crc@pipe-a-cursor-64x21-sliding.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][30] -> [FAIL][31] ([i915#72])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-glk4/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_fbcon_fbt@psr-suspend:
- shard-tglb: [PASS][32] -> [INCOMPLETE][33] ([i915#456] / [i915#460])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb6/igt@kms_fbcon_fbt@psr-suspend.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb3/igt@kms_fbcon_fbt@psr-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][34] -> [INCOMPLETE][35] ([i915#221])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl7/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite:
- shard-tglb: [PASS][36] -> [FAIL][37] ([i915#49])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-pwrite.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][38] -> [DMESG-WARN][39] ([i915#180]) +4 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-kbl1/igt@kms_frontbuffer_tracking@fbc-suspend.html
- shard-tglb: [PASS][40] -> [INCOMPLETE][41] ([i915#456] / [i915#460] / [i915#474])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-suspend.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb2/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt:
- shard-tglb: [PASS][42] -> [INCOMPLETE][43] ([i915#474] / [i915#667])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb6/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][44] -> [FAIL][45] ([fdo#108145] / [i915#265])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl7/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][46] -> [SKIP][47] ([fdo#112080])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-iclb1/igt@perf_pmu@busy-no-semaphores-vcs1.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-iclb: [SKIP][48] ([fdo#112146]) -> [PASS][49] +1 similar issue
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-iclb1/igt@gem_exec_schedule@pi-ringfull-bsd.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb6/igt@gem_exec_schedule@pi-ringfull-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][50] ([fdo#109276]) -> [PASS][51] +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-iclb5/igt@gem_exec_schedule@preempt-queue-bsd1.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb2/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1:
- shard-tglb: [INCOMPLETE][52] ([fdo#111677]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb6/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb7/igt@gem_exec_schedule@preempt-queue-contexts-chain-bsd1.html
* igt@gem_exec_schedule@smoketest-all:
- shard-tglb: [INCOMPLETE][54] ([i915#463]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb8/igt@gem_exec_schedule@smoketest-all.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb2/igt@gem_exec_schedule@smoketest-all.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-hsw: [TIMEOUT][56] ([i915#530]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-hsw7/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-snb: [FAIL][58] ([i915#520]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-snb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-snb7/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_persistent_relocs@forked-thrashing:
- shard-iclb: [INCOMPLETE][60] ([fdo#109100] / [i915#140] / [i915#530]) -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-iclb6/igt@gem_persistent_relocs@forked-thrashing.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb3/igt@gem_persistent_relocs@forked-thrashing.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-glk: [FAIL][62] ([i915#644]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-glk2/igt@gem_ppgtt@flink-and-close-vma-leak.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-glk5/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-store-each:
- shard-tglb: [INCOMPLETE][64] ([i915#435] / [i915#472]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb5/igt@gem_sync@basic-store-each.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb1/igt@gem_sync@basic-store-each.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [DMESG-WARN][66] ([fdo#111870]) -> [PASS][67] +1 similar issue
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-snb5/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-snb4/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@gem_workarounds@suspend-resume-context:
- shard-apl: [DMESG-WARN][68] ([i915#180]) -> [PASS][69] +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-apl1/igt@gem_workarounds@suspend-resume-context.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-apl3/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_selftest@mock_sanitycheck:
- shard-hsw: [DMESG-WARN][70] ([i915#747]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-hsw6/igt@i915_selftest@mock_sanitycheck.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-hsw6/igt@i915_selftest@mock_sanitycheck.html
- shard-kbl: [DMESG-WARN][72] ([i915#747]) -> [PASS][73]
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-kbl7/igt@i915_selftest@mock_sanitycheck.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-kbl7/igt@i915_selftest@mock_sanitycheck.html
* igt@kms_color@pipe-a-ctm-0-75:
- shard-skl: [DMESG-WARN][74] ([i915#109]) -> [PASS][75] +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl7/igt@kms_color@pipe-a-ctm-0-75.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl4/igt@kms_color@pipe-a-ctm-0-75.html
* igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding:
- shard-skl: [FAIL][76] ([i915#54]) -> [PASS][77] +3 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-64x64-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-tglb: [INCOMPLETE][78] ([i915#456] / [i915#460]) -> [PASS][79]
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-skl: [INCOMPLETE][80] ([i915#300]) -> [PASS][81]
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl5/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_flip@plain-flip-ts-check-interruptible:
- shard-skl: [FAIL][82] ([i915#34]) -> [PASS][83]
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl6/igt@kms_flip@plain-flip-ts-check-interruptible.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl8/igt@kms_flip@plain-flip-ts-check-interruptible.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-kbl: [DMESG-WARN][84] ([i915#180]) -> [PASS][85] +3 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-kbl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min:
- shard-skl: [FAIL][86] ([fdo#108145]) -> [PASS][87] +1 similar issue
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][88] ([i915#31]) -> [PASS][89]
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-apl1/igt@kms_setmode@basic.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-apl6/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][90] ([i915#31]) -> [PASS][91]
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-kbl7/igt@kms_setmode@basic.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-kbl1/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-tglb: [INCOMPLETE][92] ([i915#460]) -> [PASS][93]
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-tglb7/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-tglb3/igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend.html
* igt@perf_pmu@semaphore-wait-idle-vcs1:
- shard-iclb: [SKIP][94] ([fdo#112080]) -> [PASS][95]
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-iclb5/igt@perf_pmu@semaphore-wait-idle-vcs1.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-iclb2/igt@perf_pmu@semaphore-wait-idle-vcs1.html
* igt@syncobj_wait@wait-all-for-submit-snapshot:
- shard-skl: [FAIL][96] -> [PASS][97]
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl5/igt@syncobj_wait@wait-all-for-submit-snapshot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl2/igt@syncobj_wait@wait-all-for-submit-snapshot.html
#### Warnings ####
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-skl: [INCOMPLETE][98] ([fdo#112347] / [i915#648]) -> [INCOMPLETE][99] ([fdo#112391] / [i915#648] / [i915#667])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-skl2/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-skl6/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html
* igt@runner@aborted:
- shard-kbl: [FAIL][100] ([k.org#204565]) -> [FAIL][101] ([i915#716])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7523/shard-kbl7/igt@runner@aborted.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/shard-kbl6/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109100]: https://bugs.freedesktop.org/show_bug.cgi?id=109100
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347
[fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391
[i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#463]: https://gitlab.freedesktop.org/drm/intel/issues/463
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474
[i915#475]: https://gitlab.freedesktop.org/drm/intel/issues/475
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648
[i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667
[i915#707]: https://gitlab.freedesktop.org/drm/intel/issues/707
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#747]: https://gitlab.freedesktop.org/drm/intel/issues/747
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565
Participating hosts (11 -> 11)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7523 -> Patchwork_15661
CI-20190529: 20190529
CI_DRM_7523: bbcf5f94e2ae795beec14cba06533ff3a9971cc0 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5341: 5fe683cdebde2d77d16ffc42c9fdf29a9f95bb82 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_15661: 77e7a15ebe7b411500d202075ef23f08948992a4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15661/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2019-12-10 5:46 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-09 22:35 [Intel-gfx] [PATCH 0/2] Some debugfs enhancements Andi Shyti
2019-12-09 22:35 ` [Intel-gfx] [PATCH 1/2] drm/i915/rps: Add frequency translation helpers Andi Shyti
2019-12-09 23:25 ` Chris Wilson
2019-12-09 22:35 ` [Intel-gfx] [PATCH 2/2] drm/i915/gt: Move power management debugfs files into gt Andi Shyti
2019-12-09 22:47 ` Chris Wilson
2019-12-09 23:39 ` Andi Shyti
2019-12-09 23:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Some debugfs enhancements Patchwork
2019-12-10 0:14 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2019-12-10 5:46 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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