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* [v1] drm/msm: update LANE_CTRL register value from default value
@ 2019-12-23 10:19 ` Harigovindan P
  0 siblings, 0 replies; 4+ messages in thread
From: Harigovindan P @ 2019-12-23 10:19 UTC (permalink / raw)
  To: dri-devel, linux-arm-msm, freedreno, devicetree
  Cc: Harigovindan P, linux-kernel, robdclark, seanpaul, hoegsberg,
	abhinavk, jsanka, chandanu, nganji

Updating REG_DSI_LANE_CTRL register value by reading default
register value and writing it back using bitwise OR with
DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.

Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index e6289a3..d3c5233 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -816,7 +816,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
 	u32 flags = msm_host->mode_flags;
 	enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-	u32 data = 0;
+	u32 data = 0, lane_ctrl = 0;
 
 	if (!enable) {
 		dsi_write(msm_host, REG_DSI_CTRL, 0);
@@ -904,9 +904,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
 		  DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
 
-	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
+	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
+		lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
 		dsi_write(msm_host, REG_DSI_LANE_CTRL,
-			DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+			lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+	}
 
 	data |= DSI_CTRL_ENABLE;
 
-- 
2.7.4


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* [v1] drm/msm: update LANE_CTRL register value from default value
@ 2019-12-23 10:19 ` Harigovindan P
  0 siblings, 0 replies; 4+ messages in thread
From: Harigovindan P @ 2019-12-23 10:19 UTC (permalink / raw)
  To: dri-devel, linux-arm-msm, freedreno, devicetree
  Cc: Harigovindan P, abhinavk, linux-kernel, seanpaul, hoegsberg, chandanu

Updating REG_DSI_LANE_CTRL register value by reading default
register value and writing it back using bitwise OR with
DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.

Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
---
 drivers/gpu/drm/msm/dsi/dsi_host.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
index e6289a3..d3c5233 100644
--- a/drivers/gpu/drm/msm/dsi/dsi_host.c
+++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
@@ -816,7 +816,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
 	u32 flags = msm_host->mode_flags;
 	enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
 	const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
-	u32 data = 0;
+	u32 data = 0, lane_ctrl = 0;
 
 	if (!enable) {
 		dsi_write(msm_host, REG_DSI_CTRL, 0);
@@ -904,9 +904,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
 	dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
 		  DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
 
-	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
+	if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
+		lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
 		dsi_write(msm_host, REG_DSI_LANE_CTRL,
-			DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+			lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
+	}
 
 	data |= DSI_CTRL_ENABLE;
 
-- 
2.7.4

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [Freedreno] [v1] drm/msm: update LANE_CTRL register value from default value
  2019-12-23 10:19 ` Harigovindan P
@ 2019-12-23 13:58   ` Jeffrey Hugo
  -1 siblings, 0 replies; 4+ messages in thread
From: Jeffrey Hugo @ 2019-12-23 13:58 UTC (permalink / raw)
  To: Harigovindan P
  Cc: open list:DRM PANEL DRIVERS, MSM, freedreno, DTML, Abhinav Kumar,
	lkml, Rob Clark, nganji, Sean Paul, Kristian H. Kristensen,
	Jeykumar Sankaran, Chandan Uddaraju

On Mon, Dec 23, 2019 at 3:19 AM Harigovindan P <harigovi@codeaurora.org> wrote:
>
> Updating REG_DSI_LANE_CTRL register value by reading default
> register value and writing it back using bitwise OR with
> DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.

Why?
You explain what the code does, which I can tell from reading the
code.  The commit text should tell me why this change is necessary.
Why would I care if this change is in my tree or not?  What feature
does it provide or what issue does it fix?

>
> Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index e6289a3..d3c5233 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -816,7 +816,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
>         u32 flags = msm_host->mode_flags;
>         enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
>         const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> -       u32 data = 0;
> +       u32 data = 0, lane_ctrl = 0;
>
>         if (!enable) {
>                 dsi_write(msm_host, REG_DSI_CTRL, 0);
> @@ -904,9 +904,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
>         dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
>                   DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
>
> -       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
> +       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
> +               lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
>                 dsi_write(msm_host, REG_DSI_LANE_CTRL,
> -                       DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
> +                       lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
> +       }
>
>         data |= DSI_CTRL_ENABLE;
>
> --
> 2.7.4
>
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [Freedreno] [v1] drm/msm: update LANE_CTRL register value from default value
@ 2019-12-23 13:58   ` Jeffrey Hugo
  0 siblings, 0 replies; 4+ messages in thread
From: Jeffrey Hugo @ 2019-12-23 13:58 UTC (permalink / raw)
  To: Harigovindan P
  Cc: DTML, MSM, lkml, Abhinav Kumar, Sean Paul,
	open list:DRM PANEL DRIVERS, Kristian H. Kristensen, freedreno,
	Chandan Uddaraju

On Mon, Dec 23, 2019 at 3:19 AM Harigovindan P <harigovi@codeaurora.org> wrote:
>
> Updating REG_DSI_LANE_CTRL register value by reading default
> register value and writing it back using bitwise OR with
> DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST. This works for all panels.

Why?
You explain what the code does, which I can tell from reading the
code.  The commit text should tell me why this change is necessary.
Why would I care if this change is in my tree or not?  What feature
does it provide or what issue does it fix?

>
> Signed-off-by: Harigovindan P <harigovi@codeaurora.org>
> ---
>  drivers/gpu/drm/msm/dsi/dsi_host.c | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c
> index e6289a3..d3c5233 100644
> --- a/drivers/gpu/drm/msm/dsi/dsi_host.c
> +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c
> @@ -816,7 +816,7 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
>         u32 flags = msm_host->mode_flags;
>         enum mipi_dsi_pixel_format mipi_fmt = msm_host->format;
>         const struct msm_dsi_cfg_handler *cfg_hnd = msm_host->cfg_hnd;
> -       u32 data = 0;
> +       u32 data = 0, lane_ctrl = 0;
>
>         if (!enable) {
>                 dsi_write(msm_host, REG_DSI_CTRL, 0);
> @@ -904,9 +904,11 @@ static void dsi_ctrl_config(struct msm_dsi_host *msm_host, bool enable,
>         dsi_write(msm_host, REG_DSI_LANE_SWAP_CTRL,
>                   DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL(msm_host->dlane_swap));
>
> -       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS))
> +       if (!(flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) {
> +               lane_ctrl = dsi_read(msm_host, REG_DSI_LANE_CTRL);
>                 dsi_write(msm_host, REG_DSI_LANE_CTRL,
> -                       DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
> +                       lane_ctrl | DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST);
> +       }
>
>         data |= DSI_CTRL_ENABLE;
>
> --
> 2.7.4
>
> _______________________________________________
> Freedreno mailing list
> Freedreno@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/freedreno
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

^ permalink raw reply	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-12-24 14:31 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2019-12-23 10:19 [v1] drm/msm: update LANE_CTRL register value from default value Harigovindan P
2019-12-23 10:19 ` Harigovindan P
2019-12-23 13:58 ` [Freedreno] " Jeffrey Hugo
2019-12-23 13:58   ` Jeffrey Hugo

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