* [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-03 17:41 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2020-01-03 17:41 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 66 +++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 141 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..4922a2df7 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,59 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/ioctl.h>
#include <sys/sysinfo.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+ drm_unique_t u = {
+ .unique = buf + 1,
+ .unique_len = buflen - 1,
+ };
+ drm_set_version_t sv = {
+ .drm_di_major = 1,
+ .drm_di_minor = 4,
+ .drm_dd_major = -1, /* Don't care */
+ .drm_dd_minor = -1, /* Don't care */
+ };
+
+ if (ioctl(i915, DRM_IOCTL_SET_VERSION, &sv))
+ return "i915";
+
+ memset(buf, 0, buflen);
+ ioctl(i915, DRM_IOCTL_GET_UNIQUE, &u);
+
+ if (u.unique_len >= buflen)
+ return NULL;
+
+ if (strncmp(buf + 1, "pci:", 4))
+ return NULL;
+
+ if (strcmp(buf + 1, "pci:0000:00:02.0") == 0)
+ return "i915";
+
+ return memcpy(buf, "i915-", strlen("i915-"));
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +94,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-03 17:41 ` Chris Wilson
0 siblings, 0 replies; 6+ messages in thread
From: Chris Wilson @ 2020-01-03 17:41 UTC (permalink / raw)
To: intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
Since with multiple devices, we may have multiple different perf_pmu
each with their own type, we want to find the right one for the job.
The tests are run with a specific fd, from which we can extract the
appropriate bus-id and find the associated perf-type. The performance
monitoring tools are a little more general and not yet ready to probe
all device or bind to one in particular, so we just assume the default
igfx for the time being.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
benchmarks/gem_wsim.c | 4 +-
lib/igt_perf.c | 66 +++++++++++++++++++++++---
lib/igt_perf.h | 13 ++++--
overlay/gem-interrupts.c | 2 +-
overlay/gpu-freq.c | 4 +-
overlay/gpu-top.c | 12 ++---
overlay/rc6.c | 2 +-
tests/i915/gem_ctx_freq.c | 2 +-
tests/i915/gem_ctx_sseu.c | 2 +-
tests/i915/gem_exec_balancer.c | 18 +++++---
tests/perf_pmu.c | 84 ++++++++++++++++++----------------
tools/intel_gpu_top.c | 2 +-
12 files changed, 141 insertions(+), 70 deletions(-)
diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
index 6305e0d7a..9156fdc90 100644
--- a/benchmarks/gem_wsim.c
+++ b/benchmarks/gem_wsim.c
@@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
for (d = &engines[0]; d->id != VCS; d++) {
int pfd;
- pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
- d->inst),
+ pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ d->inst),
bb->fd);
if (pfd < 0) {
if (d->id != VCS2)
diff --git a/lib/igt_perf.c b/lib/igt_perf.c
index e3dec2cc2..4922a2df7 100644
--- a/lib/igt_perf.c
+++ b/lib/igt_perf.c
@@ -4,17 +4,59 @@
#include <stdlib.h>
#include <string.h>
#include <errno.h>
+#include <sys/ioctl.h>
#include <sys/sysinfo.h>
#include "igt_perf.h"
-uint64_t i915_type_id(void)
+const char *i915_perf_device(int i915, char *buf, int buflen)
+{
+ drm_unique_t u = {
+ .unique = buf + 1,
+ .unique_len = buflen - 1,
+ };
+ drm_set_version_t sv = {
+ .drm_di_major = 1,
+ .drm_di_minor = 4,
+ .drm_dd_major = -1, /* Don't care */
+ .drm_dd_minor = -1, /* Don't care */
+ };
+
+ if (ioctl(i915, DRM_IOCTL_SET_VERSION, &sv))
+ return "i915";
+
+ memset(buf, 0, buflen);
+ ioctl(i915, DRM_IOCTL_GET_UNIQUE, &u);
+
+ if (u.unique_len >= buflen)
+ return NULL;
+
+ if (strncmp(buf + 1, "pci:", 4))
+ return NULL;
+
+ if (strcmp(buf + 1, "pci:0000:00:02.0") == 0)
+ return "i915";
+
+ return memcpy(buf, "i915-", strlen("i915-"));
+}
+
+uint64_t i915_perf_type_id(int i915)
+{
+ char buf[80];
+
+ return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
+}
+
+uint64_t igt_perf_type_id(const char *device)
{
char buf[64];
ssize_t ret;
int fd;
- fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
+ snprintf(buf, sizeof(buf),
+ "/sys/bus/event_source/devices/%s/type", device);
+
+ fd = open(buf, O_RDONLY);
if (fd < 0)
return 0;
@@ -52,15 +94,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
return ret;
}
-int perf_i915_open(uint64_t config)
+int perf_igfx_open(uint64_t config)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, -1,
+ PERF_FORMAT_TOTAL_TIME_ENABLED);
+}
+
+int perf_igfx_open_group(uint64_t config, int group)
+{
+ return _perf_open(igt_perf_type_id("i915"), config, group,
+ PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
+}
+
+int perf_i915_open(int i915, uint64_t config)
{
- return _perf_open(i915_type_id(), config, -1,
+ return _perf_open(i915_perf_type_id(i915), config, -1,
PERF_FORMAT_TOTAL_TIME_ENABLED);
}
-int perf_i915_open_group(uint64_t config, int group)
+int perf_i915_open_group(int i915, uint64_t config, int group)
{
- return _perf_open(i915_type_id(), config, group,
+ return _perf_open(i915_perf_type_id(i915), config, group,
PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
}
diff --git a/lib/igt_perf.h b/lib/igt_perf.h
index e00718f47..a8328c70c 100644
--- a/lib/igt_perf.h
+++ b/lib/igt_perf.h
@@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
}
-uint64_t i915_type_id(void);
-int perf_i915_open(uint64_t config);
-int perf_i915_open_group(uint64_t config, int group);
+uint64_t igt_perf_type_id(const char *device);
int igt_perf_open(uint64_t type, uint64_t config);
int igt_perf_open_group(uint64_t type, uint64_t config, int group);
+const char *i915_perf_device(int i915, char *buf, int buflen);
+uint64_t i915_perf_type_id(int i915);
+
+int perf_igfx_open(uint64_t config);
+int perf_igfx_open_group(uint64_t config, int group);
+
+int perf_i915_open(int i915, uint64_t config);
+int perf_i915_open_group(int i915, uint64_t config, int group);
+
#endif /* I915_PERF_H */
diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
index 0233fbb05..be73b6931 100644
--- a/overlay/gem-interrupts.c
+++ b/overlay/gem-interrupts.c
@@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
{
memset(irqs, 0, sizeof(*irqs));
- irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
+ irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
if (irqs->fd < 0 && interrupts_read() < 0)
irqs->error = ENODEV;
diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
index 0d8032592..b73157d39 100644
--- a/overlay/gpu-freq.c
+++ b/overlay/gpu-freq.c
@@ -37,8 +37,8 @@ static int perf_open(void)
{
int fd;
- fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
- if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
+ fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
+ if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
close(fd);
fd = -1;
}
diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
index 6cec2e943..32123abdd 100644
--- a/overlay/gpu-top.c
+++ b/overlay/gpu-top.c
@@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
d = &engines[0];
- gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
+ gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
-1);
if (gt->fd < 0)
return -1;
- if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
gt->fd) >= 0)
gt->have_wait = 1;
- if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
+ if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
gt->fd) >= 0)
gt->have_sema = 1;
@@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
gt->num_rings = 1;
for (d++; d->name; d++) {
- if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
+ if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
d->inst),
gt->fd) < 0)
continue;
if (gt->have_wait &&
- perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
d->inst),
gt->fd) < 0)
return -1;
if (gt->have_sema &&
- perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
+ perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
d->inst),
gt->fd) < 0)
return -1;
diff --git a/overlay/rc6.c b/overlay/rc6.c
index b5286f0cf..69f95f288 100644
--- a/overlay/rc6.c
+++ b/overlay/rc6.c
@@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
{
memset(rc6, 0, sizeof(*rc6));
- rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
+ rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
if (rc6->fd < 0) {
struct stat st;
if (stat("/sys/class/drm/card0/power", &st) < 0)
diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
index 89f3d11ef..5d2d3ec31 100644
--- a/tests/i915/gem_ctx_freq.c
+++ b/tests/i915/gem_ctx_freq.c
@@ -136,7 +136,7 @@ static void sysfs_range(int i915)
triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
- pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
+ pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
igt_require(pmu >= 0);
for (int outer = 0; outer <= 2*N_STEPS; outer++) {
diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
index 48e4411c8..38dc584bc 100644
--- a/tests/i915/gem_ctx_sseu.c
+++ b/tests/i915/gem_ctx_sseu.c
@@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
static bool has_engine(int fd, unsigned int class, unsigned int instance)
{
- int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
if (pmu >= 0)
close(pmu);
diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
index f4909a978..cebcc39c7 100644
--- a/tests/i915/gem_exec_balancer.c
+++ b/tests/i915/gem_exec_balancer.c
@@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
{
int fd;
- fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
+ fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
if (fd != -1) {
close(fd);
return true;
@@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
}
}
-static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
+static int
+add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
{
- return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
+ return perf_i915_open_group(i915,
+ I915_PMU_ENGINE_BUSY(ci->engine_class,
ci->engine_instance),
pmu);
}
@@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
double load;
int pmu;
- pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
+ pmu = perf_i915_open(i915,
+ I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
ci[idx].engine_instance));
spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
@@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
pmu[0] = -1;
for (int i = 0; i < limit; i++)
- pmu[i] = add_pmu(pmu[0], &siblings[i]);
- pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
+ pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
+ pmu[limit] = add_pmu(i915,
+ pmu[0], &master_engines[bond]);
igt_assert(siblings[bond].engine_class !=
master_engines[bond].engine_class);
@@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
for (unsigned int n = 0; n < count; n++) {
uint32_t ctx;
- pmu[n] = add_pmu(pmu[0], &ci[n]);
+ pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
if (flags & PULSE) {
struct drm_i915_gem_execbuffer2 eb = {
diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
index e1bbf2410..3e179daef 100644
--- a/tests/perf_pmu.c
+++ b/tests/perf_pmu.c
@@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
const double tolerance = 0.05f;
const unsigned long batch_duration_ns = 500e6;
-static int open_pmu(uint64_t config)
+static int open_pmu(int i915, uint64_t config)
{
int fd;
- fd = perf_i915_open(config);
+ fd = perf_i915_open(i915, config);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
return fd;
}
-static int open_group(uint64_t config, int group)
+static int open_group(int i915, uint64_t config, int group)
{
int fd;
- fd = perf_i915_open_group(config, group);
+ fd = perf_i915_open_group(i915, config, group);
igt_skip_on(fd < 0 && errno == ENODEV);
igt_assert(fd >= 0);
@@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
bool exists;
errno = 0;
- fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
+ fd = perf_i915_open(gem_fd,
+ __I915_PMU_ENGINE(e->class, e->instance, sample));
if (fd < 0)
err = errno;
@@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val;
int fd;
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
spin = __spin_sync(gem_fd, 0, e);
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
* Open PMU as fast as possible after the second spin batch in attempt
* to be faster than the driver handling lite-restore.
*/
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
val = __pmu_read_single(fd, &ts[0]);
slept = measured_usleep(batch_duration_ns / 1000);
@@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
if (e->class == e_->class && e->instance == e_->instance)
busy_idx = i;
- fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
+ fd[i++] = open_group(gem_fd,
+ I915_PMU_ENGINE_BUSY(e_->class,
e_->instance),
fd[0]);
}
@@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
fd[0] = -1;
for (i = 0; i < num_engines; i++)
- fd[i] = open_group(val[i], fd[0]);
+ fd[i] = open_group(gem_fd, val[i], fd[0]);
/* Small delay to allow engines to start. */
usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
@@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
uint64_t val[2][2];
int fd;
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
if (flags & TEST_BUSY)
spin = spin_sync(gem_fd, 0, e);
@@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
* to expected time spent in semaphore wait state.
*/
- fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -817,8 +820,9 @@ sema_busy(int gem_fd,
igt_require(gem_scheduler_has_semaphores(gem_fd));
- fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
- open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
+ fd = open_group(gem_fd,
+ I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
+ open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
__for_each_physical_engine(gem_fd, signal) {
if (e->class == signal->class &&
@@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
data.pipe = p;
prepare_crtc(&data, gem_fd, output);
- fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_WAIT(e->class, e->instance));
val[0] = pmu_read_single(fd);
@@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
gem_quiescent_gpu(gem_fd);
- fd[0] = open_pmu(config);
+ fd[0] = open_pmu(gem_fd, config);
/*
* Second PMU client which is initialized after the first one,
* and exists before it, should not affect accounting as reported
* in the first client.
*/
- fd[1] = open_pmu(config);
+ fd[1] = open_pmu(gem_fd, config);
spin = spin_sync(gem_fd, 0, e);
@@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
* - cpu != 0 is not supported since i915 PMU only allows running on one cpu
* and that is normally CPU0.
*/
-static void invalid_init(void)
+static void invalid_init(int i915)
{
struct perf_event_attr attr;
@@ -1093,7 +1098,7 @@ static void invalid_init(void)
do { \
memset(&attr, 0, sizeof (attr)); \
attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
- attr.type = i915_type_id(); \
+ attr.type = i915_perf_type_id(i915); \
igt_assert(attr.type != 0); \
errno = 0; \
} while(0)
@@ -1112,11 +1117,11 @@ do { \
igt_assert_eq(errno, EINVAL);
}
-static void init_other(unsigned int i, bool valid)
+static void init_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
close(fd);
}
-static void read_other(unsigned int i, bool valid)
+static void read_other(int i915, unsigned int i, bool valid)
{
int fd;
- fd = perf_i915_open(__I915_PMU_OTHER(i));
+ fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
igt_require(!(fd < 0 && errno == ENODEV));
if (valid) {
igt_assert(fd >= 0);
@@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
igt_require(cpu0_hotplug_support());
- fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
+ fd = open_pmu(gem_fd,
+ I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
/*
* Create two spinners so test can ensure shorter gaps in engine
@@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++) {
@@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_INTERRUPTS);
+ fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
/* Queue spinning batches. */
for (int i = 0; i < target; i++)
@@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
igt_require(max_freq > min_freq);
igt_require(boost_freq > min_freq);
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
/*
* Set GPU to min frequency and read PMU counters.
@@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
/* While parked, our convention is to report the GPU at 0Hz */
- fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
- open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
+ fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
+ open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
gem_quiescent_gpu(gem_fd); /* Be idle! */
measured_usleep(2000); /* Wait for timers to cease */
@@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
gem_quiescent_gpu(gem_fd);
- fd = open_pmu(I915_PMU_RC6_RESIDENCY);
+ fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
if (flags & TEST_RUNTIME_PM) {
drmModeRes *res;
@@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
usleep(500e3);
/* Enable the PMU. */
- fd = open_pmu(config);
+ fd = open_pmu(gem_fd, config);
/* Stop load and close the PMU. */
igt_stop_helper(&engine_load);
@@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
igt_spin_free(gem_fd, spin);
}
- fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
+ fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
/* Let the child run. */
read(link[0], &expected, sizeof(expected));
@@ -1835,7 +1841,7 @@ igt_main
fd = drm_open_driver_master(DRIVER_INTEL);
igt_require_gem(fd);
- igt_require(i915_type_id() > 0);
+ igt_require(i915_perf_type_id(fd) > 0);
__for_each_physical_engine(fd, e)
num_engines++;
@@ -1845,7 +1851,7 @@ igt_main
* Test invalid access via perf API is rejected.
*/
igt_subtest("invalid-init")
- invalid_init();
+ invalid_init(fd);
__for_each_physical_engine(fd, e) {
const unsigned int pct[] = { 2, 50, 98 };
@@ -1996,10 +2002,10 @@ igt_main
*/
for (i = 0; i < num_other_metrics + 1; i++) {
igt_subtest_f("other-init-%u", i)
- init_other(i, i < num_other_metrics);
+ init_other(fd, i, i < num_other_metrics);
igt_subtest_f("other-read-%u", i)
- read_other(i, i < num_other_metrics);
+ read_other(fd, i, i < num_other_metrics);
}
/**
diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
index cc8db7c53..8197482dd 100644
--- a/tools/intel_gpu_top.c
+++ b/tools/intel_gpu_top.c
@@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
({ \
int fd__; \
\
- fd__ = perf_i915_open_group((pmu)->config, (fd)); \
+ fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
if (fd__ >= 0) { \
if ((fd) == -1) \
(fd) = fd__; \
--
2.25.0.rc0
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for i915/perf: Find the associated perf-type for a particular device
2020-01-03 17:41 ` [igt-dev] " Chris Wilson
(?)
@ 2020-01-03 18:08 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-01-03 18:08 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: i915/perf: Find the associated perf-type for a particular device
URL : https://patchwork.freedesktop.org/series/71609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7674 -> IGTPW_3897
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/index.html
Known issues
------------
Here are the changes found in IGTPW_3897 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [TIMEOUT][2] ([i915#816])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@i915_module_load@reload-with-fault-injection:
- fi-bxt-dsi: [PASS][3] -> [INCOMPLETE][4] ([fdo#103927])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/fi-bxt-dsi/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_execlists:
- fi-kbl-soraka: [PASS][5] -> [DMESG-FAIL][6] ([i915#656])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/fi-kbl-soraka/igt@i915_selftest@live_execlists.html
#### Possible fixes ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6700k2: [INCOMPLETE][7] ([i915#671]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html
- fi-kbl-7500u: [INCOMPLETE][9] ([i915#879]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/fi-kbl-7500u/igt@i915_module_load@reload-with-fault-injection.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/fi-kbl-7500u/igt@i915_module_load@reload-with-fault-injection.html
#### Warnings ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][11] ([i915#725]) -> [DMESG-FAIL][12] ([i915#553] / [i915#725])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/fi-hsw-4770/igt@i915_selftest@live_blt.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/fi-hsw-4770/igt@i915_selftest@live_blt.html
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
[i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#879]: https://gitlab.freedesktop.org/drm/intel/issues/879
Participating hosts (46 -> 40)
------------------------------
Additional (5): fi-hsw-4770r fi-bsw-n3050 fi-ilk-650 fi-elk-e7500 fi-byt-n2820
Missing (11): fi-ehl-1 fi-bdw-5557u fi-hsw-4200u fi-skl-6770hq fi-glk-dsi fi-ctg-p8600 fi-ivb-3770 fi-blb-e6850 fi-tgl-y fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5357 -> IGTPW_3897
CI-20190529: 20190529
CI_DRM_7674: 6cdc2db5a5641dd00f47fcc80b83bb8adb777797 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3897: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/index.html
IGT_5357: a555a4b98f90dab655d24bb3d07e9291a8b8dac8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
2020-01-03 17:41 ` [igt-dev] " Chris Wilson
@ 2020-01-03 21:20 ` Fosha, Robert M
-1 siblings, 0 replies; 6+ messages in thread
From: Fosha, Robert M @ 2020-01-03 21:20 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev
On 1/3/20 9:41 AM, Chris Wilson wrote:
> Since with multiple devices, we may have multiple different perf_pmu
> each with their own type, we want to find the right one for the job.
>
> The tests are run with a specific fd, from which we can extract the
> appropriate bus-id and find the associated perf-type. The performance
> monitoring tools are a little more general and not yet ready to probe
> all device or bind to one in particular, so we just assume the default
> igfx for the time being.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> benchmarks/gem_wsim.c | 4 +-
> lib/igt_perf.c | 66 +++++++++++++++++++++++---
> lib/igt_perf.h | 13 ++++--
> overlay/gem-interrupts.c | 2 +-
> overlay/gpu-freq.c | 4 +-
> overlay/gpu-top.c | 12 ++---
> overlay/rc6.c | 2 +-
> tests/i915/gem_ctx_freq.c | 2 +-
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_balancer.c | 18 +++++---
> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> tools/intel_gpu_top.c | 2 +-
> 12 files changed, 141 insertions(+), 70 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 6305e0d7a..9156fdc90 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> for (d = &engines[0]; d->id != VCS; d++) {
> int pfd;
>
> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> - d->inst),
> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + d->inst),
> bb->fd);
> if (pfd < 0) {
> if (d->id != VCS2)
> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> index e3dec2cc2..4922a2df7 100644
> --- a/lib/igt_perf.c
> +++ b/lib/igt_perf.c
> @@ -4,17 +4,59 @@
> #include <stdlib.h>
> #include <string.h>
> #include <errno.h>
> +#include <sys/ioctl.h>
> #include <sys/sysinfo.h>
>
> #include "igt_perf.h"
>
> -uint64_t i915_type_id(void)
> +const char *i915_perf_device(int i915, char *buf, int buflen)
> +{
> + drm_unique_t u = {
> + .unique = buf + 1,
> + .unique_len = buflen - 1,
> + };
> + drm_set_version_t sv = {
> + .drm_di_major = 1,
> + .drm_di_minor = 4,
> + .drm_dd_major = -1, /* Don't care */
> + .drm_dd_minor = -1, /* Don't care */
> + };
> +
> + if (ioctl(i915, DRM_IOCTL_SET_VERSION, &sv))
> + return "i915";
perf_pmu has test cases that use drm_open_driver_render() and pass the
render_fd. What about this cases?
> +
> + memset(buf, 0, buflen);
> + ioctl(i915, DRM_IOCTL_GET_UNIQUE, &u);
> +
> + if (u.unique_len >= buflen)
> + return NULL;
> +
> + if (strncmp(buf + 1, "pci:", 4))
> + return NULL;
> +
> + if (strcmp(buf + 1, "pci:0000:00:02.0") == 0)
> + return "i915";
> +
> + return memcpy(buf, "i915-", strlen("i915-"));
> +}
> +
> +uint64_t i915_perf_type_id(int i915)
> +{
> + char buf[80];
> +
> + return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
> +}
> +
> +uint64_t igt_perf_type_id(const char *device)
> {
> char buf[64];
> ssize_t ret;
> int fd;
>
> - fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
> + snprintf(buf, sizeof(buf),
> + "/sys/bus/event_source/devices/%s/type", device);
> +
> + fd = open(buf, O_RDONLY);
> if (fd < 0)
> return 0;
>
> @@ -52,15 +94,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
> return ret;
> }
>
> -int perf_i915_open(uint64_t config)
> +int perf_igfx_open(uint64_t config)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, -1,
> + PERF_FORMAT_TOTAL_TIME_ENABLED);
> +}
> +
> +int perf_igfx_open_group(uint64_t config, int group)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, group,
> + PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> +}
> +
> +int perf_i915_open(int i915, uint64_t config)
> {
> - return _perf_open(i915_type_id(), config, -1,
> + return _perf_open(i915_perf_type_id(i915), config, -1,
> PERF_FORMAT_TOTAL_TIME_ENABLED);
> }
>
> -int perf_i915_open_group(uint64_t config, int group)
> +int perf_i915_open_group(int i915, uint64_t config, int group)
> {
> - return _perf_open(i915_type_id(), config, group,
> + return _perf_open(i915_perf_type_id(i915), config, group,
> PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> }
>
> diff --git a/lib/igt_perf.h b/lib/igt_perf.h
> index e00718f47..a8328c70c 100644
> --- a/lib/igt_perf.h
> +++ b/lib/igt_perf.h
> @@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
> return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
> }
>
> -uint64_t i915_type_id(void);
> -int perf_i915_open(uint64_t config);
> -int perf_i915_open_group(uint64_t config, int group);
> +uint64_t igt_perf_type_id(const char *device);
> int igt_perf_open(uint64_t type, uint64_t config);
> int igt_perf_open_group(uint64_t type, uint64_t config, int group);
>
> +const char *i915_perf_device(int i915, char *buf, int buflen);
> +uint64_t i915_perf_type_id(int i915);
> +
> +int perf_igfx_open(uint64_t config);
> +int perf_igfx_open_group(uint64_t config, int group);
> +
> +int perf_i915_open(int i915, uint64_t config);
> +int perf_i915_open_group(int i915, uint64_t config, int group);
> +
> #endif /* I915_PERF_H */
> diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
> index 0233fbb05..be73b6931 100644
> --- a/overlay/gem-interrupts.c
> +++ b/overlay/gem-interrupts.c
> @@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
> {
> memset(irqs, 0, sizeof(*irqs));
>
> - irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
> + irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
> if (irqs->fd < 0 && interrupts_read() < 0)
> irqs->error = ENODEV;
>
> diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
> index 0d8032592..b73157d39 100644
> --- a/overlay/gpu-freq.c
> +++ b/overlay/gpu-freq.c
> @@ -37,8 +37,8 @@ static int perf_open(void)
> {
> int fd;
>
> - fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> - if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> + fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> + if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> close(fd);
> fd = -1;
> }
> diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
> index 6cec2e943..32123abdd 100644
> --- a/overlay/gpu-top.c
> +++ b/overlay/gpu-top.c
> @@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
>
> d = &engines[0];
>
> - gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> + gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> -1);
> if (gt->fd < 0)
> return -1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_wait = 1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_sema = 1;
>
> @@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
> gt->num_rings = 1;
>
> for (d++; d->name; d++) {
> - if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> d->inst),
> gt->fd) < 0)
> continue;
>
> if (gt->have_wait &&
> - perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
>
> if (gt->have_sema &&
> - perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
> diff --git a/overlay/rc6.c b/overlay/rc6.c
> index b5286f0cf..69f95f288 100644
> --- a/overlay/rc6.c
> +++ b/overlay/rc6.c
> @@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
> {
> memset(rc6, 0, sizeof(*rc6));
>
> - rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
> + rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
> if (rc6->fd < 0) {
> struct stat st;
> if (stat("/sys/class/drm/card0/power", &st) < 0)
> diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
> index 89f3d11ef..5d2d3ec31 100644
> --- a/tests/i915/gem_ctx_freq.c
> +++ b/tests/i915/gem_ctx_freq.c
> @@ -136,7 +136,7 @@ static void sysfs_range(int i915)
>
> triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
>
> - pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
> + pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
> igt_require(pmu >= 0);
>
> for (int outer = 0; outer <= 2*N_STEPS; outer++) {
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 48e4411c8..38dc584bc 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
>
> static bool has_engine(int fd, unsigned int class, unsigned int instance)
> {
> - int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
>
> if (pmu >= 0)
> close(pmu);
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index f4909a978..cebcc39c7 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
> {
> int fd;
>
> - fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
> if (fd != -1) {
> close(fd);
> return true;
> @@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
> }
> }
>
> -static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
> +static int
> +add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
> {
> - return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
> + return perf_i915_open_group(i915,
> + I915_PMU_ENGINE_BUSY(ci->engine_class,
> ci->engine_instance),
> pmu);
> }
> @@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
> double load;
> int pmu;
>
> - pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> + pmu = perf_i915_open(i915,
> + I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> ci[idx].engine_instance));
>
> spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
> @@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
>
> pmu[0] = -1;
> for (int i = 0; i < limit; i++)
> - pmu[i] = add_pmu(pmu[0], &siblings[i]);
> - pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
> + pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
> + pmu[limit] = add_pmu(i915,
> + pmu[0], &master_engines[bond]);
>
> igt_assert(siblings[bond].engine_class !=
> master_engines[bond].engine_class);
> @@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
> for (unsigned int n = 0; n < count; n++) {
> uint32_t ctx;
>
> - pmu[n] = add_pmu(pmu[0], &ci[n]);
> + pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
>
> if (flags & PULSE) {
> struct drm_i915_gem_execbuffer2 eb = {
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index e1bbf2410..3e179daef 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
> const double tolerance = 0.05f;
> const unsigned long batch_duration_ns = 500e6;
>
> -static int open_pmu(uint64_t config)
> +static int open_pmu(int i915, uint64_t config)
> {
> int fd;
>
> - fd = perf_i915_open(config);
> + fd = perf_i915_open(i915, config);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> return fd;
> }
>
> -static int open_group(uint64_t config, int group)
> +static int open_group(int i915, uint64_t config, int group)
> {
> int fd;
>
> - fd = perf_i915_open_group(config, group);
> + fd = perf_i915_open_group(i915, config, group);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> @@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> bool exists;
>
> errno = 0;
> - fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> + fd = perf_i915_open(gem_fd,
> + __I915_PMU_ENGINE(e->class, e->instance, sample));
> if (fd < 0)
> err = errno;
>
> @@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val;
> int fd;
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
>
> spin = __spin_sync(gem_fd, 0, e);
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
> * Open PMU as fast as possible after the second spin batch in attempt
> * to be faster than the driver handling lite-restore.
> */
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> if (e->class == e_->class && e->instance == e_->instance)
> busy_idx = i;
>
> - fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> + fd[i++] = open_group(gem_fd,
> + I915_PMU_ENGINE_BUSY(e_->class,
> e_->instance),
> fd[0]);
> }
> @@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val[2][2];
> int fd;
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
> * to expected time spent in semaphore wait state.
> */
>
> - fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -817,8 +820,9 @@ sema_busy(int gem_fd,
>
> igt_require(gem_scheduler_has_semaphores(gem_fd));
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
>
> __for_each_physical_engine(gem_fd, signal) {
> if (e->class == signal->class &&
> @@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
> data.pipe = p;
> prepare_crtc(&data, gem_fd, output);
>
> - fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_WAIT(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd[0] = open_pmu(config);
> + fd[0] = open_pmu(gem_fd, config);
>
> /*
> * Second PMU client which is initialized after the first one,
> * and exists before it, should not affect accounting as reported
> * in the first client.
> */
> - fd[1] = open_pmu(config);
> + fd[1] = open_pmu(gem_fd, config);
>
> spin = spin_sync(gem_fd, 0, e);
>
> @@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> * - cpu != 0 is not supported since i915 PMU only allows running on one cpu
> * and that is normally CPU0.
> */
> -static void invalid_init(void)
> +static void invalid_init(int i915)
> {
> struct perf_event_attr attr;
>
> @@ -1093,7 +1098,7 @@ static void invalid_init(void)
> do { \
> memset(&attr, 0, sizeof (attr)); \
> attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
> - attr.type = i915_type_id(); \
> + attr.type = i915_perf_type_id(i915); \
> igt_assert(attr.type != 0); \
> errno = 0; \
> } while(0)
> @@ -1112,11 +1117,11 @@ do { \
> igt_assert_eq(errno, EINVAL);
> }
>
> -static void init_other(unsigned int i, bool valid)
> +static void init_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
> close(fd);
> }
>
> -static void read_other(unsigned int i, bool valid)
> +static void read_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
>
> igt_require(cpu0_hotplug_support());
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>
> /*
> * Create two spinners so test can ensure shorter gaps in engine
> @@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++) {
> @@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++)
> @@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
> igt_require(max_freq > min_freq);
> igt_require(boost_freq > min_freq);
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> /*
> * Set GPU to min frequency and read PMU counters.
> @@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
>
> /* While parked, our convention is to report the GPU at 0Hz */
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> gem_quiescent_gpu(gem_fd); /* Be idle! */
> measured_usleep(2000); /* Wait for timers to cease */
> @@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_RC6_RESIDENCY);
> + fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>
> if (flags & TEST_RUNTIME_PM) {
> drmModeRes *res;
> @@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
> usleep(500e3);
>
> /* Enable the PMU. */
> - fd = open_pmu(config);
> + fd = open_pmu(gem_fd, config);
>
> /* Stop load and close the PMU. */
> igt_stop_helper(&engine_load);
> @@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> igt_spin_free(gem_fd, spin);
> }
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> /* Let the child run. */
> read(link[0], &expected, sizeof(expected));
> @@ -1835,7 +1841,7 @@ igt_main
> fd = drm_open_driver_master(DRIVER_INTEL);
>
> igt_require_gem(fd);
> - igt_require(i915_type_id() > 0);
> + igt_require(i915_perf_type_id(fd) > 0);
>
> __for_each_physical_engine(fd, e)
> num_engines++;
> @@ -1845,7 +1851,7 @@ igt_main
> * Test invalid access via perf API is rejected.
> */
> igt_subtest("invalid-init")
> - invalid_init();
> + invalid_init(fd);
>
> __for_each_physical_engine(fd, e) {
> const unsigned int pct[] = { 2, 50, 98 };
> @@ -1996,10 +2002,10 @@ igt_main
> */
> for (i = 0; i < num_other_metrics + 1; i++) {
> igt_subtest_f("other-init-%u", i)
> - init_other(i, i < num_other_metrics);
> + init_other(fd, i, i < num_other_metrics);
>
> igt_subtest_f("other-read-%u", i)
> - read_other(i, i < num_other_metrics);
> + read_other(fd, i, i < num_other_metrics);
> }
>
> /**
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index cc8db7c53..8197482dd 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
> ({ \
> int fd__; \
> \
> - fd__ = perf_i915_open_group((pmu)->config, (fd)); \
> + fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
> if (fd__ >= 0) { \
> if ((fd) == -1) \
> (fd) = fd__; \
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device
@ 2020-01-03 21:20 ` Fosha, Robert M
0 siblings, 0 replies; 6+ messages in thread
From: Fosha, Robert M @ 2020-01-03 21:20 UTC (permalink / raw)
To: Chris Wilson, intel-gfx; +Cc: igt-dev, Tvrtko Ursulin
On 1/3/20 9:41 AM, Chris Wilson wrote:
> Since with multiple devices, we may have multiple different perf_pmu
> each with their own type, we want to find the right one for the job.
>
> The tests are run with a specific fd, from which we can extract the
> appropriate bus-id and find the associated perf-type. The performance
> monitoring tools are a little more general and not yet ready to probe
> all device or bind to one in particular, so we just assume the default
> igfx for the time being.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: "Robert M. Fosha" <robert.m.fosha@intel.com>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
> ---
> benchmarks/gem_wsim.c | 4 +-
> lib/igt_perf.c | 66 +++++++++++++++++++++++---
> lib/igt_perf.h | 13 ++++--
> overlay/gem-interrupts.c | 2 +-
> overlay/gpu-freq.c | 4 +-
> overlay/gpu-top.c | 12 ++---
> overlay/rc6.c | 2 +-
> tests/i915/gem_ctx_freq.c | 2 +-
> tests/i915/gem_ctx_sseu.c | 2 +-
> tests/i915/gem_exec_balancer.c | 18 +++++---
> tests/perf_pmu.c | 84 ++++++++++++++++++----------------
> tools/intel_gpu_top.c | 2 +-
> 12 files changed, 141 insertions(+), 70 deletions(-)
>
> diff --git a/benchmarks/gem_wsim.c b/benchmarks/gem_wsim.c
> index 6305e0d7a..9156fdc90 100644
> --- a/benchmarks/gem_wsim.c
> +++ b/benchmarks/gem_wsim.c
> @@ -2268,8 +2268,8 @@ busy_init(const struct workload_balancer *balancer, struct workload *wrk)
> for (d = &engines[0]; d->id != VCS; d++) {
> int pfd;
>
> - pfd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> - d->inst),
> + pfd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + d->inst),
> bb->fd);
> if (pfd < 0) {
> if (d->id != VCS2)
> diff --git a/lib/igt_perf.c b/lib/igt_perf.c
> index e3dec2cc2..4922a2df7 100644
> --- a/lib/igt_perf.c
> +++ b/lib/igt_perf.c
> @@ -4,17 +4,59 @@
> #include <stdlib.h>
> #include <string.h>
> #include <errno.h>
> +#include <sys/ioctl.h>
> #include <sys/sysinfo.h>
>
> #include "igt_perf.h"
>
> -uint64_t i915_type_id(void)
> +const char *i915_perf_device(int i915, char *buf, int buflen)
> +{
> + drm_unique_t u = {
> + .unique = buf + 1,
> + .unique_len = buflen - 1,
> + };
> + drm_set_version_t sv = {
> + .drm_di_major = 1,
> + .drm_di_minor = 4,
> + .drm_dd_major = -1, /* Don't care */
> + .drm_dd_minor = -1, /* Don't care */
> + };
> +
> + if (ioctl(i915, DRM_IOCTL_SET_VERSION, &sv))
> + return "i915";
perf_pmu has test cases that use drm_open_driver_render() and pass the
render_fd. What about this cases?
> +
> + memset(buf, 0, buflen);
> + ioctl(i915, DRM_IOCTL_GET_UNIQUE, &u);
> +
> + if (u.unique_len >= buflen)
> + return NULL;
> +
> + if (strncmp(buf + 1, "pci:", 4))
> + return NULL;
> +
> + if (strcmp(buf + 1, "pci:0000:00:02.0") == 0)
> + return "i915";
> +
> + return memcpy(buf, "i915-", strlen("i915-"));
> +}
> +
> +uint64_t i915_perf_type_id(int i915)
> +{
> + char buf[80];
> +
> + return igt_perf_type_id(i915_perf_device(i915, buf, sizeof(buf)));
> +}
> +
> +uint64_t igt_perf_type_id(const char *device)
> {
> char buf[64];
> ssize_t ret;
> int fd;
>
> - fd = open("/sys/bus/event_source/devices/i915/type", O_RDONLY);
> + snprintf(buf, sizeof(buf),
> + "/sys/bus/event_source/devices/%s/type", device);
> +
> + fd = open(buf, O_RDONLY);
> if (fd < 0)
> return 0;
>
> @@ -52,15 +94,27 @@ _perf_open(uint64_t type, uint64_t config, int group, uint64_t format)
> return ret;
> }
>
> -int perf_i915_open(uint64_t config)
> +int perf_igfx_open(uint64_t config)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, -1,
> + PERF_FORMAT_TOTAL_TIME_ENABLED);
> +}
> +
> +int perf_igfx_open_group(uint64_t config, int group)
> +{
> + return _perf_open(igt_perf_type_id("i915"), config, group,
> + PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> +}
> +
> +int perf_i915_open(int i915, uint64_t config)
> {
> - return _perf_open(i915_type_id(), config, -1,
> + return _perf_open(i915_perf_type_id(i915), config, -1,
> PERF_FORMAT_TOTAL_TIME_ENABLED);
> }
>
> -int perf_i915_open_group(uint64_t config, int group)
> +int perf_i915_open_group(int i915, uint64_t config, int group)
> {
> - return _perf_open(i915_type_id(), config, group,
> + return _perf_open(i915_perf_type_id(i915), config, group,
> PERF_FORMAT_TOTAL_TIME_ENABLED | PERF_FORMAT_GROUP);
> }
>
> diff --git a/lib/igt_perf.h b/lib/igt_perf.h
> index e00718f47..a8328c70c 100644
> --- a/lib/igt_perf.h
> +++ b/lib/igt_perf.h
> @@ -51,10 +51,17 @@ perf_event_open(struct perf_event_attr *attr,
> return syscall(__NR_perf_event_open, attr, pid, cpu, group_fd, flags);
> }
>
> -uint64_t i915_type_id(void);
> -int perf_i915_open(uint64_t config);
> -int perf_i915_open_group(uint64_t config, int group);
> +uint64_t igt_perf_type_id(const char *device);
> int igt_perf_open(uint64_t type, uint64_t config);
> int igt_perf_open_group(uint64_t type, uint64_t config, int group);
>
> +const char *i915_perf_device(int i915, char *buf, int buflen);
> +uint64_t i915_perf_type_id(int i915);
> +
> +int perf_igfx_open(uint64_t config);
> +int perf_igfx_open_group(uint64_t config, int group);
> +
> +int perf_i915_open(int i915, uint64_t config);
> +int perf_i915_open_group(int i915, uint64_t config, int group);
> +
> #endif /* I915_PERF_H */
> diff --git a/overlay/gem-interrupts.c b/overlay/gem-interrupts.c
> index 0233fbb05..be73b6931 100644
> --- a/overlay/gem-interrupts.c
> +++ b/overlay/gem-interrupts.c
> @@ -113,7 +113,7 @@ int gem_interrupts_init(struct gem_interrupts *irqs)
> {
> memset(irqs, 0, sizeof(*irqs));
>
> - irqs->fd = perf_i915_open(I915_PMU_INTERRUPTS);
> + irqs->fd = perf_igfx_open(I915_PMU_INTERRUPTS);
> if (irqs->fd < 0 && interrupts_read() < 0)
> irqs->error = ENODEV;
>
> diff --git a/overlay/gpu-freq.c b/overlay/gpu-freq.c
> index 0d8032592..b73157d39 100644
> --- a/overlay/gpu-freq.c
> +++ b/overlay/gpu-freq.c
> @@ -37,8 +37,8 @@ static int perf_open(void)
> {
> int fd;
>
> - fd = perf_i915_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> - if (perf_i915_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> + fd = perf_igfx_open_group(I915_PMU_ACTUAL_FREQUENCY, -1);
> + if (perf_igfx_open_group(I915_PMU_REQUESTED_FREQUENCY, fd) < 0) {
> close(fd);
> fd = -1;
> }
> diff --git a/overlay/gpu-top.c b/overlay/gpu-top.c
> index 6cec2e943..32123abdd 100644
> --- a/overlay/gpu-top.c
> +++ b/overlay/gpu-top.c
> @@ -58,16 +58,16 @@ static int perf_init(struct gpu_top *gt)
>
> d = &engines[0];
>
> - gt->fd = perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> + gt->fd = perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class, d->inst),
> -1);
> if (gt->fd < 0)
> return -1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_wait = 1;
>
> - if (perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> + if (perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class, d->inst),
> gt->fd) >= 0)
> gt->have_sema = 1;
>
> @@ -75,19 +75,19 @@ static int perf_init(struct gpu_top *gt)
> gt->num_rings = 1;
>
> for (d++; d->name; d++) {
> - if (perf_i915_open_group(I915_PMU_ENGINE_BUSY(d->class,
> + if (perf_igfx_open_group(I915_PMU_ENGINE_BUSY(d->class,
> d->inst),
> gt->fd) < 0)
> continue;
>
> if (gt->have_wait &&
> - perf_i915_open_group(I915_PMU_ENGINE_WAIT(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_WAIT(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
>
> if (gt->have_sema &&
> - perf_i915_open_group(I915_PMU_ENGINE_SEMA(d->class,
> + perf_igfx_open_group(I915_PMU_ENGINE_SEMA(d->class,
> d->inst),
> gt->fd) < 0)
> return -1;
> diff --git a/overlay/rc6.c b/overlay/rc6.c
> index b5286f0cf..69f95f288 100644
> --- a/overlay/rc6.c
> +++ b/overlay/rc6.c
> @@ -39,7 +39,7 @@ int rc6_init(struct rc6 *rc6)
> {
> memset(rc6, 0, sizeof(*rc6));
>
> - rc6->fd = perf_i915_open(I915_PMU_RC6_RESIDENCY);
> + rc6->fd = perf_igfx_open(I915_PMU_RC6_RESIDENCY);
> if (rc6->fd < 0) {
> struct stat st;
> if (stat("/sys/class/drm/card0/power", &st) < 0)
> diff --git a/tests/i915/gem_ctx_freq.c b/tests/i915/gem_ctx_freq.c
> index 89f3d11ef..5d2d3ec31 100644
> --- a/tests/i915/gem_ctx_freq.c
> +++ b/tests/i915/gem_ctx_freq.c
> @@ -136,7 +136,7 @@ static void sysfs_range(int i915)
>
> triangle_fill(frequencies, N_STEPS, sys_min, sys_max);
>
> - pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY);
> + pmu = perf_i915_open(i915, I915_PMU_REQUESTED_FREQUENCY);
> igt_require(pmu >= 0);
>
> for (int outer = 0; outer <= 2*N_STEPS; outer++) {
> diff --git a/tests/i915/gem_ctx_sseu.c b/tests/i915/gem_ctx_sseu.c
> index 48e4411c8..38dc584bc 100644
> --- a/tests/i915/gem_ctx_sseu.c
> +++ b/tests/i915/gem_ctx_sseu.c
> @@ -119,7 +119,7 @@ kernel_has_per_context_sseu_support(int fd)
>
> static bool has_engine(int fd, unsigned int class, unsigned int instance)
> {
> - int pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + int pmu = perf_i915_open(fd, I915_PMU_ENGINE_BUSY(class, instance));
>
> if (pmu >= 0)
> close(pmu);
> diff --git a/tests/i915/gem_exec_balancer.c b/tests/i915/gem_exec_balancer.c
> index f4909a978..cebcc39c7 100644
> --- a/tests/i915/gem_exec_balancer.c
> +++ b/tests/i915/gem_exec_balancer.c
> @@ -60,7 +60,7 @@ static bool has_class_instance(int i915, uint16_t class, uint16_t instance)
> {
> int fd;
>
> - fd = perf_i915_open(I915_PMU_ENGINE_BUSY(class, instance));
> + fd = perf_i915_open(i915, I915_PMU_ENGINE_BUSY(class, instance));
> if (fd != -1) {
> close(fd);
> return true;
> @@ -483,9 +483,11 @@ static void measure_all_load(int pmu, double *v, unsigned int num, int period_us
> }
> }
>
> -static int add_pmu(int pmu, const struct i915_engine_class_instance *ci)
> +static int
> +add_pmu(int i915, int pmu, const struct i915_engine_class_instance *ci)
> {
> - return perf_i915_open_group(I915_PMU_ENGINE_BUSY(ci->engine_class,
> + return perf_i915_open_group(i915,
> + I915_PMU_ENGINE_BUSY(ci->engine_class,
> ci->engine_instance),
> pmu);
> }
> @@ -514,7 +516,8 @@ static void check_individual_engine(int i915,
> double load;
> int pmu;
>
> - pmu = perf_i915_open(I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> + pmu = perf_i915_open(i915,
> + I915_PMU_ENGINE_BUSY(ci[idx].engine_class,
> ci[idx].engine_instance));
>
> spin = igt_spin_new(i915, .ctx = ctx, .engine = idx + 1);
> @@ -636,8 +639,9 @@ static void bonded(int i915, unsigned int flags)
>
> pmu[0] = -1;
> for (int i = 0; i < limit; i++)
> - pmu[i] = add_pmu(pmu[0], &siblings[i]);
> - pmu[limit] = add_pmu(pmu[0], &master_engines[bond]);
> + pmu[i] = add_pmu(i915, pmu[0], &siblings[i]);
> + pmu[limit] = add_pmu(i915,
> + pmu[0], &master_engines[bond]);
>
> igt_assert(siblings[bond].engine_class !=
> master_engines[bond].engine_class);
> @@ -1346,7 +1350,7 @@ static void full(int i915, unsigned int flags)
> for (unsigned int n = 0; n < count; n++) {
> uint32_t ctx;
>
> - pmu[n] = add_pmu(pmu[0], &ci[n]);
> + pmu[n] = add_pmu(i915, pmu[0], &ci[n]);
>
> if (flags & PULSE) {
> struct drm_i915_gem_execbuffer2 eb = {
> diff --git a/tests/perf_pmu.c b/tests/perf_pmu.c
> index e1bbf2410..3e179daef 100644
> --- a/tests/perf_pmu.c
> +++ b/tests/perf_pmu.c
> @@ -50,22 +50,22 @@ IGT_TEST_DESCRIPTION("Test the i915 pmu perf interface");
> const double tolerance = 0.05f;
> const unsigned long batch_duration_ns = 500e6;
>
> -static int open_pmu(uint64_t config)
> +static int open_pmu(int i915, uint64_t config)
> {
> int fd;
>
> - fd = perf_i915_open(config);
> + fd = perf_i915_open(i915, config);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> return fd;
> }
>
> -static int open_group(uint64_t config, int group)
> +static int open_group(int i915, uint64_t config, int group)
> {
> int fd;
>
> - fd = perf_i915_open_group(config, group);
> + fd = perf_i915_open_group(i915, config, group);
> igt_skip_on(fd < 0 && errno == ENODEV);
> igt_assert(fd >= 0);
>
> @@ -79,7 +79,8 @@ init(int gem_fd, const struct intel_execution_engine2 *e, uint8_t sample)
> bool exists;
>
> errno = 0;
> - fd = perf_i915_open(__I915_PMU_ENGINE(e->class, e->instance, sample));
> + fd = perf_i915_open(gem_fd,
> + __I915_PMU_ENGINE(e->class, e->instance, sample));
> if (fd < 0)
> err = errno;
>
> @@ -278,7 +279,7 @@ single(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val;
> int fd;
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -332,7 +333,7 @@ busy_start(int gem_fd, const struct intel_execution_engine2 *e)
>
> spin = __spin_sync(gem_fd, 0, e);
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -384,7 +385,7 @@ busy_double_start(int gem_fd, const struct intel_execution_engine2 *e)
> * Open PMU as fast as possible after the second spin batch in attempt
> * to be faster than the driver handling lite-restore.
> */
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> val = __pmu_read_single(fd, &ts[0]);
> slept = measured_usleep(batch_duration_ns / 1000);
> @@ -453,7 +454,8 @@ busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
> if (e->class == e_->class && e->instance == e_->instance)
> busy_idx = i;
>
> - fd[i++] = open_group(I915_PMU_ENGINE_BUSY(e_->class,
> + fd[i++] = open_group(gem_fd,
> + I915_PMU_ENGINE_BUSY(e_->class,
> e_->instance),
> fd[0]);
> }
> @@ -527,7 +529,7 @@ most_busy_check_all(int gem_fd, const struct intel_execution_engine2 *e,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -581,7 +583,7 @@ all_busy_check_all(int gem_fd, const unsigned int num_engines,
>
> fd[0] = -1;
> for (i = 0; i < num_engines; i++)
> - fd[i] = open_group(val[i], fd[0]);
> + fd[i] = open_group(gem_fd, val[i], fd[0]);
>
> /* Small delay to allow engines to start. */
> usleep(__spin_wait(gem_fd, spin) * num_engines / 1e3);
> @@ -613,8 +615,9 @@ no_sema(int gem_fd, const struct intel_execution_engine2 *e, unsigned int flags)
> uint64_t val[2][2];
> int fd;
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_WAIT(e->class, e->instance), fd);
>
> if (flags & TEST_BUSY)
> spin = spin_sync(gem_fd, 0, e);
> @@ -712,7 +715,7 @@ sema_wait(int gem_fd, const struct intel_execution_engine2 *e,
> * to expected time spent in semaphore wait state.
> */
>
> - fd = open_pmu(I915_PMU_ENGINE_SEMA(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_SEMA(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -817,8 +820,9 @@ sema_busy(int gem_fd,
>
> igt_require(gem_scheduler_has_semaphores(gem_fd));
>
> - fd = open_group(I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> - open_group(I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
> + fd = open_group(gem_fd,
> + I915_PMU_ENGINE_SEMA(e->class, e->instance), -1);
> + open_group(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance), fd);
>
> __for_each_physical_engine(gem_fd, signal) {
> if (e->class == signal->class &&
> @@ -992,7 +996,8 @@ event_wait(int gem_fd, const struct intel_execution_engine2 *e)
> data.pipe = p;
> prepare_crtc(&data, gem_fd, output);
>
> - fd = open_pmu(I915_PMU_ENGINE_WAIT(e->class, e->instance));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_WAIT(e->class, e->instance));
>
> val[0] = pmu_read_single(fd);
>
> @@ -1044,14 +1049,14 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd[0] = open_pmu(config);
> + fd[0] = open_pmu(gem_fd, config);
>
> /*
> * Second PMU client which is initialized after the first one,
> * and exists before it, should not affect accounting as reported
> * in the first client.
> */
> - fd[1] = open_pmu(config);
> + fd[1] = open_pmu(gem_fd, config);
>
> spin = spin_sync(gem_fd, 0, e);
>
> @@ -1085,7 +1090,7 @@ multi_client(int gem_fd, const struct intel_execution_engine2 *e)
> * - cpu != 0 is not supported since i915 PMU only allows running on one cpu
> * and that is normally CPU0.
> */
> -static void invalid_init(void)
> +static void invalid_init(int i915)
> {
> struct perf_event_attr attr;
>
> @@ -1093,7 +1098,7 @@ static void invalid_init(void)
> do { \
> memset(&attr, 0, sizeof (attr)); \
> attr.config = I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0); \
> - attr.type = i915_type_id(); \
> + attr.type = i915_perf_type_id(i915); \
> igt_assert(attr.type != 0); \
> errno = 0; \
> } while(0)
> @@ -1112,11 +1117,11 @@ do { \
> igt_assert_eq(errno, EINVAL);
> }
>
> -static void init_other(unsigned int i, bool valid)
> +static void init_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1128,11 +1133,11 @@ static void init_other(unsigned int i, bool valid)
> close(fd);
> }
>
> -static void read_other(unsigned int i, bool valid)
> +static void read_other(int i915, unsigned int i, bool valid)
> {
> int fd;
>
> - fd = perf_i915_open(__I915_PMU_OTHER(i));
> + fd = perf_i915_open(i915, __I915_PMU_OTHER(i));
> igt_require(!(fd < 0 && errno == ENODEV));
> if (valid) {
> igt_assert(fd >= 0);
> @@ -1163,7 +1168,8 @@ static void cpu_hotplug(int gem_fd)
>
> igt_require(cpu0_hotplug_support());
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
> + fd = open_pmu(gem_fd,
> + I915_PMU_ENGINE_BUSY(I915_ENGINE_CLASS_RENDER, 0));
>
> /*
> * Create two spinners so test can ensure shorter gaps in engine
> @@ -1292,7 +1298,7 @@ test_interrupts(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++) {
> @@ -1355,7 +1361,7 @@ test_interrupts_sync(int gem_fd)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_INTERRUPTS);
> + fd = open_pmu(gem_fd, I915_PMU_INTERRUPTS);
>
> /* Queue spinning batches. */
> for (int i = 0; i < target; i++)
> @@ -1409,8 +1415,8 @@ test_frequency(int gem_fd)
> igt_require(max_freq > min_freq);
> igt_require(boost_freq > min_freq);
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> /*
> * Set GPU to min frequency and read PMU counters.
> @@ -1499,8 +1505,8 @@ test_frequency_idle(int gem_fd)
>
> /* While parked, our convention is to report the GPU at 0Hz */
>
> - fd = open_group(I915_PMU_REQUESTED_FREQUENCY, -1);
> - open_group(I915_PMU_ACTUAL_FREQUENCY, fd);
> + fd = open_group(gem_fd, I915_PMU_REQUESTED_FREQUENCY, -1);
> + open_group(gem_fd, I915_PMU_ACTUAL_FREQUENCY, fd);
>
> gem_quiescent_gpu(gem_fd); /* Be idle! */
> measured_usleep(2000); /* Wait for timers to cease */
> @@ -1554,7 +1560,7 @@ test_rc6(int gem_fd, unsigned int flags)
>
> gem_quiescent_gpu(gem_fd);
>
> - fd = open_pmu(I915_PMU_RC6_RESIDENCY);
> + fd = open_pmu(gem_fd, I915_PMU_RC6_RESIDENCY);
>
> if (flags & TEST_RUNTIME_PM) {
> drmModeRes *res;
> @@ -1651,7 +1657,7 @@ test_enable_race(int gem_fd, const struct intel_execution_engine2 *e)
> usleep(500e3);
>
> /* Enable the PMU. */
> - fd = open_pmu(config);
> + fd = open_pmu(gem_fd, config);
>
> /* Stop load and close the PMU. */
> igt_stop_helper(&engine_load);
> @@ -1797,7 +1803,7 @@ accuracy(int gem_fd, const struct intel_execution_engine2 *e,
> igt_spin_free(gem_fd, spin);
> }
>
> - fd = open_pmu(I915_PMU_ENGINE_BUSY(e->class, e->instance));
> + fd = open_pmu(gem_fd, I915_PMU_ENGINE_BUSY(e->class, e->instance));
>
> /* Let the child run. */
> read(link[0], &expected, sizeof(expected));
> @@ -1835,7 +1841,7 @@ igt_main
> fd = drm_open_driver_master(DRIVER_INTEL);
>
> igt_require_gem(fd);
> - igt_require(i915_type_id() > 0);
> + igt_require(i915_perf_type_id(fd) > 0);
>
> __for_each_physical_engine(fd, e)
> num_engines++;
> @@ -1845,7 +1851,7 @@ igt_main
> * Test invalid access via perf API is rejected.
> */
> igt_subtest("invalid-init")
> - invalid_init();
> + invalid_init(fd);
>
> __for_each_physical_engine(fd, e) {
> const unsigned int pct[] = { 2, 50, 98 };
> @@ -1996,10 +2002,10 @@ igt_main
> */
> for (i = 0; i < num_other_metrics + 1; i++) {
> igt_subtest_f("other-init-%u", i)
> - init_other(i, i < num_other_metrics);
> + init_other(fd, i, i < num_other_metrics);
>
> igt_subtest_f("other-read-%u", i)
> - read_other(i, i < num_other_metrics);
> + read_other(fd, i, i < num_other_metrics);
> }
>
> /**
> diff --git a/tools/intel_gpu_top.c b/tools/intel_gpu_top.c
> index cc8db7c53..8197482dd 100644
> --- a/tools/intel_gpu_top.c
> +++ b/tools/intel_gpu_top.c
> @@ -423,7 +423,7 @@ static const char *imc_data_writes_unit(void)
> ({ \
> int fd__; \
> \
> - fd__ = perf_i915_open_group((pmu)->config, (fd)); \
> + fd__ = perf_igfx_open_group((pmu)->config, (fd)); \
> if (fd__ >= 0) { \
> if ((fd) == -1) \
> (fd) = fd__; \
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for i915/perf: Find the associated perf-type for a particular device
2020-01-03 17:41 ` [igt-dev] " Chris Wilson
` (2 preceding siblings ...)
(?)
@ 2020-01-04 4:54 ` Patchwork
-1 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-01-04 4:54 UTC (permalink / raw)
To: Chris Wilson; +Cc: igt-dev
== Series Details ==
Series: i915/perf: Find the associated perf-type for a particular device
URL : https://patchwork.freedesktop.org/series/71609/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7674_full -> IGTPW_3897_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/index.html
Known issues
------------
Here are the changes found in IGTPW_3897_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@processes:
- shard-tglb: [PASS][1] -> [FAIL][2] ([i915#570])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb1/igt@gem_ctx_persistence@processes.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb1/igt@gem_ctx_persistence@processes.html
* igt@gem_ctx_persistence@vcs1-hostile-preempt:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +1 similar issue
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb4/igt@gem_ctx_persistence@vcs1-hostile-preempt.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb7/igt@gem_ctx_persistence@vcs1-hostile-preempt.html
* igt@gem_ctx_shared@exec-single-timeline-bsd1:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276]) +10 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb1/igt@gem_ctx_shared@exec-single-timeline-bsd1.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb3/igt@gem_ctx_shared@exec-single-timeline-bsd1.html
* igt@gem_ctx_shared@q-smoketest-all:
- shard-tglb: [PASS][7] -> [INCOMPLETE][8] ([fdo#111735])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb7/igt@gem_ctx_shared@q-smoketest-all.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb6/igt@gem_ctx_shared@q-smoketest-all.html
* igt@gem_exec_schedule@reorder-wide-bsd:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#112146]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb7/igt@gem_exec_schedule@reorder-wide-bsd.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb4/igt@gem_exec_schedule@reorder-wide-bsd.html
* igt@gem_persistent_relocs@forked-interruptible-thrash-inactive:
- shard-tglb: [PASS][11] -> [TIMEOUT][12] ([fdo#112126] / [i915#530])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb5/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb1/igt@gem_persistent_relocs@forked-interruptible-thrash-inactive.html
* igt@gem_persistent_relocs@forked-interruptible-thrashing:
- shard-iclb: [PASS][13] -> [TIMEOUT][14] ([i915#530])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb1/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
* igt@gem_ppgtt@blt-vs-render-ctxn:
- shard-tglb: [PASS][15] -> [INCOMPLETE][16] ([i915#470] / [i915#475])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb5/igt@gem_ppgtt@blt-vs-render-ctxn.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb3/igt@gem_ppgtt@blt-vs-render-ctxn.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-kbl: [PASS][17] -> [FAIL][18] ([i915#644])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-kbl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-kbl4/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_sync@basic-all:
- shard-tglb: [PASS][19] -> [INCOMPLETE][20] ([i915#470] / [i915#472])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb7/igt@gem_sync@basic-all.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb1/igt@gem_sync@basic-all.html
* igt@gem_userptr_blits@map-fixed-invalidate-busy:
- shard-snb: [PASS][21] -> [DMESG-WARN][22] ([fdo#111870]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-snb2/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-snb6/igt@gem_userptr_blits@map-fixed-invalidate-busy.html
* igt@i915_selftest@live_gt_timelines:
- shard-tglb: [PASS][23] -> [INCOMPLETE][24] ([i915#455])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb2/igt@i915_selftest@live_gt_timelines.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb3/igt@i915_selftest@live_gt_timelines.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#72])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-glk7/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled:
- shard-snb: [PASS][27] -> [DMESG-WARN][28] ([i915#478])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-snb7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-snb5/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-xtiled.html
* igt@kms_flip@flip-vs-suspend:
- shard-kbl: [PASS][29] -> [DMESG-WARN][30] ([i915#180])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-kbl6/igt@kms_flip@flip-vs-suspend.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-kbl7/igt@kms_flip@flip-vs-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt:
- shard-tglb: [PASS][31] -> [FAIL][32] ([i915#49])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb8/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][33] -> [DMESG-WARN][34] ([i915#180])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-apl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#109441])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb1/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][37] -> [FAIL][38] ([i915#31])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-apl4/igt@kms_setmode@basic.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-apl6/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-accuracy-2-vcs1:
- shard-iclb: [PASS][39] -> [SKIP][40] ([fdo#112080]) +9 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb1/igt@perf_pmu@busy-accuracy-2-vcs1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb6/igt@perf_pmu@busy-accuracy-2-vcs1.html
#### Possible fixes ####
* igt@gem_busy@busy-vcs1:
- shard-iclb: [SKIP][41] ([fdo#112080]) -> [PASS][42] +14 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb5/igt@gem_busy@busy-vcs1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb1/igt@gem_busy@busy-vcs1.html
* igt@gem_busy@close-race:
- shard-tglb: [INCOMPLETE][43] ([i915#435]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb5/igt@gem_busy@close-race.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb7/igt@gem_busy@close-race.html
* igt@gem_ctx_isolation@rcs0-s3:
- shard-kbl: [DMESG-WARN][45] ([i915#180]) -> [PASS][46] +5 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-kbl7/igt@gem_ctx_isolation@rcs0-s3.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-kbl3/igt@gem_ctx_isolation@rcs0-s3.html
- shard-iclb: [DMESG-WARN][47] ([fdo#111764]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb5/igt@gem_ctx_isolation@rcs0-s3.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb5/igt@gem_ctx_isolation@rcs0-s3.html
* igt@gem_ctx_persistence@vcs1-queued:
- shard-iclb: [SKIP][49] ([fdo#109276] / [fdo#112080]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb7/igt@gem_ctx_persistence@vcs1-queued.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb1/igt@gem_ctx_persistence@vcs1-queued.html
* igt@gem_eio@in-flight-contexts-10ms:
- shard-snb: [TIMEOUT][51] ([fdo#111518]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-snb4/igt@gem_eio@in-flight-contexts-10ms.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-snb2/igt@gem_eio@in-flight-contexts-10ms.html
* igt@gem_exec_balancer@nop:
- shard-tglb: [INCOMPLETE][53] ([fdo#111736]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb6/igt@gem_exec_balancer@nop.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb8/igt@gem_exec_balancer@nop.html
* {igt@gem_exec_schedule@pi-userfault-bsd}:
- shard-iclb: [SKIP][55] ([i915#677]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb4/igt@gem_exec_schedule@pi-userfault-bsd.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb6/igt@gem_exec_schedule@pi-userfault-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [SKIP][57] ([fdo#109276]) -> [PASS][58] +15 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb5/igt@gem_exec_schedule@preempt-queue-bsd1.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preempt-queue-chain-render:
- shard-tglb: [INCOMPLETE][59] ([fdo#111606] / [fdo#111677]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb3/igt@gem_exec_schedule@preempt-queue-chain-render.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb6/igt@gem_exec_schedule@preempt-queue-chain-render.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [SKIP][61] ([fdo#112146]) -> [PASS][62] +2 similar issues
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb1/igt@gem_exec_schedule@preempt-self-bsd.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb8/igt@gem_exec_schedule@preempt-self-bsd.html
* igt@gem_exec_suspend@basic-s3:
- shard-tglb: [INCOMPLETE][63] ([fdo#111736] / [i915#460]) -> [PASS][64]
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb3/igt@gem_exec_suspend@basic-s3.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb1/igt@gem_exec_suspend@basic-s3.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [FAIL][65] ([i915#644]) -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-apl1/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_userptr_blits@sync-unmap-cycles:
- shard-snb: [DMESG-WARN][67] ([fdo#111870]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-snb6/igt@gem_userptr_blits@sync-unmap-cycles.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-snb5/igt@gem_userptr_blits@sync-unmap-cycles.html
* {igt@gen9_exec_parse@allowed-all}:
- shard-glk: [DMESG-WARN][69] ([i915#716]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-glk9/igt@gen9_exec_parse@allowed-all.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-glk1/igt@gen9_exec_parse@allowed-all.html
* igt@i915_pm_dc@dc6-psr:
- shard-iclb: [FAIL][71] ([i915#454]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb8/igt@i915_pm_dc@dc6-psr.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb5/igt@i915_pm_dc@dc6-psr.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- shard-apl: [FAIL][73] ([i915#54]) -> [PASS][74] +2 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-apl6/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-apl7/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [FAIL][75] ([i915#54]) -> [PASS][76] +1 similar issue
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-kbl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
- shard-glk: [FAIL][77] ([i915#54]) -> [PASS][78] +1 similar issue
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-glk5/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-glk2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [DMESG-WARN][79] ([i915#180]) -> [PASS][80] +2 similar issues
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt:
- shard-tglb: [FAIL][81] ([i915#49]) -> [PASS][82] +2 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb7/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-plflip-blt.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-kbl: [INCOMPLETE][83] ([fdo#103665]) -> [PASS][84]
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_psr@psr2_cursor_blt:
- shard-iclb: [SKIP][85] ([fdo#109441]) -> [PASS][86]
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb6/igt@kms_psr@psr2_cursor_blt.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv-switch:
- shard-iclb: [SKIP][87] ([fdo#109276] / [fdo#112080]) -> [FAIL][88] ([IGT#28])
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-iclb2/igt@gem_ctx_isolation@vcs1-nonpriv-switch.html
* igt@gem_ctx_isolation@vcs2-dirty-create:
- shard-tglb: [SKIP][89] ([fdo#112080]) -> [SKIP][90] ([fdo#111912] / [fdo#112080])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-create.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb7/igt@gem_ctx_isolation@vcs2-dirty-create.html
* igt@gem_ctx_isolation@vcs2-dirty-switch:
- shard-tglb: [SKIP][91] ([fdo#111912] / [fdo#112080]) -> [SKIP][92] ([fdo#112080])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb2/igt@gem_ctx_isolation@vcs2-dirty-switch.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb9/igt@gem_ctx_isolation@vcs2-dirty-switch.html
* igt@kms_atomic_transition@6x-modeset-transitions:
- shard-tglb: [SKIP][93] ([fdo#112021]) -> [SKIP][94] ([fdo#112016] / [fdo#112021])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7674/shard-tglb9/igt@kms_atomic_transition@6x-modeset-transitions.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/shard-tglb5/igt@kms_atomic_transition@6x-modeset-transitions.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111518]: https://bugs.freedesktop.org/show_bug.cgi?id=111518
[fdo#111606]: https://bugs.freedesktop.org/show_bug.cgi?id=111606
[fdo#111677]: https://bugs.freedesktop.org/show_bug.cgi?id=111677
[fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
[fdo#111736]: https://bugs.freedesktop.org/show_bug.cgi?id=111736
[fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#111912]: https://bugs.freedesktop.org/show_bug.cgi?id=111912
[fdo#112016]: https://bugs.freedesktop.org/show_bug.cgi?id=112016
[fdo#112021]: https://bugs.freedesktop.org/show_bug.cgi?id=112021
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112126]: https://bugs.freedesktop.org/show_bug.cgi?id=112126
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#455]: https://gitlab.freedesktop.org/drm/intel/issues/455
[i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460
[i915#470]: https://gitlab.freedesktop.org/drm/intel/issues/470
[i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472
[i915#475]: https://gitlab.freedesktop.org/drm/intel/issues/475
[i915#478]: https://gitlab.freedesktop.org/drm/intel/issues/478
[i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49
[i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#570]: https://gitlab.freedesktop.org/drm/intel/issues/570
[i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
Participating hosts (10 -> 8)
------------------------------
Missing (2): pig-skl-6260u pig-glk-j5005
Build changes
-------------
* CI: CI-20190529 -> None
* IGT: IGT_5357 -> IGTPW_3897
* Piglit: piglit_4509 -> None
CI-20190529: 20190529
CI_DRM_7674: 6cdc2db5a5641dd00f47fcc80b83bb8adb777797 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_3897: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/index.html
IGT_5357: a555a4b98f90dab655d24bb3d07e9291a8b8dac8 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_3897/index.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-01-04 4:54 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-03 17:41 [Intel-gfx] [PATCH i-g-t] i915/perf: Find the associated perf-type for a particular device Chris Wilson
2020-01-03 17:41 ` [igt-dev] " Chris Wilson
2020-01-03 18:08 ` [igt-dev] ✓ Fi.CI.BAT: success for " Patchwork
2020-01-03 21:20 ` [Intel-gfx] [PATCH i-g-t] " Fosha, Robert M
2020-01-03 21:20 ` [igt-dev] " Fosha, Robert M
2020-01-04 4:54 ` [igt-dev] ✓ Fi.CI.IGT: success for " Patchwork
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