* [RESEND v2,00/10] Add support for MediaTek MT7622 SoC
@ 2020-01-10 8:30 Sam Shih
2020-01-10 8:30 ` [RESEND v2 01/10] ARM: MediaTek: " Sam Shih
` (9 more replies)
0 siblings, 10 replies; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
A gentle ping on this whole patch series
This patch series adds basic boot support on eMMC/SD/spi-nor for the
MediaTek MT7622 SoC based boards. This series add the clock, pinctrl
drivers and the SoC initializaton code.
Change since V1:
- move mt7622/23/29 u-boot properties to -u-boot.dtsi files
- pinctrl: mediatek: add support for different pinctrl:
- use gpio_mode to replace gpio_func for easier understanding
- fix mt7623n bpir2 defconfig
- ARM: MediaTek: Add support for MediaTek MT7622 SoC
- fix dram size in mm_region
Sam Shih (10):
ARM: MediaTek: Add support for MediaTek MT7622 SoC
pinctrl: mediatek: add driver for MT7622
pinctrl: mediatek: add support for different pinctrl
clk: mediatek: add driver for MT7622
clk: mediatek: fix clock-rate overflow problem
power: domain: add power domain support for MT7622
mmc: add mmc and sd support for MT7622
Add support for MT7622 reference board
arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file
configs: mediatek: fix mt7623n bpir2 defconfig
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt7622-rfb.dts | 180 +++++
arch/arm/dts/mt7622-u-boot.dtsi | 29 +
arch/arm/dts/mt7622.dtsi | 185 +++++
arch/arm/dts/mt7623-u-boot.dtsi | 29 +
arch/arm/dts/mt7623.dtsi | 6 -
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 1 +
arch/arm/dts/mt7629-rfb-u-boot.dtsi | 36 +
arch/arm/dts/mt7629-rfb.dts | 1 +
arch/arm/dts/mt7629.dtsi | 9 -
arch/arm/mach-mediatek/Kconfig | 9 +
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7622/Makefile | 3 +
arch/arm/mach-mediatek/mt7622/init.c | 51 ++
board/mediatek/mt7622/Kconfig | 17 +
board/mediatek/mt7622/MAINTAINERS | 6 +
board/mediatek/mt7622/Makefile | 4 +
board/mediatek/mt7622/mt7622_rfb.c | 23 +
configs/mt7622_rfb_defconfig | 55 ++
configs/mt7623n_bpir2_defconfig | 1 +
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7622.c | 678 ++++++++++++++++
drivers/clk/mediatek/clk-mtk.c | 6 +-
drivers/mmc/mtk-sd.c | 10 +
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt7622.c | 754 ++++++++++++++++++
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt8518.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 122 ++-
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 12 +-
drivers/power/domain/mtk-power-domain.c | 6 +
include/configs/mt7622.h | 46 ++
include/dt-bindings/clock/mt7622-clk.h | 271 +++++++
36 files changed, 2529 insertions(+), 37 deletions(-)
create mode 100644 arch/arm/dts/mt7622-rfb.dts
create mode 100644 arch/arm/dts/mt7622-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7622.dtsi
create mode 100644 arch/arm/dts/mt7623-u-boot.dtsi
create mode 100644 arch/arm/mach-mediatek/mt7622/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7622/init.c
create mode 100644 board/mediatek/mt7622/Kconfig
create mode 100644 board/mediatek/mt7622/MAINTAINERS
create mode 100644 board/mediatek/mt7622/Makefile
create mode 100644 board/mediatek/mt7622/mt7622_rfb.c
create mode 100644 configs/mt7622_rfb_defconfig
create mode 100644 drivers/clk/mediatek/clk-mt7622.c
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c
create mode 100644 include/configs/mt7622.h
create mode 100644 include/dt-bindings/clock/mt7622-clk.h
--
2.17.1
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 01/10] ARM: MediaTek: Add support for MediaTek MT7622 SoC
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:42 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 02/10] pinctrl: mediatek: add driver for MT7622 Sam Shih
` (8 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
Add support for MediaTek MT7622 SoC. This include the file
that will initialize the SoC after boot and its device tree.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
arch/arm/dts/mt7622-u-boot.dtsi | 29 ++++
arch/arm/dts/mt7622.dtsi | 185 +++++++++++++++++++++++++
arch/arm/mach-mediatek/Kconfig | 9 ++
arch/arm/mach-mediatek/Makefile | 1 +
arch/arm/mach-mediatek/mt7622/Makefile | 3 +
arch/arm/mach-mediatek/mt7622/init.c | 51 +++++++
6 files changed, 278 insertions(+)
create mode 100644 arch/arm/dts/mt7622-u-boot.dtsi
create mode 100644 arch/arm/dts/mt7622.dtsi
create mode 100644 arch/arm/mach-mediatek/mt7622/Makefile
create mode 100644 arch/arm/mach-mediatek/mt7622/init.c
diff --git a/arch/arm/dts/mt7622-u-boot.dtsi b/arch/arm/dts/mt7622-u-boot.dtsi
new file mode 100644
index 0000000000..b14b1d4344
--- /dev/null
+++ b/arch/arm/dts/mt7622-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&snfi {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt7622.dtsi b/arch/arm/dts/mt7622.dtsi
new file mode 100644
index 0000000000..7dcca5c6af
--- /dev/null
+++ b/arch/arm/dts/mt7622.dtsi
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+
+/ {
+ compatible = "mediatek,mt7622";
+ interrupt-parent = <&sysirq>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x0>;
+ clock-frequency = <1300000000>;
+ };
+
+ cpu1: cpu at 1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53";
+ reg = <0x1>;
+ clock-frequency = <1300000000>;
+ };
+ };
+
+ snfi: snfi at 1100d000 {
+ compatible = "mediatek,mtk-snfi-spi";
+ reg = <0x1100d000 0x2000>;
+ clocks = <&pericfg CLK_PERI_NFI_PD>,
+ <&pericfg CLK_PERI_SNFI_PD>;
+ clock-names = "nfi_clk", "pad_clk";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>,
+ <&topckgen CLK_TOP_NFI_INFRA_SEL>;
+
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>,
+ <&topckgen CLK_TOP_UNIVPLL2_D8>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ arm,cpu-registers-not-fw-configured;
+ };
+
+ timer0: timer at 10004000 {
+ compatible = "mediatek,timer";
+ reg = <0x10004000 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&system_clk>;
+ clock-names = "system-clk";
+ };
+
+ system_clk: dummy13m {
+ compatible = "fixed-clock";
+ clock-frequency = <13000000>;
+ #clock-cells = <0>;
+ };
+
+ infracfg: infracfg at 10000000 {
+ compatible = "mediatek,mt7622-infracfg",
+ "syscon";
+ reg = <0x10000000 0x1000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+ };
+
+ pericfg: pericfg at 10002000 {
+ compatible = "mediatek,mt7622-pericfg", "syscon";
+ reg = <0x10002000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ scpsys: scpsys at 10006000 {
+ compatible = "mediatek,mt7622-scpsys",
+ "syscon";
+ #power-domain-cells = <1>;
+ reg = <0x10006000 0x1000>;
+ interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
+ infracfg = <&infracfg>;
+ clocks = <&topckgen CLK_TOP_HIF_SEL>;
+ clock-names = "hif_sel";
+ };
+
+ sysirq: interrupt-controller at 10200620 {
+ compatible = "mediatek,sysirq";
+ reg = <0x10200620 0x20>;
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ };
+
+ apmixedsys: apmixedsys at 10209000 {
+ compatible = "mediatek,mt7622-apmixedsys";
+ reg = <0x10209000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ topckgen: topckgen at 10210000 {
+ compatible = "mediatek,mt7622-topckgen";
+ reg = <0x10210000 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pinctrl: pinctrl at 10211000 {
+ compatible = "mediatek,mt7622-pinctrl";
+ reg = <0x10211000 0x1000>;
+ gpio: gpio-controller {
+ gpio-controller;
+ #gpio-cells = <2>;
+ };
+ };
+
+ watchdog: watchdog at 10212000 {
+ compatible = "mediatek,wdt";
+ reg = <0x10212000 0x800>;
+ };
+
+ gic: interrupt-controller at 10300000 {
+ compatible = "arm,gic-400";
+ interrupt-controller;
+ #interrupt-cells = <3>;
+ interrupt-parent = <&gic>;
+ reg = <0x10310000 0x1000>,
+ <0x10320000 0x1000>,
+ <0x10340000 0x2000>,
+ <0x10360000 0x2000>;
+ };
+
+ uart0: serial at 11002000 {
+ compatible = "mediatek,hsuart";
+ reg = <0x11002000 0x400>;
+ reg-shift = <2>;
+ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_UART_SEL>,
+ <&pericfg CLK_PERI_UART0_PD>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
+ };
+
+ mmc0: mmc at 11230000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x11230000 0x1000>;
+ interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
+ <&topckgen CLK_TOP_MSDC50_0_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+
+ mmc1: mmc at 11240000 {
+ compatible = "mediatek,mt7622-mmc";
+ reg = <0x11240000 0x1000>;
+ interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
+ <&topckgen CLK_TOP_AXI_SEL>;
+ clock-names = "source", "hclk";
+ status = "disabled";
+ };
+};
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index ad453a60c1..908ca48b47 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -9,6 +9,14 @@ config SYS_VENDOR
choice
prompt "MediaTek board select"
+config TARGET_MT7622
+ bool "MediaTek MT7622 SoC"
+ select ARM64
+ help
+ The MediaTek MT7622 is a ARM64-based SoC with a dual-core Cortex-A53.
+ including UART, SPI, USB3.0, SD and MMC cards, NAND, SNFI, PWM, PCIe,
+ Gigabit Ethernet, I2C, built-in Wi-Fi, and PCIe.
+
config TARGET_MT7623
bool "MediaTek MT7623 SoC"
select CPU_V7A
@@ -49,6 +57,7 @@ config TARGET_MT8518
endchoice
+source "board/mediatek/mt7622/Kconfig"
source "board/mediatek/mt7623/Kconfig"
source "board/mediatek/mt7629/Kconfig"
source "board/mediatek/mt8518/Kconfig"
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile
index b9b2355e03..7e1e4a986c 100644
--- a/arch/arm/mach-mediatek/Makefile
+++ b/arch/arm/mach-mediatek/Makefile
@@ -3,6 +3,7 @@
obj-y += cpu.o
obj-$(CONFIG_SPL_BUILD) += spl.o
+obj-$(CONFIG_TARGET_MT7622) += mt7622/
obj-$(CONFIG_TARGET_MT7623) += mt7623/
obj-$(CONFIG_TARGET_MT7629) += mt7629/
obj-$(CONFIG_TARGET_MT8516) += mt8516/
diff --git a/arch/arm/mach-mediatek/mt7622/Makefile b/arch/arm/mach-mediatek/mt7622/Makefile
new file mode 100644
index 0000000000..886ab7e4eb
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7622/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += init.o
diff --git a/arch/arm/mach-mediatek/mt7622/init.c b/arch/arm/mach-mediatek/mt7622/init.c
new file mode 100644
index 0000000000..1e527c0485
--- /dev/null
+++ b/arch/arm/mach-mediatek/mt7622/init.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <common.h>
+#include <fdtdec.h>
+#include <asm/armv8/mmu.h>
+
+int print_cpuinfo(void)
+{
+ printf("CPU: MediaTek MT7622\n");
+ return 0;
+}
+
+int dram_init(void)
+{
+ int ret;
+
+ ret = fdtdec_setup_memory_banksize();
+ if (ret)
+ return ret;
+ return fdtdec_setup_mem_size_base();
+
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
+
+static struct mm_region mt7622_mem_map[] = {
+ {
+ /* DDR */
+ .virt = 0x40000000UL,
+ .phys = 0x40000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,
+ }, {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x40000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ 0,
+ }
+};
+struct mm_region *mem_map = mt7622_mem_map;
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 02/10] pinctrl: mediatek: add driver for MT7622
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
2020-01-10 8:30 ` [RESEND v2 01/10] ARM: MediaTek: " Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 03/10] pinctrl: mediatek: add support for different pinctrl Sam Shih
` (7 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch add Pinctrl driver for MediaTek MT7622 SoC.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pinctrl/mediatek/Kconfig | 4 +
drivers/pinctrl/mediatek/Makefile | 1 +
drivers/pinctrl/mediatek/pinctrl-mt7622.c | 752 ++++++++++++++++++++++
3 files changed, 757 insertions(+)
create mode 100644 drivers/pinctrl/mediatek/pinctrl-mt7622.c
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 22ee62362b..b5d0baee38 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -4,6 +4,10 @@ config PINCTRL_MTK
depends on PINCTRL_GENERIC
bool
+config PINCTRL_MT7622
+ bool "MT7622 SoC pinctrl driver"
+ select PINCTRL_MTK
+
config PINCTRL_MT7623
bool "MT7623 SoC pinctrl driver"
select PINCTRL_MTK
--- a/drivers/pinctrl/mediatek/Makefile
+++ b/drivers/pinctrl/mediatek/Makefile
@@ -3,6 +3,7 @@
obj-$(CONFIG_PINCTRL_MTK) += pinctrl-mtk-common.o
# SoC Drivers
+obj-$(CONFIG_PINCTRL_MT7622) += pinctrl-mt7622.o
obj-$(CONFIG_PINCTRL_MT7623) += pinctrl-mt7623.o
obj-$(CONFIG_PINCTRL_MT7629) += pinctrl-mt7629.o
obj-$(CONFIG_PINCTRL_MT8516) += pinctrl-mt8516.o
--- /dev/null
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -0,0 +1,752 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <dm.h>
+
+#include "pinctrl-mtk-common.h"
+
+#define MT7622_PIN(_number, _name) MTK_PIN(_number, _name, DRV_GRP1)
+
+#define PIN_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 0)
+
+#define PINS_FIELD(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, _x_bits) \
+ PIN_FIELD_CALC(_s_pin, _e_pin, _s_addr, _x_addrs, _s_bit, \
+ _x_bits, 32, 1)
+
+static const struct mtk_pin_field_calc mt7622_pin_mode_range[] = {
+ PIN_FIELD(0, 0, 0x320, 0x10, 16, 4),
+ PIN_FIELD(1, 4, 0x3a0, 0x10, 16, 4),
+ PIN_FIELD(5, 5, 0x320, 0x10, 0, 4),
+ PINS_FIELD(6, 7, 0x300, 0x10, 4, 4),
+ PIN_FIELD(8, 9, 0x350, 0x10, 20, 4),
+ PINS_FIELD(10, 13, 0x300, 0x10, 8, 4),
+ PIN_FIELD(14, 15, 0x320, 0x10, 4, 4),
+ PIN_FIELD(16, 17, 0x320, 0x10, 20, 4),
+ PIN_FIELD(18, 21, 0x310, 0x10, 16, 4),
+ PIN_FIELD(22, 22, 0x380, 0x10, 16, 4),
+ PINS_FIELD(23, 24, 0x300, 0x10, 24, 4),
+ PINS_FIELD(25, 36, 0x300, 0x10, 12, 4),
+ PINS_FIELD(37, 50, 0x300, 0x10, 20, 4),
+ PIN_FIELD(51, 70, 0x330, 0x10, 4, 4),
+ PINS_FIELD(71, 72, 0x300, 0x10, 16, 4),
+ PIN_FIELD(73, 76, 0x310, 0x10, 0, 4),
+ PIN_FIELD(77, 77, 0x320, 0x10, 28, 4),
+ PIN_FIELD(78, 78, 0x320, 0x10, 12, 4),
+ PIN_FIELD(79, 82, 0x3a0, 0x10, 0, 4),
+ PIN_FIELD(83, 83, 0x350, 0x10, 28, 4),
+ PIN_FIELD(84, 84, 0x330, 0x10, 0, 4),
+ PIN_FIELD(85, 90, 0x360, 0x10, 4, 4),
+ PIN_FIELD(91, 94, 0x390, 0x10, 16, 4),
+ PIN_FIELD(95, 97, 0x380, 0x10, 20, 4),
+ PIN_FIELD(98, 101, 0x390, 0x10, 0, 4),
+ PIN_FIELD(102, 102, 0x360, 0x10, 0, 4),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_dir_range[] = {
+ PIN_FIELD(0, 102, 0x0, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_di_range[] = {
+ PIN_FIELD(0, 102, 0x200, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_do_range[] = {
+ PIN_FIELD(0, 102, 0x100, 0x10, 0, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_smt_range[] = {
+ PIN_FIELD(0, 31, 0x920, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa20, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x820, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb20, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb20, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc20, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb20, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_pu_range[] = {
+ PIN_FIELD(0, 31, 0x930, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa30, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x830, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb30, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb30, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc30, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb30, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_pd_range[] = {
+ PIN_FIELD(0, 31, 0x940, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa40, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x840, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb40, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb40, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc40, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb40, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_e4_range[] = {
+ PIN_FIELD(0, 31, 0x960, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa60, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x860, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb60, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb60, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc60, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb60, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_field_calc mt7622_pin_e8_range[] = {
+ PIN_FIELD(0, 31, 0x970, 0x10, 0, 1),
+ PIN_FIELD(32, 50, 0xa70, 0x10, 0, 1),
+ PIN_FIELD(51, 70, 0x870, 0x10, 0, 1),
+ PIN_FIELD(71, 72, 0xb70, 0x10, 0, 1),
+ PIN_FIELD(73, 86, 0xb70, 0x10, 4, 1),
+ PIN_FIELD(87, 90, 0xc70, 0x10, 0, 1),
+ PIN_FIELD(91, 102, 0xb70, 0x10, 18, 1),
+};
+
+static const struct mtk_pin_reg_calc mt7622_reg_cals[PINCTRL_PIN_REG_MAX] = {
+ [PINCTRL_PIN_REG_MODE] = MTK_RANGE(mt7622_pin_mode_range),
+ [PINCTRL_PIN_REG_DIR] = MTK_RANGE(mt7622_pin_dir_range),
+ [PINCTRL_PIN_REG_DI] = MTK_RANGE(mt7622_pin_di_range),
+ [PINCTRL_PIN_REG_DO] = MTK_RANGE(mt7622_pin_do_range),
+ [PINCTRL_PIN_REG_SMT] = MTK_RANGE(mt7622_pin_smt_range),
+ [PINCTRL_PIN_REG_PU] = MTK_RANGE(mt7622_pin_pu_range),
+ [PINCTRL_PIN_REG_PD] = MTK_RANGE(mt7622_pin_pd_range),
+ [PINCTRL_PIN_REG_E4] = MTK_RANGE(mt7622_pin_e4_range),
+ [PINCTRL_PIN_REG_E8] = MTK_RANGE(mt7622_pin_e8_range),
+};
+
+static const struct mtk_pin_desc mt7622_pins[] = {
+ MT7622_PIN(0, "GPIO_A"),
+ MT7622_PIN(1, "I2S1_IN"),
+ MT7622_PIN(2, "I2S1_OUT"),
+ MT7622_PIN(3, "I2S_BCLK"),
+ MT7622_PIN(4, "I2S_WS"),
+ MT7622_PIN(5, "I2S_MCLK"),
+ MT7622_PIN(6, "TXD0"),
+ MT7622_PIN(7, "RXD0"),
+ MT7622_PIN(8, "SPI_WP"),
+ MT7622_PIN(9, "SPI_HOLD"),
+ MT7622_PIN(10, "SPI_CLK"),
+ MT7622_PIN(11, "SPI_MOSI"),
+ MT7622_PIN(12, "SPI_MISO"),
+ MT7622_PIN(13, "SPI_CS"),
+ MT7622_PIN(14, "I2C_SDA"),
+ MT7622_PIN(15, "I2C_SCL"),
+ MT7622_PIN(16, "I2S2_IN"),
+ MT7622_PIN(17, "I2S3_IN"),
+ MT7622_PIN(18, "I2S4_IN"),
+ MT7622_PIN(19, "I2S2_OUT"),
+ MT7622_PIN(20, "I2S3_OUT"),
+ MT7622_PIN(21, "I2S4_OUT"),
+ MT7622_PIN(22, "GPIO_B"),
+ MT7622_PIN(23, "MDC"),
+ MT7622_PIN(24, "MDIO"),
+ MT7622_PIN(25, "G2_TXD0"),
+ MT7622_PIN(26, "G2_TXD1"),
+ MT7622_PIN(27, "G2_TXD2"),
+ MT7622_PIN(28, "G2_TXD3"),
+ MT7622_PIN(29, "G2_TXEN"),
+ MT7622_PIN(30, "G2_TXC"),
+ MT7622_PIN(31, "G2_RXD0"),
+ MT7622_PIN(32, "G2_RXD1"),
+ MT7622_PIN(33, "G2_RXD2"),
+ MT7622_PIN(34, "G2_RXD3"),
+ MT7622_PIN(35, "G2_RXDV"),
+ MT7622_PIN(36, "G2_RXC"),
+ MT7622_PIN(37, "NCEB"),
+ MT7622_PIN(38, "NWEB"),
+ MT7622_PIN(39, "NREB"),
+ MT7622_PIN(40, "NDL4"),
+ MT7622_PIN(41, "NDL5"),
+ MT7622_PIN(42, "NDL6"),
+ MT7622_PIN(43, "NDL7"),
+ MT7622_PIN(44, "NRB"),
+ MT7622_PIN(45, "NCLE"),
+ MT7622_PIN(46, "NALE"),
+ MT7622_PIN(47, "NDL0"),
+ MT7622_PIN(48, "NDL1"),
+ MT7622_PIN(49, "NDL2"),
+ MT7622_PIN(50, "NDL3"),
+ MT7622_PIN(51, "MDI_TP_P0"),
+ MT7622_PIN(52, "MDI_TN_P0"),
+ MT7622_PIN(53, "MDI_RP_P0"),
+ MT7622_PIN(54, "MDI_RN_P0"),
+ MT7622_PIN(55, "MDI_TP_P1"),
+ MT7622_PIN(56, "MDI_TN_P1"),
+ MT7622_PIN(57, "MDI_RP_P1"),
+ MT7622_PIN(58, "MDI_RN_P1"),
+ MT7622_PIN(59, "MDI_RP_P2"),
+ MT7622_PIN(60, "MDI_RN_P2"),
+ MT7622_PIN(61, "MDI_TP_P2"),
+ MT7622_PIN(62, "MDI_TN_P2"),
+ MT7622_PIN(63, "MDI_TP_P3"),
+ MT7622_PIN(64, "MDI_TN_P3"),
+ MT7622_PIN(65, "MDI_RP_P3"),
+ MT7622_PIN(66, "MDI_RN_P3"),
+ MT7622_PIN(67, "MDI_RP_P4"),
+ MT7622_PIN(68, "MDI_RN_P4"),
+ MT7622_PIN(69, "MDI_TP_P4"),
+ MT7622_PIN(70, "MDI_TN_P4"),
+ MT7622_PIN(71, "PMIC_SCL"),
+ MT7622_PIN(72, "PMIC_SDA"),
+ MT7622_PIN(73, "SPIC1_CLK"),
+ MT7622_PIN(74, "SPIC1_MOSI"),
+ MT7622_PIN(75, "SPIC1_MISO"),
+ MT7622_PIN(76, "SPIC1_CS"),
+ MT7622_PIN(77, "GPIO_D"),
+ MT7622_PIN(78, "WATCHDOG"),
+ MT7622_PIN(79, "RTS3_N"),
+ MT7622_PIN(80, "CTS3_N"),
+ MT7622_PIN(81, "TXD3"),
+ MT7622_PIN(82, "RXD3"),
+ MT7622_PIN(83, "PERST0_N"),
+ MT7622_PIN(84, "PERST1_N"),
+ MT7622_PIN(85, "WLED_N"),
+ MT7622_PIN(86, "EPHY_LED0_N"),
+ MT7622_PIN(87, "AUXIN0"),
+ MT7622_PIN(88, "AUXIN1"),
+ MT7622_PIN(89, "AUXIN2"),
+ MT7622_PIN(90, "AUXIN3"),
+ MT7622_PIN(91, "TXD4"),
+ MT7622_PIN(92, "RXD4"),
+ MT7622_PIN(93, "RTS4_N"),
+ MT7622_PIN(94, "CTS4_N"),
+ MT7622_PIN(95, "PWM1"),
+ MT7622_PIN(96, "PWM2"),
+ MT7622_PIN(97, "PWM3"),
+ MT7622_PIN(98, "PWM4"),
+ MT7622_PIN(99, "PWM5"),
+ MT7622_PIN(100, "PWM6"),
+ MT7622_PIN(101, "PWM7"),
+ MT7622_PIN(102, "GPIO_E"),
+};
+
+/* List all groups consisting of these pins dedicated to the enablement of
+ * certain hardware block and the corresponding mode for all of the pins. The
+ * hardware probably has multiple combinations of these pinouts.
+ */
+
+/* EMMC */
+static int mt7622_emmc_pins[] = { 40, 41, 42, 43, 44, 45, 47, 48, 49, 50, };
+static int mt7622_emmc_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, };
+
+static int mt7622_emmc_rst_pins[] = { 37, };
+static int mt7622_emmc_rst_funcs[] = { 1, };
+
+/* LED for EPHY */
+static int mt7622_ephy_leds_pins[] = { 86, 91, 92, 93, 94, };
+static int mt7622_ephy_leds_funcs[] = { 0, 0, 0, 0, 0, };
+static int mt7622_ephy0_led_pins[] = { 86, };
+static int mt7622_ephy0_led_funcs[] = { 0, };
+static int mt7622_ephy1_led_pins[] = { 91, };
+static int mt7622_ephy1_led_funcs[] = { 2, };
+static int mt7622_ephy2_led_pins[] = { 92, };
+static int mt7622_ephy2_led_funcs[] = { 2, };
+static int mt7622_ephy3_led_pins[] = { 93, };
+static int mt7622_ephy3_led_funcs[] = { 2, };
+static int mt7622_ephy4_led_pins[] = { 94, };
+static int mt7622_ephy4_led_funcs[] = { 2, };
+
+/* Embedded Switch */
+static int mt7622_esw_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61,
+ 62, 63, 64, 65, 66, 67, 68, 69, 70, };
+static int mt7622_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+static int mt7622_esw_p0_p1_pins[] = { 51, 52, 53, 54, 55, 56, 57, 58, };
+static int mt7622_esw_p0_p1_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, };
+static int mt7622_esw_p2_p3_p4_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66, 67,
+ 68, 69, 70, };
+static int mt7622_esw_p2_p3_p4_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, };
+/* RGMII via ESW */
+static int mt7622_rgmii_via_esw_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
+ 67, 68, 69, 70, };
+static int mt7622_rgmii_via_esw_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, };
+
+/* RGMII via GMAC1 */
+static int mt7622_rgmii_via_gmac1_pins[] = { 59, 60, 61, 62, 63, 64, 65, 66,
+ 67, 68, 69, 70, };
+static int mt7622_rgmii_via_gmac1_funcs[] = { 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2,
+ 2, };
+
+/* RGMII via GMAC2 */
+static int mt7622_rgmii_via_gmac2_pins[] = { 25, 26, 27, 28, 29, 30, 31, 32,
+ 33, 34, 35, 36, };
+static int mt7622_rgmii_via_gmac2_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, };
+
+/* I2C */
+static int mt7622_i2c0_pins[] = { 14, 15, };
+static int mt7622_i2c0_funcs[] = { 0, 0, };
+static int mt7622_i2c1_0_pins[] = { 55, 56, };
+static int mt7622_i2c1_0_funcs[] = { 0, 0, };
+static int mt7622_i2c1_1_pins[] = { 73, 74, };
+static int mt7622_i2c1_1_funcs[] = { 3, 3, };
+static int mt7622_i2c1_2_pins[] = { 87, 88, };
+static int mt7622_i2c1_2_funcs[] = { 0, 0, };
+static int mt7622_i2c2_0_pins[] = { 57, 58, };
+static int mt7622_i2c2_0_funcs[] = { 0, 0, };
+static int mt7622_i2c2_1_pins[] = { 75, 76, };
+static int mt7622_i2c2_1_funcs[] = { 3, 3, };
+static int mt7622_i2c2_2_pins[] = { 89, 90, };
+static int mt7622_i2c2_2_funcs[] = { 0, 0, };
+
+/* I2S */
+static int mt7622_i2s_in_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static int mt7622_i2s_in_mclk_bclk_ws_funcs[] = { 3, 3, 0, };
+static int mt7622_i2s1_in_data_pins[] = { 1, };
+static int mt7622_i2s1_in_data_funcs[] = { 0, };
+static int mt7622_i2s2_in_data_pins[] = { 16, };
+static int mt7622_i2s2_in_data_funcs[] = { 0, };
+static int mt7622_i2s3_in_data_pins[] = { 17, };
+static int mt7622_i2s3_in_data_funcs[] = { 0, };
+static int mt7622_i2s4_in_data_pins[] = { 18, };
+static int mt7622_i2s4_in_data_funcs[] = { 0, };
+static int mt7622_i2s_out_mclk_bclk_ws_pins[] = { 3, 4, 5, };
+static int mt7622_i2s_out_mclk_bclk_ws_funcs[] = { 0, 0, 0, };
+static int mt7622_i2s1_out_data_pins[] = { 2, };
+static int mt7622_i2s1_out_data_funcs[] = { 0, };
+static int mt7622_i2s2_out_data_pins[] = { 19, };
+static int mt7622_i2s2_out_data_funcs[] = { 0, };
+static int mt7622_i2s3_out_data_pins[] = { 20, };
+static int mt7622_i2s3_out_data_funcs[] = { 0, };
+static int mt7622_i2s4_out_data_pins[] = { 21, };
+static int mt7622_i2s4_out_data_funcs[] = { 0, };
+
+/* IR */
+static int mt7622_ir_0_tx_pins[] = { 16, };
+static int mt7622_ir_0_tx_funcs[] = { 4, };
+static int mt7622_ir_1_tx_pins[] = { 59, };
+static int mt7622_ir_1_tx_funcs[] = { 5, };
+static int mt7622_ir_2_tx_pins[] = { 99, };
+static int mt7622_ir_2_tx_funcs[] = { 3, };
+static int mt7622_ir_0_rx_pins[] = { 17, };
+static int mt7622_ir_0_rx_funcs[] = { 4, };
+static int mt7622_ir_1_rx_pins[] = { 60, };
+static int mt7622_ir_1_rx_funcs[] = { 5, };
+static int mt7622_ir_2_rx_pins[] = { 100, };
+static int mt7622_ir_2_rx_funcs[] = { 3, };
+
+/* MDIO */
+static int mt7622_mdc_mdio_pins[] = { 23, 24, };
+static int mt7622_mdc_mdio_funcs[] = { 0, 0, };
+
+/* PCIE */
+static int mt7622_pcie0_0_waken_pins[] = { 14, };
+static int mt7622_pcie0_0_waken_funcs[] = { 2, };
+static int mt7622_pcie0_0_clkreq_pins[] = { 15, };
+static int mt7622_pcie0_0_clkreq_funcs[] = { 2, };
+static int mt7622_pcie0_1_waken_pins[] = { 79, };
+static int mt7622_pcie0_1_waken_funcs[] = { 4, };
+static int mt7622_pcie0_1_clkreq_pins[] = { 80, };
+static int mt7622_pcie0_1_clkreq_funcs[] = { 4, };
+static int mt7622_pcie1_0_waken_pins[] = { 14, };
+static int mt7622_pcie1_0_waken_funcs[] = { 3, };
+static int mt7622_pcie1_0_clkreq_pins[] = { 15, };
+static int mt7622_pcie1_0_clkreq_funcs[] = { 3, };
+
+static int mt7622_pcie0_pad_perst_pins[] = { 83, };
+static int mt7622_pcie0_pad_perst_funcs[] = { 0, };
+static int mt7622_pcie1_pad_perst_pins[] = { 84, };
+static int mt7622_pcie1_pad_perst_funcs[] = { 0, };
+
+/* PMIC bus */
+static int mt7622_pmic_bus_pins[] = { 71, 72, };
+static int mt7622_pmic_bus_funcs[] = { 0, 0, };
+
+/* Parallel NAND */
+static int mt7622_pnand_pins[] = { 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, };
+static int mt7622_pnand_funcs[] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, };
+
+/* PWM */
+static int mt7622_pwm_ch1_0_pins[] = { 51, };
+static int mt7622_pwm_ch1_0_funcs[] = { 3, };
+static int mt7622_pwm_ch1_1_pins[] = { 73, };
+static int mt7622_pwm_ch1_1_funcs[] = { 4, };
+static int mt7622_pwm_ch1_2_pins[] = { 95, };
+static int mt7622_pwm_ch1_2_funcs[] = { 0, };
+static int mt7622_pwm_ch2_0_pins[] = { 52, };
+static int mt7622_pwm_ch2_0_funcs[] = { 3, };
+static int mt7622_pwm_ch2_1_pins[] = { 74, };
+static int mt7622_pwm_ch2_1_funcs[] = { 4, };
+static int mt7622_pwm_ch2_2_pins[] = { 96, };
+static int mt7622_pwm_ch2_2_funcs[] = { 0, };
+static int mt7622_pwm_ch3_0_pins[] = { 53, };
+static int mt7622_pwm_ch3_0_funcs[] = { 3, };
+static int mt7622_pwm_ch3_1_pins[] = { 75, };
+static int mt7622_pwm_ch3_1_funcs[] = { 4, };
+static int mt7622_pwm_ch3_2_pins[] = { 97, };
+static int mt7622_pwm_ch3_2_funcs[] = { 0, };
+static int mt7622_pwm_ch4_0_pins[] = { 54, };
+static int mt7622_pwm_ch4_0_funcs[] = { 3, };
+static int mt7622_pwm_ch4_1_pins[] = { 67, };
+static int mt7622_pwm_ch4_1_funcs[] = { 3, };
+static int mt7622_pwm_ch4_2_pins[] = { 76, };
+static int mt7622_pwm_ch4_2_funcs[] = { 4, };
+static int mt7622_pwm_ch4_3_pins[] = { 98, };
+static int mt7622_pwm_ch4_3_funcs[] = { 0, };
+static int mt7622_pwm_ch5_0_pins[] = { 68, };
+static int mt7622_pwm_ch5_0_funcs[] = { 3, };
+static int mt7622_pwm_ch5_1_pins[] = { 77, };
+static int mt7622_pwm_ch5_1_funcs[] = { 4, };
+static int mt7622_pwm_ch5_2_pins[] = { 99, };
+static int mt7622_pwm_ch5_2_funcs[] = { 0, };
+static int mt7622_pwm_ch6_0_pins[] = { 69, };
+static int mt7622_pwm_ch6_0_funcs[] = { 3, };
+static int mt7622_pwm_ch6_1_pins[] = { 78, };
+static int mt7622_pwm_ch6_1_funcs[] = { 4, };
+static int mt7622_pwm_ch6_2_pins[] = { 81, };
+static int mt7622_pwm_ch6_2_funcs[] = { 4, };
+static int mt7622_pwm_ch6_3_pins[] = { 100, };
+static int mt7622_pwm_ch6_3_funcs[] = { 0, };
+static int mt7622_pwm_ch7_0_pins[] = { 70, };
+static int mt7622_pwm_ch7_0_funcs[] = { 3, };
+static int mt7622_pwm_ch7_1_pins[] = { 82, };
+static int mt7622_pwm_ch7_1_funcs[] = { 4, };
+static int mt7622_pwm_ch7_2_pins[] = { 101, };
+static int mt7622_pwm_ch7_2_funcs[] = { 0, };
+
+/* SD */
+static int mt7622_sd_0_pins[] = { 16, 17, 18, 19, 20, 21, };
+static int mt7622_sd_0_funcs[] = { 2, 2, 2, 2, 2, 2, };
+static int mt7622_sd_1_pins[] = { 25, 26, 27, 28, 29, 30, };
+static int mt7622_sd_1_funcs[] = { 2, 2, 2, 2, 2, 2, };
+
+/* Serial NAND */
+static int mt7622_snfi_pins[] = { 8, 9, 10, 11, 12, 13, };
+static int mt7622_snfi_funcs[] = { 2, 2, 2, 2, 2, 2, };
+
+/* SPI NOR */
+static int mt7622_spi_pins[] = { 8, 9, 10, 11, 12, 13 };
+static int mt7622_spi_funcs[] = { 0, 0, 0, 0, 0, 0, };
+
+/* SPIC */
+static int mt7622_spic0_0_pins[] = { 63, 64, 65, 66, };
+static int mt7622_spic0_0_funcs[] = { 4, 4, 4, 4, };
+static int mt7622_spic0_1_pins[] = { 79, 80, 81, 82, };
+static int mt7622_spic0_1_funcs[] = { 3, 3, 3, 3, };
+static int mt7622_spic1_0_pins[] = { 67, 68, 69, 70, };
+static int mt7622_spic1_0_funcs[] = { 4, 4, 4, 4, };
+static int mt7622_spic1_1_pins[] = { 73, 74, 75, 76, };
+static int mt7622_spic1_1_funcs[] = { 0, 0, 0, 0, };
+static int mt7622_spic2_0_pins[] = { 10, 11, 12, 13, };
+static int mt7622_spic2_0_funcs[] = { 0, 0, 0, 0, };
+static int mt7622_spic2_0_wp_hold_pins[] = { 8, 9, };
+static int mt7622_spic2_0_wp_hold_funcs[] = { 0, 0, };
+
+/* TDM */
+static int mt7622_tdm_0_out_mclk_bclk_ws_pins[] = { 8, 9, 10, };
+static int mt7622_tdm_0_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_0_in_mclk_bclk_ws_pins[] = { 11, 12, 13, };
+static int mt7622_tdm_0_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_0_out_data_pins[] = { 20, };
+static int mt7622_tdm_0_out_data_funcs[] = { 3, };
+static int mt7622_tdm_0_in_data_pins[] = { 21, };
+static int mt7622_tdm_0_in_data_funcs[] = { 3, };
+static int mt7622_tdm_1_out_mclk_bclk_ws_pins[] = { 57, 58, 59, };
+static int mt7622_tdm_1_out_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_1_in_mclk_bclk_ws_pins[] = { 60, 61, 62, };
+static int mt7622_tdm_1_in_mclk_bclk_ws_funcs[] = { 3, 3, 3, };
+static int mt7622_tdm_1_out_data_pins[] = { 55, };
+static int mt7622_tdm_1_out_data_funcs[] = { 3, };
+static int mt7622_tdm_1_in_data_pins[] = { 56, };
+static int mt7622_tdm_1_in_data_funcs[] = { 3, };
+
+/* UART */
+static int mt7622_uart0_0_tx_rx_pins[] = { 6, 7, };
+static int mt7622_uart0_0_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart1_0_tx_rx_pins[] = { 55, 56, };
+static int mt7622_uart1_0_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart1_0_rts_cts_pins[] = { 57, 58, };
+static int mt7622_uart1_0_rts_cts_funcs[] = { 2, 2, };
+static int mt7622_uart1_1_tx_rx_pins[] = { 73, 74, };
+static int mt7622_uart1_1_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart1_1_rts_cts_pins[] = { 75, 76, };
+static int mt7622_uart1_1_rts_cts_funcs[] = { 2, 2, };
+static int mt7622_uart2_0_tx_rx_pins[] = { 3, 4, };
+static int mt7622_uart2_0_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart2_0_rts_cts_pins[] = { 1, 2, };
+static int mt7622_uart2_0_rts_cts_funcs[] = { 2, 2, };
+static int mt7622_uart2_1_tx_rx_pins[] = { 51, 52, };
+static int mt7622_uart2_1_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart2_1_rts_cts_pins[] = { 53, 54, };
+static int mt7622_uart2_1_rts_cts_funcs[] = { 0, 0, };
+static int mt7622_uart2_2_tx_rx_pins[] = { 59, 60, };
+static int mt7622_uart2_2_tx_rx_funcs[] = { 4, 4, };
+static int mt7622_uart2_2_rts_cts_pins[] = { 61, 62, };
+static int mt7622_uart2_2_rts_cts_funcs[] = { 4, 4, };
+static int mt7622_uart2_3_tx_rx_pins[] = { 95, 96, };
+static int mt7622_uart2_3_tx_rx_funcs[] = { 3, 3, };
+static int mt7622_uart3_0_tx_rx_pins[] = { 57, 58, };
+static int mt7622_uart3_0_tx_rx_funcs[] = { 5, 5, };
+static int mt7622_uart3_1_tx_rx_pins[] = { 81, 82, };
+static int mt7622_uart3_1_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart3_1_rts_cts_pins[] = { 79, 80, };
+static int mt7622_uart3_1_rts_cts_funcs[] = { 0, 0, };
+static int mt7622_uart4_0_tx_rx_pins[] = { 61, 62, };
+static int mt7622_uart4_0_tx_rx_funcs[] = { 5, 5, };
+static int mt7622_uart4_1_tx_rx_pins[] = { 91, 92, };
+static int mt7622_uart4_1_tx_rx_funcs[] = { 0, 0, };
+static int mt7622_uart4_1_rts_cts_pins[] = { 93, 94 };
+static int mt7622_uart4_1_rts_cts_funcs[] = { 0, 0, };
+static int mt7622_uart4_2_tx_rx_pins[] = { 97, 98, };
+static int mt7622_uart4_2_tx_rx_funcs[] = { 2, 2, };
+static int mt7622_uart4_2_rts_cts_pins[] = { 95, 96 };
+static int mt7622_uart4_2_rts_cts_funcs[] = { 2, 2, };
+
+/* Watchdog */
+static int mt7622_watchdog_pins[] = { 78, };
+static int mt7622_watchdog_funcs[] = { 0, };
+
+/* WLAN LED */
+static int mt7622_wled_pins[] = { 85, };
+static int mt7622_wled_funcs[] = { 0, };
+
+static const struct mtk_group_desc mt7622_groups[] = {
+ PINCTRL_PIN_GROUP("emmc", mt7622_emmc),
+ PINCTRL_PIN_GROUP("emmc_rst", mt7622_emmc_rst),
+ PINCTRL_PIN_GROUP("ephy_leds", mt7622_ephy_leds),
+ PINCTRL_PIN_GROUP("ephy0_led", mt7622_ephy0_led),
+ PINCTRL_PIN_GROUP("ephy1_led", mt7622_ephy1_led),
+ PINCTRL_PIN_GROUP("ephy2_led", mt7622_ephy2_led),
+ PINCTRL_PIN_GROUP("ephy3_led", mt7622_ephy3_led),
+ PINCTRL_PIN_GROUP("ephy4_led", mt7622_ephy4_led),
+ PINCTRL_PIN_GROUP("esw", mt7622_esw),
+ PINCTRL_PIN_GROUP("esw_p0_p1", mt7622_esw_p0_p1),
+ PINCTRL_PIN_GROUP("esw_p2_p3_p4", mt7622_esw_p2_p3_p4),
+ PINCTRL_PIN_GROUP("rgmii_via_esw", mt7622_rgmii_via_esw),
+ PINCTRL_PIN_GROUP("rgmii_via_gmac1", mt7622_rgmii_via_gmac1),
+ PINCTRL_PIN_GROUP("rgmii_via_gmac2", mt7622_rgmii_via_gmac2),
+ PINCTRL_PIN_GROUP("i2c0", mt7622_i2c0),
+ PINCTRL_PIN_GROUP("i2c1_0", mt7622_i2c1_0),
+ PINCTRL_PIN_GROUP("i2c1_1", mt7622_i2c1_1),
+ PINCTRL_PIN_GROUP("i2c1_2", mt7622_i2c1_2),
+ PINCTRL_PIN_GROUP("i2c2_0", mt7622_i2c2_0),
+ PINCTRL_PIN_GROUP("i2c2_1", mt7622_i2c2_1),
+ PINCTRL_PIN_GROUP("i2c2_2", mt7622_i2c2_2),
+ PINCTRL_PIN_GROUP("i2s_out_mclk_bclk_ws", mt7622_i2s_out_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("i2s_in_mclk_bclk_ws", mt7622_i2s_in_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("i2s1_in_data", mt7622_i2s1_in_data),
+ PINCTRL_PIN_GROUP("i2s2_in_data", mt7622_i2s2_in_data),
+ PINCTRL_PIN_GROUP("i2s3_in_data", mt7622_i2s3_in_data),
+ PINCTRL_PIN_GROUP("i2s4_in_data", mt7622_i2s4_in_data),
+ PINCTRL_PIN_GROUP("i2s1_out_data", mt7622_i2s1_out_data),
+ PINCTRL_PIN_GROUP("i2s2_out_data", mt7622_i2s2_out_data),
+ PINCTRL_PIN_GROUP("i2s3_out_data", mt7622_i2s3_out_data),
+ PINCTRL_PIN_GROUP("i2s4_out_data", mt7622_i2s4_out_data),
+ PINCTRL_PIN_GROUP("ir_0_tx", mt7622_ir_0_tx),
+ PINCTRL_PIN_GROUP("ir_1_tx", mt7622_ir_1_tx),
+ PINCTRL_PIN_GROUP("ir_2_tx", mt7622_ir_2_tx),
+ PINCTRL_PIN_GROUP("ir_0_rx", mt7622_ir_0_rx),
+ PINCTRL_PIN_GROUP("ir_1_rx", mt7622_ir_1_rx),
+ PINCTRL_PIN_GROUP("ir_2_rx", mt7622_ir_2_rx),
+ PINCTRL_PIN_GROUP("mdc_mdio", mt7622_mdc_mdio),
+ PINCTRL_PIN_GROUP("pcie0_0_waken", mt7622_pcie0_0_waken),
+ PINCTRL_PIN_GROUP("pcie0_0_clkreq", mt7622_pcie0_0_clkreq),
+ PINCTRL_PIN_GROUP("pcie0_1_waken", mt7622_pcie0_1_waken),
+ PINCTRL_PIN_GROUP("pcie0_1_clkreq", mt7622_pcie0_1_clkreq),
+ PINCTRL_PIN_GROUP("pcie1_0_waken", mt7622_pcie1_0_waken),
+ PINCTRL_PIN_GROUP("pcie1_0_clkreq", mt7622_pcie1_0_clkreq),
+ PINCTRL_PIN_GROUP("pcie0_pad_perst", mt7622_pcie0_pad_perst),
+ PINCTRL_PIN_GROUP("pcie1_pad_perst", mt7622_pcie1_pad_perst),
+ PINCTRL_PIN_GROUP("par_nand", mt7622_pnand),
+ PINCTRL_PIN_GROUP("pmic_bus", mt7622_pmic_bus),
+ PINCTRL_PIN_GROUP("pwm_ch1_0", mt7622_pwm_ch1_0),
+ PINCTRL_PIN_GROUP("pwm_ch1_1", mt7622_pwm_ch1_1),
+ PINCTRL_PIN_GROUP("pwm_ch1_2", mt7622_pwm_ch1_2),
+ PINCTRL_PIN_GROUP("pwm_ch2_0", mt7622_pwm_ch2_0),
+ PINCTRL_PIN_GROUP("pwm_ch2_1", mt7622_pwm_ch2_1),
+ PINCTRL_PIN_GROUP("pwm_ch2_2", mt7622_pwm_ch2_2),
+ PINCTRL_PIN_GROUP("pwm_ch3_0", mt7622_pwm_ch3_0),
+ PINCTRL_PIN_GROUP("pwm_ch3_1", mt7622_pwm_ch3_1),
+ PINCTRL_PIN_GROUP("pwm_ch3_2", mt7622_pwm_ch3_2),
+ PINCTRL_PIN_GROUP("pwm_ch4_0", mt7622_pwm_ch4_0),
+ PINCTRL_PIN_GROUP("pwm_ch4_1", mt7622_pwm_ch4_1),
+ PINCTRL_PIN_GROUP("pwm_ch4_2", mt7622_pwm_ch4_2),
+ PINCTRL_PIN_GROUP("pwm_ch4_3", mt7622_pwm_ch4_3),
+ PINCTRL_PIN_GROUP("pwm_ch5_0", mt7622_pwm_ch5_0),
+ PINCTRL_PIN_GROUP("pwm_ch5_1", mt7622_pwm_ch5_1),
+ PINCTRL_PIN_GROUP("pwm_ch5_2", mt7622_pwm_ch5_2),
+ PINCTRL_PIN_GROUP("pwm_ch6_0", mt7622_pwm_ch6_0),
+ PINCTRL_PIN_GROUP("pwm_ch6_1", mt7622_pwm_ch6_1),
+ PINCTRL_PIN_GROUP("pwm_ch6_2", mt7622_pwm_ch6_2),
+ PINCTRL_PIN_GROUP("pwm_ch6_3", mt7622_pwm_ch6_3),
+ PINCTRL_PIN_GROUP("pwm_ch7_0", mt7622_pwm_ch7_0),
+ PINCTRL_PIN_GROUP("pwm_ch7_1", mt7622_pwm_ch7_1),
+ PINCTRL_PIN_GROUP("pwm_ch7_2", mt7622_pwm_ch7_2),
+ PINCTRL_PIN_GROUP("sd_0", mt7622_sd_0),
+ PINCTRL_PIN_GROUP("sd_1", mt7622_sd_1),
+ PINCTRL_PIN_GROUP("snfi", mt7622_snfi),
+ PINCTRL_PIN_GROUP("spi_nor", mt7622_spi),
+ PINCTRL_PIN_GROUP("spic0_0", mt7622_spic0_0),
+ PINCTRL_PIN_GROUP("spic0_1", mt7622_spic0_1),
+ PINCTRL_PIN_GROUP("spic1_0", mt7622_spic1_0),
+ PINCTRL_PIN_GROUP("spic1_1", mt7622_spic1_1),
+ PINCTRL_PIN_GROUP("spic2_0", mt7622_spic2_0),
+ PINCTRL_PIN_GROUP("spic2_0_wp_hold", mt7622_spic2_0_wp_hold),
+ PINCTRL_PIN_GROUP("tdm_0_out_mclk_bclk_ws",
+ mt7622_tdm_0_out_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_0_in_mclk_bclk_ws",
+ mt7622_tdm_0_in_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_0_out_data", mt7622_tdm_0_out_data),
+ PINCTRL_PIN_GROUP("tdm_0_in_data", mt7622_tdm_0_in_data),
+ PINCTRL_PIN_GROUP("tdm_1_out_mclk_bclk_ws",
+ mt7622_tdm_1_out_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_1_in_mclk_bclk_ws",
+ mt7622_tdm_1_in_mclk_bclk_ws),
+ PINCTRL_PIN_GROUP("tdm_1_out_data", mt7622_tdm_1_out_data),
+ PINCTRL_PIN_GROUP("tdm_1_in_data", mt7622_tdm_1_in_data),
+ PINCTRL_PIN_GROUP("uart0_0_tx_rx", mt7622_uart0_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart1_0_tx_rx", mt7622_uart1_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart1_0_rts_cts", mt7622_uart1_0_rts_cts),
+ PINCTRL_PIN_GROUP("uart1_1_tx_rx", mt7622_uart1_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart1_1_rts_cts", mt7622_uart1_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_0_tx_rx", mt7622_uart2_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart2_0_rts_cts", mt7622_uart2_0_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_1_tx_rx", mt7622_uart2_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart2_1_rts_cts", mt7622_uart2_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_2_tx_rx", mt7622_uart2_2_tx_rx),
+ PINCTRL_PIN_GROUP("uart2_2_rts_cts", mt7622_uart2_2_rts_cts),
+ PINCTRL_PIN_GROUP("uart2_3_tx_rx", mt7622_uart2_3_tx_rx),
+ PINCTRL_PIN_GROUP("uart3_0_tx_rx", mt7622_uart3_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart3_1_tx_rx", mt7622_uart3_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart3_1_rts_cts", mt7622_uart3_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart4_0_tx_rx", mt7622_uart4_0_tx_rx),
+ PINCTRL_PIN_GROUP("uart4_1_tx_rx", mt7622_uart4_1_tx_rx),
+ PINCTRL_PIN_GROUP("uart4_1_rts_cts", mt7622_uart4_1_rts_cts),
+ PINCTRL_PIN_GROUP("uart4_2_tx_rx", mt7622_uart4_2_tx_rx),
+ PINCTRL_PIN_GROUP("uart4_2_rts_cts", mt7622_uart4_2_rts_cts),
+ PINCTRL_PIN_GROUP("watchdog", mt7622_watchdog),
+ PINCTRL_PIN_GROUP("wled", mt7622_wled),
+};
+
+/* Joint those groups owning the same capability in user point of view which
+ * allows that people tend to use through the device tree.
+ */
+static const char *const mt7622_emmc_groups[] = { "emmc", "emmc_rst", };
+static const char *const mt7622_ethernet_groups[] = { "esw", "esw_p0_p1",
+ "esw_p2_p3_p4", "mdc_mdio",
+ "rgmii_via_gmac1",
+ "rgmii_via_gmac2",
+ "rgmii_via_esw", };
+static const char *const mt7622_i2c_groups[] = { "i2c0", "i2c1_0", "i2c1_1",
+ "i2c1_2", "i2c2_0", "i2c2_1",
+ "i2c2_2", };
+static const char *const mt7622_i2s_groups[] = { "i2s_out_mclk_bclk_ws",
+ "i2s_in_mclk_bclk_ws",
+ "i2s1_in_data", "i2s2_in_data",
+ "i2s3_in_data", "i2s4_in_data",
+ "i2s1_out_data", "i2s2_out_data",
+ "i2s3_out_data", "i2s4_out_data", };
+static const char *const mt7622_ir_groups[] = { "ir_0_tx", "ir_1_tx", "ir_2_tx",
+ "ir_0_rx", "ir_1_rx", "ir_2_rx"};
+static const char *const mt7622_led_groups[] = { "ephy_leds", "ephy0_led",
+ "ephy1_led", "ephy2_led",
+ "ephy3_led", "ephy4_led",
+ "wled", };
+static const char *const mt7622_flash_groups[] = { "par_nand", "snfi",
+ "spi_nor"};
+static const char *const mt7622_pcie_groups[] = { "pcie0_0_waken",
+ "pcie0_0_clkreq", "pcie0_1_waken",
+ "pcie0_1_clkreq", "pcie1_0_waken",
+ "pcie1_0_clkreq", "pcie0_pad_perst",
+ "pcie1_pad_perst", };
+static const char *const mt7622_pmic_bus_groups[] = { "pmic_bus", };
+static const char *const mt7622_pwm_groups[] = { "pwm_ch1_0", "pwm_ch1_1",
+ "pwm_ch1_2", "pwm_ch2_0",
+ "pwm_ch2_1", "pwm_ch2_2",
+ "pwm_ch3_0", "pwm_ch3_1",
+ "pwm_ch3_2", "pwm_ch4_0",
+ "pwm_ch4_1", "pwm_ch4_2",
+ "pwm_ch4_3", "pwm_ch5_0",
+ "pwm_ch5_1", "pwm_ch5_2",
+ "pwm_ch6_0", "pwm_ch6_1",
+ "pwm_ch6_2", "pwm_ch6_3",
+ "pwm_ch7_0", "pwm_ch7_1",
+ "pwm_ch7_2", };
+static const char *const mt7622_sd_groups[] = { "sd_0", "sd_1", };
+static const char *const mt7622_spic_groups[] = { "spic0_0", "spic0_1",
+ "spic1_0", "spic1_1", "spic2_0",
+ "spic2_0_wp_hold", };
+static const char *const mt7622_tdm_groups[] = { "tdm_0_out_mclk_bclk_ws",
+ "tdm_0_in_mclk_bclk_ws",
+ "tdm_0_out_data",
+ "tdm_0_in_data",
+ "tdm_1_out_mclk_bclk_ws",
+ "tdm_1_in_mclk_bclk_ws",
+ "tdm_1_out_data",
+ "tdm_1_in_data", };
+
+static const char *const mt7622_uart_groups[] = { "uart0_0_tx_rx",
+ "uart1_0_tx_rx", "uart1_0_rts_cts",
+ "uart1_1_tx_rx", "uart1_1_rts_cts",
+ "uart2_0_tx_rx", "uart2_0_rts_cts",
+ "uart2_1_tx_rx", "uart2_1_rts_cts",
+ "uart2_2_tx_rx", "uart2_2_rts_cts",
+ "uart2_3_tx_rx",
+ "uart3_0_tx_rx",
+ "uart3_1_tx_rx", "uart3_1_rts_cts",
+ "uart4_0_tx_rx",
+ "uart4_1_tx_rx", "uart4_1_rts_cts",
+ "uart4_2_tx_rx",
+ "uart4_2_rts_cts",};
+static const char *const mt7622_wdt_groups[] = { "watchdog", };
+
+static const struct mtk_function_desc mt7622_functions[] = {
+ {"emmc", mt7622_emmc_groups, ARRAY_SIZE(mt7622_emmc_groups)},
+ {"eth", mt7622_ethernet_groups, ARRAY_SIZE(mt7622_ethernet_groups)},
+ {"i2c", mt7622_i2c_groups, ARRAY_SIZE(mt7622_i2c_groups)},
+ {"i2s", mt7622_i2s_groups, ARRAY_SIZE(mt7622_i2s_groups)},
+ {"ir", mt7622_ir_groups, ARRAY_SIZE(mt7622_ir_groups)},
+ {"led", mt7622_led_groups, ARRAY_SIZE(mt7622_led_groups)},
+ {"flash", mt7622_flash_groups, ARRAY_SIZE(mt7622_flash_groups)},
+ {"pcie", mt7622_pcie_groups, ARRAY_SIZE(mt7622_pcie_groups)},
+ {"pmic", mt7622_pmic_bus_groups, ARRAY_SIZE(mt7622_pmic_bus_groups)},
+ {"pwm", mt7622_pwm_groups, ARRAY_SIZE(mt7622_pwm_groups)},
+ {"sd", mt7622_sd_groups, ARRAY_SIZE(mt7622_sd_groups)},
+ {"spi", mt7622_spic_groups, ARRAY_SIZE(mt7622_spic_groups)},
+ {"tdm", mt7622_tdm_groups, ARRAY_SIZE(mt7622_tdm_groups)},
+ {"uart", mt7622_uart_groups, ARRAY_SIZE(mt7622_uart_groups)},
+ {"watchdog", mt7622_wdt_groups, ARRAY_SIZE(mt7622_wdt_groups)},
+};
+
+static struct mtk_pinctrl_soc mt7622_data = {
+ .name = "mt7622_pinctrl",
+ .reg_cal = mt7622_reg_cals,
+ .pins = mt7622_pins,
+ .npins = ARRAY_SIZE(mt7622_pins),
+ .grps = mt7622_groups,
+ .ngrps = ARRAY_SIZE(mt7622_groups),
+ .funcs = mt7622_functions,
+ .nfuncs = ARRAY_SIZE(mt7622_functions),
+};
+
+static int mtk_pinctrl_mt7622_probe(struct udevice *dev)
+{
+ return mtk_pinctrl_common_probe(dev, &mt7622_data);
+}
+
+static const struct udevice_id mt7622_pctrl_match[] = {
+ { .compatible = "mediatek,mt7622-pinctrl" },
+ { /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt7622_pinctrl) = {
+ .name = "mt7622_pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = mt7622_pctrl_match,
+ .ops = &mtk_pinctrl_ops,
+ .probe = mtk_pinctrl_mt7622_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_pinctrl_priv),
+};
+
+
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 03/10] pinctrl: mediatek: add support for different pinctrl
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
2020-01-10 8:30 ` [RESEND v2 01/10] ARM: MediaTek: " Sam Shih
2020-01-10 8:30 ` [RESEND v2 02/10] pinctrl: mediatek: add driver for MT7622 Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 04/10] clk: mediatek: add driver for MT7622 Sam Shih
` (6 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
Due to the pinctrl hardware of MT7622 is difference from others
SoC which using the common part of mediatek pinctrl.
So we need to modify the common part of mediatek pinctrl.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/pinctrl/mediatek/pinctrl-mt7622.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt7623.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt7629.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt8516.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mt8518.c | 2 +
drivers/pinctrl/mediatek/pinctrl-mtk-common.c | 122 +++++++++++++++---
drivers/pinctrl/mediatek/pinctrl-mtk-common.h | 12 +-
7 files changed, 125 insertions(+), 19 deletions(-)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7622.c b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
index 2a4bf43c32..1aa323c009 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7622.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7622.c
@@ -728,6 +728,8 @@ static struct mtk_pinctrl_soc mt7622_data = {
.ngrps = ARRAY_SIZE(mt7622_groups),
.funcs = mt7622_functions,
.nfuncs = ARRAY_SIZE(mt7622_functions),
+ .gpio_mode = 1,
+ .rev = MTK_PINCTRL_V0,
};
static int mtk_pinctrl_mt7622_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7623.c b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
index fd37dfa442..d58d840e08 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7623.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7623.c
@@ -1242,6 +1242,8 @@ static struct mtk_pinctrl_soc mt7623_data = {
.ngrps = ARRAY_SIZE(mt7623_groups),
.funcs = mt7623_functions,
.nfuncs = ARRAY_SIZE(mt7623_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
/*
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt7629.c b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
index aa6d1c2d91..37640dd2b6 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt7629.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt7629.c
@@ -387,6 +387,8 @@ static struct mtk_pinctrl_soc mt7629_data = {
.ngrps = ARRAY_SIZE(mt7629_groups),
.funcs = mt7629_functions,
.nfuncs = ARRAY_SIZE(mt7629_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
static int mtk_pinctrl_mt7629_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8516.c b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
index 829b30e5a2..62e339e931 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8516.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8516.c
@@ -369,6 +369,8 @@ static struct mtk_pinctrl_soc mt8516_data = {
.ngrps = ARRAY_SIZE(mt8516_groups),
.funcs = mt8516_functions,
.nfuncs = ARRAY_SIZE(mt8516_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
static int mtk_pinctrl_mt8516_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mt8518.c b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
index 8d2cd948f6..91427aed4b 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mt8518.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mt8518.c
@@ -389,6 +389,8 @@ static struct mtk_pinctrl_soc mt8518_data = {
.ngrps = ARRAY_SIZE(mt8518_groups),
.funcs = mt8518_functions,
.nfuncs = ARRAY_SIZE(mt8518_functions),
+ .gpio_mode = 0,
+ .rev = MTK_PINCTRL_V1,
};
static int mtk_pinctrl_mt8518_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
index 3004335c57..c7351f32bb 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.c
@@ -294,7 +294,72 @@ static const struct pinconf_param mtk_conf_params[] = {
{ "drive-strength", PIN_CONFIG_DRIVE_STRENGTH, 0 },
};
-int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
+
+int mtk_pinconf_bias_set_v0(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err, disable, pullup;
+
+ disable = (arg == PIN_CONFIG_BIAS_DISABLE);
+ pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+
+ if (disable) {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, 0);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, 0);
+ if (err)
+ return err;
+
+ } else {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PU, pullup);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PD, !pullup);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int mtk_pinconf_bias_set_v1(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err, disable, pullup;
+
+ disable = (arg == PIN_CONFIG_BIAS_DISABLE);
+ pullup = (arg == PIN_CONFIG_BIAS_PULL_UP);
+
+ if (disable) {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 0);
+ if (err)
+ return err;
+ } else {
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN, 1);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
+ pullup);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+int mtk_pinconf_input_enable_v1(struct udevice *dev, u32 pin, u32 arg)
+{
+ int err;
+
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
+ if (err)
+ return err;
+ return 0;
+}
+
+int mtk_pinconf_drive_set_v0(struct udevice *dev, u32 pin, u32 arg)
{
struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
@@ -309,7 +374,30 @@ int mtk_pinconf_drive_set(struct udevice *dev, u32 pin, u32 arg)
*/
if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
arg = (arg / tb->step - 1) * tb->scal;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E4,
+ arg & 0x1);
+ if (err)
+ return err;
+ err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_E8,
+ (arg & 0x2) >> 1);
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
+
+int mtk_pinconf_drive_set_v1(struct udevice *dev, u32 pin, u32 arg)
+{
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ const struct mtk_pin_desc *desc = &priv->soc->pins[pin];
+ const struct mtk_drive_desc *tb;
+ int err = -ENOTSUPP;
+ tb = &mtk_drive[desc->drv_n];
+ if ((arg >= tb->min && arg <= tb->max) && !(arg % tb->step)) {
+ arg = (arg / tb->step - 1) * tb->scal;
err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DRV, arg);
if (err)
return err;
@@ -322,21 +410,17 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
unsigned int param, unsigned int arg)
{
int err = 0;
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev);
+ int rev = priv->soc->rev;
switch (param) {
case PIN_CONFIG_BIAS_DISABLE:
case PIN_CONFIG_BIAS_PULL_UP:
case PIN_CONFIG_BIAS_PULL_DOWN:
- arg = (param == PIN_CONFIG_BIAS_DISABLE) ? 0 :
- (param == PIN_CONFIG_BIAS_PULL_UP) ? 3 : 2;
-
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLSEL,
- arg & 1);
- if (err)
- goto err;
-
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_PULLEN,
- !!(arg & 2));
+ if (rev == MTK_PINCTRL_V0)
+ err = mtk_pinconf_bias_set_v0(dev, pin, param);
+ else
+ err = mtk_pinconf_bias_set_v1(dev, pin, param);
if (err)
goto err;
break;
@@ -349,10 +433,8 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
goto err;
break;
case PIN_CONFIG_INPUT_ENABLE:
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_IES, 1);
- if (err)
- goto err;
- err = mtk_hw_set_value(dev, pin, PINCTRL_PIN_REG_DIR, 0);
+ if (rev == MTK_PINCTRL_V1)
+ err = mtk_pinconf_input_enable_v1(dev, pin, param);
if (err)
goto err;
break;
@@ -381,7 +463,10 @@ static int mtk_pinconf_set(struct udevice *dev, unsigned int pin,
goto err;
break;
case PIN_CONFIG_DRIVE_STRENGTH:
- err = mtk_pinconf_drive_set(dev, pin, arg);
+ if (rev == MTK_PINCTRL_V0)
+ err = mtk_pinconf_drive_set_v0(dev, pin, arg);
+ else
+ err = mtk_pinconf_drive_set_v1(dev, pin, arg);
if (err)
goto err;
break;
@@ -475,7 +560,10 @@ static int mtk_gpio_direction_output(struct udevice *dev,
static int mtk_gpio_request(struct udevice *dev, unsigned int off,
const char *label)
{
- return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE, 0);
+ struct mtk_pinctrl_priv *priv = dev_get_priv(dev->parent);
+
+ return mtk_hw_set_value(dev->parent, off, PINCTRL_PIN_REG_MODE,
+ priv->soc->gpio_mode);
}
static int mtk_gpio_probe(struct udevice *dev)
diff --git a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
index 86559f0f14..e815761450 100644
--- a/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
+++ b/drivers/pinctrl/mediatek/pinctrl-mtk-common.h
@@ -3,10 +3,12 @@
* Copyright (C) 2018 MediaTek Inc.
* Author: Ryder Lee <ryder.lee@mediatek.com>
*/
-
#ifndef __PINCTRL_MEDIATEK_H__
#define __PINCTRL_MEDIATEK_H__
+#define MTK_PINCTRL_V0 0x0
+#define MTK_PINCTRL_V1 0x1
+
#define MTK_RANGE(_a) { .range = (_a), .nranges = ARRAY_SIZE(_a), }
#define MTK_PIN(_number, _name, _drv_n) { \
.number = _number, \
@@ -40,8 +42,12 @@ enum {
PINCTRL_PIN_REG_DIR,
PINCTRL_PIN_REG_DI,
PINCTRL_PIN_REG_DO,
- PINCTRL_PIN_REG_IES,
PINCTRL_PIN_REG_SMT,
+ PINCTRL_PIN_REG_PD,
+ PINCTRL_PIN_REG_PU,
+ PINCTRL_PIN_REG_E4,
+ PINCTRL_PIN_REG_E8,
+ PINCTRL_PIN_REG_IES,
PINCTRL_PIN_REG_PULLEN,
PINCTRL_PIN_REG_PULLSEL,
PINCTRL_PIN_REG_DRV,
@@ -161,6 +167,8 @@ struct mtk_pinctrl_soc {
int ngrps;
const struct mtk_function_desc *funcs;
int nfuncs;
+ int gpio_mode;
+ int rev;
};
/**
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 04/10] clk: mediatek: add driver for MT7622
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (2 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 03/10] pinctrl: mediatek: add support for different pinctrl Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 05/10] clk: mediatek: fix clock-rate overflow problem Sam Shih
` (5 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch add clock driver for MediaTek MT7622 SoC.
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
drivers/clk/mediatek/Makefile | 1 +
drivers/clk/mediatek/clk-mt7622.c | 678 +++++++++++++++++++++++++
include/dt-bindings/clock/mt7622-clk.h | 271 ++++++++++
3 files changed, 950 insertions(+)
create mode 100644 drivers/clk/mediatek/clk-mt7622.c
create mode 100644 include/dt-bindings/clock/mt7622-clk.h
diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
index e92bcd4efe..755e24c651 100644
--- a/drivers/clk/mediatek/Makefile
+++ b/drivers/clk/mediatek/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_MEDIATEK) += clk-mtk.o
# SoC Drivers
obj-$(CONFIG_TARGET_MT7623) += clk-mt7623.o
+obj-$(CONFIG_TARGET_MT7622) += clk-mt7622.o
obj-$(CONFIG_TARGET_MT7629) += clk-mt7629.o
obj-$(CONFIG_TARGET_MT8516) += clk-mt8516.o
obj-$(CONFIG_TARGET_MT8518) += clk-mt8518.o
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
new file mode 100644
index 0000000000..a5b61a190b
--- /dev/null
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -0,0 +1,678 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * MediaTek clock driver for MT7622 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Ryder Lee <ryder.lee@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch-mediatek/reset.h>
+#include <asm/io.h>
+#include <dt-bindings/clock/mt7622-clk.h>
+
+#include "clk-mtk.h"
+
+#define MT7622_CLKSQ_STB_CON0 0x20
+#define MT7622_PLL_ISO_CON0 0x2c
+#define MT7622_PLL_FMAX (2500UL * MHZ)
+#define MT7622_CON0_RST_BAR BIT(24)
+
+#define MCU_AXI_DIV 0x640
+#define AXI_DIV_MSK GENMASK(4, 0)
+#define AXI_DIV_SEL(x) (x)
+
+#define MCU_BUS_MUX 0x7c0
+#define MCU_BUS_MSK GENMASK(10, 9)
+#define MCU_BUS_SEL(x) ((x) << 9)
+
+/* apmixedsys */
+#define PLL(_id, _reg, _pwr_reg, _en_mask, _flags, _pcwbits, _pd_reg, \
+ _pd_shift, _pcw_reg, _pcw_shift) { \
+ .id = _id, \
+ .reg = _reg, \
+ .pwr_reg = _pwr_reg, \
+ .en_mask = _en_mask, \
+ .rst_bar_mask = MT7622_CON0_RST_BAR, \
+ .fmax = MT7622_PLL_FMAX, \
+ .flags = _flags, \
+ .pcwbits = _pcwbits, \
+ .pd_reg = _pd_reg, \
+ .pd_shift = _pd_shift, \
+ .pcw_reg = _pcw_reg, \
+ .pcw_shift = _pcw_shift, \
+ }
+
+static const struct mtk_pll_data apmixed_plls[] = {
+ PLL(CLK_APMIXED_ARMPLL, 0x200, 0x20c, 0x1, 0,
+ 21, 0x204, 24, 0x204, 0),
+ PLL(CLK_APMIXED_MAINPLL, 0x210, 0x21c, 0x1, HAVE_RST_BAR,
+ 21, 0x214, 24, 0x214, 0),
+ PLL(CLK_APMIXED_UNIV2PLL, 0x220, 0x22c, 0x1, HAVE_RST_BAR,
+ 7, 0x224, 24, 0x224, 14),
+ PLL(CLK_APMIXED_ETH1PLL, 0x300, 0x310, 0x1, 0,
+ 21, 0x300, 1, 0x304, 0),
+ PLL(CLK_APMIXED_ETH2PLL, 0x314, 0x320, 0x1, 0,
+ 21, 0x314, 1, 0x318, 0),
+ PLL(CLK_APMIXED_AUD1PLL, 0x324, 0x330, 0x1, 0,
+ 31, 0x324, 1, 0x328, 0),
+ PLL(CLK_APMIXED_AUD2PLL, 0x334, 0x340, 0x1, 0,
+ 31, 0x334, 1, 0x338, 0),
+ PLL(CLK_APMIXED_TRGPLL, 0x344, 0x354, 0x1, 0,
+ 21, 0x344, 1, 0x348, 0),
+ PLL(CLK_APMIXED_SGMIPLL, 0x358, 0x368, 0x1, 0,
+ 21, 0x358, 1, 0x35c, 0),
+};
+
+/* topckgen */
+#define FACTOR0(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_APMIXED)
+
+#define FACTOR1(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, CLK_PARENT_TOPCKGEN)
+
+#define FACTOR2(_id, _parent, _mult, _div) \
+ FACTOR(_id, _parent, _mult, _div, 0)
+
+static const struct mtk_fixed_clk top_fixed_clks[] = {
+ FIXED_CLK(CLK_TOP_TO_U2_PHY, CLK_XTAL, 31250000),
+ FIXED_CLK(CLK_TOP_TO_U2_PHY_1P, CLK_XTAL, 31250000),
+ FIXED_CLK(CLK_TOP_PCIE0_PIPE_EN, CLK_XTAL, 125000000),
+ FIXED_CLK(CLK_TOP_PCIE1_PIPE_EN, CLK_XTAL, 125000000),
+ FIXED_CLK(CLK_TOP_SSUSB_TX250M, CLK_XTAL, 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_EQ_RX250M, CLK_XTAL, 250000000),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_REF, CLK_XTAL, 33333333),
+ FIXED_CLK(CLK_TOP_SSUSB_CDR_FB, CLK_XTAL, 50000000),
+ FIXED_CLK(CLK_TOP_SATA_ASIC, CLK_XTAL, 50000000),
+ FIXED_CLK(CLK_TOP_SATA_RBC, CLK_XTAL, 50000000),
+};
+
+static const struct mtk_fixed_factor top_fixed_divs[] = {
+ FACTOR0(CLK_TOP_TO_USB3_SYS, CLK_APMIXED_ETH1PLL, 1, 4),
+ FACTOR0(CLK_TOP_P1_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+ FACTOR0(CLK_TOP_4MHZ, CLK_APMIXED_ETH1PLL, 1, 125),
+ FACTOR0(CLK_TOP_P0_1MHZ, CLK_APMIXED_ETH1PLL, 1, 500),
+ FACTOR1(CLK_TOP_TXCLK_SRC_PRE, CLK_TOP_SGMIIPLL_D2, 1, 1),
+ FACTOR2(CLK_TOP_RTC, CLK_XTAL, 1, 1024),
+ FACTOR2(CLK_TOP_MEMPLL, CLK_XTAL, 32, 1),
+ FACTOR1(CLK_TOP_DMPLL, CLK_TOP_MEMPLL, 1, 1),
+ FACTOR0(CLK_TOP_SYSPLL_D2, CLK_APMIXED_MAINPLL, 1, 2),
+ FACTOR0(CLK_TOP_SYSPLL1_D2, CLK_APMIXED_MAINPLL, 1, 4),
+ FACTOR0(CLK_TOP_SYSPLL1_D4, CLK_APMIXED_MAINPLL, 1, 8),
+ FACTOR0(CLK_TOP_SYSPLL1_D8, CLK_APMIXED_MAINPLL, 1, 16),
+ FACTOR0(CLK_TOP_SYSPLL2_D4, CLK_APMIXED_MAINPLL, 1, 12),
+ FACTOR0(CLK_TOP_SYSPLL2_D8, CLK_APMIXED_MAINPLL, 1, 24),
+ FACTOR0(CLK_TOP_SYSPLL_D5, CLK_APMIXED_MAINPLL, 1, 5),
+ FACTOR0(CLK_TOP_SYSPLL3_D2, CLK_APMIXED_MAINPLL, 1, 10),
+ FACTOR0(CLK_TOP_SYSPLL3_D4, CLK_APMIXED_MAINPLL, 1, 20),
+ FACTOR0(CLK_TOP_SYSPLL4_D2, CLK_APMIXED_MAINPLL, 1, 14),
+ FACTOR0(CLK_TOP_SYSPLL4_D4, CLK_APMIXED_MAINPLL, 1, 28),
+ FACTOR0(CLK_TOP_SYSPLL4_D16, CLK_APMIXED_MAINPLL, 1, 112),
+ FACTOR0(CLK_TOP_UNIVPLL, CLK_APMIXED_UNIV2PLL, 1, 2),
+ FACTOR0(CLK_TOP_UNIVPLL_D2, CLK_TOP_UNIVPLL, 1, 2),
+ FACTOR1(CLK_TOP_UNIVPLL1_D2, CLK_TOP_UNIVPLL, 1, 4),
+ FACTOR1(CLK_TOP_UNIVPLL1_D4, CLK_TOP_UNIVPLL, 1, 8),
+ FACTOR1(CLK_TOP_UNIVPLL1_D8, CLK_TOP_UNIVPLL, 1, 16),
+ FACTOR1(CLK_TOP_UNIVPLL1_D16, CLK_TOP_UNIVPLL, 1, 32),
+ FACTOR1(CLK_TOP_UNIVPLL2_D2, CLK_TOP_UNIVPLL, 1, 6),
+ FACTOR1(CLK_TOP_UNIVPLL2_D4, CLK_TOP_UNIVPLL, 1, 12),
+ FACTOR1(CLK_TOP_UNIVPLL2_D8, CLK_TOP_UNIVPLL, 1, 24),
+ FACTOR1(CLK_TOP_UNIVPLL2_D16, CLK_TOP_UNIVPLL, 1, 48),
+ FACTOR1(CLK_TOP_UNIVPLL_D5, CLK_TOP_UNIVPLL, 1, 5),
+ FACTOR1(CLK_TOP_UNIVPLL3_D2, CLK_TOP_UNIVPLL, 1, 10),
+ FACTOR1(CLK_TOP_UNIVPLL3_D4, CLK_TOP_UNIVPLL, 1, 20),
+ FACTOR1(CLK_TOP_UNIVPLL3_D16, CLK_TOP_UNIVPLL, 1, 80),
+ FACTOR1(CLK_TOP_UNIVPLL_D7, CLK_TOP_UNIVPLL, 1, 7),
+ FACTOR1(CLK_TOP_UNIVPLL_D80_D4, CLK_TOP_UNIVPLL, 1, 320),
+ FACTOR1(CLK_TOP_UNIV48M, CLK_TOP_UNIVPLL, 1, 25),
+ FACTOR0(CLK_TOP_SGMIIPLL, CLK_APMIXED_SGMIPLL, 1, 1),
+ FACTOR0(CLK_TOP_SGMIIPLL_D2, CLK_APMIXED_SGMIPLL, 1, 2),
+ FACTOR0(CLK_TOP_AUD1PLL, CLK_APMIXED_AUD1PLL, 1, 1),
+ FACTOR0(CLK_TOP_AUD2PLL, CLK_APMIXED_AUD2PLL, 1, 1),
+ FACTOR1(CLK_TOP_AUD_I2S2_MCK, CLK_TOP_I2S2_MCK_SEL, 1, 2),
+ FACTOR1(CLK_TOP_TO_USB3_REF, CLK_TOP_UNIVPLL2_D4, 1, 4),
+ FACTOR1(CLK_TOP_PCIE1_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+ FACTOR1(CLK_TOP_PCIE0_MAC_EN, CLK_TOP_UNIVPLL1_D4, 1, 1),
+ FACTOR0(CLK_TOP_ETH_500M, CLK_APMIXED_ETH1PLL, 1, 1),
+};
+
+static const int axi_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL_D7
+};
+
+static const int mem_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_DMPLL
+};
+
+static const int ddrphycfg_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D8
+};
+
+static const int eth_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL1_D2,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_UNIVPLL_D5,
+ -1,
+ CLK_TOP_UNIVPLL_D7
+};
+
+static const int pwm_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int f10m_ref_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL4_D16
+};
+
+static const int nfi_infra_parents[] = {
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D8,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL3_D2,
+ CLK_TOP_SYSPLL1_D4
+};
+
+static const int flash_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL_D80_D4,
+ CLK_TOP_SYSPLL2_D8,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int uart_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D8
+};
+
+static const int spi0_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL3_D2,
+ CLK_XTAL,
+ CLK_TOP_SYSPLL2_D4,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_XTAL
+};
+
+static const int spi1_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL3_D2,
+ CLK_XTAL,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_UNIVPLL2_D4,
+ CLK_TOP_UNIVPLL1_D8,
+ CLK_XTAL
+};
+
+static const int msdc30_0_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL2_D16,
+ CLK_TOP_UNIV48M
+};
+
+static const int a1sys_hp_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_AUD1PLL,
+ CLK_TOP_AUD2PLL,
+ CLK_XTAL
+};
+
+static const int intdir_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_UNIVPLL_D2,
+ CLK_TOP_SGMIIPLL
+};
+
+static const int aud_intbus_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D4,
+ CLK_TOP_SYSPLL4_D2,
+ CLK_TOP_SYSPLL3_D2
+};
+
+static const int pmicspi_parents[] = {
+ CLK_XTAL,
+ -1,
+ -1,
+ -1,
+ -1,
+ CLK_TOP_UNIVPLL2_D16
+};
+
+static const int atb_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL1_D2,
+ CLK_TOP_SYSPLL_D5
+};
+
+static const int audio_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL3_D4,
+ CLK_TOP_SYSPLL4_D4,
+ CLK_TOP_UNIVPLL1_D16
+};
+
+static const int usb20_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_UNIVPLL3_D4,
+ CLK_TOP_SYSPLL1_D8,
+ CLK_XTAL
+};
+
+static const int aud1_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_AUD1PLL
+};
+
+static const int asm_l_parents[] = {
+ CLK_XTAL,
+ CLK_TOP_SYSPLL_D5,
+ CLK_TOP_UNIVPLL2_D2,
+ CLK_TOP_UNIVPLL2_D4
+};
+
+static const int apll1_ck_parents[] = {
+ CLK_TOP_AUD1_SEL,
+ CLK_TOP_AUD2_SEL
+};
+
+static const struct mtk_composite top_muxes[] = {
+ /* CLK_CFG_0 */
+ MUX_GATE(CLK_TOP_AXI_SEL, axi_parents, 0x40, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MEM_SEL, mem_parents, 0x40, 8, 1, 15),
+ MUX_GATE(CLK_TOP_DDRPHYCFG_SEL, ddrphycfg_parents, 0x40, 16, 1, 23),
+ MUX_GATE(CLK_TOP_ETH_SEL, eth_parents, 0x40, 24, 3, 31),
+
+ /* CLK_CFG_1 */
+ MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7),
+ MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15),
+ MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23),
+ MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31),
+
+ /* CLK_CFG_2 */
+ MUX_GATE(CLK_TOP_UART_SEL, uart_parents, 0x60, 0, 1, 7),
+ MUX_GATE(CLK_TOP_SPI0_SEL, spi0_parents, 0x60, 8, 3, 15),
+ MUX_GATE(CLK_TOP_SPI1_SEL, spi1_parents, 0x60, 16, 3, 23),
+ MUX_GATE(CLK_TOP_MSDC50_0_SEL, uart_parents, 0x60, 24, 3, 31),
+
+ /* CLK_CFG_3 */
+ MUX_GATE(CLK_TOP_MSDC30_0_SEL, msdc30_0_parents, 0x70, 0, 3, 7),
+ MUX_GATE(CLK_TOP_MSDC30_1_SEL, msdc30_0_parents, 0x70, 8, 3, 15),
+ MUX_GATE(CLK_TOP_A1SYS_HP_SEL, a1sys_hp_parents, 0x70, 16, 3, 23),
+ MUX_GATE(CLK_TOP_A2SYS_HP_SEL, a1sys_hp_parents, 0x70, 24, 3, 31),
+
+ /* CLK_CFG_4 */
+ MUX_GATE(CLK_TOP_INTDIR_SEL, intdir_parents, 0x80, 0, 2, 7),
+ MUX_GATE(CLK_TOP_AUD_INTBUS_SEL, aud_intbus_parents, 0x80, 8, 2, 15),
+ MUX_GATE(CLK_TOP_PMICSPI_SEL, pmicspi_parents, 0x80, 16, 3, 23),
+ MUX_GATE(CLK_TOP_SCP_SEL, ddrphycfg_parents, 0x80, 24, 2, 31),
+
+ /* CLK_CFG_5 */
+ MUX_GATE(CLK_TOP_ATB_SEL, atb_parents, 0x90, 0, 2, 7),
+ MUX_GATE_FLAGS(CLK_TOP_HIF_SEL, eth_parents, 0x90, 8, 3, 15,
+ CLK_DOMAIN_SCPSYS),
+ MUX_GATE(CLK_TOP_AUDIO_SEL, audio_parents, 0x90, 16, 2, 23),
+ MUX_GATE(CLK_TOP_U2_SEL, usb20_parents, 0x90, 24, 2, 31),
+
+ /* CLK_CFG_6 */
+ MUX_GATE(CLK_TOP_AUD1_SEL, aud1_parents, 0xA0, 0, 1, 7),
+ MUX_GATE(CLK_TOP_AUD2_SEL, aud1_parents, 0xA0, 8, 1, 15),
+ MUX_GATE(CLK_TOP_IRRX_SEL, f10m_ref_parents, 0xA0, 16, 1, 23),
+ MUX_GATE(CLK_TOP_IRTX_SEL, f10m_ref_parents, 0xA0, 24, 1, 31),
+
+ /* CLK_CFG_7 */
+ MUX_GATE(CLK_TOP_ASM_L_SEL, asm_l_parents, 0xB0, 0, 2, 7),
+ MUX_GATE(CLK_TOP_ASM_M_SEL, asm_l_parents, 0xB0, 8, 2, 15),
+ MUX_GATE(CLK_TOP_ASM_H_SEL, asm_l_parents, 0xB0, 16, 2, 23),
+
+ /* CLK_AUDDIV_0 */
+ MUX(CLK_TOP_APLL1_SEL, apll1_ck_parents, 0x120, 6, 1),
+ MUX(CLK_TOP_APLL2_SEL, apll1_ck_parents, 0x120, 7, 1),
+ MUX(CLK_TOP_I2S0_MCK_SEL, apll1_ck_parents, 0x120, 8, 1),
+ MUX(CLK_TOP_I2S1_MCK_SEL, apll1_ck_parents, 0x120, 9, 1),
+ MUX(CLK_TOP_I2S2_MCK_SEL, apll1_ck_parents, 0x120, 10, 1),
+ MUX(CLK_TOP_I2S3_MCK_SEL, apll1_ck_parents, 0x120, 161, 1),
+};
+
+/* infracfg */
+static const struct mtk_gate_regs infra_cg_regs = {
+ .set_ofs = 0x40,
+ .clr_ofs = 0x44,
+ .sta_ofs = 0x48,
+};
+
+#define GATE_INFRA(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &infra_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate infra_cgs[] = {
+ GATE_INFRA(CLK_INFRA_DBGCLK_PD, CLK_TOP_AXI_SEL, 0),
+ GATE_INFRA(CLK_INFRA_TRNG, CLK_TOP_AXI_SEL, 2),
+ GATE_INFRA(CLK_INFRA_AUDIO_PD, CLK_TOP_AUD_INTBUS_SEL, 5),
+ GATE_INFRA(CLK_INFRA_IRRX_PD, CLK_TOP_IRRX_SEL, 16),
+ GATE_INFRA(CLK_INFRA_APXGPT_PD, CLK_TOP_F10M_REF_SEL, 18),
+ GATE_INFRA(CLK_INFRA_PMIC_PD, CLK_TOP_PMICSPI_SEL, 22),
+};
+
+/* pericfg */
+static const struct mtk_gate_regs peri0_cg_regs = {
+ .set_ofs = 0x8,
+ .clr_ofs = 0x10,
+ .sta_ofs = 0x18,
+};
+
+static const struct mtk_gate_regs peri1_cg_regs = {
+ .set_ofs = 0xC,
+ .clr_ofs = 0x14,
+ .sta_ofs = 0x1C,
+};
+
+#define GATE_PERI0(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &peri0_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+#define GATE_PERI1(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &peri1_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_SETCLR | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate peri_cgs[] = {
+ /* PERI0 */
+ GATE_PERI0(CLK_PERI_THERM_PD, CLK_TOP_AXI_SEL, 1),
+ GATE_PERI0(CLK_PERI_PWM1_PD, CLK_XTAL, 2),
+ GATE_PERI0(CLK_PERI_PWM2_PD, CLK_XTAL, 3),
+ GATE_PERI0(CLK_PERI_PWM3_PD, CLK_XTAL, 4),
+ GATE_PERI0(CLK_PERI_PWM4_PD, CLK_XTAL, 5),
+ GATE_PERI0(CLK_PERI_PWM5_PD, CLK_XTAL, 6),
+ GATE_PERI0(CLK_PERI_PWM6_PD, CLK_XTAL, 7),
+ GATE_PERI0(CLK_PERI_PWM7_PD, CLK_XTAL, 8),
+ GATE_PERI0(CLK_PERI_PWM_PD, CLK_XTAL, 9),
+ GATE_PERI0(CLK_PERI_AP_DMA_PD, CLK_TOP_AXI_SEL, 12),
+ GATE_PERI0(CLK_PERI_MSDC30_0_PD, CLK_TOP_MSDC30_0_SEL, 13),
+ GATE_PERI0(CLK_PERI_MSDC30_1_PD, CLK_TOP_MSDC30_1_SEL, 14),
+ GATE_PERI0(CLK_PERI_UART0_PD, CLK_TOP_AXI_SEL, 17),
+ GATE_PERI0(CLK_PERI_UART1_PD, CLK_TOP_AXI_SEL, 18),
+ GATE_PERI0(CLK_PERI_UART2_PD, CLK_TOP_AXI_SEL, 19),
+ GATE_PERI0(CLK_PERI_UART3_PD, CLK_TOP_AXI_SEL, 20),
+ GATE_PERI0(CLK_PERI_BTIF_PD, CLK_TOP_AXI_SEL, 22),
+ GATE_PERI0(CLK_PERI_I2C0_PD, CLK_TOP_AXI_SEL, 23),
+ GATE_PERI0(CLK_PERI_I2C1_PD, CLK_TOP_AXI_SEL, 24),
+ GATE_PERI0(CLK_PERI_I2C2_PD, CLK_TOP_AXI_SEL, 25),
+ GATE_PERI0(CLK_PERI_SPI1_PD, CLK_TOP_SPI1_SEL, 26),
+ GATE_PERI0(CLK_PERI_AUXADC_PD, CLK_XTAL, 27),
+ GATE_PERI0(CLK_PERI_SPI0_PD, CLK_TOP_SPI0_SEL, 28),
+ GATE_PERI0(CLK_PERI_SNFI_PD, CLK_TOP_NFI_INFRA_SEL, 29),
+ GATE_PERI0(CLK_PERI_NFI_PD, CLK_TOP_AXI_SEL, 30),
+ GATE_PERI1(CLK_PERI_NFIECC_PD, CLK_TOP_AXI_SEL, 31),
+
+ /* PERI1 */
+ GATE_PERI1(CLK_PERI_FLASH_PD, CLK_TOP_FLASH_SEL, 1),
+ GATE_PERI1(CLK_PERI_IRTX_PD, CLK_TOP_IRTX_SEL, 2),
+};
+
+/* ethsys */
+static const struct mtk_gate_regs eth_cg_regs = {
+ .sta_ofs = 0x30,
+};
+
+#define GATE_ETH(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = ð_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+ }
+
+static const struct mtk_gate eth_cgs[] = {
+ GATE_ETH(CLK_ETH_HSDMA_EN, CLK_TOP_ETH_SEL, 5),
+ GATE_ETH(CLK_ETH_ESW_EN, CLK_TOP_ETH_500M, 6),
+ GATE_ETH(CLK_ETH_GP2_EN, CLK_TOP_TXCLK_SRC_PRE, 7),
+ GATE_ETH(CLK_ETH_GP1_EN, CLK_TOP_TXCLK_SRC_PRE, 8),
+ GATE_ETH(CLK_ETH_GP0_EN, CLK_TOP_TXCLK_SRC_PRE, 9),
+};
+
+static const struct mtk_gate_regs sgmii_cg_regs = {
+ .sta_ofs = 0xE4,
+};
+
+#define GATE_SGMII(_id, _parent, _shift) { \
+ .id = _id, \
+ .parent = _parent, \
+ .regs = &sgmii_cg_regs, \
+ .shift = _shift, \
+ .flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_TOPCKGEN, \
+}
+
+static const struct mtk_gate sgmii_cgs[] = {
+ GATE_SGMII(CLK_SGMII_TX250M_EN, CLK_TOP_SSUSB_TX250M, 2),
+ GATE_SGMII(CLK_SGMII_RX250M_EN, CLK_TOP_SSUSB_EQ_RX250M, 3),
+ GATE_SGMII(CLK_SGMII_CDR_REF, CLK_TOP_SSUSB_CDR_REF, 4),
+ GATE_SGMII(CLK_SGMII_CDR_FB, CLK_TOP_SSUSB_CDR_FB, 5),
+};
+
+static const struct mtk_clk_tree mt7622_clk_tree = {
+ .xtal_rate = 25 * MHZ,
+ .xtal2_rate = 25 * MHZ,
+ .fdivs_offs = CLK_TOP_TO_USB3_SYS,
+ .muxes_offs = CLK_TOP_AXI_SEL,
+ .plls = apmixed_plls,
+ .fclks = top_fixed_clks,
+ .fdivs = top_fixed_divs,
+ .muxes = top_muxes,
+};
+
+static int mt7622_mcucfg_probe(struct udevice *dev)
+{
+ void __iomem *base;
+
+ base = dev_read_addr_ptr(dev);
+ if (!base)
+ return -ENOENT;
+
+ clrsetbits_le32(base + MCU_AXI_DIV, AXI_DIV_MSK,
+ AXI_DIV_SEL(0x12));
+ clrsetbits_le32(base + MCU_BUS_MUX, MCU_BUS_MSK,
+ MCU_BUS_SEL(0x1));
+
+ return 0;
+}
+
+static int mt7622_apmixedsys_probe(struct udevice *dev)
+{
+ struct mtk_clk_priv *priv = dev_get_priv(dev);
+ int ret;
+
+ ret = mtk_common_clk_init(dev, &mt7622_clk_tree);
+ if (ret)
+ return ret;
+
+ /* reduce clock square disable time */
+ // writel(0x501, priv->base + MT7622_CLKSQ_STB_CON0);
+ writel(0x98940501, priv->base + MT7622_CLKSQ_STB_CON0);
+
+ /* extend pwr/iso control timing to 1us */
+ writel(0x80008, priv->base + MT7622_PLL_ISO_CON0);
+
+ return 0;
+}
+
+static int mt7622_topckgen_probe(struct udevice *dev)
+{
+ return mtk_common_clk_init(dev, &mt7622_clk_tree);
+}
+
+static int mt7622_infracfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, infra_cgs);
+}
+
+static int mt7622_pericfg_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, peri_cgs);
+}
+
+static int mt7622_ethsys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, eth_cgs);
+}
+
+static int mt7622_ethsys_bind(struct udevice *dev)
+{
+ int ret = 0;
+
+#if CONFIG_IS_ENABLED(RESET_MEDIATEK)
+ ret = mediatek_reset_bind(dev, ETHSYS_HIFSYS_RST_CTRL_OFS, 1);
+ if (ret)
+ debug("Warning: failed to bind reset controller\n");
+#endif
+
+ return ret;
+}
+
+static int mt7622_sgmiisys_probe(struct udevice *dev)
+{
+ return mtk_common_clk_gate_init(dev, &mt7622_clk_tree, sgmii_cgs);
+}
+
+static const struct udevice_id mt7622_apmixed_compat[] = {
+ { .compatible = "mediatek,mt7622-apmixedsys" },
+ { }
+};
+
+static const struct udevice_id mt7622_topckgen_compat[] = {
+ { .compatible = "mediatek,mt7622-topckgen" },
+ { }
+};
+
+static const struct udevice_id mt7622_infracfg_compat[] = {
+ { .compatible = "mediatek,mt7622-infracfg", },
+ { }
+};
+
+static const struct udevice_id mt7622_pericfg_compat[] = {
+ { .compatible = "mediatek,mt7622-pericfg", },
+ { }
+};
+
+static const struct udevice_id mt7622_ethsys_compat[] = {
+ { .compatible = "mediatek,mt7622-ethsys", },
+ { }
+};
+
+static const struct udevice_id mt7622_sgmiisys_compat[] = {
+ { .compatible = "mediatek,mt7622-sgmiisys", },
+ { }
+};
+
+static const struct udevice_id mt7622_mcucfg_compat[] = {
+ { .compatible = "mediatek,mt7622-mcucfg" },
+ { }
+};
+
+U_BOOT_DRIVER(mtk_mcucfg) = {
+ .name = "mt7622-mcucfg",
+ .id = UCLASS_SYSCON,
+ .of_match = mt7622_mcucfg_compat,
+ .probe = mt7622_mcucfg_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+ .name = "mt7622-clock-apmixedsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_apmixed_compat,
+ .probe = mt7622_apmixedsys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_apmixedsys_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_topckgen) = {
+ .name = "mt7622-clock-topckgen",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_topckgen_compat,
+ .probe = mt7622_topckgen_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_clk_priv),
+ .ops = &mtk_clk_topckgen_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_infracfg) = {
+ .name = "mt7622-clock-infracfg",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_infracfg_compat,
+ .probe = mt7622_infracfg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_pericfg) = {
+ .name = "mt7622-clock-pericfg",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_pericfg_compat,
+ .probe = mt7622_pericfg_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
+
+U_BOOT_DRIVER(mtk_clk_ethsys) = {
+ .name = "mt7622-clock-ethsys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_ethsys_compat,
+ .probe = mt7622_ethsys_probe,
+ .bind = mt7622_ethsys_bind,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
+
+U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
+ .name = "mt7622-clock-sgmiisys",
+ .id = UCLASS_CLK,
+ .of_match = mt7622_sgmiisys_compat,
+ .probe = mt7622_sgmiisys_probe,
+ .priv_auto_alloc_size = sizeof(struct mtk_cg_priv),
+ .ops = &mtk_clk_gate_ops,
+};
diff --git a/include/dt-bindings/clock/mt7622-clk.h b/include/dt-bindings/clock/mt7622-clk.h
new file mode 100644
index 0000000000..22b8d08b60
--- /dev/null
+++ b/include/dt-bindings/clock/mt7622-clk.h
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ */
+#ifndef _DT_BINDINGS_CLK_MT7622_H
+#define _DT_BINDINGS_CLK_MT7622_H
+
+/* TOPCKGEN */
+
+/* FIXED_CLKS */
+#define CLK_TOP_TO_U2_PHY 0
+#define CLK_TOP_TO_U2_PHY_1P 1
+#define CLK_TOP_PCIE0_PIPE_EN 2
+#define CLK_TOP_PCIE1_PIPE_EN 3
+#define CLK_TOP_SSUSB_TX250M 4
+#define CLK_TOP_SSUSB_EQ_RX250M 5
+#define CLK_TOP_SSUSB_CDR_REF 6
+#define CLK_TOP_SSUSB_CDR_FB 7
+#define CLK_TOP_SATA_ASIC 8
+#define CLK_TOP_SATA_RBC 9
+/* FIXED_DIVS */
+#define CLK_TOP_TO_USB3_SYS 10
+#define CLK_TOP_P1_1MHZ 11
+#define CLK_TOP_4MHZ 12
+#define CLK_TOP_P0_1MHZ 13
+#define CLK_TOP_TXCLK_SRC_PRE 14
+#define CLK_TOP_RTC 15
+#define CLK_TOP_MEMPLL 16
+#define CLK_TOP_DMPLL 17
+#define CLK_TOP_SYSPLL_D2 18
+#define CLK_TOP_SYSPLL1_D2 19
+#define CLK_TOP_SYSPLL1_D4 20
+#define CLK_TOP_SYSPLL1_D8 21
+#define CLK_TOP_SYSPLL2_D4 22
+#define CLK_TOP_SYSPLL2_D8 23
+#define CLK_TOP_SYSPLL_D5 24
+#define CLK_TOP_SYSPLL3_D2 25
+#define CLK_TOP_SYSPLL3_D4 26
+#define CLK_TOP_SYSPLL4_D2 27
+#define CLK_TOP_SYSPLL4_D4 28
+#define CLK_TOP_SYSPLL4_D16 29
+#define CLK_TOP_UNIVPLL 30
+#define CLK_TOP_UNIVPLL_D2 31
+#define CLK_TOP_UNIVPLL1_D2 32
+#define CLK_TOP_UNIVPLL1_D4 33
+#define CLK_TOP_UNIVPLL1_D8 34
+#define CLK_TOP_UNIVPLL1_D16 35
+#define CLK_TOP_UNIVPLL2_D2 36
+#define CLK_TOP_UNIVPLL2_D4 37
+#define CLK_TOP_UNIVPLL2_D8 38
+#define CLK_TOP_UNIVPLL2_D16 39
+#define CLK_TOP_UNIVPLL_D5 40
+#define CLK_TOP_UNIVPLL3_D2 41
+#define CLK_TOP_UNIVPLL3_D4 42
+#define CLK_TOP_UNIVPLL3_D16 43
+#define CLK_TOP_UNIVPLL_D7 44
+#define CLK_TOP_UNIVPLL_D80_D4 45
+#define CLK_TOP_UNIV48M 46
+#define CLK_TOP_SGMIIPLL 47
+#define CLK_TOP_SGMIIPLL_D2 48
+#define CLK_TOP_AUD1PLL 49
+#define CLK_TOP_AUD2PLL 50
+#define CLK_TOP_AUD_I2S2_MCK 51
+#define CLK_TOP_TO_USB3_REF 52
+#define CLK_TOP_PCIE1_MAC_EN 53
+#define CLK_TOP_PCIE0_MAC_EN 54
+#define CLK_TOP_ETH_500M 55
+/* TOP_MUXES */
+#define CLK_TOP_AXI_SEL 56
+#define CLK_TOP_MEM_SEL 57
+#define CLK_TOP_DDRPHYCFG_SEL 58
+#define CLK_TOP_ETH_SEL 59
+#define CLK_TOP_PWM_SEL 60
+#define CLK_TOP_F10M_REF_SEL 61
+#define CLK_TOP_NFI_INFRA_SEL 62
+#define CLK_TOP_FLASH_SEL 63
+#define CLK_TOP_UART_SEL 64
+#define CLK_TOP_SPI0_SEL 65
+#define CLK_TOP_SPI1_SEL 66
+#define CLK_TOP_MSDC50_0_SEL 67
+#define CLK_TOP_MSDC30_0_SEL 68
+#define CLK_TOP_MSDC30_1_SEL 69
+#define CLK_TOP_A1SYS_HP_SEL 70
+#define CLK_TOP_A2SYS_HP_SEL 71
+#define CLK_TOP_INTDIR_SEL 72
+#define CLK_TOP_AUD_INTBUS_SEL 73
+#define CLK_TOP_PMICSPI_SEL 74
+#define CLK_TOP_SCP_SEL 75
+#define CLK_TOP_ATB_SEL 76
+#define CLK_TOP_HIF_SEL 77
+#define CLK_TOP_AUDIO_SEL 78
+#define CLK_TOP_U2_SEL 79
+#define CLK_TOP_AUD1_SEL 80
+#define CLK_TOP_AUD2_SEL 81
+#define CLK_TOP_IRRX_SEL 82
+#define CLK_TOP_IRTX_SEL 83
+#define CLK_TOP_ASM_L_SEL 84
+#define CLK_TOP_ASM_M_SEL 85
+#define CLK_TOP_ASM_H_SEL 86
+#define CLK_TOP_APLL1_SEL 87
+#define CLK_TOP_APLL2_SEL 88
+#define CLK_TOP_I2S0_MCK_SEL 89
+#define CLK_TOP_I2S1_MCK_SEL 90
+#define CLK_TOP_I2S2_MCK_SEL 91
+#define CLK_TOP_I2S3_MCK_SEL 92
+#define CLK_TOP_APLL1_DIV 93
+#define CLK_TOP_APLL2_DIV 94
+#define CLK_TOP_I2S0_MCK_DIV 95
+#define CLK_TOP_I2S1_MCK_DIV 96
+#define CLK_TOP_I2S2_MCK_DIV 97
+#define CLK_TOP_I2S3_MCK_DIV 98
+#define CLK_TOP_A1SYS_HP_DIV 99
+#define CLK_TOP_A2SYS_HP_DIV 100
+#define CLK_TOP_APLL1_DIV_PD 101
+#define CLK_TOP_APLL2_DIV_PD 102
+#define CLK_TOP_I2S0_MCK_DIV_PD 103
+#define CLK_TOP_I2S1_MCK_DIV_PD 104
+#define CLK_TOP_I2S2_MCK_DIV_PD 105
+#define CLK_TOP_I2S3_MCK_DIV_PD 106
+
+/* INFRACFG */
+
+#define CLK_INFRA_DBGCLK_PD 0
+#define CLK_INFRA_TRNG 1
+#define CLK_INFRA_AUDIO_PD 2
+#define CLK_INFRA_IRRX_PD 3
+#define CLK_INFRA_APXGPT_PD 4
+#define CLK_INFRA_PMIC_PD 5
+
+/* PERICFG */
+
+#define CLK_PERI_THERM_PD 0
+#define CLK_PERI_PWM1_PD 1
+#define CLK_PERI_PWM2_PD 2
+#define CLK_PERI_PWM3_PD 3
+#define CLK_PERI_PWM4_PD 4
+#define CLK_PERI_PWM5_PD 5
+#define CLK_PERI_PWM6_PD 6
+#define CLK_PERI_PWM7_PD 7
+#define CLK_PERI_PWM_PD 8
+#define CLK_PERI_AP_DMA_PD 9
+#define CLK_PERI_MSDC30_0_PD 10
+#define CLK_PERI_MSDC30_1_PD 11
+#define CLK_PERI_UART0_PD 12
+#define CLK_PERI_UART1_PD 13
+#define CLK_PERI_UART2_PD 14
+#define CLK_PERI_UART3_PD 15
+#define CLK_PERI_BTIF_PD 16
+#define CLK_PERI_I2C0_PD 17
+#define CLK_PERI_I2C1_PD 18
+#define CLK_PERI_I2C2_PD 19
+#define CLK_PERI_SPI1_PD 20
+#define CLK_PERI_AUXADC_PD 21
+#define CLK_PERI_SPI0_PD 22
+#define CLK_PERI_SNFI_PD 23
+#define CLK_PERI_NFI_PD 24
+#define CLK_PERI_NFIECC_PD 25
+#define CLK_PERI_FLASH_PD 26
+#define CLK_PERI_IRTX_PD 27
+
+/* APMIXEDSYS */
+
+#define CLK_APMIXED_ARMPLL 0
+#define CLK_APMIXED_MAINPLL 1
+#define CLK_APMIXED_UNIV2PLL 2
+#define CLK_APMIXED_ETH1PLL 3
+#define CLK_APMIXED_ETH2PLL 4
+#define CLK_APMIXED_AUD1PLL 5
+#define CLK_APMIXED_AUD2PLL 6
+#define CLK_APMIXED_TRGPLL 7
+#define CLK_APMIXED_SGMIPLL 8
+
+/* AUDIOSYS */
+
+#define CLK_AUDIO_AFE 0
+#define CLK_AUDIO_HDMI 1
+#define CLK_AUDIO_SPDF 2
+#define CLK_AUDIO_APLL 3
+#define CLK_AUDIO_I2SIN1 4
+#define CLK_AUDIO_I2SIN2 5
+#define CLK_AUDIO_I2SIN3 6
+#define CLK_AUDIO_I2SIN4 7
+#define CLK_AUDIO_I2SO1 8
+#define CLK_AUDIO_I2SO2 9
+#define CLK_AUDIO_I2SO3 10
+#define CLK_AUDIO_I2SO4 11
+#define CLK_AUDIO_ASRCI1 12
+#define CLK_AUDIO_ASRCI2 13
+#define CLK_AUDIO_ASRCO1 14
+#define CLK_AUDIO_ASRCO2 15
+#define CLK_AUDIO_INTDIR 16
+#define CLK_AUDIO_A1SYS 17
+#define CLK_AUDIO_A2SYS 18
+#define CLK_AUDIO_UL1 19
+#define CLK_AUDIO_UL2 20
+#define CLK_AUDIO_UL3 21
+#define CLK_AUDIO_UL4 22
+#define CLK_AUDIO_UL5 23
+#define CLK_AUDIO_UL6 24
+#define CLK_AUDIO_DL1 25
+#define CLK_AUDIO_DL2 26
+#define CLK_AUDIO_DL3 27
+#define CLK_AUDIO_DL4 28
+#define CLK_AUDIO_DL5 29
+#define CLK_AUDIO_DL6 30
+#define CLK_AUDIO_DLMCH 31
+#define CLK_AUDIO_ARB1 32
+#define CLK_AUDIO_AWB 33
+#define CLK_AUDIO_AWB3 34
+#define CLK_AUDIO_DAI 35
+#define CLK_AUDIO_MOD 36
+#define CLK_AUDIO_ASRCI3 37
+#define CLK_AUDIO_ASRCI4 38
+#define CLK_AUDIO_ASRCO3 39
+#define CLK_AUDIO_ASRCO4 40
+#define CLK_AUDIO_MEM_ASRC1 41
+#define CLK_AUDIO_MEM_ASRC2 42
+#define CLK_AUDIO_MEM_ASRC3 43
+#define CLK_AUDIO_MEM_ASRC4 44
+#define CLK_AUDIO_MEM_ASRC5 45
+#define CLK_AUDIO_AFE_CONN 46
+#define CLK_AUDIO_NR_CLK 47
+
+/* SSUSBSYS */
+
+#define CLK_SSUSB_U2_PHY_1P_EN 0
+#define CLK_SSUSB_U2_PHY_EN 1
+#define CLK_SSUSB_REF_EN 2
+#define CLK_SSUSB_SYS_EN 3
+#define CLK_SSUSB_MCU_EN 4
+#define CLK_SSUSB_DMA_EN 5
+#define CLK_SSUSB_NR_CLK 6
+
+/* PCIESYS */
+
+#define CLK_PCIE_P1_AUX_EN 0
+#define CLK_PCIE_P1_OBFF_EN 1
+#define CLK_PCIE_P1_AHB_EN 2
+#define CLK_PCIE_P1_AXI_EN 3
+#define CLK_PCIE_P1_MAC_EN 4
+#define CLK_PCIE_P1_PIPE_EN 5
+#define CLK_PCIE_P0_AUX_EN 6
+#define CLK_PCIE_P0_OBFF_EN 7
+#define CLK_PCIE_P0_AHB_EN 8
+#define CLK_PCIE_P0_AXI_EN 9
+#define CLK_PCIE_P0_MAC_EN 10
+#define CLK_PCIE_P0_PIPE_EN 11
+#define CLK_SATA_AHB_EN 12
+#define CLK_SATA_AXI_EN 13
+#define CLK_SATA_ASIC_EN 14
+#define CLK_SATA_RBC_EN 15
+#define CLK_SATA_PM_EN 16
+#define CLK_PCIE_NR_CLK 17
+
+/* ETHSYS */
+
+#define CLK_ETH_HSDMA_EN 0
+#define CLK_ETH_ESW_EN 1
+#define CLK_ETH_GP2_EN 2
+#define CLK_ETH_GP1_EN 3
+#define CLK_ETH_GP0_EN 4
+
+/* SGMIISYS */
+
+#define CLK_SGMII_TX250M_EN 0
+#define CLK_SGMII_RX250M_EN 1
+#define CLK_SGMII_CDR_REF 2
+#define CLK_SGMII_CDR_FB 3
+
+#endif /* _DT_BINDINGS_CLK_MT7622_H */
+
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 05/10] clk: mediatek: fix clock-rate overflow problem
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (3 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 04/10] clk: mediatek: add driver for MT7622 Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 06/10] power: domain: add power domain support for MT7622 Sam Shih
` (4 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch fix clock-rate overflow problem in mediatek
clock driver common part.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/clk/mediatek/clk-mtk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 6c6b500d9b..9c30be994e 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -39,7 +39,7 @@
* this function is recursively called to find the parent to calculate
* the accurate frequency.
*/
-static int mtk_clk_find_parent_rate(struct clk *clk, int id,
+static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
const struct driver *drv)
{
struct clk parent = { .id = id, };
@@ -265,7 +265,7 @@ static ulong mtk_factor_recalc_rate(const struct mtk_fixed_factor *fdiv,
return rate;
}
-static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
+static ulong mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_fixed_factor *fdiv = &priv->tree->fdivs[off];
@@ -287,7 +287,7 @@ static int mtk_topckgen_get_factor_rate(struct clk *clk, u32 off)
return mtk_factor_recalc_rate(fdiv, rate);
}
-static int mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
+static ulong mtk_topckgen_get_mux_rate(struct clk *clk, u32 off)
{
struct mtk_clk_priv *priv = dev_get_priv(clk->dev);
const struct mtk_composite *mux = &priv->tree->muxes[off];
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 06/10] power: domain: add power domain support for MT7622
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (4 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 05/10] clk: mediatek: fix clock-rate overflow problem Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 07/10] mmc: add mmc and sd " Sam Shih
` (3 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch add power domain support for Mediatek MT7622 SoCs
Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
---
drivers/power/domain/mtk-power-domain.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c
index c67e8804b1..0bf8a16447 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -60,6 +60,7 @@
#define DCM_TOP_EN BIT(0)
enum scp_domain_type {
+ SCPSYS_MT7622,
SCPSYS_MT7623,
SCPSYS_MT7629,
};
@@ -328,6 +329,7 @@ static int mtk_power_domain_hook(struct udevice *dev)
case SCPSYS_MT7623:
scpd->data = scp_domain_mt7623;
break;
+ case SCPSYS_MT7622:
case SCPSYS_MT7629:
scpd->data = scp_domain_mt7629;
break;
@@ -378,6 +380,10 @@ static int mtk_power_domain_probe(struct udevice *dev)
}
static const struct udevice_id mtk_power_domain_ids[] = {
+ {
+ .compatible = "mediatek,mt7622-scpsys",
+ .data = SCPSYS_MT7622,
+ },
{
.compatible = "mediatek,mt7623-scpsys",
.data = SCPSYS_MT7623,
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 07/10] mmc: add mmc and sd support for MT7622
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (5 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 06/10] power: domain: add power domain support for MT7622 Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 08/10] Add support for MT7622 reference board Sam Shih
` (2 subsequent siblings)
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch add mmc and sd support for Mediatek MT7622 SoCs
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
drivers/mmc/mtk-sd.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index eaa584a4df..a3ede3070a 100644
--- a/drivers/mmc/mtk-sd.c
+++ b/drivers/mmc/mtk-sd.c
@@ -1568,6 +1568,15 @@ static const struct msdc_compatible mt7620_compat = {
.enhance_rx = false
};
+static const struct msdc_compatible mt7622_compat = {
+ .clk_div_bits = 12,
+ .pad_tune0 = true,
+ .async_fifo = true,
+ .data_tune = true,
+ .busy_check = true,
+ .stop_clk_fix = true,
+};
+
static const struct msdc_compatible mt7623_compat = {
.clk_div_bits = 12,
.sclk_cycle_shift = 20,
@@ -1601,6 +1610,7 @@ static const struct msdc_compatible mt8183_compat = {
static const struct udevice_id msdc_ids[] = {
{ .compatible = "mediatek,mt7620-mmc", .data = (ulong)&mt7620_compat },
+ { .compatible = "mediatek,mt7622-mmc", .data = (ulong)&mt7622_compat },
{ .compatible = "mediatek,mt7623-mmc", .data = (ulong)&mt7623_compat },
{ .compatible = "mediatek,mt8516-mmc", .data = (ulong)&mt8516_compat },
{ .compatible = "mediatek,mt8183-mmc", .data = (ulong)&mt8183_compat },
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 08/10] Add support for MT7622 reference board
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (6 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 07/10] mmc: add mmc and sd " Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 09/10] arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file Sam Shih
2020-01-10 8:30 ` [RESEND v2 10/10] configs: mediatek: fix mt7623n bpir2 defconfig Sam Shih
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This adds a general board file based on MT7622 SoCs from MediaTek.
This commit is adding the basic boot support for the MT7622 rfb.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Tested-by: Frank Wunderlich <frank-w@public-files.de>
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/mt7622-rfb.dts | 180 +++++++++++++++++++++++++++++
board/mediatek/mt7622/Kconfig | 17 +++
board/mediatek/mt7622/MAINTAINERS | 6 +
board/mediatek/mt7622/Makefile | 4 +
board/mediatek/mt7622/mt7622_rfb.c | 23 ++++
configs/mt7622_rfb_defconfig | 55 +++++++++
include/configs/mt7622.h | 46 ++++++++
8 files changed, 332 insertions(+)
create mode 100644 arch/arm/dts/mt7622-rfb.dts
create mode 100644 board/mediatek/mt7622/Kconfig
create mode 100644 board/mediatek/mt7622/MAINTAINERS
create mode 100644 board/mediatek/mt7622/Makefile
create mode 100644 board/mediatek/mt7622/mt7622_rfb.c
create mode 100644 configs/mt7622_rfb_defconfig
create mode 100644 include/configs/mt7622.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3dc9c4d41c..b92980bd76 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -833,6 +833,7 @@ dtb-$(CONFIG_SOC_K3_J721E) += k3-j721e-common-proc-board.dtb \
k3-j721e-r5-common-proc-board.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += \
+ mt7622-rfb.dtb \
mt7623n-bananapi-bpi-r2.dtb \
mt7629-rfb.dtb \
mt8516-pumpkin.dtb \
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
new file mode 100644
index 0000000000..ec30f5c6eb
--- /dev/null
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -0,0 +1,180 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+/dts-v1/;
+#include "mt7622.dtsi"
+#include "mt7622-u-boot.dtsi"
+
+/ {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ model = "mt7622-rfb";
+ compatible = "mediatek,mt7622", "mediatek,mt7622-rfb";
+ chosen {
+ stdout-path = &uart0;
+ tick-timer = &timer0;
+ };
+
+ aliases {
+ spi0 = &snfi;
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0x40000000 0x10000000>;
+ };
+
+ reg_1p8v: regulator-1p8v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-1.8V";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+
+ reg_3p3v: regulator-3p3v {
+ compatible = "regulator-fixed";
+ regulator-name = "fixed-3.3V";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-boot-on;
+ regulator-always-on;
+ };
+};
+
+
+&pinctrl {
+ snfi_pins: snfi-pins {
+ mux {
+ function = "flash";
+ groups = "snfi";
+ };
+ };
+
+ snor_pins: snor-pins {
+ mux {
+ function = "flash";
+ groups = "spi_nor";
+ };
+ };
+
+ uart0_pins: uart0 {
+ mux {
+ function = "uart";
+ groups = "uart0_0_tx_rx" ;
+ };
+ };
+
+ watchdog_pins: watchdog-default {
+ mux {
+ function = "watchdog";
+ groups = "watchdog";
+ };
+ };
+
+ mmc0_pins_default: mmc0default {
+ mux {
+ function = "emmc";
+ groups = "emmc";
+ };
+
+ /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
+ * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
+ * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
+ */
+ conf-cmd-dat {
+ pins = "NDL0", "NDL1", "NDL2",
+ "NDL3", "NDL4", "NDL5",
+ "NDL6", "NDL7", "NRB";
+ input-enable;
+ bias-pull-up;
+ };
+
+ conf-clk {
+ pins = "NCLE";
+ bias-pull-down;
+ };
+
+ };
+
+ mmc1_pins_default: mmc1default {
+ mux {
+ function = "sd";
+ groups = "sd_0";
+ };
+ /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
+ * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
+ * DAT2, DAT3, CMD, CLK for SD respectively.
+ */
+ conf-cmd-data {
+ pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
+ "I2S2_IN","I2S4_OUT";
+ input-enable;
+ drive-strength = <8>;
+ bias-pull-up;
+ };
+ conf-clk {
+ pins = "I2S3_OUT";
+ drive-strength = <12>;
+ bias-pull-down;
+ };
+ conf-cd {
+ pins = "TXD3";
+ bias-pull-up;
+ };
+
+ };
+};
+
+&snfi {
+ pinctrl-names = "default", "snfi";
+ pinctrl-0 = <&snor_pins>;
+ pinctrl-1 = <&snfi_pins>;
+ status = "okay";
+
+ spi-flash at 0{
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ u-boot,dm-pre-reloc;
+ };
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pins>;
+ status = "okay";
+};
+
+&mmc0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins_default>;
+ status = "okay";
+ bus-width = <8>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+ non-removable;
+};
+
+&mmc1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc1_pins_default>;
+ status = "okay";
+ bus-width = <4>;
+ max-frequency = <50000000>;
+ cap-sd-highspeed;
+ r_smpl = <1>;
+ vmmc-supply = <®_3p3v>;
+ vqmmc-supply = <®_3p3v>;
+};
+
+&watchdog {
+ pinctrl-names = "default";
+ pinctrl-0 = <&watchdog_pins>;
+ status = "okay";
+};
diff --git a/board/mediatek/mt7622/Kconfig b/board/mediatek/mt7622/Kconfig
new file mode 100644
index 0000000000..d0abdc0a67
--- /dev/null
+++ b/board/mediatek/mt7622/Kconfig
@@ -0,0 +1,17 @@
+if TARGET_MT7622
+
+config SYS_BOARD
+ default "mt7622"
+
+config SYS_CONFIG_NAME
+ default "mt7622"
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "lk=1"
+
+config MTK_BROM_HEADER_INFO
+ string
+ default "media=nor"
+
+endif
diff --git a/board/mediatek/mt7622/MAINTAINERS b/board/mediatek/mt7622/MAINTAINERS
new file mode 100644
index 0000000000..a3e0e75ca0
--- /dev/null
+++ b/board/mediatek/mt7622/MAINTAINERS
@@ -0,0 +1,6 @@
+MT7622
+M: Sam Shih <sam.shih@mediatek.com>
+S: Maintained
+F: board/mediatek/mt7622
+F: include/configs/mt7622.h
+F: configs/mt7622_rfb_defconfig
diff --git a/board/mediatek/mt7622/Makefile b/board/mediatek/mt7622/Makefile
new file mode 100644
index 0000000000..2c54d86fff
--- /dev/null
+++ b/board/mediatek/mt7622/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-y += mt7622_rfb.o
+
diff --git a/board/mediatek/mt7622/mt7622_rfb.c b/board/mediatek/mt7622/mt7622_rfb.c
new file mode 100644
index 0000000000..b9296bede2
--- /dev/null
+++ b/board/mediatek/mt7622/mt7622_rfb.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#include <common.h>
+#include <config.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int board_init(void)
+{
+ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
+ return 0;
+}
+
+int board_late_init(void)
+{
+ gd->env_valid = 1; //to load environment variable from persistent store
+ env_relocate();
+ return 0;
+}
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
new file mode 100644
index 0000000000..e1917e70e7
--- /dev/null
+++ b/configs/mt7622_rfb_defconfig
@@ -0,0 +1,55 @@
+CONFIG_ARM=y
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_MEDIATEK=y
+CONFIG_TARGET_MT7622=y
+CONFIG_SYS_TEXT_BASE=0x41e00000
+CONFIG_SYS_MALLOC_F_LEN=0x4000
+CONFIG_NR_DRAM_BANKS=1
+CONFIG_SMBIOS_PRODUCT_NAME=""
+CONFIG_FIT=y
+CONFIG_LOGLEVEL=7
+CONFIG_LOG=y
+CONFIG_LOG_MAX_LEVEL=6
+CONFIG_DEFAULT_FDT_FILE="mt7622-rfb"
+CONFIG_SYS_PROMPT="MT7622> "
+CONFIG_CMD_BOOTMENU=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF_TEST=y
+CONFIG_CMD_SMC=y
+CONFIG_DEFAULT_DEVICE_TREE="mt7622-rfb"
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_CLK=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MTK=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_ISSI=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_SPANSION=y
+CONFIG_SPI_FLASH_STMICRO=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_DM_ETH=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MT7622=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_RAM=y
+CONFIG_DM_RESET=y
+CONFIG_DM_SERIAL=y
+CONFIG_MTK_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_MTK_SNFI_SPI=y
+CONFIG_SYSRESET_WATCHDOG=y
+CONFIG_TIMER=y
+CONFIG_MTK_TIMER=y
+CONFIG_WDT_MTK=y
+CONFIG_LZ4=y
+CONFIG_LZO=y
+CONFIG_HEXDUMP=y
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h
new file mode 100644
index 0000000000..dfd506ed24
--- /dev/null
+++ b/include/configs/mt7622.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Configuration for MediaTek MT7629 SoC
+ *
+ * Copyright (C) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+#ifndef __MT7622_H
+#define __MT7622_H
+
+#include <linux/sizes.h>
+
+#define CONFIG_SYS_MAXARGS 8
+#define CONFIG_SYS_BOOTM_LEN SZ_64M
+#define CONFIG_SYS_CBSIZE SZ_1K
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
+ sizeof(CONFIG_SYS_PROMPT) + 16)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN SZ_4M
+#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M
+
+/* Allow to overwrite serial and ethaddr */
+#define CONFIG_ENV_OVERWRITE
+
+#define CONFIG_SYS_MMC_ENV_DEV 0
+
+/* Uboot definition */
+#define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
+
+/* SPL -> Uboot */
+#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + SZ_2M - \
+ GENERATED_GBL_DATA_SIZE)
+/* UBoot -> Kernel */
+#define CONFIG_LOADADDR 0x4007ff28
+#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
+
+/* DRAM */
+#define CONFIG_SYS_SDRAM_BASE 0x40000000
+
+/* Ethernet */
+#define CONFIG_IPADDR 192.168.1.1
+#define CONFIG_SERVERIP 192.168.1.3
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 09/10] arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (7 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 08/10] Add support for MT7622 reference board Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 10/10] configs: mediatek: fix mt7623n bpir2 defconfig Sam Shih
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch move u-boot properties to -u-boot.dtsi file.
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
arch/arm/dts/mt7623-u-boot.dtsi | 29 +++++++++++++++++++
arch/arm/dts/mt7623.dtsi | 6 ----
arch/arm/dts/mt7623n-bananapi-bpi-r2.dts | 1 +
arch/arm/dts/mt7629-rfb-u-boot.dtsi | 36 ++++++++++++++++++++++++
arch/arm/dts/mt7629-rfb.dts | 1 +
arch/arm/dts/mt7629.dtsi | 9 ------
6 files changed, 67 insertions(+), 15 deletions(-)
create mode 100644 arch/arm/dts/mt7623-u-boot.dtsi
diff --git a/arch/arm/dts/mt7623-u-boot.dtsi b/arch/arm/dts/mt7623-u-boot.dtsi
new file mode 100644
index 0000000000..832c16dca8
--- /dev/null
+++ b/arch/arm/dts/mt7623-u-boot.dtsi
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 MediaTek Inc.
+ * Author: Sam Shih <sam.shih@mediatek.com>
+ */
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&uart2 {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt7623.dtsi b/arch/arm/dts/mt7623.dtsi
index 1135b1e1ae..1f45dea575 100644
--- a/arch/arm/dts/mt7623.dtsi
+++ b/arch/arm/dts/mt7623.dtsi
@@ -101,21 +101,18 @@
compatible = "mediatek,mt7623-topckgen";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
infracfg: syscon at 10001000 {
compatible = "mediatek,mt7623-infracfg", "syscon";
reg = <0x10001000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
pericfg: syscon at 10003000 {
compatible = "mediatek,mt7623-pericfg", "syscon";
reg = <0x10003000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
pinctrl: pinctrl at 10005000 {
@@ -155,7 +152,6 @@
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_LOW>;
clocks = <&system_clk>;
clock-names = "system-clk";
- u-boot,dm-pre-reloc;
};
sysirq: interrupt-controller at 10200100 {
@@ -170,7 +166,6 @@
compatible = "mediatek,mt7623-apmixedsys";
reg = <0x10209000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
gic: interrupt-controller at 10211000 {
@@ -215,7 +210,6 @@
<&pericfg CLK_PERI_UART2>;
clock-names = "baud", "bus";
status = "disabled";
- u-boot,dm-pre-reloc;
};
uart3: serial at 11005000 {
diff --git a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
index b0c86219b6..bcedcf20f1 100644
--- a/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
+++ b/arch/arm/dts/mt7623n-bananapi-bpi-r2.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "mt7623.dtsi"
+#include "mt7623-u-boot.dtsi"
/ {
model = "Bananapi BPI-R2";
diff --git a/arch/arm/dts/mt7629-rfb-u-boot.dtsi b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
index 1ef5568518..164afd633b 100644
--- a/arch/arm/dts/mt7629-rfb-u-boot.dtsi
+++ b/arch/arm/dts/mt7629-rfb-u-boot.dtsi
@@ -22,3 +22,39 @@
#endif
};
};
+
+&infracfg {
+ u-boot,dm-pre-reloc;
+};
+
+&pericfg {
+ u-boot,dm-pre-reloc;
+};
+
+&timer0 {
+ u-boot,dm-pre-reloc;
+};
+
+&mcucfg {
+ u-boot,dm-pre-reloc;
+};
+
+&dramc {
+ u-boot,dm-pre-reloc;
+};
+
+&apmixedsys {
+ u-boot,dm-pre-reloc;
+};
+
+&topckgen {
+ u-boot,dm-pre-reloc;
+};
+
+&uart0 {
+ u-boot,dm-pre-reloc;
+};
+
+&snfi {
+ u-boot,dm-pre-reloc;
+};
diff --git a/arch/arm/dts/mt7629-rfb.dts b/arch/arm/dts/mt7629-rfb.dts
index 0981f9b3b1..687fe1c029 100644
--- a/arch/arm/dts/mt7629-rfb.dts
+++ b/arch/arm/dts/mt7629-rfb.dts
@@ -7,6 +7,7 @@
/dts-v1/;
#include "mt7629.dtsi"
+#include "mt7629-rfb-u-boot.dtsi"
/ {
model = "MediaTek MT7629 RFB";
diff --git a/arch/arm/dts/mt7629.dtsi b/arch/arm/dts/mt7629.dtsi
index b0c843bafd..a33a74a556 100644
--- a/arch/arm/dts/mt7629.dtsi
+++ b/arch/arm/dts/mt7629.dtsi
@@ -68,14 +68,12 @@
compatible = "mediatek,mt7629-infracfg", "syscon";
reg = <0x10000000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
pericfg: syscon at 10002000 {
compatible = "mediatek,mt7629-pericfg", "syscon";
reg = <0x10002000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
timer0: timer at 10004000 {
@@ -85,7 +83,6 @@
clocks = <&topckgen CLK_TOP_CLKXTAL_D4>,
<&topckgen CLK_TOP_10M_SEL>;
clock-names = "mux", "src";
- u-boot,dm-pre-reloc;
};
scpsys: scpsys at 10006000 {
@@ -103,7 +100,6 @@
compatible = "mediatek,mt7629-mcucfg", "syscon";
reg = <0x10200000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
sysirq: interrupt-controller at 10200a80 {
@@ -124,21 +120,18 @@
<&topckgen CLK_TOP_MEM_SEL>,
<&topckgen CLK_TOP_DMPLL>;
clock-names = "phy", "phy_mux", "mem", "mem_mux";
- u-boot,dm-pre-reloc;
};
apmixedsys: clock-controller at 10209000 {
compatible = "mediatek,mt7629-apmixedsys";
reg = <0x10209000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
topckgen: clock-controller at 10210000 {
compatible = "mediatek,mt7629-topckgen";
reg = <0x10210000 0x1000>;
#clock-cells = <1>;
- u-boot,dm-pre-reloc;
};
watchdog: watchdog at 10212000 {
@@ -186,7 +179,6 @@
status = "disabled";
assigned-clocks = <&topckgen CLK_TOP_AXI_SEL>;
assigned-clock-parents = <&topckgen CLK_TOP_SYSPLL1_D2>;
- u-boot,dm-pre-reloc;
};
uart1: serial at 11003000 {
@@ -228,7 +220,6 @@
status = "disabled";
#address-cells = <1>;
#size-cells = <0>;
- u-boot,dm-pre-reloc;
};
ethsys: syscon at 1b000000 {
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 10/10] configs: mediatek: fix mt7623n bpir2 defconfig
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
` (8 preceding siblings ...)
2020-01-10 8:30 ` [RESEND v2 09/10] arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file Sam Shih
@ 2020-01-10 8:30 ` Sam Shih
2020-01-16 14:43 ` Tom Rini
9 siblings, 1 reply; 21+ messages in thread
From: Sam Shih @ 2020-01-10 8:30 UTC (permalink / raw)
To: u-boot
This patch add CONFIG_TARGET_MT7623 into mt7623n_bpir2_defconfig
to fix the mt7623 compile error after building others mediatek target
platform
Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
---
configs/mt7623n_bpir2_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index 58e93d5da6..d6ccae1942 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -1,6 +1,7 @@
CONFIG_ARM=y
CONFIG_SYS_THUMB_BUILD=y
CONFIG_ARCH_MEDIATEK=y
+CONFIG_TARGET_MT7623=y
CONFIG_SYS_TEXT_BASE=0x81e00000
CONFIG_SYS_MALLOC_F_LEN=0x4000
CONFIG_ENV_SIZE=0x1000
--
2.17.1
^ permalink raw reply related [flat|nested] 21+ messages in thread
* [RESEND v2 01/10] ARM: MediaTek: Add support for MediaTek MT7622 SoC
2020-01-10 8:30 ` [RESEND v2 01/10] ARM: MediaTek: " Sam Shih
@ 2020-01-16 14:42 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:42 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:26PM +0800, Sam Shih wrote:
> Add support for MediaTek MT7622 SoC. This include the file
> that will initialize the SoC after boot and its device tree.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/4d3a0bf9/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 02/10] pinctrl: mediatek: add driver for MT7622
2020-01-10 8:30 ` [RESEND v2 02/10] pinctrl: mediatek: add driver for MT7622 Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:27PM +0800, Sam Shih wrote:
> This patch add Pinctrl driver for MediaTek MT7622 SoC.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/90b62734/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 03/10] pinctrl: mediatek: add support for different pinctrl
2020-01-10 8:30 ` [RESEND v2 03/10] pinctrl: mediatek: add support for different pinctrl Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:28PM +0800, Sam Shih wrote:
> Due to the pinctrl hardware of MT7622 is difference from others
> SoC which using the common part of mediatek pinctrl.
> So we need to modify the common part of mediatek pinctrl.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/096c237a/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 04/10] clk: mediatek: add driver for MT7622
2020-01-10 8:30 ` [RESEND v2 04/10] clk: mediatek: add driver for MT7622 Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:29PM +0800, Sam Shih wrote:
> This patch add clock driver for MediaTek MT7622 SoC.
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/cd2d5461/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 05/10] clk: mediatek: fix clock-rate overflow problem
2020-01-10 8:30 ` [RESEND v2 05/10] clk: mediatek: fix clock-rate overflow problem Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:30PM +0800, Sam Shih wrote:
> This patch fix clock-rate overflow problem in mediatek
> clock driver common part.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/e049fa0d/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 06/10] power: domain: add power domain support for MT7622
2020-01-10 8:30 ` [RESEND v2 06/10] power: domain: add power domain support for MT7622 Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:31PM +0800, Sam Shih wrote:
> This patch add power domain support for Mediatek MT7622 SoCs
>
> Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/312a911e/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 07/10] mmc: add mmc and sd support for MT7622
2020-01-10 8:30 ` [RESEND v2 07/10] mmc: add mmc and sd " Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:32PM +0800, Sam Shih wrote:
> This patch add mmc and sd support for Mediatek MT7622 SoCs
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/e48123db/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 08/10] Add support for MT7622 reference board
2020-01-10 8:30 ` [RESEND v2 08/10] Add support for MT7622 reference board Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:33PM +0800, Sam Shih wrote:
> This adds a general board file based on MT7622 SoCs from MediaTek.
> This commit is adding the basic boot support for the MT7622 rfb.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
> Tested-by: Frank Wunderlich <frank-w@public-files.de>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/7771387a/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 09/10] arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file
2020-01-10 8:30 ` [RESEND v2 09/10] arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:34PM +0800, Sam Shih wrote:
> This patch move u-boot properties to -u-boot.dtsi file.
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/608f7bfd/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
* [RESEND v2 10/10] configs: mediatek: fix mt7623n bpir2 defconfig
2020-01-10 8:30 ` [RESEND v2 10/10] configs: mediatek: fix mt7623n bpir2 defconfig Sam Shih
@ 2020-01-16 14:43 ` Tom Rini
0 siblings, 0 replies; 21+ messages in thread
From: Tom Rini @ 2020-01-16 14:43 UTC (permalink / raw)
To: u-boot
On Fri, Jan 10, 2020 at 04:30:35PM +0800, Sam Shih wrote:
> This patch add CONFIG_TARGET_MT7623 into mt7623n_bpir2_defconfig
> to fix the mt7623 compile error after building others mediatek target
> platform
>
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>
> Reviewed-by: Ryder Lee <ryder.lee@mediatek.com>
Applied to u-boot/master, thanks!
--
Tom
-------------- next part --------------
A non-text attachment was scrubbed...
Name: signature.asc
Type: application/pgp-signature
Size: 833 bytes
Desc: not available
URL: <https://lists.denx.de/pipermail/u-boot/attachments/20200116/6b352451/attachment.sig>
^ permalink raw reply [flat|nested] 21+ messages in thread
end of thread, other threads:[~2020-01-16 14:43 UTC | newest]
Thread overview: 21+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-10 8:30 [RESEND v2,00/10] Add support for MediaTek MT7622 SoC Sam Shih
2020-01-10 8:30 ` [RESEND v2 01/10] ARM: MediaTek: " Sam Shih
2020-01-16 14:42 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 02/10] pinctrl: mediatek: add driver for MT7622 Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 03/10] pinctrl: mediatek: add support for different pinctrl Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 04/10] clk: mediatek: add driver for MT7622 Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 05/10] clk: mediatek: fix clock-rate overflow problem Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 06/10] power: domain: add power domain support for MT7622 Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 07/10] mmc: add mmc and sd " Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 08/10] Add support for MT7622 reference board Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 09/10] arm: dts: mediatek: move u-boot properties to -u-boot.dtsi file Sam Shih
2020-01-16 14:43 ` Tom Rini
2020-01-10 8:30 ` [RESEND v2 10/10] configs: mediatek: fix mt7623n bpir2 defconfig Sam Shih
2020-01-16 14:43 ` Tom Rini
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.