* [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32
@ 2020-01-13 10:16 chen gong
2020-01-13 10:16 ` [PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro chen gong
2020-01-13 15:56 ` [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 Huang Rui
0 siblings, 2 replies; 6+ messages in thread
From: chen gong @ 2020-01-13 10:16 UTC (permalink / raw)
To: amd-gfx; +Cc: chen gong
Reading some registers by mmio will result in hang when GPU is in
"gfxoff" state.
This problem can be solved by GPU in "ring command packages" way.
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index 63eab0c..92c5ee4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1016,10 +1016,13 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
#define AMDGPU_REGS_IDX (1<<0)
#define AMDGPU_REGS_NO_KIQ (1<<1)
+#define AMDGPU_REGS_KIQ (1<<2)
#define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
#define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
+#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)
+
#define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
#define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2c64d2a..4045b56 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -217,7 +217,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
{
uint32_t ret;
- if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
+ if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
return amdgpu_virt_kiq_rreg(adev, reg);
if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro
2020-01-13 10:16 [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 chen gong
@ 2020-01-13 10:16 ` chen gong
2020-01-13 15:58 ` Huang Rui
2020-01-13 15:56 ` [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 Huang Rui
1 sibling, 1 reply; 6+ messages in thread
From: chen gong @ 2020-01-13 10:16 UTC (permalink / raw)
To: amd-gfx; +Cc: chen gong
Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
hang when GPU is in "gfxoff" state.
Signed-off-by: chen gong <curry.gong@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index e3d466b..a666086 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -4702,7 +4702,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
*flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
/* AMD_CG_SUPPORT_GFX_CP_LS */
- data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
+ data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
*flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
--
2.7.4
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32
2020-01-13 10:16 [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 chen gong
2020-01-13 10:16 ` [PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro chen gong
@ 2020-01-13 15:56 ` Huang Rui
2020-01-14 4:20 ` Huang Rui
1 sibling, 1 reply; 6+ messages in thread
From: Huang Rui @ 2020-01-13 15:56 UTC (permalink / raw)
To: chen gong; +Cc: amd-gfx
On Mon, Jan 13, 2020 at 06:16:21PM +0800, chen gong wrote:
> Reading some registers by mmio will result in hang when GPU is in
> "gfxoff" state.
>
> This problem can be solved by GPU in "ring command packages" way.
>
> Signed-off-by: chen gong <curry.gong@amd.com>
Acked-by: Huang Rui <ray.huang@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> 2 files changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index 63eab0c..92c5ee4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1016,10 +1016,13 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>
> #define AMDGPU_REGS_IDX (1<<0)
> #define AMDGPU_REGS_NO_KIQ (1<<1)
> +#define AMDGPU_REGS_KIQ (1<<2)
>
> #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
> #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
>
> +#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)
> +
> #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
> #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> index 2c64d2a..4045b56 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> @@ -217,7 +217,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> {
> uint32_t ret;
>
> - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
> + if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
> return amdgpu_virt_kiq_rreg(adev, reg);
>
> if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cray.huang%40amd.com%7C30ace3a1329f439cb69508d79811d5aa%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637145074676514100&sdata=t6rAUcThU9cmcu5Rwh%2BuHFDtj7Yie4tRN%2FgF2OSBZ00%3D&reserved=0
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro
2020-01-13 10:16 ` [PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro chen gong
@ 2020-01-13 15:58 ` Huang Rui
0 siblings, 0 replies; 6+ messages in thread
From: Huang Rui @ 2020-01-13 15:58 UTC (permalink / raw)
To: chen gong; +Cc: amd-gfx
On Mon, Jan 13, 2020 at 06:16:22PM +0800, chen gong wrote:
> Reading CP_MEM_SLP_CNTL register with RREG32_SOC15 macro will lead to
> hang when GPU is in "gfxoff" state.
>
> Signed-off-by: chen gong <curry.gong@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index e3d466b..a666086 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -4702,7 +4702,7 @@ static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
> *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
>
> /* AMD_CG_SUPPORT_GFX_CP_LS */
> - data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
> + data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
We should use kiq instead of mmio access for the whole
gfx_v9_0_get_clockgating_state().
Thanks,
Ray
> if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
> *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
>
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cray.huang%40amd.com%7Cc8b2a8c2091f4336ee5708d79811af07%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637145074034487948&sdata=emUuTvGn3FGbQGrIs%2FkoR3d0YAQYvHUjBqA5cYlkL2g%3D&reserved=0
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32
2020-01-14 4:20 ` Huang Rui
@ 2020-01-13 21:07 ` Christian König
0 siblings, 0 replies; 6+ messages in thread
From: Christian König @ 2020-01-13 21:07 UTC (permalink / raw)
To: Huang Rui, chen gong; +Cc: Alex Deucher, Felix Kuehling, amd-gfx
Am 14.01.20 um 05:20 schrieb Huang Rui:
> On Mon, Jan 13, 2020 at 11:56:46PM +0800, Huang Rui wrote:
>> On Mon, Jan 13, 2020 at 06:16:21PM +0800, chen gong wrote:
>>> Reading some registers by mmio will result in hang when GPU is in
>>> "gfxoff" state.
>>>
>>> This problem can be solved by GPU in "ring command packages" way.
>>>
>>> Signed-off-by: chen gong <curry.gong@amd.com>
>> Acked-by: Huang Rui <ray.huang@amd.com>
>>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
>>> 2 files changed, 4 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> index 63eab0c..92c5ee4 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
>>> @@ -1016,10 +1016,13 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
>>>
>>> #define AMDGPU_REGS_IDX (1<<0)
>>> #define AMDGPU_REGS_NO_KIQ (1<<1)
>>> +#define AMDGPU_REGS_KIQ (1<<2)
>>>
>>> #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
>>> #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
>>>
>>> +#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)
>>> +
>>> #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
>>> #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> index 2c64d2a..4045b56 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
>>> @@ -217,7 +217,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
>>> {
>>> uint32_t ret;
>>>
>>> - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
>>> + if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
>>> return amdgpu_virt_kiq_rreg(adev, reg);
> Hi Curry,
>
> I read this patch again, we would better move the
> amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg out of amdgpu_virt to amdgpu.h.
>
> Because these functions are not only used for virtualization but also for
> the case while gfxoff enabled. We will continue using this interface
> instead of MMIO access in KFD driver as well.
Yes, that is a really good idea.
We should probably start a amdgpu_kiq.c file and move quite a bunch of
stuff over there.
Regards,
Christian.
>
> Thanks,
> Ray
>
>>>
>>> if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
>>> --
>>> 2.7.4
>>>
>>> _______________________________________________
>>> amd-gfx mailing list
>>> amd-gfx@lists.freedesktop.org
>>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cray.huang%40amd.com%7C30ace3a1329f439cb69508d79811d5aa%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637145074676514100&sdata=t6rAUcThU9cmcu5Rwh%2BuHFDtj7Yie4tRN%2FgF2OSBZ00%3D&reserved=0
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32
2020-01-13 15:56 ` [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 Huang Rui
@ 2020-01-14 4:20 ` Huang Rui
2020-01-13 21:07 ` Christian König
0 siblings, 1 reply; 6+ messages in thread
From: Huang Rui @ 2020-01-14 4:20 UTC (permalink / raw)
To: chen gong; +Cc: Alex Deucher, Felix Kuehling, Christian König, amd-gfx
On Mon, Jan 13, 2020 at 11:56:46PM +0800, Huang Rui wrote:
> On Mon, Jan 13, 2020 at 06:16:21PM +0800, chen gong wrote:
> > Reading some registers by mmio will result in hang when GPU is in
> > "gfxoff" state.
> >
> > This problem can be solved by GPU in "ring command packages" way.
> >
> > Signed-off-by: chen gong <curry.gong@amd.com>
>
> Acked-by: Huang Rui <ray.huang@amd.com>
>
> > ---
> > drivers/gpu/drm/amd/amdgpu/amdgpu.h | 3 +++
> > drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 2 +-
> > 2 files changed, 4 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > index 63eab0c..92c5ee4 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> > @@ -1016,10 +1016,13 @@ int emu_soc_asic_init(struct amdgpu_device *adev);
> >
> > #define AMDGPU_REGS_IDX (1<<0)
> > #define AMDGPU_REGS_NO_KIQ (1<<1)
> > +#define AMDGPU_REGS_KIQ (1<<2)
> >
> > #define RREG32_NO_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_NO_KIQ)
> > #define WREG32_NO_KIQ(reg, v) amdgpu_mm_wreg(adev, (reg), (v), AMDGPU_REGS_NO_KIQ)
> >
> > +#define RREG32_KIQ(reg) amdgpu_mm_rreg(adev, (reg), AMDGPU_REGS_KIQ)
> > +
> > #define RREG8(reg) amdgpu_mm_rreg8(adev, (reg))
> > #define WREG8(reg, v) amdgpu_mm_wreg8(adev, (reg), (v))
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > index 2c64d2a..4045b56 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
> > @@ -217,7 +217,7 @@ uint32_t amdgpu_mm_rreg(struct amdgpu_device *adev, uint32_t reg,
> > {
> > uint32_t ret;
> >
> > - if (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev))
> > + if ((acc_flags & AMDGPU_REGS_KIQ) || (!(acc_flags & AMDGPU_REGS_NO_KIQ) && amdgpu_sriov_runtime(adev)))
> > return amdgpu_virt_kiq_rreg(adev, reg);
Hi Curry,
I read this patch again, we would better move the
amdgpu_virt_kiq_rreg/amdgpu_virt_kiq_wreg out of amdgpu_virt to amdgpu.h.
Because these functions are not only used for virtualization but also for
the case while gfxoff enabled. We will continue using this interface
instead of MMIO access in KFD driver as well.
Thanks,
Ray
> >
> > if ((reg * 4) < adev->rmmio_size && !(acc_flags & AMDGPU_REGS_IDX))
> > --
> > 2.7.4
> >
> > _______________________________________________
> > amd-gfx mailing list
> > amd-gfx@lists.freedesktop.org
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&data=02%7C01%7Cray.huang%40amd.com%7C30ace3a1329f439cb69508d79811d5aa%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637145074676514100&sdata=t6rAUcThU9cmcu5Rwh%2BuHFDtj7Yie4tRN%2FgF2OSBZ00%3D&reserved=0
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-01-14 7:57 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-13 10:16 [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 chen gong
2020-01-13 10:16 ` [PATCH 2/2] drm/amdgpu: reading CP_MEM_SLP_CNTL register using RREG32_KIQ macro chen gong
2020-01-13 15:58 ` Huang Rui
2020-01-13 15:56 ` [PATCH 1/2] drm/amdgpu: add kiq version interface for RREG32 Huang Rui
2020-01-14 4:20 ` Huang Rui
2020-01-13 21:07 ` Christian König
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