* [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5
@ 2020-01-21 16:19 James Zhu
2020-01-21 16:19 ` [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance James Zhu
` (3 more replies)
0 siblings, 4 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 16:19 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Share vcn_v2_0_dec_ring_test_ring to vcn2.5 to support
vcn software ring.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 1 +
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
3 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index f4db8af6..e2ad5afe 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -1624,7 +1624,7 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
return 0;
}
-static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
+int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
{
struct amdgpu_device *adev = ring->adev;
uint32_t tmp = 0;
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
index ef749b0..6c9de18 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
@@ -37,6 +37,7 @@ extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
unsigned vmid, uint64_t pd_addr);
extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
uint32_t reg, uint32_t val);
+extern int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring);
extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index c8b63d5..c351d1a 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -1488,7 +1488,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
.emit_ib = vcn_v2_0_dec_ring_emit_ib,
.emit_fence = vcn_v2_0_dec_ring_emit_fence,
.emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
- .test_ring = amdgpu_vcn_dec_ring_test_ring,
+ .test_ring = vcn_v2_0_dec_ring_test_ring,
.test_ib = amdgpu_vcn_dec_ring_test_ib,
.insert_nop = vcn_v2_0_dec_ring_insert_nop,
.insert_start = vcn_v2_0_dec_ring_insert_start,
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance
2020-01-21 16:19 [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 James Zhu
@ 2020-01-21 16:19 ` James Zhu
2020-01-21 17:29 ` Leo Liu
2020-01-21 16:19 ` [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue James Zhu
` (2 subsequent siblings)
3 siblings, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 16:19 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Fix a bug for the 2nd vcn instance at start and stop.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index c351d1a..740a291 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -891,8 +891,10 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
- if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
- return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
+ r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
+ continue;
+ }
/* disable register anti-hang mechanism */
WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
@@ -903,6 +905,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
}
+ if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
+ return 0;
+
/*SW clock gating */
vcn_v2_5_disable_clock_gating(adev);
@@ -1294,10 +1299,9 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
if (adev->vcn.harvest_config & (1 << i))
continue;
-
if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
r = vcn_v2_5_stop_dpg_mode(adev, i);
- goto power_off;
+ continue;
}
/* wait for vcn idle */
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 16:19 [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 James Zhu
2020-01-21 16:19 ` [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance James Zhu
@ 2020-01-21 16:19 ` James Zhu
2020-01-21 17:40 ` Leo Liu
2020-01-21 22:21 ` [PATCH v2 3/5] " James Zhu
2020-01-21 16:19 ` [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
2020-01-21 17:25 ` [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 Leo Liu
3 siblings, 2 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 16:19 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86 ++++++++++++++++----------------
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88 ++++++++++++++++-----------------
3 files changed, 89 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index c4984c5..60fe3c4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -86,12 +86,12 @@
(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
} while (0)
-#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \
+#define SOC15_DPG_MODE_OFFSET_2_0(ip, reg) \
({ \
uint32_t internal_reg_offset, addr; \
bool video_range, aon_range; \
\
- addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+ addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg); \
addr <<= 2; \
video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
index e2ad5afe..ad11c8e 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
@@ -352,88 +352,88 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
} else {
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
}
offset = 0;
} else {
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
offset = size;
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
+ UVD, mmUVD_VCPU_CACHE_OFFSET0),
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
}
if (!indirect)
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
else
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
/* cache window 1: stack */
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
} else {
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
}
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
/* cache window 2: context */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
/* non-cache window */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
/* VCN global tiling registers */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
+ UVD, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
}
/**
@@ -579,19 +579,19 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
UVD_CGC_CTRL__VCPU_MODE_MASK |
UVD_CGC_CTRL__SCPU_MODE_MASK);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
+ UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
/* turn off clock gating */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
+ UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
/* turn on SUVD clock gating */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
+ UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
/* turn on sw mode in UVD_SUVD_CGC_CTRL */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
+ UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
}
/**
@@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
+ UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
/* disable master interupt */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
+ UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
/* setup mmUVD_LMI_CTRL */
tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
@@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
0x00100000L);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
+ UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_MPC_CNTL),
+ UVD, mmUVD_MPC_CNTL),
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_MPC_SET_MUXA0),
+ UVD, mmUVD_MPC_SET_MUXA0),
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_MPC_SET_MUXB0),
+ UVD, mmUVD_MPC_SET_MUXB0),
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_MPC_SET_MUX),
+ UVD, mmUVD_MPC_SET_MUX),
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
@@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
+ UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
+ UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
/* release VCPU reset to boot */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
+ UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
/* enable LMI MC and UMC channels */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_LMI_CTRL2),
+ UVD, mmUVD_LMI_CTRL2),
0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
/* enable master interrupt */
WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, 0, mmUVD_MASTINT_EN),
+ UVD, mmUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 740a291..42ca36c 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -435,88 +435,88 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
} else {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
}
offset = 0;
} else {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
offset = size;
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
+ UVD, mmUVD_VCPU_CACHE_OFFSET0),
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
}
if (!indirect)
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
else
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
/* cache window 1: stack */
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
} else {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
}
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
/* cache window 2: context */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+ UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+ UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
+ UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
/* non-cache window */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+ UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
/* VCN global tiling registers */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
+ UVD, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
}
/**
@@ -670,19 +670,19 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
UVD_CGC_CTRL__VCPU_MODE_MASK |
UVD_CGC_CTRL__MMSCH_MODE_MASK);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
+ UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
/* turn off clock gating */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
+ UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
/* turn on SUVD clock gating */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
+ UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
/* turn on sw mode in UVD_SUVD_CGC_CTRL */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
+ UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
}
/**
@@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
+ UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
/* disable master interupt */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
+ UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
/* setup mmUVD_LMI_CTRL */
tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
@@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
0x00100000L);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
+ UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_CNTL),
+ UVD, mmUVD_MPC_CNTL),
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
+ UVD, mmUVD_MPC_SET_MUXA0),
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
+ UVD, mmUVD_MPC_SET_MUXB0),
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_SET_MUX),
+ UVD, mmUVD_MPC_SET_MUX),
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
@@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
+ UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
+ UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
/* enable LMI MC and UMC channels */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
+ UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
/* unblock VCPU register access */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
+ UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
+ UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
/* enable master interrupt */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MASTINT_EN),
+ UVD, mmUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 16:19 [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 James Zhu
2020-01-21 16:19 ` [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance James Zhu
2020-01-21 16:19 ` [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue James Zhu
@ 2020-01-21 16:19 ` James Zhu
2020-01-21 17:43 ` Leo Liu
2020-01-21 21:39 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error James Zhu
2020-01-21 17:25 ` [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 Leo Liu
3 siblings, 2 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 16:19 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Use inst_idx relacing inst in SOC15_DPG_MODE macro
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 +++++++++++-----------
1 file changed, 11 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 60fe3c4..98c1893 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -65,23 +65,23 @@
/* 1 second timeout */
#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
-#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
- ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
+#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask, sram_sel) \
+ ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
UVD_DPG_LMA_CTL__MASK_EN_MASK | \
- ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
+ ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
- RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
+ RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
})
-#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
+#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask, sram_sel) \
do { \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
- ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
+ ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
} while (0)
@@ -111,7 +111,7 @@
#define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en) \
({ \
- WREG32_SOC15(VCN, inst, mmUVD_DPG_LMA_CTL, \
+ WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5
2020-01-21 16:19 [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 James Zhu
` (2 preceding siblings ...)
2020-01-21 16:19 ` [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
@ 2020-01-21 17:25 ` Leo Liu
3 siblings, 0 replies; 25+ messages in thread
From: Leo Liu @ 2020-01-21 17:25 UTC (permalink / raw)
To: James Zhu, amd-gfx; +Cc: jamesz
This patch is
Reviewed-by: Leo Liu <leo.liu@amd.com>
On 2020-01-21 11:19 a.m., James Zhu wrote:
> Share vcn_v2_0_dec_ring_test_ring to vcn2.5 to support
> vcn software ring.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h | 1 +
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 2 +-
> 3 files changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index f4db8af6..e2ad5afe 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -1624,7 +1624,7 @@ static int vcn_v2_0_process_interrupt(struct amdgpu_device *adev,
> return 0;
> }
>
> -static int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
> +int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring)
> {
> struct amdgpu_device *adev = ring->adev;
> uint32_t tmp = 0;
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
> index ef749b0..6c9de18 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.h
> @@ -37,6 +37,7 @@ extern void vcn_v2_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
> unsigned vmid, uint64_t pd_addr);
> extern void vcn_v2_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
> uint32_t reg, uint32_t val);
> +extern int vcn_v2_0_dec_ring_test_ring(struct amdgpu_ring *ring);
>
> extern void vcn_v2_0_enc_ring_insert_end(struct amdgpu_ring *ring);
> extern void vcn_v2_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index c8b63d5..c351d1a 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -1488,7 +1488,7 @@ static const struct amdgpu_ring_funcs vcn_v2_5_dec_ring_vm_funcs = {
> .emit_ib = vcn_v2_0_dec_ring_emit_ib,
> .emit_fence = vcn_v2_0_dec_ring_emit_fence,
> .emit_vm_flush = vcn_v2_0_dec_ring_emit_vm_flush,
> - .test_ring = amdgpu_vcn_dec_ring_test_ring,
> + .test_ring = vcn_v2_0_dec_ring_test_ring,
> .test_ib = amdgpu_vcn_dec_ring_test_ib,
> .insert_nop = vcn_v2_0_dec_ring_insert_nop,
> .insert_start = vcn_v2_0_dec_ring_insert_start,
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance
2020-01-21 16:19 ` [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance James Zhu
@ 2020-01-21 17:29 ` Leo Liu
2020-01-21 17:47 ` James Zhu
0 siblings, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 17:29 UTC (permalink / raw)
To: James Zhu, amd-gfx; +Cc: jamesz
On 2020-01-21 11:19 a.m., James Zhu wrote:
> Fix a bug for the 2nd vcn instance at start and stop.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++----
> 1 file changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index c351d1a..740a291 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -891,8 +891,10 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> - return vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> + r = vcn_v2_5_start_dpg_mode(adev, i, adev->vcn.indirect_sram);
> + continue;
> + }
>
"r" is not being considered, and after the loop, it will be going to the
code below, is it correct?
> /* disable register anti-hang mechanism */
> WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
> @@ -903,6 +905,9 @@ static int vcn_v2_5_start(struct amdgpu_device *adev)
> WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
> }
>
> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
> + return 0;
> +
> /*SW clock gating */
> vcn_v2_5_disable_clock_gating(adev);
>
> @@ -1294,10 +1299,9 @@ static int vcn_v2_5_stop(struct amdgpu_device *adev)
> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
> if (adev->vcn.harvest_config & (1 << i))
> continue;
> -
> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
> r = vcn_v2_5_stop_dpg_mode(adev, i);
> - goto power_off;
> + continue;
> }
same problem as above, don't go through the code that isn't necessary.
Regards,
Leo
>
> /* wait for vcn idle */
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* Re: [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 16:19 ` [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue James Zhu
@ 2020-01-21 17:40 ` Leo Liu
2020-01-21 17:48 ` James Zhu
2020-01-21 22:21 ` [PATCH v2 3/5] " James Zhu
1 sibling, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 17:40 UTC (permalink / raw)
To: James Zhu, amd-gfx; +Cc: jamesz
On 2020-01-21 11:19 a.m., James Zhu wrote:
> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86 ++++++++++++++++----------------
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88 ++++++++++++++++-----------------
> 3 files changed, 89 insertions(+), 89 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index c4984c5..60fe3c4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -86,12 +86,12 @@
> (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
> } while (0)
>
> -#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst, reg) \
> +#define SOC15_DPG_MODE_OFFSET_2_0(ip, reg) \
> ({ \
> uint32_t internal_reg_offset, addr; \
> bool video_range, aon_range; \
> \
> - addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
This is based the soc15_common.h
#define SOC15_REG_OFFSET(ip, inst, reg)
(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
You are saying that is not right offset for 2nd instance?
Leo
> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg); \
> addr <<= 2; \
> video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> index e2ad5afe..ad11c8e 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
> @@ -352,88 +352,88 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> } else {
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> }
> offset = 0;
> } else {
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
> offset = size;
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
> }
>
> if (!indirect)
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
> else
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>
> /* cache window 1: stack */
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> } else {
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> }
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
>
> /* cache window 2: context */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>
> /* non-cache window */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>
> /* VCN global tiling registers */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> + UVD, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> }
>
> /**
> @@ -579,19 +579,19 @@ static void vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
> UVD_CGC_CTRL__VCPU_MODE_MASK |
> UVD_CGC_CTRL__SCPU_MODE_MASK);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>
> /* turn off clock gating */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>
> /* turn on SUVD clock gating */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>
> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
> }
>
> /**
> @@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>
> /* disable master interupt */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>
> /* setup mmUVD_LMI_CTRL */
> tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
> @@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
> 0x00100000L);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_MPC_CNTL),
> + UVD, mmUVD_MPC_CNTL),
> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_MPC_SET_MUXA0),
> + UVD, mmUVD_MPC_SET_MUXA0),
> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_MPC_SET_MUXB0),
> + UVD, mmUVD_MPC_SET_MUXB0),
> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_MPC_SET_MUX),
> + UVD, mmUVD_MPC_SET_MUX),
> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
> @@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct amdgpu_device *adev, bool indirect)
> vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>
> /* release VCPU reset to boot */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
> + UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
>
> /* enable LMI MC and UMC channels */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_LMI_CTRL2),
> + UVD, mmUVD_LMI_CTRL2),
> 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0, indirect);
>
> /* enable master interrupt */
> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, 0, mmUVD_MASTINT_EN),
> + UVD, mmUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> if (indirect)
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 740a291..42ca36c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -435,88 +435,88 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> } else {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> }
> offset = 0;
> } else {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
> offset = size;
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
> }
>
> if (!indirect)
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
> else
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>
> /* cache window 1: stack */
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> } else {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> }
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
>
> /* cache window 2: context */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>
> /* non-cache window */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>
> /* VCN global tiling registers */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> + UVD, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> }
>
> /**
> @@ -670,19 +670,19 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
> UVD_CGC_CTRL__VCPU_MODE_MASK |
> UVD_CGC_CTRL__MMSCH_MODE_MASK);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>
> /* turn off clock gating */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>
> /* turn on SUVD clock gating */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>
> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
> }
>
> /**
> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>
> /* disable master interupt */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>
> /* setup mmUVD_LMI_CTRL */
> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
> 0x00100000L);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_CNTL),
> + UVD, mmUVD_MPC_CNTL),
> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
> + UVD, mmUVD_MPC_SET_MUXA0),
> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
> + UVD, mmUVD_MPC_SET_MUXB0),
> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
> + UVD, mmUVD_MPC_SET_MUX),
> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>
> /* enable LMI MC and UMC channels */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
> + UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
>
> /* unblock VCPU register access */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
> + UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>
> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>
> /* enable master interrupt */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MASTINT_EN),
> + UVD, mmUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> if (indirect)
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 16:19 ` [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
@ 2020-01-21 17:43 ` Leo Liu
2020-01-21 17:50 ` James Zhu
2020-01-21 21:39 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error James Zhu
1 sibling, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 17:43 UTC (permalink / raw)
To: James Zhu, amd-gfx; +Cc: jamesz
On 2020-01-21 11:19 a.m., James Zhu wrote:
> Use inst_idx relacing inst in SOC15_DPG_MODE macro
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 +++++++++++-----------
> 1 file changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 60fe3c4..98c1893 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -65,23 +65,23 @@
> /* 1 second timeout */
> #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
>
> -#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
> - ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
> +#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask, sram_sel) \
> + ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
I have only seen you are using inst_idx to replace inst, havn't you?
this is not necessary, because we are using inst as the idx.
Leo
> UVD_DPG_LMA_CTL__MASK_EN_MASK | \
> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
> (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
> - RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
> + RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
> })
>
> -#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
> +#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask, sram_sel) \
> do { \
> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
> UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
> (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
> } while (0)
> @@ -111,7 +111,7 @@
>
> #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en) \
> ({ \
> - WREG32_SOC15(VCN, inst, mmUVD_DPG_LMA_CTL, \
> + WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
> (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
> mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
> offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance
2020-01-21 17:29 ` Leo Liu
@ 2020-01-21 17:47 ` James Zhu
2020-01-21 20:20 ` Leo Liu
0 siblings, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 17:47 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
On 2020-01-21 12:29 p.m., Leo Liu wrote:
>
> On 2020-01-21 11:19 a.m., James Zhu wrote:
>> Fix a bug for the 2nd vcn instance at start and stop.
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++----
>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index c351d1a..740a291 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -891,8 +891,10 @@ static int vcn_v2_5_start(struct amdgpu_device
>> *adev)
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.harvest_config & (1 << i))
>> continue;
>> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
>> - return vcn_v2_5_start_dpg_mode(adev, i,
>> adev->vcn.indirect_sram);
>> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>> + r = vcn_v2_5_start_dpg_mode(adev, i,
>> adev->vcn.indirect_sram);
>> + continue;
>> + }
>
> "r" is not being considered, and after the loop, it will be going to
> the code below, is it correct?
Since DPG mode start/stop always return 0. I have added code to return 0
below under DPG mode
>
>
>> /* disable register anti-hang mechanism */
>> WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
>> @@ -903,6 +905,9 @@ static int vcn_v2_5_start(struct amdgpu_device
>> *adev)
>> WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
>> }
>> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
>> + return 0;
>> +
>> /*SW clock gating */
>> vcn_v2_5_disable_clock_gating(adev);
>> @@ -1294,10 +1299,9 @@ static int vcn_v2_5_stop(struct
>> amdgpu_device *adev)
>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>> if (adev->vcn.harvest_config & (1 << i))
>> continue;
>> -
>> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>> r = vcn_v2_5_stop_dpg_mode(adev, i);
>> - goto power_off;
>> + continue;
>> }
>
> same problem as above, don't go through the code that isn't necessary.
should be fine under DPG mode.
JAmes
>
> Regards,
>
> Leo
>
>
>> /* wait for vcn idle */
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 17:40 ` Leo Liu
@ 2020-01-21 17:48 ` James Zhu
2020-01-21 20:23 ` Leo Liu
0 siblings, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 17:48 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
On 2020-01-21 12:40 p.m., Leo Liu wrote:
>
> On 2020-01-21 11:19 a.m., James Zhu wrote:
>> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86
>> ++++++++++++++++----------------
>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88
>> ++++++++++++++++-----------------
>> 3 files changed, 89 insertions(+), 89 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index c4984c5..60fe3c4 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -86,12 +86,12 @@
>> (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>> } while (0)
>> -#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst,
>> reg) \
>> +#define SOC15_DPG_MODE_OFFSET_2_0(ip,
>> reg) \
>> ({ \
>> uint32_t internal_reg_offset, addr; \
>> bool video_range, aon_range; \
>> \
>> - addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
>> reg); \
>
> This is based the soc15_common.h
>
> #define SOC15_REG_OFFSET(ip, inst, reg)
> (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>
> You are saying that is not right offset for 2nd instance?
Yes, DPG mode is executed by individual instance, so the register
offset is the same.
James
>
>
> Leo
>
>
>> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] +
>> reg); \
>> addr <<= 2; \
>> video_range = ((((0xFFFFF & addr) >=
>> (VCN_VID_SOC_ADDRESS_2_0)) && \
>> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 +
>> 0x2600))))); \
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> index e2ad5afe..ad11c8e 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>> @@ -352,88 +352,88 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
>> amdgpu_device *adev, bool indirec
>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>> if (!indirect) {
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>> } else {
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>> indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>> }
>> offset = 0;
>> } else {
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>> offset = size;
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>> }
>> if (!indirect)
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>> else
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>> /* cache window 1: stack */
>> if (!indirect) {
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>> lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>> upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> } else {
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>> indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> }
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>> indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>> indirect);
>> /* cache window 2: context */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> lower_32_bits(adev->vcn.inst->gpu_addr + offset +
>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> upper_32_bits(adev->vcn.inst->gpu_addr + offset +
>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>> indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>> indirect);
>> /* non-cache window */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>> /* VCN global tiling registers */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG),
>> adev->gfx.config.gb_addr_config, 0, indirect);
>> + UVD, mmUVD_GFX10_ADDR_CONFIG),
>> adev->gfx.config.gb_addr_config, 0, indirect);
>> }
>> /**
>> @@ -579,19 +579,19 @@ static void
>> vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>> UVD_CGC_CTRL__SCPU_MODE_MASK);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>> /* turn off clock gating */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>> /* turn on SUVD clock gating */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>> }
>> /**
>> @@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct
>> amdgpu_device *adev, bool indirect)
>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>> tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>> /* disable master interupt */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>> /* setup mmUVD_LMI_CTRL */
>> tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>> @@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct
>> amdgpu_device *adev, bool indirect)
>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>> 0x00100000L);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_MPC_CNTL),
>> + UVD, mmUVD_MPC_CNTL),
>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_MPC_SET_MUXA0),
>> + UVD, mmUVD_MPC_SET_MUXA0),
>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_MPC_SET_MUXB0),
>> + UVD, mmUVD_MPC_SET_MUXB0),
>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_MPC_SET_MUX),
>> + UVD, mmUVD_MPC_SET_MUX),
>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>> @@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct
>> amdgpu_device *adev, bool indirect)
>> vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>> /* release VCPU reset to boot */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
>> + UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
>> /* enable LMI MC and UMC channels */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_LMI_CTRL2),
>> + UVD, mmUVD_LMI_CTRL2),
>> 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0,
>> indirect);
>> /* enable master interrupt */
>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, 0, mmUVD_MASTINT_EN),
>> + UVD, mmUVD_MASTINT_EN),
>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>> if (indirect)
>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> index 740a291..42ca36c 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>> @@ -435,88 +435,88 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct
>> amdgpu_device *adev, int inst_idx
>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>> if (!indirect) {
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>> SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>> inst_idx].tmr_mc_addr_lo), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>> SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>> inst_idx].tmr_mc_addr_hi), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>> SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>> indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>> } else {
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>> SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> 0, 0, indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>> SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> 0, 0, indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>> SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>> indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>> }
>> offset = 0;
>> } else {
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>> offset = size;
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>> }
>> if (!indirect)
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>> else
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>> /* cache window 1: stack */
>> if (!indirect) {
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr +
>> offset), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr +
>> offset), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> } else {
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0,
>> 0, indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0,
>> 0, indirect);
>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>> }
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1),
>> AMDGPU_VCN_STACK_SIZE, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>> indirect);
>> /* cache window 2: context */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2),
>> AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>> indirect);
>> /* non-cache window */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0,
>> indirect);
>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0,
>> indirect);
>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>> /* VCN global tiling registers */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG),
>> adev->gfx.config.gb_addr_config, 0, indirect);
>> + UVD, mmUVD_GFX8_ADDR_CONFIG),
>> adev->gfx.config.gb_addr_config, 0, indirect);
>> }
>> /**
>> @@ -670,19 +670,19 @@ static void
>> vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>> UVD_CGC_CTRL__MMSCH_MODE_MASK);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>> /* turn off clock gating */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>> /* turn on SUVD clock gating */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>> }
>> /**
>> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct
>> amdgpu_device *adev, int inst_idx, boo
>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>> /* disable master interupt */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>> /* setup mmUVD_LMI_CTRL */
>> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct
>> amdgpu_device *adev, int inst_idx, boo
>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>> 0x00100000L);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_MPC_CNTL),
>> + UVD, mmUVD_MPC_CNTL),
>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
>> + UVD, mmUVD_MPC_SET_MUXA0),
>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
>> + UVD, mmUVD_MPC_SET_MUXB0),
>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
>> + UVD, mmUVD_MPC_SET_MUX),
>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct
>> amdgpu_device *adev, int inst_idx, boo
>> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>> /* enable LMI MC and UMC channels */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
>> + UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
>> /* unblock VCPU register access */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>> + UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>> /* enable master interrupt */
>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>> - UVD, inst_idx, mmUVD_MASTINT_EN),
>> + UVD, mmUVD_MASTINT_EN),
>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>> if (indirect)
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* Re: [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 17:43 ` Leo Liu
@ 2020-01-21 17:50 ` James Zhu
2020-01-21 20:30 ` Leo Liu
0 siblings, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 17:50 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
On 2020-01-21 12:43 p.m., Leo Liu wrote:
>
> On 2020-01-21 11:19 a.m., James Zhu wrote:
>> Use inst_idx relacing inst in SOC15_DPG_MODE macro
>>
>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 +++++++++++-----------
>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> index 60fe3c4..98c1893 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>> @@ -65,23 +65,23 @@
>> /* 1 second timeout */
>> #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
>> -#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask,
>> sram_sel) \
>> - ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>> mask); \
>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>> +#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask,
>> sram_sel) \
>> + ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>> mask); \
>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
>
> I have only seen you are using inst_idx to replace inst, havn't you?
> this is not necessary, because we are using inst as the idx.
Since we use inst for instance in struct amdgpu_vcn. To avoid confusing,
I create this patch,
James
>
> Leo
>
>
>
>> UVD_DPG_LMA_CTL__MASK_EN_MASK | \
>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>> | \
>> (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>> - RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
>> + RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
>> })
>> -#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask,
>> sram_sel) \
>> +#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask,
>> sram_sel) \
>> do { \
>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA,
>> value); \
>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA,
>> value); \
>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>> mask); \
>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
>> UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>> | \
>> (sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>> } while (0)
>> @@ -111,7 +111,7 @@
>> #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset,
>> mask_en) \
>> ({ \
>> - WREG32_SOC15(VCN, inst,
>> mmUVD_DPG_LMA_CTL, \
>> + WREG32_SOC15(VCN, inst_idx,
>> mmUVD_DPG_LMA_CTL, \
>> (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT
>> | \
>> mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT
>> | \
>> offset <<
>> UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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* Re: [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance
2020-01-21 17:47 ` James Zhu
@ 2020-01-21 20:20 ` Leo Liu
2020-01-21 20:49 ` James Zhu
0 siblings, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 20:20 UTC (permalink / raw)
To: James Zhu, James Zhu, amd-gfx
On 2020-01-21 12:47 p.m., James Zhu wrote:
>
> On 2020-01-21 12:29 p.m., Leo Liu wrote:
>>
>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>> Fix a bug for the 2nd vcn instance at start and stop.
>>>
>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++----
>>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> index c351d1a..740a291 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> @@ -891,8 +891,10 @@ static int vcn_v2_5_start(struct amdgpu_device
>>> *adev)
>>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>> if (adev->vcn.harvest_config & (1 << i))
>>> continue;
>>> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
>>> - return vcn_v2_5_start_dpg_mode(adev, i,
>>> adev->vcn.indirect_sram);
>>> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>>> + r = vcn_v2_5_start_dpg_mode(adev, i,
>>> adev->vcn.indirect_sram);
>>> + continue;
>>> + }
>>
>> "r" is not being considered, and after the loop, it will be going to
>> the code below, is it correct?
> Since DPG mode start/stop always return 0. I have added code to return
> 0 below under DPG mode
Then you should move the "return 0" here instead of adding two more
unnecessary lines.
>>
>>
>>> /* disable register anti-hang mechanism */
>>> WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
>>> @@ -903,6 +905,9 @@ static int vcn_v2_5_start(struct amdgpu_device
>>> *adev)
>>> WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
>>> }
>>> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
>>> + return 0;
>>> +
>>> /*SW clock gating */
>>> vcn_v2_5_disable_clock_gating(adev);
>>> @@ -1294,10 +1299,9 @@ static int vcn_v2_5_stop(struct
>>> amdgpu_device *adev)
>>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>> if (adev->vcn.harvest_config & (1 << i))
>>> continue;
>>> -
>>> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>>> r = vcn_v2_5_stop_dpg_mode(adev, i);
>>> - goto power_off;
>>> + continue;
>>> }
>>
>> same problem as above, don't go through the code that isn't necessary.
>
> should be fine under DPG mode.
It's about clean implementation. if not necessary, why do we need to add
them.
Leo
>
> JAmes
>
>>
>> Regards,
>>
>> Leo
>>
>>
>>> /* wait for vcn idle */
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* Re: [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 17:48 ` James Zhu
@ 2020-01-21 20:23 ` Leo Liu
2020-01-21 20:55 ` James Zhu
0 siblings, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 20:23 UTC (permalink / raw)
To: James Zhu, James Zhu, amd-gfx
On 2020-01-21 12:48 p.m., James Zhu wrote:
>
> On 2020-01-21 12:40 p.m., Leo Liu wrote:
>>
>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>>>
>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86
>>> ++++++++++++++++----------------
>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88
>>> ++++++++++++++++-----------------
>>> 3 files changed, 89 insertions(+), 89 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> index c4984c5..60fe3c4 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> @@ -86,12 +86,12 @@
>>> (sram_sel <<
>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>> } while (0)
>>> -#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst,
>>> reg) \
>>> +#define SOC15_DPG_MODE_OFFSET_2_0(ip,
>>> reg) \
>>> ({ \
>>> uint32_t internal_reg_offset, addr; \
>>> bool video_range, aon_range; \
>>> \
>>> - addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] +
>>> reg); \
>>
>> This is based the soc15_common.h
>>
>> #define SOC15_REG_OFFSET(ip, inst, reg)
>> (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>>
>> You are saying that is not right offset for 2nd instance?
>
> Yes, DPG mode is executed by individual instance, so the register
> offset is the same.
Then you should use inst idx as 0 for the 2nd instance as well, instead
of changing the Macro.
Leo
>
> James
>
>>
>>
>> Leo
>>
>>
>>> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] +
>>> reg); \
>>> addr <<= 2; \
>>> video_range = ((((0xFFFFF & addr) >=
>>> (VCN_VID_SOC_ADDRESS_2_0)) && \
>>> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 +
>>> 0x2600))))); \
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>> index e2ad5afe..ad11c8e 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>> @@ -352,88 +352,88 @@ static void vcn_v2_0_mc_resume_dpg_mode(struct
>>> amdgpu_device *adev, bool indirec
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>> if (!indirect) {
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>> } else {
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>> }
>>> offset = 0;
>>> } else {
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>> offset = size;
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>> }
>>> if (!indirect)
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>> else
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>> /* cache window 1: stack */
>>> if (!indirect) {
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> } else {
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> }
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>> indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>> indirect);
>>> /* cache window 2: context */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset +
>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset +
>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE,
>>> 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>>> indirect);
>>> /* non-cache window */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>> /* VCN global tiling registers */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG),
>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>> + UVD, mmUVD_GFX10_ADDR_CONFIG),
>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>> }
>>> /**
>>> @@ -579,19 +579,19 @@ static void
>>> vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>> UVD_CGC_CTRL__SCPU_MODE_MASK);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>> /* turn off clock gating */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>> /* turn on SUVD clock gating */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>> }
>>> /**
>>> @@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct
>>> amdgpu_device *adev, bool indirect)
>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>> tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>> /* disable master interupt */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>> /* setup mmUVD_LMI_CTRL */
>>> tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>> @@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct
>>> amdgpu_device *adev, bool indirect)
>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>> 0x00100000L);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_MPC_CNTL),
>>> + UVD, mmUVD_MPC_CNTL),
>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_MPC_SET_MUXA0),
>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_MPC_SET_MUXB0),
>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_MPC_SET_MUX),
>>> + UVD, mmUVD_MPC_SET_MUX),
>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>> @@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct
>>> amdgpu_device *adev, bool indirect)
>>> vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>> /* release VCPU reset to boot */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
>>> + UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
>>> /* enable LMI MC and UMC channels */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_LMI_CTRL2),
>>> + UVD, mmUVD_LMI_CTRL2),
>>> 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0,
>>> indirect);
>>> /* enable master interrupt */
>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, 0, mmUVD_MASTINT_EN),
>>> + UVD, mmUVD_MASTINT_EN),
>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>> if (indirect)
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> index 740a291..42ca36c 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>> @@ -435,88 +435,88 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct
>>> amdgpu_device *adev, int inst_idx
>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>> if (!indirect) {
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>> inst_idx].tmr_mc_addr_lo), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>> inst_idx].tmr_mc_addr_hi), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>> } else {
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> 0, 0, indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx,
>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>> }
>>> offset = 0;
>>> } else {
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>> offset = size;
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>> }
>>> if (!indirect)
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0,
>>> indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>> else
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>> /* cache window 1: stack */
>>> if (!indirect) {
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> } else {
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0,
>>> 0, indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>> 0, 0, indirect);
>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>> SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>> }
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1),
>>> AMDGPU_VCN_STACK_SIZE, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>> indirect);
>>> /* cache window 2: context */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2),
>>> AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>>> indirect);
>>> /* non-cache window */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0,
>>> indirect);
>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>> /* VCN global tiling registers */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG),
>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>> + UVD, mmUVD_GFX8_ADDR_CONFIG),
>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>> }
>>> /**
>>> @@ -670,19 +670,19 @@ static void
>>> vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>> UVD_CGC_CTRL__MMSCH_MODE_MASK);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>> /* turn off clock gating */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>> /* turn on SUVD clock gating */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>> }
>>> /**
>>> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct
>>> amdgpu_device *adev, int inst_idx, boo
>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>> /* disable master interupt */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>> /* setup mmUVD_LMI_CTRL */
>>> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct
>>> amdgpu_device *adev, int inst_idx, boo
>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>> 0x00100000L);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_MPC_CNTL),
>>> + UVD, mmUVD_MPC_CNTL),
>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
>>> + UVD, mmUVD_MPC_SET_MUX),
>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct
>>> amdgpu_device *adev, int inst_idx, boo
>>> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>> /* enable LMI MC and UMC channels */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>> + UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>> /* unblock VCPU register access */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>> + UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>> /* enable master interrupt */
>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>> - UVD, inst_idx, mmUVD_MASTINT_EN),
>>> + UVD, mmUVD_MASTINT_EN),
>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>> if (indirect)
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 17:50 ` James Zhu
@ 2020-01-21 20:30 ` Leo Liu
2020-01-21 20:58 ` James Zhu
0 siblings, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 20:30 UTC (permalink / raw)
To: James Zhu, James Zhu, amd-gfx
On 2020-01-21 12:50 p.m., James Zhu wrote:
>
> On 2020-01-21 12:43 p.m., Leo Liu wrote:
>>
>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>> Use inst_idx relacing inst in SOC15_DPG_MODE macro
>>>
>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>> ---
>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 +++++++++++-----------
>>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> index 60fe3c4..98c1893 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>> @@ -65,23 +65,23 @@
>>> /* 1 second timeout */
>>> #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
>>> -#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask,
>>> sram_sel) \
>>> - ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>>> mask); \
>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>>> +#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask,
>>> sram_sel) \
>>> + ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>>> mask); \
>>> + WREG32_SOC15(ip, inst_idx,
>>> mmUVD_DPG_LMA_CTL, \
>>
>> I have only seen you are using inst_idx to replace inst, havn't you?
>> this is not necessary, because we are using inst as the idx.
>
> Since we use inst for instance in struct amdgpu_vcn. To avoid
> confusing, I create this patch,
If only variable name changes, please drop these patch, we are using
inst all the places.
Leo
>
> James
>
>>
>> Leo
>>
>>
>>
>>> UVD_DPG_LMA_CTL__MASK_EN_MASK | \
>>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
>>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>>> | \
>>> (sram_sel <<
>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>> - RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
>>> + RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
>>> })
>>> -#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask,
>>> sram_sel) \
>>> +#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask,
>>> sram_sel) \
>>> do { \
>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA,
>>> value); \
>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>>> mask); \
>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA,
>>> value); \
>>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>>> mask); \
>>> + WREG32_SOC15(ip, inst_idx,
>>> mmUVD_DPG_LMA_CTL, \
>>> UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
>>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
>>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>>> | \
>>> (sram_sel <<
>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>> } while (0)
>>> @@ -111,7 +111,7 @@
>>> #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset,
>>> mask_en) \
>>> ({ \
>>> - WREG32_SOC15(VCN, inst,
>>> mmUVD_DPG_LMA_CTL, \
>>> + WREG32_SOC15(VCN, inst_idx,
>>> mmUVD_DPG_LMA_CTL, \
>>> (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT
>>> | \
>>> mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT
>>> | \
>>> offset <<
>>> UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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* Re: [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance
2020-01-21 20:20 ` Leo Liu
@ 2020-01-21 20:49 ` James Zhu
0 siblings, 0 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 20:49 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
It is not for DPG mode, but for SPG mode.
Just want to reuse the SPG mode instance harvest check here.
James
On 2020-01-21 3:20 p.m., Leo Liu wrote:
>
> On 2020-01-21 12:47 p.m., James Zhu wrote:
>>
>> On 2020-01-21 12:29 p.m., Leo Liu wrote:
>>>
>>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>>> Fix a bug for the 2nd vcn instance at start and stop.
>>>>
>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 12 ++++++++----
>>>> 1 file changed, 8 insertions(+), 4 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> index c351d1a..740a291 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> @@ -891,8 +891,10 @@ static int vcn_v2_5_start(struct amdgpu_device
>>>> *adev)
>>>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>>> if (adev->vcn.harvest_config & (1 << i))
>>>> continue;
>>>> - if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
>>>> - return vcn_v2_5_start_dpg_mode(adev, i,
>>>> adev->vcn.indirect_sram);
>>>> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>>>> + r = vcn_v2_5_start_dpg_mode(adev, i,
>>>> adev->vcn.indirect_sram);
>>>> + continue;
>>>> + }
>>>
>>> "r" is not being considered, and after the loop, it will be going to
>>> the code below, is it correct?
>> Since DPG mode start/stop always return 0. I have added code to
>> return 0 below under DPG mode
>
> Then you should move the "return 0" here instead of adding two more
> unnecessary lines.
>
>
>>>
>>>
>>>> /* disable register anti-hang mechanism */
>>>> WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_POWER_STATUS), 0,
>>>> @@ -903,6 +905,9 @@ static int vcn_v2_5_start(struct amdgpu_device
>>>> *adev)
>>>> WREG32_SOC15(UVD, i, mmUVD_STATUS, tmp);
>>>> }
>>>> + if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
>>>> + return 0;
>>>> +
>>>> /*SW clock gating */
>>>> vcn_v2_5_disable_clock_gating(adev);
>>>> @@ -1294,10 +1299,9 @@ static int vcn_v2_5_stop(struct
>>>> amdgpu_device *adev)
>>>> for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
>>>> if (adev->vcn.harvest_config & (1 << i))
>>>> continue;
>>>> -
>>>> if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
>>>> r = vcn_v2_5_stop_dpg_mode(adev, i);
>>>> - goto power_off;
>>>> + continue;
>>>> }
>>>
>>> same problem as above, don't go through the code that isn't necessary.
>>
>> should be fine under DPG mode.
>
> It's about clean implementation. if not necessary, why do we need to
> add them.
>
> Leo
>
>
>
>>
>> JAmes
>>
>>>
>>> Regards,
>>>
>>> Leo
>>>
>>>
>>>> /* wait for vcn idle */
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* Re: [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 20:23 ` Leo Liu
@ 2020-01-21 20:55 ` James Zhu
2020-01-21 21:06 ` Leo Liu
0 siblings, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 20:55 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
Since SOC15_DPG_MODE_OFFSET is always the same for all instances, we
should not put [inst]
in the argument list. I will easily make bug in the future.
James
On 2020-01-21 3:23 p.m., Leo Liu wrote:
>
> On 2020-01-21 12:48 p.m., James Zhu wrote:
>>
>> On 2020-01-21 12:40 p.m., Leo Liu wrote:
>>>
>>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>>> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>>>>
>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86
>>>> ++++++++++++++++----------------
>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88
>>>> ++++++++++++++++-----------------
>>>> 3 files changed, 89 insertions(+), 89 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> index c4984c5..60fe3c4 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> @@ -86,12 +86,12 @@
>>>> (sram_sel <<
>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>> } while (0)
>>>> -#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst,
>>>> reg) \
>>>> +#define SOC15_DPG_MODE_OFFSET_2_0(ip,
>>>> reg) \
>>>> ({ \
>>>> uint32_t internal_reg_offset, addr; \
>>>> bool video_range, aon_range; \
>>>> \
>>>> - addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
>>>> + reg); \
>>>
>>> This is based the soc15_common.h
>>>
>>> #define SOC15_REG_OFFSET(ip, inst, reg)
>>> (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>>>
>>> You are saying that is not right offset for 2nd instance?
>>
>> Yes, DPG mode is executed by individual instance, so the register
>> offset is the same.
>
> Then you should use inst idx as 0 for the 2nd instance as well,
> instead of changing the Macro.
>
> Leo
>
>
>
>>
>> James
>>
>>>
>>>
>>> Leo
>>>
>>>
>>>> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] +
>>>> reg); \
>>>> addr <<= 2; \
>>>> video_range = ((((0xFFFFF & addr) >=
>>>> (VCN_VID_SOC_ADDRESS_2_0)) && \
>>>> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 +
>>>> 0x2600))))); \
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>> index e2ad5afe..ad11c8e 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>> @@ -352,88 +352,88 @@ static void
>>>> vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
>>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>>> if (!indirect) {
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>> } else {
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0,
>>>> 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>> }
>>>> offset = 0;
>>>> } else {
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>>> offset = size;
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>>> }
>>>> if (!indirect)
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>> else
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>> /* cache window 1: stack */
>>>> if (!indirect) {
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>> } else {
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>> }
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>> indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>> indirect);
>>>> /* cache window 2: context */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset +
>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset +
>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE,
>>>> 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>>>> indirect);
>>>> /* non-cache window */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>> /* VCN global tiling registers */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG),
>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>> + UVD, mmUVD_GFX10_ADDR_CONFIG),
>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>> }
>>>> /**
>>>> @@ -579,19 +579,19 @@ static void
>>>> vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>>> UVD_CGC_CTRL__SCPU_MODE_MASK);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>> /* turn off clock gating */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>> /* turn on SUVD clock gating */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>> }
>>>> /**
>>>> @@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>> amdgpu_device *adev, bool indirect)
>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>> tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>> /* disable master interupt */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>> /* setup mmUVD_LMI_CTRL */
>>>> tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>>> @@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>> amdgpu_device *adev, bool indirect)
>>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>>> 0x00100000L);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_MPC_CNTL),
>>>> + UVD, mmUVD_MPC_CNTL),
>>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_MPC_SET_MUXA0),
>>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_MPC_SET_MUXB0),
>>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_MPC_SET_MUX),
>>>> + UVD, mmUVD_MPC_SET_MUX),
>>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>>> @@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>> amdgpu_device *adev, bool indirect)
>>>> vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>> /* release VCPU reset to boot */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
>>>> + UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
>>>> /* enable LMI MC and UMC channels */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_LMI_CTRL2),
>>>> + UVD, mmUVD_LMI_CTRL2),
>>>> 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0,
>>>> indirect);
>>>> /* enable master interrupt */
>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, 0, mmUVD_MASTINT_EN),
>>>> + UVD, mmUVD_MASTINT_EN),
>>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>>> if (indirect)
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> index 740a291..42ca36c 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>> @@ -435,88 +435,88 @@ static void
>>>> vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
>>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>>> if (!indirect) {
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>>> inst_idx].tmr_mc_addr_lo), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>>> inst_idx].tmr_mc_addr_hi), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>> } else {
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx,
>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx,
>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>> }
>>>> offset = 0;
>>>> } else {
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>>> offset = size;
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>>> }
>>>> if (!indirect)
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0,
>>>> indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>> else
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>> /* cache window 1: stack */
>>>> if (!indirect) {
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>> } else {
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>> 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>> 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>> indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>> }
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1),
>>>> AMDGPU_VCN_STACK_SIZE, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>> indirect);
>>>> /* cache window 2: context */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset
>>>> + AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset
>>>> + AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2),
>>>> AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>>>> indirect);
>>>> /* non-cache window */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0,
>>>> indirect);
>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>> /* VCN global tiling registers */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG),
>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>> + UVD, mmUVD_GFX8_ADDR_CONFIG),
>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>> }
>>>> /**
>>>> @@ -670,19 +670,19 @@ static void
>>>> vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>>> UVD_CGC_CTRL__MMSCH_MODE_MASK);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel,
>>>> indirect);
>>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>> /* turn off clock gating */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>> /* turn on SUVD clock gating */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>> }
>>>> /**
>>>> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>> amdgpu_device *adev, int inst_idx, boo
>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>> /* disable master interupt */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>> /* setup mmUVD_LMI_CTRL */
>>>> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>>> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>> amdgpu_device *adev, int inst_idx, boo
>>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>>> 0x00100000L);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_MPC_CNTL),
>>>> + UVD, mmUVD_MPC_CNTL),
>>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
>>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
>>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
>>>> + UVD, mmUVD_MPC_SET_MUX),
>>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>>> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>> amdgpu_device *adev, int inst_idx, boo
>>>> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>> /* enable LMI MC and UMC channels */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>>> + UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>>> /* unblock VCPU register access */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>>> + UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>>> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>> /* enable master interrupt */
>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>> - UVD, inst_idx, mmUVD_MASTINT_EN),
>>>> + UVD, mmUVD_MASTINT_EN),
>>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>>> if (indirect)
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* Re: [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 20:30 ` Leo Liu
@ 2020-01-21 20:58 ` James Zhu
2020-01-21 21:08 ` Leo Liu
0 siblings, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 20:58 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
Actually RREG32_SOC15_DPG_MODE_2_0 has a bug inside to miss using inst
as inst_idx,
So I want to clean up the header first to use inst_idx for abbreviation
of instance index.
James
On 2020-01-21 3:30 p.m., Leo Liu wrote:
>
> On 2020-01-21 12:50 p.m., James Zhu wrote:
>>
>> On 2020-01-21 12:43 p.m., Leo Liu wrote:
>>>
>>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>>> Use inst_idx relacing inst in SOC15_DPG_MODE macro
>>>>
>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>> ---
>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 +++++++++++-----------
>>>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> index 60fe3c4..98c1893 100644
>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>> @@ -65,23 +65,23 @@
>>>> /* 1 second timeout */
>>>> #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
>>>> -#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask,
>>>> sram_sel) \
>>>> - ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>>>> mask); \
>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>>>> +#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask,
>>>> sram_sel) \
>>>> + ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>>>> mask); \
>>>> + WREG32_SOC15(ip, inst_idx,
>>>> mmUVD_DPG_LMA_CTL, \
>>>
>>> I have only seen you are using inst_idx to replace inst, havn't you?
>>> this is not necessary, because we are using inst as the idx.
>>
>> Since we use inst for instance in struct amdgpu_vcn. To avoid
>> confusing, I create this patch,
>
> If only variable name changes, please drop these patch, we are using
> inst all the places.
>
> Leo
>
>
>
>
>>
>> James
>>
>>>
>>> Leo
>>>
>>>
>>>
>>>> UVD_DPG_LMA_CTL__MASK_EN_MASK | \
>>>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>>>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
>>>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>>>> | \
>>>> (sram_sel <<
>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>> - RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
>>>> + RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
>>>> })
>>>> -#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask,
>>>> sram_sel) \
>>>> +#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask,
>>>> sram_sel) \
>>>> do { \
>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA,
>>>> value); \
>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>>>> mask); \
>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>>>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA,
>>>> value); \
>>>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>>>> mask); \
>>>> + WREG32_SOC15(ip, inst_idx,
>>>> mmUVD_DPG_LMA_CTL, \
>>>> UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
>>>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>>>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
>>>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>>>> | \
>>>> (sram_sel <<
>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>> } while (0)
>>>> @@ -111,7 +111,7 @@
>>>> #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset,
>>>> mask_en) \
>>>> ({ \
>>>> - WREG32_SOC15(VCN, inst,
>>>> mmUVD_DPG_LMA_CTL, \
>>>> + WREG32_SOC15(VCN, inst_idx,
>>>> mmUVD_DPG_LMA_CTL, \
>>>> (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT
>>>> | \
>>>> mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT
>>>> | \
>>>> offset <<
>>>> UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 20:55 ` James Zhu
@ 2020-01-21 21:06 ` Leo Liu
2020-01-21 22:24 ` James Zhu
0 siblings, 1 reply; 25+ messages in thread
From: Leo Liu @ 2020-01-21 21:06 UTC (permalink / raw)
To: James Zhu, James Zhu, amd-gfx
On 2020-01-21 3:55 p.m., James Zhu wrote:
> Since SOC15_DPG_MODE_OFFSET is always the same for all instances, we
> should not put [inst]
>
> in the argument list. I will easily make bug in the future.
Like being said, we have the consistent format throughout the entire
driver for the offset as
"adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg",
so the format should be kept here as well
Leo
>
> James
>
> On 2020-01-21 3:23 p.m., Leo Liu wrote:
>>
>> On 2020-01-21 12:48 p.m., James Zhu wrote:
>>>
>>> On 2020-01-21 12:40 p.m., Leo Liu wrote:
>>>>
>>>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>>>> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>>>>>
>>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
>>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86
>>>>> ++++++++++++++++----------------
>>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88
>>>>> ++++++++++++++++-----------------
>>>>> 3 files changed, 89 insertions(+), 89 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> index c4984c5..60fe3c4 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> @@ -86,12 +86,12 @@
>>>>> (sram_sel <<
>>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>>> } while (0)
>>>>> -#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst,
>>>>> reg) \
>>>>> +#define SOC15_DPG_MODE_OFFSET_2_0(ip,
>>>>> reg) \
>>>>> ({ \
>>>>> uint32_t internal_reg_offset,
>>>>> addr; \
>>>>> bool video_range, aon_range; \
>>>>> \
>>>>> - addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX]
>>>>> + reg); \
>>>>
>>>> This is based the soc15_common.h
>>>>
>>>> #define SOC15_REG_OFFSET(ip, inst, reg)
>>>> (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>>>>
>>>> You are saying that is not right offset for 2nd instance?
>>>
>>> Yes, DPG mode is executed by individual instance, so the register
>>> offset is the same.
>>
>> Then you should use inst idx as 0 for the 2nd instance as well,
>> instead of changing the Macro.
>>
>> Leo
>>
>>
>>
>>>
>>> James
>>>
>>>>
>>>>
>>>> Leo
>>>>
>>>>
>>>>> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] +
>>>>> reg); \
>>>>> addr <<= 2; \
>>>>> video_range = ((((0xFFFFF & addr) >=
>>>>> (VCN_VID_SOC_ADDRESS_2_0)) && \
>>>>> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 +
>>>>> 0x2600))))); \
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>> index e2ad5afe..ad11c8e 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>> @@ -352,88 +352,88 @@ static void
>>>>> vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
>>>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>>>> if (!indirect) {
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>> } else {
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0,
>>>>> 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0,
>>>>> 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>> }
>>>>> offset = 0;
>>>>> } else {
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>>>> offset = size;
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>>>> }
>>>>> if (!indirect)
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>>> else
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>> /* cache window 1: stack */
>>>>> if (!indirect) {
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>> } else {
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>> }
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE,
>>>>> 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>>> indirect);
>>>>> /* cache window 2: context */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset +
>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset +
>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE,
>>>>> 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>>>>> indirect);
>>>>> /* non-cache window */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>> /* VCN global tiling registers */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG),
>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>> + UVD, mmUVD_GFX10_ADDR_CONFIG),
>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>> }
>>>>> /**
>>>>> @@ -579,19 +579,19 @@ static void
>>>>> vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>>>> UVD_CGC_CTRL__SCPU_MODE_MASK);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>>> /* turn off clock gating */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>> /* turn on SUVD clock gating */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>> }
>>>>> /**
>>>>> @@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>>> amdgpu_device *adev, bool indirect)
>>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>>> tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>> /* disable master interupt */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>> /* setup mmUVD_LMI_CTRL */
>>>>> tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>>>> @@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>>> amdgpu_device *adev, bool indirect)
>>>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>>>> 0x00100000L);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_MPC_CNTL),
>>>>> + UVD, mmUVD_MPC_CNTL),
>>>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_MPC_SET_MUXA0),
>>>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_MPC_SET_MUXB0),
>>>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_MPC_SET_MUX),
>>>>> + UVD, mmUVD_MPC_SET_MUX),
>>>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>>>> @@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>>> amdgpu_device *adev, bool indirect)
>>>>> vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>>> /* release VCPU reset to boot */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
>>>>> + UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
>>>>> /* enable LMI MC and UMC channels */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_LMI_CTRL2),
>>>>> + UVD, mmUVD_LMI_CTRL2),
>>>>> 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT, 0,
>>>>> indirect);
>>>>> /* enable master interrupt */
>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, 0, mmUVD_MASTINT_EN),
>>>>> + UVD, mmUVD_MASTINT_EN),
>>>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>>>> if (indirect)
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>> index 740a291..42ca36c 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>> @@ -435,88 +435,88 @@ static void
>>>>> vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
>>>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>>>> if (!indirect) {
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>>>> inst_idx].tmr_mc_addr_lo), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>>>> inst_idx].tmr_mc_addr_hi), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>> } else {
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx,
>>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx,
>>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>> }
>>>>> offset = 0;
>>>>> } else {
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>>>> offset = size;
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>>>> }
>>>>> if (!indirect)
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>>> else
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>> /* cache window 1: stack */
>>>>> if (!indirect) {
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>> } else {
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>> 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>> 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>>> indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>> }
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1),
>>>>> AMDGPU_VCN_STACK_SIZE, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>>> indirect);
>>>>> /* cache window 2: context */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2),
>>>>> AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0,
>>>>> indirect);
>>>>> /* non-cache window */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>> /* VCN global tiling registers */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG),
>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>> + UVD, mmUVD_GFX8_ADDR_CONFIG),
>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>> }
>>>>> /**
>>>>> @@ -670,19 +670,19 @@ static void
>>>>> vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>>>> UVD_CGC_CTRL__MMSCH_MODE_MASK);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel,
>>>>> indirect);
>>>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>>> /* turn off clock gating */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>> /* turn on SUVD clock gating */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>> }
>>>>> /**
>>>>> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>>> amdgpu_device *adev, int inst_idx, boo
>>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>>> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>> /* disable master interupt */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>> /* setup mmUVD_LMI_CTRL */
>>>>> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>>>> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>>> amdgpu_device *adev, int inst_idx, boo
>>>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>>>> 0x00100000L);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_MPC_CNTL),
>>>>> + UVD, mmUVD_MPC_CNTL),
>>>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
>>>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
>>>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
>>>>> + UVD, mmUVD_MPC_SET_MUX),
>>>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>>>> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>>> amdgpu_device *adev, int inst_idx, boo
>>>>> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0,
>>>>> indirect);
>>>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>>> /* enable LMI MC and UMC channels */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>>>> + UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>>>> /* unblock VCPU register access */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>>>> + UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>>>> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
>>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>> /* enable master interrupt */
>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>> - UVD, inst_idx, mmUVD_MASTINT_EN),
>>>>> + UVD, mmUVD_MASTINT_EN),
>>>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>>>> if (indirect)
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* Re: [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 20:58 ` James Zhu
@ 2020-01-21 21:08 ` Leo Liu
0 siblings, 0 replies; 25+ messages in thread
From: Leo Liu @ 2020-01-21 21:08 UTC (permalink / raw)
To: James Zhu, James Zhu, amd-gfx
On 2020-01-21 3:58 p.m., James Zhu wrote:
> Actually RREG32_SOC15_DPG_MODE_2_0 has a bug inside to miss using inst
> as inst_idx,
If there is a bug, you should clearly specify the bug in the commit
message and fix it in a patch, and then if you think the code-name
conversion need to be fixed, you should have that in a separated patch.
Leo
>
> So I want to clean up the header first to use inst_idx for
> abbreviation of instance index.
>
> James
>
> On 2020-01-21 3:30 p.m., Leo Liu wrote:
>>
>> On 2020-01-21 12:50 p.m., James Zhu wrote:
>>>
>>> On 2020-01-21 12:43 p.m., Leo Liu wrote:
>>>>
>>>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>>>> Use inst_idx relacing inst in SOC15_DPG_MODE macro
>>>>>
>>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>>> ---
>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 22 +++++++++++-----------
>>>>> 1 file changed, 11 insertions(+), 11 deletions(-)
>>>>>
>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> index 60fe3c4..98c1893 100644
>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>> @@ -65,23 +65,23 @@
>>>>> /* 1 second timeout */
>>>>> #define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
>>>>> -#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask,
>>>>> sram_sel) \
>>>>> - ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>>>>> mask); \
>>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>>>>> +#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask,
>>>>> sram_sel) \
>>>>> + ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>>>>> mask); \
>>>>> + WREG32_SOC15(ip, inst_idx,
>>>>> mmUVD_DPG_LMA_CTL, \
>>>>
>>>> I have only seen you are using inst_idx to replace inst, havn't
>>>> you? this is not necessary, because we are using inst as the idx.
>>>
>>> Since we use inst for instance in struct amdgpu_vcn. To avoid
>>> confusing, I create this patch,
>>
>> If only variable name changes, please drop these patch, we are using
>> inst all the places.
>>
>> Leo
>>
>>
>>
>>
>>>
>>> James
>>>
>>>>
>>>> Leo
>>>>
>>>>
>>>>
>>>>> UVD_DPG_LMA_CTL__MASK_EN_MASK | \
>>>>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>>>>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] +
>>>>> reg) \
>>>>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>>>>> | \
>>>>> (sram_sel <<
>>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>>> - RREG32_SOC15(ip, inst,
>>>>> mmUVD_DPG_LMA_DATA); \
>>>>> + RREG32_SOC15(ip, inst_idx,
>>>>> mmUVD_DPG_LMA_DATA); \
>>>>> })
>>>>> -#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask,
>>>>> sram_sel) \
>>>>> +#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask,
>>>>> sram_sel) \
>>>>> do { \
>>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA,
>>>>> value); \
>>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK,
>>>>> mask); \
>>>>> - WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
>>>>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA,
>>>>> value); \
>>>>> + WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK,
>>>>> mask); \
>>>>> + WREG32_SOC15(ip, inst_idx,
>>>>> mmUVD_DPG_LMA_CTL, \
>>>>> UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
>>>>> - ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
>>>>> + ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] +
>>>>> reg) \
>>>>> << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)
>>>>> | \
>>>>> (sram_sel <<
>>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>>> } while (0)
>>>>> @@ -111,7 +111,7 @@
>>>>> #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset,
>>>>> mask_en) \
>>>>> ({ \
>>>>> - WREG32_SOC15(VCN, inst,
>>>>> mmUVD_DPG_LMA_CTL, \
>>>>> + WREG32_SOC15(VCN, inst_idx,
>>>>> mmUVD_DPG_LMA_CTL, \
>>>>> (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT
>>>>> | \
>>>>> mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT
>>>>> | \
>>>>> offset <<
>>>>> UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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* [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error
2020-01-21 16:19 ` [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
2020-01-21 17:43 ` Leo Liu
@ 2020-01-21 21:39 ` James Zhu
2020-01-21 21:39 ` [PATCH v2 5/5] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
2020-01-21 22:06 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error Leo Liu
1 sibling, 2 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 21:39 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Fix typo error, should be inst_idx instead of inst.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index 60fe3c4..ff4f4f7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -111,7 +111,7 @@
#define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en) \
({ \
- WREG32_SOC15(VCN, inst, mmUVD_DPG_LMA_CTL, \
+ WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
(0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
--
2.7.4
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^ permalink raw reply related [flat|nested] 25+ messages in thread
* [PATCH v2 5/5] drm/amdgpu/vcn: use inst_idx relacing inst
2020-01-21 21:39 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error James Zhu
@ 2020-01-21 21:39 ` James Zhu
2020-01-21 22:06 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error Leo Liu
1 sibling, 0 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 21:39 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Use inst_idx relacing inst in SOC15_DPG_MODE macro to avoid confusion.
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index ff4f4f7..98c1893 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -65,23 +65,23 @@
/* 1 second timeout */
#define VCN_IDLE_TIMEOUT msecs_to_jiffies(1000)
-#define RREG32_SOC15_DPG_MODE(ip, inst, reg, mask, sram_sel) \
- ({ WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
+#define RREG32_SOC15_DPG_MODE(ip, inst_idx, reg, mask, sram_sel) \
+ ({ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
UVD_DPG_LMA_CTL__MASK_EN_MASK | \
- ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
+ ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
- RREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA); \
+ RREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA); \
})
-#define WREG32_SOC15_DPG_MODE(ip, inst, reg, value, mask, sram_sel) \
+#define WREG32_SOC15_DPG_MODE(ip, inst_idx, reg, value, mask, sram_sel) \
do { \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_DATA, value); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_MASK, mask); \
- WREG32_SOC15(ip, inst, mmUVD_DPG_LMA_CTL, \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_DATA, value); \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_MASK, mask); \
+ WREG32_SOC15(ip, inst_idx, mmUVD_DPG_LMA_CTL, \
UVD_DPG_LMA_CTL__READ_WRITE_MASK | \
- ((adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg) \
+ ((adev->reg_offset[ip##_HWIP][inst_idx][reg##_BASE_IDX] + reg) \
<< UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT) | \
(sram_sel << UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
} while (0)
--
2.7.4
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* Re: [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error
2020-01-21 21:39 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error James Zhu
2020-01-21 21:39 ` [PATCH v2 5/5] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
@ 2020-01-21 22:06 ` Leo Liu
1 sibling, 0 replies; 25+ messages in thread
From: Leo Liu @ 2020-01-21 22:06 UTC (permalink / raw)
To: James Zhu, amd-gfx; +Cc: jamesz
Patch v2 4 and 5 are:
Reviewed-by: Leo Liu <leo.liu@amd.com>
On 2020-01-21 4:39 p.m., James Zhu wrote:
> Fix typo error, should be inst_idx instead of inst.
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index 60fe3c4..ff4f4f7 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -111,7 +111,7 @@
>
> #define RREG32_SOC15_DPG_MODE_2_0(inst_idx, offset, mask_en) \
> ({ \
> - WREG32_SOC15(VCN, inst, mmUVD_DPG_LMA_CTL, \
> + WREG32_SOC15(VCN, inst_idx, mmUVD_DPG_LMA_CTL, \
> (0x0 << UVD_DPG_LMA_CTL__READ_WRITE__SHIFT | \
> mask_en << UVD_DPG_LMA_CTL__MASK_EN__SHIFT | \
> offset << UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT)); \
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* [PATCH v2 3/5] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 16:19 ` [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue James Zhu
2020-01-21 17:40 ` Leo Liu
@ 2020-01-21 22:21 ` James Zhu
2020-01-21 22:32 ` Leo Liu
1 sibling, 1 reply; 25+ messages in thread
From: James Zhu @ 2020-01-21 22:21 UTC (permalink / raw)
To: amd-gfx; +Cc: jamesz
Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
Signed-off-by: James Zhu <James.Zhu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88 ++++++++++++++++-----------------
2 files changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
index c4984c5..bf7f2aa 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
@@ -91,7 +91,7 @@
uint32_t internal_reg_offset, addr; \
bool video_range, aon_range; \
\
- addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
+ addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg); \
addr <<= 2; \
video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
index 740a291..f513c6d 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
@@ -435,88 +435,88 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
(adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
} else {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
}
offset = 0;
} else {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
offset = size;
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
}
if (!indirect)
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
else
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
/* cache window 1: stack */
if (!indirect) {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
} else {
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
}
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
/* cache window 2: context */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
+ UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
/* non-cache window */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
+ UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
/* VCN global tiling registers */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
+ UVD, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
}
/**
@@ -670,19 +670,19 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
UVD_CGC_CTRL__VCPU_MODE_MASK |
UVD_CGC_CTRL__MMSCH_MODE_MASK);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
+ UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
/* turn off clock gating */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
+ UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
/* turn on SUVD clock gating */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
+ UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
/* turn on sw mode in UVD_SUVD_CGC_CTRL */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
+ UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
}
/**
@@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
/* disable master interupt */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
+ UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
/* setup mmUVD_LMI_CTRL */
tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
@@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
(8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
0x00100000L);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
+ UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_CNTL),
+ UVD, 0, mmUVD_MPC_CNTL),
0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
+ UVD, 0, mmUVD_MPC_SET_MUXA0),
((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
+ UVD, 0, mmUVD_MPC_SET_MUXB0),
((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
(0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
(0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MPC_SET_MUX),
+ UVD, 0, mmUVD_MPC_SET_MUX),
((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
(0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
(0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
@@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
+ UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
+ UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
/* enable LMI MC and UMC channels */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
+ UVD, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
/* unblock VCPU register access */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
+ UVD, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
+ UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
/* enable master interrupt */
WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
- UVD, inst_idx, mmUVD_MASTINT_EN),
+ UVD, 0, mmUVD_MASTINT_EN),
UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
if (indirect)
--
2.7.4
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 25+ messages in thread
* Re: [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 21:06 ` Leo Liu
@ 2020-01-21 22:24 ` James Zhu
0 siblings, 0 replies; 25+ messages in thread
From: James Zhu @ 2020-01-21 22:24 UTC (permalink / raw)
To: Leo Liu, James Zhu, amd-gfx
On 2020-01-21 4:06 p.m., Leo Liu wrote:
>
> On 2020-01-21 3:55 p.m., James Zhu wrote:
>> Since SOC15_DPG_MODE_OFFSET is always the same for all instances, we
>> should not put [inst]
>>
>> in the argument list. I will easily make bug in the future.
>
> Like being said, we have the consistent format throughout the entire
> driver for the offset as
> "adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg",
>
> so the format should be kept here as well
Really don't think it is worthy to keep this format. more than one day's
debug effort is wasted.
If Format is more important, then let us choose the v2 patch.
James
>
> Leo
>
>
>>
>> James
>>
>> On 2020-01-21 3:23 p.m., Leo Liu wrote:
>>>
>>> On 2020-01-21 12:48 p.m., James Zhu wrote:
>>>>
>>>> On 2020-01-21 12:40 p.m., Leo Liu wrote:
>>>>>
>>>>> On 2020-01-21 11:19 a.m., James Zhu wrote:
>>>>>> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>>>>>>
>>>>>> Signed-off-by: James Zhu <James.Zhu@amd.com>
>>>>>> ---
>>>>>> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 4 +-
>>>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c | 86
>>>>>> ++++++++++++++++----------------
>>>>>> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88
>>>>>> ++++++++++++++++-----------------
>>>>>> 3 files changed, 89 insertions(+), 89 deletions(-)
>>>>>>
>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>>> index c4984c5..60fe3c4 100644
>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
>>>>>> @@ -86,12 +86,12 @@
>>>>>> (sram_sel <<
>>>>>> UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT)); \
>>>>>> } while (0)
>>>>>> -#define SOC15_DPG_MODE_OFFSET_2_0(ip, inst,
>>>>>> reg) \
>>>>>> +#define SOC15_DPG_MODE_OFFSET_2_0(ip,
>>>>>> reg) \
>>>>>> ({ \
>>>>>> uint32_t internal_reg_offset,
>>>>>> addr; \
>>>>>> bool video_range, aon_range; \
>>>>>> \
>>>>>> - addr =
>>>>>> (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
>>>>>
>>>>> This is based the soc15_common.h
>>>>>
>>>>> #define SOC15_REG_OFFSET(ip, inst, reg)
>>>>> (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg)
>>>>>
>>>>> You are saying that is not right offset for 2nd instance?
>>>>
>>>> Yes, DPG mode is executed by individual instance, so the register
>>>> offset is the same.
>>>
>>> Then you should use inst idx as 0 for the 2nd instance as well,
>>> instead of changing the Macro.
>>>
>>> Leo
>>>
>>>
>>>
>>>>
>>>> James
>>>>
>>>>>
>>>>>
>>>>> Leo
>>>>>
>>>>>
>>>>>> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] +
>>>>>> reg); \
>>>>>> addr <<= 2; \
>>>>>> video_range = ((((0xFFFFF & addr) >=
>>>>>> (VCN_VID_SOC_ADDRESS_2_0)) && \
>>>>>> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 +
>>>>>> 0x2600))))); \
>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>>> index e2ad5afe..ad11c8e 100644
>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_0.c
>>>>>> @@ -352,88 +352,88 @@ static void
>>>>>> vcn_v2_0_mc_resume_dpg_mode(struct amdgpu_device *adev, bool indirec
>>>>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>>>>> if (!indirect) {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo), 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi), 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>>> } else {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0,
>>>>>> 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0,
>>>>>> 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>>> }
>>>>>> offset = 0;
>>>>>> } else {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect);
>>>>>> offset = size;
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>>>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>>>>> }
>>>>>> if (!indirect)
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>>>> else
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>>> /* cache window 1: stack */
>>>>>> if (!indirect) {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>>> } else {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>>> }
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE,
>>>>>> 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>>>> indirect);
>>>>>> /* cache window 2: context */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>>> lower_32_bits(adev->vcn.inst->gpu_addr + offset +
>>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>>> upper_32_bits(adev->vcn.inst->gpu_addr + offset +
>>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CACHE_SIZE2),
>>>>>> AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE,
>>>>>> 0, indirect);
>>>>>> /* non-cache window */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>>> /* VCN global tiling registers */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG),
>>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>>> + UVD, mmUVD_GFX10_ADDR_CONFIG),
>>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>>> }
>>>>>> /**
>>>>>> @@ -579,19 +579,19 @@ static void
>>>>>> vcn_v2_0_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>>>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>>>>> UVD_CGC_CTRL__SCPU_MODE_MASK);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>>>> /* turn off clock gating */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>>> /* turn on SUVD clock gating */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>>> }
>>>>>> /**
>>>>>> @@ -764,11 +764,11 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>>>> amdgpu_device *adev, bool indirect)
>>>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>>>> tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>>> /* disable master interupt */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>>> /* setup mmUVD_LMI_CTRL */
>>>>>> tmp = (UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>>>>> @@ -780,28 +780,28 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>>>> amdgpu_device *adev, bool indirect)
>>>>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>>>>> 0x00100000L);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_MPC_CNTL),
>>>>>> + UVD, mmUVD_MPC_CNTL),
>>>>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_MPC_SET_MUXA0),
>>>>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>>>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>>>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>>>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>>>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_MPC_SET_MUXB0),
>>>>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>>>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>>>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>>>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>>>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_MPC_SET_MUX),
>>>>>> + UVD, mmUVD_MPC_SET_MUX),
>>>>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>>>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>>>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>>>>> @@ -809,22 +809,22 @@ static int vcn_v2_0_start_dpg_mode(struct
>>>>>> amdgpu_device *adev, bool indirect)
>>>>>> vcn_v2_0_mc_resume_dpg_mode(adev, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>>>> /* release VCPU reset to boot */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_SOFT_RESET), 0, 0, indirect);
>>>>>> + UVD, mmUVD_SOFT_RESET), 0, 0, indirect);
>>>>>> /* enable LMI MC and UMC channels */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_LMI_CTRL2),
>>>>>> + UVD, mmUVD_LMI_CTRL2),
>>>>>> 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
>>>>>> 0, indirect);
>>>>>> /* enable master interrupt */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(0, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, 0, mmUVD_MASTINT_EN),
>>>>>> + UVD, mmUVD_MASTINT_EN),
>>>>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>>>>> if (indirect)
>>>>>> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>>> b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>>> index 740a291..42ca36c 100644
>>>>>> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>>> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
>>>>>> @@ -435,88 +435,88 @@ static void
>>>>>> vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
>>>>>> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
>>>>>> if (!indirect) {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>>>>> inst_idx].tmr_mc_addr_lo), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx,
>>>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN +
>>>>>> inst_idx].tmr_mc_addr_hi), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>>> } else {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx,
>>>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx,
>>>>>> mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
>>>>>> }
>>>>>> offset = 0;
>>>>>> } else {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
>>>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
>>>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
>>>>>> offset = size;
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET0),
>>>>>> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
>>>>>> }
>>>>>> if (!indirect)
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
>>>>>> else
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>>>>>> /* cache window 1: stack */
>>>>>> if (!indirect) {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
>>>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>>> } else {
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
>>>>>> 0, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx,
>>>>>> mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
>>>>>> }
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1),
>>>>>> AMDGPU_VCN_STACK_SIZE, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0,
>>>>>> indirect);
>>>>>> /* cache window 2: context */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
>>>>>> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>>> + UVD, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
>>>>>> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset +
>>>>>> AMDGPU_VCN_STACK_SIZE), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2),
>>>>>> AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE,
>>>>>> 0, indirect);
>>>>>> /* non-cache window */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>>>>>> /* VCN global tiling registers */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG),
>>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>>> + UVD, mmUVD_GFX8_ADDR_CONFIG),
>>>>>> adev->gfx.config.gb_addr_config, 0, indirect);
>>>>>> }
>>>>>> /**
>>>>>> @@ -670,19 +670,19 @@ static void
>>>>>> vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
>>>>>> UVD_CGC_CTRL__VCPU_MODE_MASK |
>>>>>> UVD_CGC_CTRL__MMSCH_MODE_MASK);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>>>>>> /* turn off clock gating */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>>> + UVD, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>>>>>> /* turn on SUVD clock gating */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>>>>>> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
>>>>>> }
>>>>>> /**
>>>>>> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>>>> amdgpu_device *adev, int inst_idx, boo
>>>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>>>> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>>> /* disable master interupt */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>>> + UVD, mmUVD_MASTINT_EN), 0, 0, indirect);
>>>>>> /* setup mmUVD_LMI_CTRL */
>>>>>> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
>>>>>> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>>>> amdgpu_device *adev, int inst_idx, boo
>>>>>> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
>>>>>> 0x00100000L);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_CTRL), tmp, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_MPC_CNTL),
>>>>>> + UVD, mmUVD_MPC_CNTL),
>>>>>> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0,
>>>>>> indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
>>>>>> + UVD, mmUVD_MPC_SET_MUXA0),
>>>>>> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
>>>>>> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
>>>>>> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
>>>>>> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
>>>>>> + UVD, mmUVD_MPC_SET_MUXB0),
>>>>>> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
>>>>>> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
>>>>>> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
>>>>>> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
>>>>>> + UVD, mmUVD_MPC_SET_MUX),
>>>>>> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
>>>>>> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
>>>>>> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
>>>>>> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct
>>>>>> amdgpu_device *adev, int inst_idx, boo
>>>>>> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx,
>>>>>> SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>>> + UVD, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0,
>>>>>> indirect);
>>>>>> + UVD, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>>>>>> /* enable LMI MC and UMC channels */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>>>>> + UVD, mmUVD_LMI_CTRL2), 0, 0, indirect);
>>>>>> /* unblock VCPU register access */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>>>>> + UVD, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>>>>>> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
>>>>>> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>>> + UVD, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>>>>>> /* enable master interrupt */
>>>>>> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
>>>>>> - UVD, inst_idx, mmUVD_MASTINT_EN),
>>>>>> + UVD, mmUVD_MASTINT_EN),
>>>>>> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>>>>>> if (indirect)
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^ permalink raw reply [flat|nested] 25+ messages in thread
* Re: [PATCH v2 3/5] drm/amdgpu/vcn: fix vcn2.5 instance issue
2020-01-21 22:21 ` [PATCH v2 3/5] " James Zhu
@ 2020-01-21 22:32 ` Leo Liu
0 siblings, 0 replies; 25+ messages in thread
From: Leo Liu @ 2020-01-21 22:32 UTC (permalink / raw)
To: James Zhu, amd-gfx; +Cc: jamesz
On 2020-01-21 5:21 p.m., James Zhu wrote:
> Fix vcn2.5 instance issue, vcn0 and vcn1 have same register offset
>
> Signed-off-by: James Zhu <James.Zhu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h | 2 +-
> drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c | 88 ++++++++++++++++-----------------
> 2 files changed, 45 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> index c4984c5..bf7f2aa 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h
> @@ -91,7 +91,7 @@
> uint32_t internal_reg_offset, addr; \
> bool video_range, aon_range; \
> \
> - addr = (adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] + reg); \
> + addr = (adev->reg_offset[ip##_HWIP][0][reg##_BASE_IDX] + reg); \
Why do you still have hard coded here? please have it reverted. With
that fixed the patch is:
Reviewed-by: Leo Liu <leo.liu@amd.com>
> addr <<= 2; \
> video_range = ((((0xFFFFF & addr) >= (VCN_VID_SOC_ADDRESS_2_0)) && \
> ((0xFFFFF & addr) < ((VCN_VID_SOC_ADDRESS_2_0 + 0x2600))))); \
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> index 740a291..f513c6d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v2_5.c
> @@ -435,88 +435,88 @@ static void vcn_v2_5_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_lo), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN + inst_idx].tmr_mc_addr_hi), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> } else {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_OFFSET0), 0, 0, indirect);
> }
> offset = 0;
> } else {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect);
> offset = size;
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET0),
> + UVD, 0, mmUVD_VCPU_CACHE_OFFSET0),
> AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0, indirect);
> }
>
> if (!indirect)
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_SIZE0), size, 0, indirect);
> else
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_SIZE0), 0, 0, indirect);
>
> /* cache window 1: stack */
> if (!indirect) {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> } else {
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_OFFSET1), 0, 0, indirect);
> }
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_VCN_STACK_SIZE, 0, indirect);
>
> /* cache window 2: context */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
> lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> + UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
> upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_OFFSET2), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CACHE_SIZE2), AMDGPU_VCN_CONTEXT_SIZE, 0, indirect);
>
> /* non-cache window */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_LOW), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_VCPU_NC0_64BIT_BAR_HIGH), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_NONCACHE_OFFSET0), 0, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
> + UVD, 0, mmUVD_VCPU_NONCACHE_SIZE0), 0, 0, indirect);
>
> /* VCN global tiling registers */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> + UVD, 0, mmUVD_GFX8_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> }
>
> /**
> @@ -670,19 +670,19 @@ static void vcn_v2_5_clock_gating_dpg_mode(struct amdgpu_device *adev,
> UVD_CGC_CTRL__VCPU_MODE_MASK |
> UVD_CGC_CTRL__MMSCH_MODE_MASK);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
> + UVD, 0, mmUVD_CGC_CTRL), reg_data, sram_sel, indirect);
>
> /* turn off clock gating */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_CGC_GATE), 0, sram_sel, indirect);
> + UVD, 0, mmUVD_CGC_GATE), 0, sram_sel, indirect);
>
> /* turn on SUVD clock gating */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
> + UVD, 0, mmUVD_SUVD_CGC_GATE), 1, sram_sel, indirect);
>
> /* turn on sw mode in UVD_SUVD_CGC_CTRL */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
> + UVD, 0, mmUVD_SUVD_CGC_CTRL), 0, sram_sel, indirect);
> }
>
> /**
> @@ -772,11 +772,11 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> tmp |= UVD_VCPU_CNTL__BLK_RST_MASK;
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>
> /* disable master interupt */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MASTINT_EN), 0, 0, indirect);
> + UVD, 0, mmUVD_MASTINT_EN), 0, 0, indirect);
>
> /* setup mmUVD_LMI_CTRL */
> tmp = (0x8 | UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
> @@ -788,28 +788,28 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
> 0x00100000L);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_CTRL), tmp, 0, indirect);
> + UVD, 0, mmUVD_LMI_CTRL), tmp, 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_CNTL),
> + UVD, 0, mmUVD_MPC_CNTL),
> 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_SET_MUXA0),
> + UVD, 0, mmUVD_MPC_SET_MUXA0),
> ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
> (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
> (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_SET_MUXB0),
> + UVD, 0, mmUVD_MPC_SET_MUXB0),
> ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
> (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
> (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MPC_SET_MUX),
> + UVD, 0, mmUVD_MPC_SET_MUX),
> ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
> (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
> (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0, indirect);
> @@ -817,26 +817,26 @@ static int vcn_v2_5_start_dpg_mode(struct amdgpu_device *adev, int inst_idx, boo
> vcn_v2_5_mc_resume_dpg_mode(adev, inst_idx, indirect);
>
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
> + UVD, 0, mmUVD_REG_XX_MASK), 0x10, 0, indirect);
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
> + UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK), 0x3, 0, indirect);
>
> /* enable LMI MC and UMC channels */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_LMI_CTRL2), 0, 0, indirect);
> + UVD, 0, mmUVD_LMI_CTRL2), 0, 0, indirect);
>
> /* unblock VCPU register access */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
> + UVD, 0, mmUVD_RB_ARB_CTRL), 0, 0, indirect);
>
> tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
> tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_VCPU_CNTL), tmp, 0, indirect);
> + UVD, 0, mmUVD_VCPU_CNTL), tmp, 0, indirect);
>
> /* enable master interrupt */
> WREG32_SOC15_DPG_MODE_2_0(inst_idx, SOC15_DPG_MODE_OFFSET_2_0(
> - UVD, inst_idx, mmUVD_MASTINT_EN),
> + UVD, 0, mmUVD_MASTINT_EN),
> UVD_MASTINT_EN__VCPU_EN_MASK, 0, indirect);
>
> if (indirect)
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^ permalink raw reply [flat|nested] 25+ messages in thread
end of thread, other threads:[~2020-01-21 22:32 UTC | newest]
Thread overview: 25+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-21 16:19 [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 James Zhu
2020-01-21 16:19 ` [PATCH 2/4] drm/amdgpu/vcn2.5: fix a bug for the 2nd vcn instance James Zhu
2020-01-21 17:29 ` Leo Liu
2020-01-21 17:47 ` James Zhu
2020-01-21 20:20 ` Leo Liu
2020-01-21 20:49 ` James Zhu
2020-01-21 16:19 ` [PATCH 3/4] drm/amdgpu/vcn: fix vcn2.5 instance issue James Zhu
2020-01-21 17:40 ` Leo Liu
2020-01-21 17:48 ` James Zhu
2020-01-21 20:23 ` Leo Liu
2020-01-21 20:55 ` James Zhu
2020-01-21 21:06 ` Leo Liu
2020-01-21 22:24 ` James Zhu
2020-01-21 22:21 ` [PATCH v2 3/5] " James Zhu
2020-01-21 22:32 ` Leo Liu
2020-01-21 16:19 ` [PATCH 4/4] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
2020-01-21 17:43 ` Leo Liu
2020-01-21 17:50 ` James Zhu
2020-01-21 20:30 ` Leo Liu
2020-01-21 20:58 ` James Zhu
2020-01-21 21:08 ` Leo Liu
2020-01-21 21:39 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error James Zhu
2020-01-21 21:39 ` [PATCH v2 5/5] drm/amdgpu/vcn: use inst_idx relacing inst James Zhu
2020-01-21 22:06 ` [PATCH v2 4/5] drm/amdgpu/vcn: fix typo error Leo Liu
2020-01-21 17:25 ` [PATCH 1/4] drm/amdgpu/vcn: Share vcn_v2_0_dec_ring_test_ring to vcn2.5 Leo Liu
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