* [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages
@ 2020-01-22 20:18 Chris Wilson
2020-01-22 21:02 ` Chris Wilson
` (9 more replies)
0 siblings, 10 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-22 20:18 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..aaba06a774ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -331,6 +331,21 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)) {
+ kunmap_atomic(memset64(kmap_atomic(page),
+ POISON_FREE,
+ size / sizeof(64)));
+ }
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
@ 2020-01-22 21:02 ` Chris Wilson
2020-01-23 7:40 ` Chris Wilson
2020-01-23 3:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev2) Patchwork
` (8 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2020-01-22 21:02 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gtt.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..804da478d8f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,14 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ kunmap_atomic(memset(kmap_atomic(page), POISON_FREE, size));
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +339,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev2)
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
2020-01-22 21:02 ` Chris Wilson
@ 2020-01-23 3:42 ` Patchwork
2020-01-23 8:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev3) Patchwork
` (7 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-23 3:42 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Poison GTT scratch pages (rev2)
URL : https://patchwork.freedesktop.org/series/72423/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7799 -> Patchwork_16221
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16221 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16221, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16221:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_parallel@fds:
- fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-peppy/igt@gem_exec_parallel@fds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-hsw-peppy/igt@gem_exec_parallel@fds.html
* igt@i915_selftest@live_gem_contexts:
- fi-apl-guc: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-apl-guc/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-apl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-skl-lmem: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
- fi-bxt-dsi: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bxt-dsi/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-bxt-dsi/igt@i915_selftest@live_gem_contexts.html
- fi-icl-u2: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-u2/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-icl-u2/igt@i915_selftest@live_gem_contexts.html
- fi-skl-6600u: [PASS][11] -> [DMESG-FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-6600u/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-skl-6600u/igt@i915_selftest@live_gem_contexts.html
- fi-cml-u2: [PASS][13] -> [DMESG-FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cml-u2/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-cml-u2/igt@i915_selftest@live_gem_contexts.html
- fi-whl-u: [PASS][15] -> [DMESG-FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-whl-u/igt@i915_selftest@live_gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-whl-u/igt@i915_selftest@live_gem_contexts.html
- fi-cfl-8700k: [PASS][17] -> [DMESG-FAIL][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-icl-dsi: [PASS][19] -> [DMESG-FAIL][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-guc: [PASS][21] -> [DMESG-FAIL][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-7500u: [PASS][23] -> [DMESG-FAIL][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-7500u/igt@i915_selftest@live_gem_contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-kbl-7500u/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770: [PASS][25] -> [DMESG-FAIL][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
- fi-skl-guc: [PASS][27] -> [DMESG-FAIL][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-bdw-5557u: [PASS][29] -> [DMESG-FAIL][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bdw-5557u/igt@i915_selftest@live_gem_contexts.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-bdw-5557u/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-r: [PASS][31] -> [DMESG-FAIL][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
- fi-icl-y: [PASS][33] -> [DMESG-FAIL][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-y/igt@i915_selftest@live_gem_contexts.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-icl-y/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-8809g: [PASS][35] -> [DMESG-FAIL][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-8809g/igt@i915_selftest@live_gem_contexts.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-kbl-8809g/igt@i915_selftest@live_gem_contexts.html
- fi-glk-dsi: NOTRUN -> [DMESG-FAIL][37]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-glk-dsi/igt@i915_selftest@live_gem_contexts.html
- fi-tgl-y: [PASS][38] -> [DMESG-FAIL][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-tgl-y/igt@i915_selftest@live_gem_contexts.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-tgl-y/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770r: [PASS][40] -> [DMESG-FAIL][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
- fi-icl-u3: [PASS][42] -> [DMESG-FAIL][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-u3/igt@i915_selftest@live_gem_contexts.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-icl-u3/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-x1275: [PASS][44] -> [DMESG-FAIL][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
- fi-skl-6700k2: [PASS][46] -> [DMESG-FAIL][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-6700k2/igt@i915_selftest@live_gem_contexts.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-skl-6700k2/igt@i915_selftest@live_gem_contexts.html
- fi-icl-guc: [PASS][48] -> [DMESG-FAIL][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gem_contexts:
- {fi-tgl-u}: [PASS][50] -> [DMESG-FAIL][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
- {fi-kbl-7560u}: NOTRUN -> [DMESG-FAIL][52]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-kbl-7560u/igt@i915_selftest@live_gem_contexts.html
- {fi-ehl-1}: [PASS][53] -> [DMESG-FAIL][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-ehl-1/igt@i915_selftest@live_gem_contexts.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-ehl-1/igt@i915_selftest@live_gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_16221 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-skl-6700k2: [PASS][55] -> [DMESG-WARN][56] ([i915#889])
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-skl-6700k2/igt@i915_module_load@reload-with-fault-injection.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][57] ([i915#553] / [i915#725]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-hsw-4770r/igt@i915_selftest@live_blt.html
#### Warnings ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-cfl-guc: [INCOMPLETE][59] ([i915#505] / [i915#671]) -> [DMESG-WARN][60] ([i915#889])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#889]: https://gitlab.freedesktop.org/drm/intel/issues/889
Participating hosts (50 -> 45)
------------------------------
Additional (3): fi-kbl-7560u fi-glk-dsi fi-ilk-650
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7799 -> Patchwork_16221
CI-20190529: 20190529
CI_DRM_7799: 0f8a46a25a7781ef6ede604c9cb50f82cfb5e960 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5377: 1e6cb3e75925cf623df04f78430ae9299632ec3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16221: 58d849b5ac8cc5d37f94d8e0ef6b5b1b691b3ff7 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
58d849b5ac8c drm/i915/gt: Poison GTT scratch pages
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16221/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages
2020-01-22 21:02 ` Chris Wilson
@ 2020-01-23 7:40 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 7:40 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 30 ++++++++++++++++++-
drivers/gpu/drm/i915/gt/intel_gtt.c | 19 ++++++++++++
2 files changed, 48 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 7fc46861a54d..62c2babf2bd3 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1686,6 +1686,24 @@ static int read_from_scratch(struct i915_gem_context *ctx,
return err;
}
+static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
+{
+ struct page *page = ctx_vm(ctx)->scratch[0].base.page;
+ unsigned long size = 1ul << (ctx_vm(ctx)->scratch_order + PAGE_SHIFT);
+ u32 *vaddr;
+ int err = 0;
+
+ vaddr = kmap(page);
+ memcpy(out, vaddr, sizeof(*out));
+ if (memchr_inv(vaddr, *out, size)) {
+ pr_err("Inconsistent initial state of scratch page!\n");
+ err = -EINVAL;
+ }
+ kunmap(page);
+
+ return err;
+}
+
static int igt_vm_isolation(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1696,6 +1714,7 @@ static int igt_vm_isolation(void *arg)
I915_RND_STATE(prng);
struct file *file;
u64 vm_total;
+ u32 expected;
int err;
if (INTEL_GEN(i915) < 7)
@@ -1720,12 +1739,21 @@ static int igt_vm_isolation(void *arg)
goto out_file;
}
+ /* Read the initial state of the scratch page */
+ err = check_scratch_page(ctx_a, &expected);
+ if (err)
+ goto out_file;
+
ctx_b = live_context(i915, file);
if (IS_ERR(ctx_b)) {
err = PTR_ERR(ctx_b);
goto out_file;
}
+ err = check_scratch_page(ctx_b, &expected);
+ if (err)
+ goto out_file;
+
/* We can only test vm isolation, if the vm are distinct */
if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
@@ -1760,7 +1788,7 @@ static int igt_vm_isolation(void *arg)
if (err)
goto out_file;
- if (value) {
+ if (value != expected) {
pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
engine->name, value,
upper_32_bits(offset),
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..804da478d8f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,14 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ kunmap_atomic(memset(kmap_atomic(page), POISON_FREE, size));
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +339,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev3)
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
2020-01-22 21:02 ` Chris Wilson
2020-01-23 3:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev2) Patchwork
@ 2020-01-23 8:25 ` Patchwork
2020-01-23 8:51 ` [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (6 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-23 8:25 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Poison GTT scratch pages (rev3)
URL : https://patchwork.freedesktop.org/series/72423/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7799 -> Patchwork_16225
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16225 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16225, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16225:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_gem_contexts:
- fi-apl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-apl-guc/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-apl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-skl-lmem: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-skl-lmem/igt@i915_selftest@live_gem_contexts.html
- fi-bxt-dsi: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bxt-dsi/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-bxt-dsi/igt@i915_selftest@live_gem_contexts.html
- fi-icl-u2: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-u2/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-icl-u2/igt@i915_selftest@live_gem_contexts.html
- fi-ivb-3770: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
- fi-skl-6600u: [PASS][11] -> [DMESG-FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-6600u/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-skl-6600u/igt@i915_selftest@live_gem_contexts.html
- fi-cml-u2: [PASS][13] -> [DMESG-FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cml-u2/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-cml-u2/igt@i915_selftest@live_gem_contexts.html
- fi-whl-u: [PASS][15] -> [DMESG-FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-whl-u/igt@i915_selftest@live_gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-whl-u/igt@i915_selftest@live_gem_contexts.html
- fi-cfl-8700k: [PASS][17] -> [DMESG-FAIL][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-icl-dsi: [PASS][19] -> [DMESG-FAIL][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-icl-dsi/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-guc: [PASS][21] -> [DMESG-FAIL][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-kbl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-7500u: [PASS][23] -> [DMESG-FAIL][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-7500u/igt@i915_selftest@live_gem_contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-kbl-7500u/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770: [PASS][25] -> [DMESG-FAIL][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
- fi-skl-guc: [PASS][27] -> [DMESG-FAIL][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-skl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-bdw-5557u: [PASS][29] -> [DMESG-FAIL][30]
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bdw-5557u/igt@i915_selftest@live_gem_contexts.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-bdw-5557u/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-r: [PASS][31] -> [DMESG-FAIL][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-kbl-r/igt@i915_selftest@live_gem_contexts.html
- fi-icl-y: [PASS][33] -> [DMESG-FAIL][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-y/igt@i915_selftest@live_gem_contexts.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-icl-y/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-8809g: [PASS][35] -> [DMESG-FAIL][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-8809g/igt@i915_selftest@live_gem_contexts.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-kbl-8809g/igt@i915_selftest@live_gem_contexts.html
- fi-glk-dsi: NOTRUN -> [DMESG-FAIL][37]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-glk-dsi/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-peppy: [PASS][38] -> [DMESG-FAIL][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
- fi-tgl-y: [PASS][40] -> [DMESG-FAIL][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-tgl-y/igt@i915_selftest@live_gem_contexts.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-tgl-y/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770r: [PASS][42] -> [DMESG-FAIL][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
- fi-icl-u3: [PASS][44] -> [DMESG-FAIL][45]
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-u3/igt@i915_selftest@live_gem_contexts.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-icl-u3/igt@i915_selftest@live_gem_contexts.html
- fi-kbl-x1275: [PASS][46] -> [DMESG-FAIL][47]
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-kbl-x1275/igt@i915_selftest@live_gem_contexts.html
- fi-skl-6700k2: [PASS][48] -> [DMESG-FAIL][49]
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-skl-6700k2/igt@i915_selftest@live_gem_contexts.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-skl-6700k2/igt@i915_selftest@live_gem_contexts.html
- fi-icl-guc: [PASS][50] -> [DMESG-FAIL][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-icl-guc/igt@i915_selftest@live_gem_contexts.html
- fi-cfl-guc: NOTRUN -> [DMESG-FAIL][52]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live_gem_contexts:
- {fi-tgl-u}: [PASS][53] -> [DMESG-FAIL][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-tgl-u/igt@i915_selftest@live_gem_contexts.html
- {fi-ehl-1}: [PASS][55] -> [DMESG-FAIL][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-ehl-1/igt@i915_selftest@live_gem_contexts.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-ehl-1/igt@i915_selftest@live_gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_16225 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [PASS][57] -> [DMESG-FAIL][58] ([i915#563])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770/igt@i915_selftest@live_blt.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-bsw-nick: [PASS][59] -> [INCOMPLETE][60] ([i915#392])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
- fi-bsw-kefka: [PASS][61] -> [INCOMPLETE][62] ([i915#392])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
- fi-bsw-n3050: [PASS][63] -> [INCOMPLETE][64] ([i915#392])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: [PASS][65] -> [FAIL][66] ([i915#217])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
#### Possible fixes ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-cfl-guc: [INCOMPLETE][67] ([i915#505] / [i915#671]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_blt:
- fi-hsw-4770r: [DMESG-FAIL][69] ([i915#553] / [i915#725]) -> [PASS][70]
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770r/igt@i915_selftest@live_blt.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/fi-hsw-4770r/igt@i915_selftest@live_blt.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
[i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
[i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
[i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (50 -> 44)
------------------------------
Additional (2): fi-glk-dsi fi-ilk-650
Missing (8): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7799 -> Patchwork_16225
CI-20190529: 20190529
CI_DRM_7799: 0f8a46a25a7781ef6ede604c9cb50f82cfb5e960 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5377: 1e6cb3e75925cf623df04f78430ae9299632ec3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16225: dd9d5619b95bd1a232a5b21e34153cf91f1428c4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
dd9d5619b95b drm/i915/gt: Poison GTT scratch pages
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16225/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (2 preceding siblings ...)
2020-01-23 8:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev3) Patchwork
@ 2020-01-23 8:51 ` Chris Wilson
2020-01-23 9:38 ` Matthew Auld
2020-01-23 9:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev4) Patchwork
` (5 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 8:51 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 43 ++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gtt.c | 19 ++++++++
2 files changed, 56 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 7fc46861a54d..c93fb0d8c597 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1575,7 +1575,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
- const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
+ const u32 GPR0 = engine->mmio_base + 0x600;
const u32 result = 0x100;
struct i915_request *rq;
struct i915_vma *vma;
@@ -1597,19 +1597,19 @@ static int read_from_scratch(struct i915_gem_context *ctx,
memset(cmd, POISON_INUSE, PAGE_SIZE);
if (INTEL_GEN(i915) >= 8) {
*cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
*cmd++ = 0;
} else {
*cmd++ = MI_LOAD_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
}
*cmd = MI_BATCH_BUFFER_END;
@@ -1686,6 +1686,23 @@ static int read_from_scratch(struct i915_gem_context *ctx,
return err;
}
+static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
+{
+ struct page *page = ctx_vm(ctx)->scratch[0].base.page;
+ u32 *vaddr;
+ int err = 0;
+
+ vaddr = kmap(page);
+ memcpy(out, vaddr, sizeof(*out));
+ if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
+ pr_err("Inconsistent initial state of scratch page!\n");
+ err = -EINVAL;
+ }
+ kunmap(page);
+
+ return err;
+}
+
static int igt_vm_isolation(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1696,6 +1713,7 @@ static int igt_vm_isolation(void *arg)
I915_RND_STATE(prng);
struct file *file;
u64 vm_total;
+ u32 expected;
int err;
if (INTEL_GEN(i915) < 7)
@@ -1720,12 +1738,21 @@ static int igt_vm_isolation(void *arg)
goto out_file;
}
+ /* Read the initial state of the scratch page */
+ err = check_scratch_page(ctx_a, &expected);
+ if (err)
+ goto out_file;
+
ctx_b = live_context(i915, file);
if (IS_ERR(ctx_b)) {
err = PTR_ERR(ctx_b);
goto out_file;
}
+ err = check_scratch_page(ctx_b, &expected);
+ if (err)
+ goto out_file;
+
/* We can only test vm isolation, if the vm are distinct */
if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
@@ -1743,6 +1770,10 @@ static int igt_vm_isolation(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
+ /* not all engines have their own GPR! */
+ if (INTEL_GEN(i915) < 9 && engine->class != RENDER_CLASS)
+ continue;
+
while (!__igt_timeout(end_time, NULL)) {
u32 value = 0xc5c5c5c5;
u64 offset;
@@ -1760,7 +1791,7 @@ static int igt_vm_isolation(void *arg)
if (err)
goto out_file;
- if (value) {
+ if (value != expected) {
pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
engine->name, value,
upper_32_bits(offset),
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..804da478d8f9 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,14 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ kunmap_atomic(memset(kmap_atomic(page), POISON_FREE, size));
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +339,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages
2020-01-23 8:51 ` [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
@ 2020-01-23 9:38 ` Matthew Auld
2020-01-23 9:55 ` Chris Wilson
0 siblings, 1 reply; 16+ messages in thread
From: Matthew Auld @ 2020-01-23 9:38 UTC (permalink / raw)
To: Chris Wilson; +Cc: Intel Graphics Development
On Thu, 23 Jan 2020 at 08:51, Chris Wilson <chris@chris-wilson.co.uk> wrote:
>
> Using a clear page for scratch means that we have relatively benign
> errors in case it is accidentally used, but that can be rather too
> benign for debugging. If we poison the scratch, ideally it quickly
> results in an obvious error.
>
> Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
[snip]
>
> +static void poison_scratch_page(struct page *page, unsigned long size)
> +{
> + if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + return;
> +
> + kunmap_atomic(memset(kmap_atomic(page), POISON_FREE, size));
kmap works for !order-zero?
> +}
> +
> int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> {
> unsigned long size;
> @@ -331,6 +339,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> if (unlikely(!page))
> goto skip;
>
> + /*
> + * Use a non-zero scratch page for debugging.
> + *
> + * We want a value that should be reasonably obvious
> + * to spot in the error state, while also causing a GPU hang
> + * if executed. We prefer using a clear page in production, so
> + * should it ever be accidentally used, the effect should be
> + * fairly benign.
> + */
> + poison_scratch_page(page, size);
> +
> addr = dma_map_page_attrs(vm->dma,
> page, 0, size,
> PCI_DMA_BIDIRECTIONAL,
> --
> 2.25.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev4)
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (3 preceding siblings ...)
2020-01-23 8:51 ` [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
@ 2020-01-23 9:50 ` Patchwork
2020-01-23 10:12 ` [Intel-gfx] [PATCH v2] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (4 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-23 9:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Poison GTT scratch pages (rev4)
URL : https://patchwork.freedesktop.org/series/72423/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7799 -> Patchwork_16226
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16226 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16226, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16226:
### IGT changes ###
#### Possible regressions ####
* igt@gem_exec_parallel@fds:
- fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-peppy/igt@gem_exec_parallel@fds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-hsw-peppy/igt@gem_exec_parallel@fds.html
* igt@i915_selftest@live_gem_contexts:
- fi-ivb-3770: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-ivb-3770/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770: [PASS][5] -> [DMESG-FAIL][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770r: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
- fi-byt-n2820: [PASS][9] -> [DMESG-FAIL][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_16226 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@fds:
- fi-byt-n2820: [PASS][11] -> [TIMEOUT][12] ([fdo#112271])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-byt-n2820/igt@gem_exec_parallel@fds.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-byt-n2820/igt@gem_exec_parallel@fds.html
* igt@i915_selftest@live_active:
- fi-icl-y: [PASS][13] -> [DMESG-FAIL][14] ([i915#765])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-icl-y/igt@i915_selftest@live_active.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-icl-y/igt@i915_selftest@live_active.html
* igt@i915_selftest@live_blt:
- fi-ivb-3770: [PASS][15] -> [DMESG-FAIL][16] ([i915#725])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-ivb-3770/igt@i915_selftest@live_blt.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-ivb-3770/igt@i915_selftest@live_blt.html
- fi-hsw-4770: [PASS][17] -> [DMESG-FAIL][18] ([i915#553])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-hsw-4770/igt@i915_selftest@live_blt.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [PASS][19] -> [INCOMPLETE][20] ([CI#80] / [i915#424])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-bsw-nick: [PASS][21] -> [INCOMPLETE][22] ([i915#392])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-bsw-nick/igt@i915_selftest@live_gem_contexts.html
- fi-bsw-kefka: [PASS][23] -> [INCOMPLETE][24] ([i915#392])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-bsw-kefka/igt@i915_selftest@live_gem_contexts.html
- fi-bsw-n3050: [PASS][25] -> [INCOMPLETE][26] ([i915#392])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-bsw-n3050/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-cfl-guc: [INCOMPLETE][27] ([i915#505] / [i915#671]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-cfl-guc/igt@i915_module_load@reload-with-fault-injection.html
#### Warnings ####
* igt@gem_exec_parallel@contexts:
- fi-byt-n2820: [FAIL][29] -> [TIMEOUT][30] ([fdo#112271])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7799/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/fi-byt-n2820/igt@gem_exec_parallel@contexts.html
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
[i915#392]: https://gitlab.freedesktop.org/drm/intel/issues/392
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#505]: https://gitlab.freedesktop.org/drm/intel/issues/505
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#671]: https://gitlab.freedesktop.org/drm/intel/issues/671
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
Participating hosts (50 -> 44)
------------------------------
Additional (1): fi-ilk-650
Missing (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7799 -> Patchwork_16226
CI-20190529: 20190529
CI_DRM_7799: 0f8a46a25a7781ef6ede604c9cb50f82cfb5e960 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5377: 1e6cb3e75925cf623df04f78430ae9299632ec3f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16226: f03c220f7aa5c54ec5037e609756d9ad37aa144b @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f03c220f7aa5 drm/i915/gt: Poison GTT scratch pages
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16226/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages
2020-01-23 9:38 ` Matthew Auld
@ 2020-01-23 9:55 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 9:55 UTC (permalink / raw)
To: Matthew Auld; +Cc: Intel Graphics Development
Quoting Matthew Auld (2020-01-23 09:38:02)
> On Thu, 23 Jan 2020 at 08:51, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> >
> > Using a clear page for scratch means that we have relatively benign
> > errors in case it is accidentally used, but that can be rather too
> > benign for debugging. If we poison the scratch, ideally it quickly
> > results in an obvious error.
> >
> > Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> [snip]
>
> >
> > +static void poison_scratch_page(struct page *page, unsigned long size)
> > +{
> > + if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> > + return;
> > +
> > + kunmap_atomic(memset(kmap_atomic(page), POISON_FREE, size));
>
> kmap works for !order-zero?
Definitely works if not highmem :)
But needs a page by page approach just in case, fine.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v2] drm/i915/gt: Poison GTT scratch pages
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (4 preceding siblings ...)
2020-01-23 9:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev4) Patchwork
@ 2020-01-23 10:12 ` Chris Wilson
2020-01-23 11:18 ` [Intel-gfx] [PATCH v3] " Chris Wilson
` (3 subsequent siblings)
9 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 10:12 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
v2: Set each page individual just in case we are using highmem for our
scratch page.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 48 ++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gtt.c | 30 ++++++++++++
2 files changed, 72 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 7fc46861a54d..e23280dd8a98 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1575,7 +1575,7 @@ static int read_from_scratch(struct i915_gem_context *ctx,
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
- const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
+ const u32 GPR0 = engine->mmio_base + 0x600;
const u32 result = 0x100;
struct i915_request *rq;
struct i915_vma *vma;
@@ -1597,19 +1597,19 @@ static int read_from_scratch(struct i915_gem_context *ctx,
memset(cmd, POISON_INUSE, PAGE_SIZE);
if (INTEL_GEN(i915) >= 8) {
*cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
*cmd++ = 0;
} else {
*cmd++ = MI_LOAD_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
}
*cmd = MI_BATCH_BUFFER_END;
@@ -1686,6 +1686,28 @@ static int read_from_scratch(struct i915_gem_context *ctx,
return err;
}
+static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
+{
+ struct page *page = ctx_vm(ctx)->scratch[0].base.page;
+ u32 *vaddr;
+ int err = 0;
+
+ if (!page) {
+ pr_err("No scratch page!\n");
+ return -EINVAL;
+ }
+
+ vaddr = kmap(page);
+ memcpy(out, vaddr, sizeof(*out));
+ if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
+ pr_err("Inconsistent initial state of scratch page!\n");
+ err = -EINVAL;
+ }
+ kunmap(page);
+
+ return err;
+}
+
static int igt_vm_isolation(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1696,6 +1718,7 @@ static int igt_vm_isolation(void *arg)
I915_RND_STATE(prng);
struct file *file;
u64 vm_total;
+ u32 expected;
int err;
if (INTEL_GEN(i915) < 7)
@@ -1720,12 +1743,21 @@ static int igt_vm_isolation(void *arg)
goto out_file;
}
+ /* Read the initial state of the scratch page */
+ err = check_scratch_page(ctx_a, &expected);
+ if (err)
+ goto out_file;
+
ctx_b = live_context(i915, file);
if (IS_ERR(ctx_b)) {
err = PTR_ERR(ctx_b);
goto out_file;
}
+ err = check_scratch_page(ctx_b, &expected);
+ if (err)
+ goto out_file;
+
/* We can only test vm isolation, if the vm are distinct */
if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
@@ -1743,6 +1775,10 @@ static int igt_vm_isolation(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
+ /* Not all engines have their own GPR! */
+ if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
+ continue;
+
while (!__igt_timeout(end_time, NULL)) {
u32 value = 0xc5c5c5c5;
u64 offset;
@@ -1760,7 +1796,7 @@ static int igt_vm_isolation(void *arg)
if (err)
goto out_file;
- if (value) {
+ if (value != expected) {
pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
engine->name, value,
upper_32_bits(offset),
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..bb9a6e638175 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,25 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+ do {
+ void *vaddr;
+
+ vaddr = kmap(page);
+ memset(vaddr, POISON_FREE, PAGE_SIZE);
+ kunmap(page);
+
+ page = pfn_to_page(page_to_pfn(page) + 1);
+ size -= PAGE_SIZE;
+ } while (size);
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +350,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v3] drm/i915/gt: Poison GTT scratch pages
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (5 preceding siblings ...)
2020-01-23 10:12 ` [Intel-gfx] [PATCH v2] drm/i915/gt: Poison GTT scratch pages Chris Wilson
@ 2020-01-23 11:18 ` Chris Wilson
2020-01-23 11:56 ` Mika Kuoppala
2020-01-23 14:47 ` Chris Wilson
` (2 subsequent siblings)
9 siblings, 1 reply; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 11:18 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
v2: Set each page individually just in case we are using highmem for our
scratch page.
v3: Pick a new scratch register as MI_STORE_REGISTER_MEM does not work
with GPR0 on gen7, unbelievably.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 51 ++++++++++++++++---
drivers/gpu/drm/i915/gt/intel_gtt.c | 30 +++++++++++
2 files changed, 75 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 7fc46861a54d..00a56a8b309a 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1575,7 +1575,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
- const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
const u32 result = 0x100;
struct i915_request *rq;
struct i915_vma *vma;
@@ -1596,20 +1595,24 @@ static int read_from_scratch(struct i915_gem_context *ctx,
memset(cmd, POISON_INUSE, PAGE_SIZE);
if (INTEL_GEN(i915) >= 8) {
+ const u32 GPR0 = engine->mmio_base + 0x600;
+
*cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
*cmd++ = 0;
} else {
+ const u32 reg = engine->mmio_base + 0x420;
+
*cmd++ = MI_LOAD_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = reg;
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = reg;
*cmd++ = result;
}
*cmd = MI_BATCH_BUFFER_END;
@@ -1686,6 +1689,28 @@ static int read_from_scratch(struct i915_gem_context *ctx,
return err;
}
+static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
+{
+ struct page *page = ctx_vm(ctx)->scratch[0].base.page;
+ u32 *vaddr;
+ int err = 0;
+
+ if (!page) {
+ pr_err("No scratch page!\n");
+ return -EINVAL;
+ }
+
+ vaddr = kmap(page);
+ memcpy(out, vaddr, sizeof(*out));
+ if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
+ pr_err("Inconsistent initial state of scratch page!\n");
+ err = -EINVAL;
+ }
+ kunmap(page);
+
+ return err;
+}
+
static int igt_vm_isolation(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1696,6 +1721,7 @@ static int igt_vm_isolation(void *arg)
I915_RND_STATE(prng);
struct file *file;
u64 vm_total;
+ u32 expected;
int err;
if (INTEL_GEN(i915) < 7)
@@ -1720,12 +1746,21 @@ static int igt_vm_isolation(void *arg)
goto out_file;
}
+ /* Read the initial state of the scratch page */
+ err = check_scratch_page(ctx_a, &expected);
+ if (err)
+ goto out_file;
+
ctx_b = live_context(i915, file);
if (IS_ERR(ctx_b)) {
err = PTR_ERR(ctx_b);
goto out_file;
}
+ err = check_scratch_page(ctx_b, &expected);
+ if (err)
+ goto out_file;
+
/* We can only test vm isolation, if the vm are distinct */
if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
@@ -1743,6 +1778,10 @@ static int igt_vm_isolation(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
+ /* Not all engines have their own GPR! */
+ if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
+ continue;
+
while (!__igt_timeout(end_time, NULL)) {
u32 value = 0xc5c5c5c5;
u64 offset;
@@ -1760,7 +1799,7 @@ static int igt_vm_isolation(void *arg)
if (err)
goto out_file;
- if (value) {
+ if (value != expected) {
pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
engine->name, value,
upper_32_bits(offset),
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..bb9a6e638175 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,25 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+ do {
+ void *vaddr;
+
+ vaddr = kmap(page);
+ memset(vaddr, POISON_FREE, PAGE_SIZE);
+ kunmap(page);
+
+ page = pfn_to_page(page_to_pfn(page) + 1);
+ size -= PAGE_SIZE;
+ } while (size);
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +350,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/gt: Poison GTT scratch pages
2020-01-23 11:18 ` [Intel-gfx] [PATCH v3] " Chris Wilson
@ 2020-01-23 11:56 ` Mika Kuoppala
2020-01-23 12:12 ` Chris Wilson
0 siblings, 1 reply; 16+ messages in thread
From: Mika Kuoppala @ 2020-01-23 11:56 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Using a clear page for scratch means that we have relatively benign
> errors in case it is accidentally used, but that can be rather too
> benign for debugging. If we poison the scratch, ideally it quickly
> results in an obvious error.
>
> v2: Set each page individually just in case we are using highmem for our
> scratch page.
> v3: Pick a new scratch register as MI_STORE_REGISTER_MEM does not work
> with GPR0 on gen7, unbelievably.
>
> Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
I have a faint memory...aeons ago..might have.
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Matthew Auld <matthew.william.auld@gmail.com>
> ---
> .../drm/i915/gem/selftests/i915_gem_context.c | 51 ++++++++++++++++---
> drivers/gpu/drm/i915/gt/intel_gtt.c | 30 +++++++++++
> 2 files changed, 75 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> index 7fc46861a54d..00a56a8b309a 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> @@ -1575,7 +1575,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> struct drm_i915_private *i915 = ctx->i915;
> struct drm_i915_gem_object *obj;
> struct i915_address_space *vm;
> - const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
> const u32 result = 0x100;
> struct i915_request *rq;
> struct i915_vma *vma;
> @@ -1596,20 +1595,24 @@ static int read_from_scratch(struct i915_gem_context *ctx,
>
> memset(cmd, POISON_INUSE, PAGE_SIZE);
> if (INTEL_GEN(i915) >= 8) {
> + const u32 GPR0 = engine->mmio_base + 0x600;
> +
> *cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
> - *cmd++ = RCS_GPR0;
> + *cmd++ = GPR0;
> *cmd++ = lower_32_bits(offset);
> *cmd++ = upper_32_bits(offset);
> *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> - *cmd++ = RCS_GPR0;
> + *cmd++ = GPR0;
> *cmd++ = result;
> *cmd++ = 0;
> } else {
> + const u32 reg = engine->mmio_base + 0x420;
3d prim end offset? Well should not matter for this selftest
but did you check 0xA198?
How have 0x600 been been working in gen7 previously?
-Mika
> +
> *cmd++ = MI_LOAD_REGISTER_MEM;
> - *cmd++ = RCS_GPR0;
> + *cmd++ = reg;
> *cmd++ = offset;
> *cmd++ = MI_STORE_REGISTER_MEM;
> - *cmd++ = RCS_GPR0;
> + *cmd++ = reg;
> *cmd++ = result;
> }
> *cmd = MI_BATCH_BUFFER_END;
> @@ -1686,6 +1689,28 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> return err;
> }
>
> +static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
> +{
> + struct page *page = ctx_vm(ctx)->scratch[0].base.page;
> + u32 *vaddr;
> + int err = 0;
> +
> + if (!page) {
> + pr_err("No scratch page!\n");
> + return -EINVAL;
> + }
> +
> + vaddr = kmap(page);
> + memcpy(out, vaddr, sizeof(*out));
> + if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
> + pr_err("Inconsistent initial state of scratch page!\n");
> + err = -EINVAL;
> + }
> + kunmap(page);
> +
> + return err;
> +}
> +
> static int igt_vm_isolation(void *arg)
> {
> struct drm_i915_private *i915 = arg;
> @@ -1696,6 +1721,7 @@ static int igt_vm_isolation(void *arg)
> I915_RND_STATE(prng);
> struct file *file;
> u64 vm_total;
> + u32 expected;
> int err;
>
> if (INTEL_GEN(i915) < 7)
> @@ -1720,12 +1746,21 @@ static int igt_vm_isolation(void *arg)
> goto out_file;
> }
>
> + /* Read the initial state of the scratch page */
> + err = check_scratch_page(ctx_a, &expected);
> + if (err)
> + goto out_file;
> +
> ctx_b = live_context(i915, file);
> if (IS_ERR(ctx_b)) {
> err = PTR_ERR(ctx_b);
> goto out_file;
> }
>
> + err = check_scratch_page(ctx_b, &expected);
> + if (err)
> + goto out_file;
> +
> /* We can only test vm isolation, if the vm are distinct */
> if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
> goto out_file;
> @@ -1743,6 +1778,10 @@ static int igt_vm_isolation(void *arg)
> if (!intel_engine_can_store_dword(engine))
> continue;
>
> + /* Not all engines have their own GPR! */
> + if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
> + continue;
> +
> while (!__igt_timeout(end_time, NULL)) {
> u32 value = 0xc5c5c5c5;
> u64 offset;
> @@ -1760,7 +1799,7 @@ static int igt_vm_isolation(void *arg)
> if (err)
> goto out_file;
>
> - if (value) {
> + if (value != expected) {
> pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
> engine->name, value,
> upper_32_bits(offset),
> diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
> index 45d8e0019a8e..bb9a6e638175 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gtt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
> @@ -299,6 +299,25 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
> kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
> }
>
> +static void poison_scratch_page(struct page *page, unsigned long size)
> +{
> + if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
> + return;
> +
> + GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
> +
> + do {
> + void *vaddr;
> +
> + vaddr = kmap(page);
> + memset(vaddr, POISON_FREE, PAGE_SIZE);
> + kunmap(page);
> +
> + page = pfn_to_page(page_to_pfn(page) + 1);
> + size -= PAGE_SIZE;
> + } while (size);
> +}
> +
> int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> {
> unsigned long size;
> @@ -331,6 +350,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
> if (unlikely(!page))
> goto skip;
>
> + /*
> + * Use a non-zero scratch page for debugging.
> + *
> + * We want a value that should be reasonably obvious
> + * to spot in the error state, while also causing a GPU hang
> + * if executed. We prefer using a clear page in production, so
> + * should it ever be accidentally used, the effect should be
> + * fairly benign.
> + */
> + poison_scratch_page(page, size);
> +
> addr = dma_map_page_attrs(vm->dma,
> page, 0, size,
> PCI_DMA_BIDIRECTIONAL,
> --
> 2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [Intel-gfx] [PATCH v3] drm/i915/gt: Poison GTT scratch pages
2020-01-23 11:56 ` Mika Kuoppala
@ 2020-01-23 12:12 ` Chris Wilson
0 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 12:12 UTC (permalink / raw)
To: Mika Kuoppala, intel-gfx
Quoting Mika Kuoppala (2020-01-23 11:56:20)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Using a clear page for scratch means that we have relatively benign
> > errors in case it is accidentally used, but that can be rather too
> > benign for debugging. If we poison the scratch, ideally it quickly
> > results in an obvious error.
> >
> > v2: Set each page individually just in case we are using highmem for our
> > scratch page.
> > v3: Pick a new scratch register as MI_STORE_REGISTER_MEM does not work
> > with GPR0 on gen7, unbelievably.
> >
> > Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>
> I have a faint memory...aeons ago..might have.
>
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > Cc: Matthew Auld <matthew.william.auld@gmail.com>
> > ---
> > .../drm/i915/gem/selftests/i915_gem_context.c | 51 ++++++++++++++++---
> > drivers/gpu/drm/i915/gt/intel_gtt.c | 30 +++++++++++
> > 2 files changed, 75 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > index 7fc46861a54d..00a56a8b309a 100644
> > --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
> > @@ -1575,7 +1575,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> > struct drm_i915_private *i915 = ctx->i915;
> > struct drm_i915_gem_object *obj;
> > struct i915_address_space *vm;
> > - const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
> > const u32 result = 0x100;
> > struct i915_request *rq;
> > struct i915_vma *vma;
> > @@ -1596,20 +1595,24 @@ static int read_from_scratch(struct i915_gem_context *ctx,
> >
> > memset(cmd, POISON_INUSE, PAGE_SIZE);
> > if (INTEL_GEN(i915) >= 8) {
> > + const u32 GPR0 = engine->mmio_base + 0x600;
> > +
> > *cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
> > - *cmd++ = RCS_GPR0;
> > + *cmd++ = GPR0;
> > *cmd++ = lower_32_bits(offset);
> > *cmd++ = upper_32_bits(offset);
> > *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
> > - *cmd++ = RCS_GPR0;
> > + *cmd++ = GPR0;
> > *cmd++ = result;
> > *cmd++ = 0;
> > } else {
> > + const u32 reg = engine->mmio_base + 0x420;
>
> 3d prim end offset? Well should not matter for this selftest
> but did you check 0xA198?
Forcewake is handled by MI from the engines, if I understood you
correctly. First thought it was indeed just that that !rcs engines
couldn't read from the rcs, so limited it to just rcs and still it
failed.
>
> How have 0x600 been been working in gen7 previously?
No idea. Tried to use I915_DISPATCH_SECURE (fixing up the batch vma to
be in the GGTT) and it still returned 0. Even after poisoning the GPR
with MI_LOAD_REG_IMM. Ergo it had to be the read of GPR that was being
scrubbed (since we poison the destination to verify the write lands).
But 3DPRIM_END_OFFSET worked (I suspected it might since it's part of
the indirect glDrawArrays), so I assume it's just some more of the
wonderfully askew validation on gen7.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v3] drm/i915/gt: Poison GTT scratch pages
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (6 preceding siblings ...)
2020-01-23 11:18 ` [Intel-gfx] [PATCH v3] " Chris Wilson
@ 2020-01-23 14:47 ` Chris Wilson
2020-01-23 14:53 ` [Intel-gfx] [PATCH v4] " Chris Wilson
2020-01-24 0:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev8) Patchwork
9 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 14:47 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
v2: Set each page individually just in case we are using highmem for our
scratch page.
v3: Pick a new scratch register as MI_STORE_REGISTER_MEM does not work
with GPR0 on gen7, unbelievably.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 62 +++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 30 +++++++++
2 files changed, 86 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 7fc46861a54d..cae3c0004a40 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1575,7 +1575,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
- const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
const u32 result = 0x100;
struct i915_request *rq;
struct i915_vma *vma;
@@ -1596,20 +1595,24 @@ static int read_from_scratch(struct i915_gem_context *ctx,
memset(cmd, POISON_INUSE, PAGE_SIZE);
if (INTEL_GEN(i915) >= 8) {
+ const u32 GPR0 = engine->mmio_base + 0x600;
+
*cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
*cmd++ = 0;
} else {
+ const u32 reg = engine->mmio_base + 0x420;
+
*cmd++ = MI_LOAD_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = reg;
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = reg;
*cmd++ = result;
}
*cmd = MI_BATCH_BUFFER_END;
@@ -1686,6 +1689,39 @@ static int read_from_scratch(struct i915_gem_context *ctx,
return err;
}
+static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
+{
+ struct i915_address_space *vm;
+ struct page *page;
+ u32 *vaddr;
+ int err = 0;
+
+ vm = ctx_vm(ctx);
+ if (!vm)
+ return -ENODEV;
+
+ page = vm->scratch[0].base.page;
+ if (!page) {
+ pr_err("No scratch page!\n");
+ return -EINVAL;
+ }
+
+ vaddr = kmap(page);
+ if (vaddr) {
+ pr_err("No (mappable) scratch page!\n");
+ return -EINVAL;
+ }
+
+ memcpy(out, vaddr, sizeof(*out));
+ if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
+ pr_err("Inconsistent initial state of scratch page!\n");
+ err = -EINVAL;
+ }
+ kunmap(page);
+
+ return err;
+}
+
static int igt_vm_isolation(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1696,6 +1732,7 @@ static int igt_vm_isolation(void *arg)
I915_RND_STATE(prng);
struct file *file;
u64 vm_total;
+ u32 expected;
int err;
if (INTEL_GEN(i915) < 7)
@@ -1730,6 +1767,15 @@ static int igt_vm_isolation(void *arg)
if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
+ /* Read the initial state of the scratch page */
+ err = check_scratch_page(ctx_a, &expected);
+ if (err)
+ goto out_file;
+
+ err = check_scratch_page(ctx_b, &expected);
+ if (err)
+ goto out_file;
+
vm_total = ctx_vm(ctx_a)->total;
GEM_BUG_ON(ctx_vm(ctx_b)->total != vm_total);
vm_total -= I915_GTT_PAGE_SIZE;
@@ -1743,6 +1789,10 @@ static int igt_vm_isolation(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
+ /* Not all engines have their own GPR! */
+ if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
+ continue;
+
while (!__igt_timeout(end_time, NULL)) {
u32 value = 0xc5c5c5c5;
u64 offset;
@@ -1760,7 +1810,7 @@ static int igt_vm_isolation(void *arg)
if (err)
goto out_file;
- if (value) {
+ if (value != expected) {
pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
engine->name, value,
upper_32_bits(offset),
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..bb9a6e638175 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,25 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+ do {
+ void *vaddr;
+
+ vaddr = kmap(page);
+ memset(vaddr, POISON_FREE, PAGE_SIZE);
+ kunmap(page);
+
+ page = pfn_to_page(page_to_pfn(page) + 1);
+ size -= PAGE_SIZE;
+ } while (size);
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +350,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH v4] drm/i915/gt: Poison GTT scratch pages
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (7 preceding siblings ...)
2020-01-23 14:47 ` Chris Wilson
@ 2020-01-23 14:53 ` Chris Wilson
2020-01-24 0:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev8) Patchwork
9 siblings, 0 replies; 16+ messages in thread
From: Chris Wilson @ 2020-01-23 14:53 UTC (permalink / raw)
To: intel-gfx
Using a clear page for scratch means that we have relatively benign
errors in case it is accidentally used, but that can be rather too
benign for debugging. If we poison the scratch, ideally it quickly
results in an obvious error.
v2: Set each page individually just in case we are using highmem for our
scratch page.
v3: Pick a new scratch register as MI_STORE_REGISTER_MEM does not work
with GPR0 on gen7, unbelievably.
Suggested-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
---
.../drm/i915/gem/selftests/i915_gem_context.c | 62 +++++++++++++++++--
drivers/gpu/drm/i915/gt/intel_gtt.c | 30 +++++++++
2 files changed, 86 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index 7fc46861a54d..d61f9934a244 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -1575,7 +1575,6 @@ static int read_from_scratch(struct i915_gem_context *ctx,
struct drm_i915_private *i915 = ctx->i915;
struct drm_i915_gem_object *obj;
struct i915_address_space *vm;
- const u32 RCS_GPR0 = 0x2600; /* not all engines have their own GPR! */
const u32 result = 0x100;
struct i915_request *rq;
struct i915_vma *vma;
@@ -1596,20 +1595,24 @@ static int read_from_scratch(struct i915_gem_context *ctx,
memset(cmd, POISON_INUSE, PAGE_SIZE);
if (INTEL_GEN(i915) >= 8) {
+ const u32 GPR0 = engine->mmio_base + 0x600;
+
*cmd++ = MI_LOAD_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = lower_32_bits(offset);
*cmd++ = upper_32_bits(offset);
*cmd++ = MI_STORE_REGISTER_MEM_GEN8;
- *cmd++ = RCS_GPR0;
+ *cmd++ = GPR0;
*cmd++ = result;
*cmd++ = 0;
} else {
+ const u32 reg = engine->mmio_base + 0x420;
+
*cmd++ = MI_LOAD_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = reg;
*cmd++ = offset;
*cmd++ = MI_STORE_REGISTER_MEM;
- *cmd++ = RCS_GPR0;
+ *cmd++ = reg;
*cmd++ = result;
}
*cmd = MI_BATCH_BUFFER_END;
@@ -1686,6 +1689,39 @@ static int read_from_scratch(struct i915_gem_context *ctx,
return err;
}
+static int check_scratch_page(struct i915_gem_context *ctx, u32 *out)
+{
+ struct i915_address_space *vm;
+ struct page *page;
+ u32 *vaddr;
+ int err = 0;
+
+ vm = ctx_vm(ctx);
+ if (!vm)
+ return -ENODEV;
+
+ page = vm->scratch[0].base.page;
+ if (!page) {
+ pr_err("No scratch page!\n");
+ return -EINVAL;
+ }
+
+ vaddr = kmap(page);
+ if (!vaddr) {
+ pr_err("No (mappable) scratch page!\n");
+ return -EINVAL;
+ }
+
+ memcpy(out, vaddr, sizeof(*out));
+ if (memchr_inv(vaddr, *out, PAGE_SIZE)) {
+ pr_err("Inconsistent initial state of scratch page!\n");
+ err = -EINVAL;
+ }
+ kunmap(page);
+
+ return err;
+}
+
static int igt_vm_isolation(void *arg)
{
struct drm_i915_private *i915 = arg;
@@ -1696,6 +1732,7 @@ static int igt_vm_isolation(void *arg)
I915_RND_STATE(prng);
struct file *file;
u64 vm_total;
+ u32 expected;
int err;
if (INTEL_GEN(i915) < 7)
@@ -1730,6 +1767,15 @@ static int igt_vm_isolation(void *arg)
if (ctx_vm(ctx_a) == ctx_vm(ctx_b))
goto out_file;
+ /* Read the initial state of the scratch page */
+ err = check_scratch_page(ctx_a, &expected);
+ if (err)
+ goto out_file;
+
+ err = check_scratch_page(ctx_b, &expected);
+ if (err)
+ goto out_file;
+
vm_total = ctx_vm(ctx_a)->total;
GEM_BUG_ON(ctx_vm(ctx_b)->total != vm_total);
vm_total -= I915_GTT_PAGE_SIZE;
@@ -1743,6 +1789,10 @@ static int igt_vm_isolation(void *arg)
if (!intel_engine_can_store_dword(engine))
continue;
+ /* Not all engines have their own GPR! */
+ if (INTEL_GEN(i915) < 8 && engine->class != RENDER_CLASS)
+ continue;
+
while (!__igt_timeout(end_time, NULL)) {
u32 value = 0xc5c5c5c5;
u64 offset;
@@ -1760,7 +1810,7 @@ static int igt_vm_isolation(void *arg)
if (err)
goto out_file;
- if (value) {
+ if (value != expected) {
pr_err("%s: Read %08x from scratch (offset 0x%08x_%08x), after %lu reads!\n",
engine->name, value,
upper_32_bits(offset),
diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.c b/drivers/gpu/drm/i915/gt/intel_gtt.c
index 45d8e0019a8e..bb9a6e638175 100644
--- a/drivers/gpu/drm/i915/gt/intel_gtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.c
@@ -299,6 +299,25 @@ fill_page_dma(const struct i915_page_dma *p, const u64 val, unsigned int count)
kunmap_atomic(memset64(kmap_atomic(p->page), val, count));
}
+static void poison_scratch_page(struct page *page, unsigned long size)
+{
+ if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
+ return;
+
+ GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
+
+ do {
+ void *vaddr;
+
+ vaddr = kmap(page);
+ memset(vaddr, POISON_FREE, PAGE_SIZE);
+ kunmap(page);
+
+ page = pfn_to_page(page_to_pfn(page) + 1);
+ size -= PAGE_SIZE;
+ } while (size);
+}
+
int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
{
unsigned long size;
@@ -331,6 +350,17 @@ int setup_scratch_page(struct i915_address_space *vm, gfp_t gfp)
if (unlikely(!page))
goto skip;
+ /*
+ * Use a non-zero scratch page for debugging.
+ *
+ * We want a value that should be reasonably obvious
+ * to spot in the error state, while also causing a GPU hang
+ * if executed. We prefer using a clear page in production, so
+ * should it ever be accidentally used, the effect should be
+ * fairly benign.
+ */
+ poison_scratch_page(page, size);
+
addr = dma_map_page_attrs(vm->dma,
page, 0, size,
PCI_DMA_BIDIRECTIONAL,
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev8)
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
` (8 preceding siblings ...)
2020-01-23 14:53 ` [Intel-gfx] [PATCH v4] " Chris Wilson
@ 2020-01-24 0:50 ` Patchwork
9 siblings, 0 replies; 16+ messages in thread
From: Patchwork @ 2020-01-24 0:50 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt: Poison GTT scratch pages (rev8)
URL : https://patchwork.freedesktop.org/series/72423/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7805 -> Patchwork_16239
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16239 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16239, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16239:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_gem_contexts:
- fi-hsw-4770: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-hsw-4770/igt@i915_selftest@live_gem_contexts.html
- fi-hsw-4770r: [PASS][3] -> [DMESG-FAIL][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-hsw-4770r/igt@i915_selftest@live_gem_contexts.html
Known issues
------------
Here are the changes found in Patchwork_16239 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_parallel@basic:
- fi-tgl-y: [PASS][5] -> [DMESG-WARN][6] ([CI#94] / [i915#402]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-tgl-y/igt@gem_exec_parallel@basic.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-tgl-y/igt@gem_exec_parallel@basic.html
* igt@gem_exec_parallel@fds:
- fi-hsw-peppy: [PASS][7] -> [INCOMPLETE][8] ([i915#694])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-hsw-peppy/igt@gem_exec_parallel@fds.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-hsw-peppy/igt@gem_exec_parallel@fds.html
#### Possible fixes ####
* igt@i915_module_load@reload-with-fault-injection:
- fi-kbl-x1275: [INCOMPLETE][9] ([i915#879]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-kbl-x1275/igt@i915_module_load@reload-with-fault-injection.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-kbl-x1275/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [INCOMPLETE][11] ([fdo#106070] / [i915#424]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
* igt@kms_prop_blob@basic:
- fi-tgl-y: [DMESG-WARN][13] ([CI#94] / [i915#402]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-tgl-y/igt@kms_prop_blob@basic.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-tgl-y/igt@kms_prop_blob@basic.html
#### Warnings ####
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111096] / [i915#323])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7805/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
[CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
[fdo#106070]: https://bugs.freedesktop.org/show_bug.cgi?id=106070
[fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
[fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
[i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#879]: https://gitlab.freedesktop.org/drm/intel/issues/879
Participating hosts (45 -> 44)
------------------------------
Additional (8): fi-kbl-7560u fi-bsw-n3050 fi-gdg-551 fi-skl-lmem fi-blb-e6850 fi-bsw-nick fi-skl-6600u fi-snb-2600
Missing (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-byt-n2820 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7805 -> Patchwork_16239
CI-20190529: 20190529
CI_DRM_7805: 447386749394e3b5cf296bfada83ed429fa5f1fe @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5382: 8dbe5ce61baa2d563d4dd7c56a018bb1e1077467 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16239: 9d845748883a06142161a6a8c74c0bc34577a3f9 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
9d845748883a drm/i915/gt: Poison GTT scratch pages
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16239/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2020-01-24 0:50 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-22 20:18 [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
2020-01-22 21:02 ` Chris Wilson
2020-01-23 7:40 ` Chris Wilson
2020-01-23 3:42 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev2) Patchwork
2020-01-23 8:25 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev3) Patchwork
2020-01-23 8:51 ` [Intel-gfx] [PATCH] drm/i915/gt: Poison GTT scratch pages Chris Wilson
2020-01-23 9:38 ` Matthew Auld
2020-01-23 9:55 ` Chris Wilson
2020-01-23 9:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev4) Patchwork
2020-01-23 10:12 ` [Intel-gfx] [PATCH v2] drm/i915/gt: Poison GTT scratch pages Chris Wilson
2020-01-23 11:18 ` [Intel-gfx] [PATCH v3] " Chris Wilson
2020-01-23 11:56 ` Mika Kuoppala
2020-01-23 12:12 ` Chris Wilson
2020-01-23 14:47 ` Chris Wilson
2020-01-23 14:53 ` [Intel-gfx] [PATCH v4] " Chris Wilson
2020-01-24 0:50 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt: Poison GTT scratch pages (rev8) Patchwork
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