* [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros.
@ 2020-01-28 7:14 Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 1/8] drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available Wambui Karuga
` (10 more replies)
0 siblings, 11 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
This series continues the conversion to the new drm logging macros
focused on the drm/i915/gt folder. This was done both manually and using
coccinelle.
Wambui Karuga (8):
drm/i915/gt: conversion to struct drm_device macros when struct
drm_i915_private is available.
drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c
drm/i915/reset: conversion to new drm logging macros in
gt/intel_reset.c
drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c
drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c
drm/i915/gt: convert to new logging macros in gt/intel_gt.c
drm/i915/ring: convert to new logging macros in
gt/intel_ring_submission.c
drm/i915/rps: move to new drm logging macros in gt/intel_rps.c
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 +--
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 63 +++++++++------
drivers/gpu/drm/i915/gt/intel_gt.c | 49 ++++++-----
drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +++---
drivers/gpu/drm/i915/gt/intel_rc6.c | 30 ++++---
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
drivers/gpu/drm/i915/gt/intel_reset.c | 48 ++++++-----
.../gpu/drm/i915/gt/intel_ring_submission.c | 36 +++++----
drivers/gpu/drm/i915/gt/intel_rps.c | 81 +++++++++----------
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 3 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
13 files changed, 196 insertions(+), 164 deletions(-)
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 1/8] drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available.
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 2/8] drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c Wambui Karuga
` (9 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
This patch is the conversion of printk based logging macros to the new
struct drm_device based logging macros in the drm/i915/gt folder by
running the following coccinelle script that matches when the struct
drm_i915_private device is present:
@rule1@
identifier fn, T;
@@
fn(...,struct drm_i915_private *T,...) {
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
@rule2@
identifier fn, T;
@@
fn(...) {
...
struct drm_i915_private *T = ...;
<+...
(
-DRM_INFO(
+drm_info(&T->drm,
...)
|
-DRM_ERROR(
+drm_err(&T->drm,
...)
|
-DRM_WARN(
+drm_warn(&T->drm,
...)
|
-DRM_DEBUG(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_KMS(
+drm_dbg_kms(&T->drm,
...)
|
-DRM_DEBUG_DRIVER(
+drm_dbg(&T->drm,
...)
|
-DRM_DEBUG_ATOMIC(
+drm_dbg_atomic(&T->drm,
...)
)
...+>
}
Checkpatch warnings were fixed manually.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
drivers/gpu/drm/i915/gt/intel_ggtt.c | 38 ++++++-----
drivers/gpu/drm/i915/gt/intel_gt.c | 6 +-
drivers/gpu/drm/i915/gt/intel_lrc.c | 2 +-
drivers/gpu/drm/i915/gt/intel_rc6.c | 30 +++++----
drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
.../gpu/drm/i915/gt/intel_ring_submission.c | 33 +++++-----
drivers/gpu/drm/i915/gt/intel_rps.c | 66 +++++++++----------
drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-
drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 3 +-
drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
11 files changed, 101 insertions(+), 92 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_user.c b/drivers/gpu/drm/i915/gt/intel_engine_user.c
index 848decee9066..c8a63e9c8f0d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_user.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_user.c
@@ -215,7 +215,7 @@ void intel_engines_driver_register(struct drm_i915_private *i915)
scnprintf(engine->name, sizeof(engine->name), "%s%u",
intel_engine_class_repr(engine->class),
engine->uabi_instance);
- DRM_DEBUG_DRIVER("renamed %s to %s\n", old, engine->name);
+ drm_dbg(&i915->drm, "renamed %s to %s\n", old, engine->name);
rb_link_node(&engine->uabi_node, prev, p);
rb_insert_color(&engine->uabi_node, &i915->uabi_engines);
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index 79096722ce16..d938cf8db460 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -791,13 +791,13 @@ static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size)
else
ggtt->gsm = ioremap_wc(phys_addr, size);
if (!ggtt->gsm) {
- DRM_ERROR("Failed to map the ggtt page table\n");
+ drm_err(&i915->drm, "Failed to map the ggtt page table\n");
return -ENOMEM;
}
ret = setup_scratch_page(&ggtt->vm, GFP_DMA32);
if (ret) {
- DRM_ERROR("Scratch setup failed\n");
+ drm_err(&i915->drm, "Scratch setup failed\n");
/* iounmap will also get called at remove, but meh */
iounmap(ggtt->gsm);
return ret;
@@ -857,7 +857,8 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
if (!err)
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
if (err)
- DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
+ drm_err(&i915->drm,
+ "Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
if (IS_CHERRYVIEW(i915))
@@ -1004,7 +1005,8 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
* just a coarse sanity check.
*/
if (ggtt->mappable_end < (64<<20) || ggtt->mappable_end > (512<<20)) {
- DRM_ERROR("Unknown GMADR size (%pa)\n", &ggtt->mappable_end);
+ drm_err(&i915->drm, "Unknown GMADR size (%pa)\n",
+ &ggtt->mappable_end);
return -ENXIO;
}
@@ -1012,7 +1014,8 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
if (!err)
err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
if (err)
- DRM_ERROR("Can't set DMA mask/consistent mask (%d)\n", err);
+ drm_err(&i915->drm,
+ "Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
size = gen6_get_total_gtt_size(snb_gmch_ctl);
@@ -1059,7 +1062,7 @@ static int i915_gmch_probe(struct i915_ggtt *ggtt)
ret = intel_gmch_probe(i915->bridge_dev, i915->drm.pdev, NULL);
if (!ret) {
- DRM_ERROR("failed to set up gmch\n");
+ drm_err(&i915->drm, "failed to set up gmch\n");
return -EIO;
}
@@ -1107,26 +1110,29 @@ static int ggtt_probe_hw(struct i915_ggtt *ggtt, struct intel_gt *gt)
return ret;
if ((ggtt->vm.total - 1) >> 32) {
- DRM_ERROR("We never expected a Global GTT with more than 32bits"
- " of address space! Found %lldM!\n",
- ggtt->vm.total >> 20);
+ drm_err(&i915->drm,
+ "We never expected a Global GTT with more than 32bits"
+ " of address space! Found %lldM!\n",
+ ggtt->vm.total >> 20);
ggtt->vm.total = 1ULL << 32;
ggtt->mappable_end =
min_t(u64, ggtt->mappable_end, ggtt->vm.total);
}
if (ggtt->mappable_end > ggtt->vm.total) {
- DRM_ERROR("mappable aperture extends past end of GGTT,"
- " aperture=%pa, total=%llx\n",
- &ggtt->mappable_end, ggtt->vm.total);
+ drm_err(&i915->drm,
+ "mappable aperture extends past end of GGTT,"
+ " aperture=%pa, total=%llx\n",
+ &ggtt->mappable_end, ggtt->vm.total);
ggtt->mappable_end = ggtt->vm.total;
}
/* GMADR is the PCI mmio aperture into the global GTT. */
- DRM_DEBUG_DRIVER("GGTT size = %lluM\n", ggtt->vm.total >> 20);
- DRM_DEBUG_DRIVER("GMADR size = %lluM\n", (u64)ggtt->mappable_end >> 20);
- DRM_DEBUG_DRIVER("DSM size = %lluM\n",
- (u64)resource_size(&intel_graphics_stolen_res) >> 20);
+ drm_dbg(&i915->drm, "GGTT size = %lluM\n", ggtt->vm.total >> 20);
+ drm_dbg(&i915->drm, "GMADR size = %lluM\n",
+ (u64)ggtt->mappable_end >> 20);
+ drm_dbg(&i915->drm, "DSM size = %lluM\n",
+ (u64)resource_size(&intel_graphics_stolen_res) >> 20);
return 0;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index da2b6e2ae692..a1ba0097117e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -106,7 +106,7 @@ int intel_gt_init_hw(struct intel_gt *gt)
ret = i915_ppgtt_init_hw(gt);
if (ret) {
- DRM_ERROR("Enabling PPGTT failed (%d)\n", ret);
+ drm_err(&i915->drm, "Enabling PPGTT failed (%d)\n", ret);
goto out;
}
@@ -168,7 +168,7 @@ intel_gt_clear_error_registers(struct intel_gt *gt,
* some errors might have become stuck,
* mask them.
*/
- DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir);
+ drm_dbg(&i915->drm, "EIR stuck: 0x%08x, masking\n", eir);
rmw_set(uncore, EMR, eir);
intel_uncore_write(uncore, GEN2_IIR,
I915_MASTER_ERROR_INTERRUPT);
@@ -335,7 +335,7 @@ static int intel_gt_init_scratch(struct intel_gt *gt, unsigned int size)
if (IS_ERR(obj))
obj = i915_gem_object_create_internal(i915, size);
if (IS_ERR(obj)) {
- DRM_ERROR("Failed to allocate scratch page\n");
+ drm_err(&i915->drm, "Failed to allocate scratch page\n");
return PTR_ERR(obj);
}
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index a13a8c4b65ab..5003c2e84786 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -4334,7 +4334,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
* because we only expect rare glitches but nothing
* critical to prevent us from using GPU
*/
- DRM_ERROR("WA batch buffer initialization failed\n");
+ drm_err(&i915->drm, "WA batch buffer initialization failed\n");
if (HAS_LOGICAL_RING_ELSQ(i915)) {
execlists->submit_reg = uncore->regs +
diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
index 01a99fdbb3c4..84b9853967fd 100644
--- a/drivers/gpu/drm/i915/gt/intel_rc6.c
+++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
@@ -248,16 +248,18 @@ static void gen6_rc6_enable(struct intel_rc6 *rc6)
ret = sandybridge_pcode_read(i915, GEN6_PCODE_READ_RC6VIDS,
&rc6vids, NULL);
if (IS_GEN(i915, 6) && ret) {
- DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
+ drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
} else if (IS_GEN(i915, 6) &&
(GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
- DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
- GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
+ drm_dbg(&i915->drm,
+ "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
+ GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
rc6vids &= 0xffff00;
rc6vids |= GEN6_ENCODE_RC6_VID(450);
ret = sandybridge_pcode_write(i915, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
if (ret)
- DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
+ drm_err(&i915->drm,
+ "Couldn't fix incorrect rc6 voltage\n");
}
}
@@ -307,7 +309,7 @@ static int vlv_rc6_init(struct intel_rc6 *rc6)
goto out;
}
- DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
+ drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
/*
* From the Gunit register HAS:
@@ -319,7 +321,8 @@ static int vlv_rc6_init(struct intel_rc6 *rc6)
*/
pctx = i915_gem_object_create_stolen(i915, pctx_size);
if (IS_ERR(pctx)) {
- DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
+ drm_dbg(&i915->drm,
+ "not enough stolen space for PCTX, disabling\n");
return PTR_ERR(pctx);
}
@@ -401,14 +404,14 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE);
rc_sw_target &= RC_SW_TARGET_STATE_MASK;
rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT;
- DRM_DEBUG_DRIVER("BIOS enabled RC states: "
+ drm_dbg(&i915->drm, "BIOS enabled RC states: "
"HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
rc_sw_target);
if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
- DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
+ drm_dbg(&i915->drm, "RC6 Base location not set properly.\n");
enable_rc6 = false;
}
@@ -420,7 +423,7 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
if (!(rc6_ctx_base >= i915->dsm_reserved.start &&
rc6_ctx_base + PAGE_SIZE < i915->dsm_reserved.end)) {
- DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
+ drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");
enable_rc6 = false;
}
@@ -428,24 +431,25 @@ static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
(intel_uncore_read(uncore, PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1 &&
(intel_uncore_read(uncore, PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1 &&
(intel_uncore_read(uncore, PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1)) {
- DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
+ drm_dbg(&i915->drm,
+ "Engine Idle wait time not set properly.\n");
enable_rc6 = false;
}
if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) ||
!intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) ||
!intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) {
- DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
+ drm_dbg(&i915->drm, "Pushbus not setup properly.\n");
enable_rc6 = false;
}
if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) {
- DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
+ drm_dbg(&i915->drm, "GFX pause not setup properly.\n");
enable_rc6 = false;
}
if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) {
- DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
+ drm_dbg(&i915->drm, "GPM control not setup properly.\n");
enable_rc6 = false;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_renderstate.c b/drivers/gpu/drm/i915/gt/intel_renderstate.c
index 5954ecc3207f..26e78db33675 100644
--- a/drivers/gpu/drm/i915/gt/intel_renderstate.c
+++ b/drivers/gpu/drm/i915/gt/intel_renderstate.c
@@ -102,7 +102,7 @@ static int render_state_setup(struct intel_renderstate *so,
}
if (rodata->reloc[reloc_index] != -1) {
- DRM_ERROR("only %d relocs resolved\n", reloc_index);
+ drm_err(&i915->drm, "only %d relocs resolved\n", reloc_index);
goto err;
}
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 7e2c6ac7d6b0..964a8d8d28b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -578,8 +578,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
RING_INSTPM(engine->mmio_base),
INSTPM_SYNC_FLUSH, 0,
1000))
- DRM_ERROR("%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
- engine->name);
+ drm_err(&dev_priv->drm,
+ "%s: wait for SyncFlush to complete for TLB invalidation timed out\n",
+ engine->name);
}
static void ring_setup_status_page(struct intel_engine_cs *engine)
@@ -602,8 +603,9 @@ static bool stop_ring(struct intel_engine_cs *engine)
MODE_IDLE,
MODE_IDLE,
1000)) {
- DRM_ERROR("%s : timed out trying to stop ring\n",
- engine->name);
+ drm_err(&dev_priv->drm,
+ "%s : timed out trying to stop ring\n",
+ engine->name);
/*
* Sometimes we observe that the idle flag is not
@@ -641,22 +643,23 @@ static int xcs_resume(struct intel_engine_cs *engine)
/* WaClearRingBufHeadRegAtInit:ctg,elk */
if (!stop_ring(engine)) {
/* G45 ring initialization often fails to reset head to zero */
- DRM_DEBUG_DRIVER("%s head not reset to zero "
+ drm_dbg(&dev_priv->drm, "%s head not reset to zero "
+ "ctl %08x head %08x tail %08x start %08x\n",
+ engine->name,
+ ENGINE_READ(engine, RING_CTL),
+ ENGINE_READ(engine, RING_HEAD),
+ ENGINE_READ(engine, RING_TAIL),
+ ENGINE_READ(engine, RING_START));
+
+ if (!stop_ring(engine)) {
+ drm_err(&dev_priv->drm,
+ "failed to set %s head to zero "
"ctl %08x head %08x tail %08x start %08x\n",
engine->name,
ENGINE_READ(engine, RING_CTL),
ENGINE_READ(engine, RING_HEAD),
ENGINE_READ(engine, RING_TAIL),
ENGINE_READ(engine, RING_START));
-
- if (!stop_ring(engine)) {
- DRM_ERROR("failed to set %s head to zero "
- "ctl %08x head %08x tail %08x start %08x\n",
- engine->name,
- ENGINE_READ(engine, RING_CTL),
- ENGINE_READ(engine, RING_HEAD),
- ENGINE_READ(engine, RING_TAIL),
- ENGINE_READ(engine, RING_START));
ret = -EIO;
goto out;
}
@@ -697,7 +700,7 @@ static int xcs_resume(struct intel_engine_cs *engine)
RING_CTL(engine->mmio_base),
RING_VALID, RING_VALID,
50)) {
- DRM_ERROR("%s initialization failed "
+ drm_err(&dev_priv->drm, "%s initialization failed "
"ctl %08x (valid? %d) head %08x [%08x] tail %08x [%08x] start %08x [expected %08x]\n",
engine->name,
ENGINE_READ(engine, RING_CTL),
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 30ae29b30f11..54e63435ccfe 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -180,8 +180,8 @@ static void gen5_rps_init(struct intel_rps *rps)
fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
MEMMODE_FSTART_SHIFT;
- DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
- fmax, fmin, fstart);
+ drm_dbg(&i915->drm, "fmax: %d, fmin: %d, fstart: %d\n",
+ fmax, fmin, fstart);
rps->min_freq = fmax;
rps->max_freq = fmin;
@@ -1029,8 +1029,8 @@ static bool chv_rps_enable(struct intel_rps *rps)
drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
"GPLL not enabled\n");
- DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
- DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+ drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE));
+ drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val);
return rps_reset(rps);
}
@@ -1127,8 +1127,8 @@ static bool vlv_rps_enable(struct intel_rps *rps)
drm_WARN_ONCE(&i915->drm, (val & GPLLENABLE) == 0,
"GPLL not enabled\n");
- DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
- DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
+ drm_dbg(&i915->drm, "GPLL enabled? %s\n", yesno(val & GPLLENABLE));
+ drm_dbg(&i915->drm, "GPU status: 0x%08x\n", val);
return rps_reset(rps);
}
@@ -1285,7 +1285,8 @@ static void vlv_init_gpll_ref_freq(struct intel_rps *rps)
CCK_GPLL_CLOCK_CONTROL,
i915->czclk_freq);
- DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n", rps->gpll_ref_freq);
+ drm_dbg(&i915->drm, "GPLL reference freq: %d kHz\n",
+ rps->gpll_ref_freq);
}
static void vlv_rps_init(struct intel_rps *rps)
@@ -1313,28 +1314,24 @@ static void vlv_rps_init(struct intel_rps *rps)
i915->mem_freq = 1333;
break;
}
- DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", i915->mem_freq);
+ drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
rps->max_freq = vlv_rps_max_freq(rps);
rps->rp0_freq = rps->max_freq;
- DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->max_freq),
- rps->max_freq);
+ drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->max_freq), rps->max_freq);
rps->efficient_freq = vlv_rps_rpe_freq(rps);
- DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->efficient_freq),
- rps->efficient_freq);
+ drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq);
rps->rp1_freq = vlv_rps_guar_freq(rps);
- DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->rp1_freq),
- rps->rp1_freq);
+ drm_dbg(&i915->drm, "RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq);
rps->min_freq = vlv_rps_min_freq(rps);
- DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->min_freq),
- rps->min_freq);
+ drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->min_freq), rps->min_freq);
vlv_iosf_sb_put(i915,
BIT(VLV_IOSF_SB_PUNIT) |
@@ -1364,28 +1361,24 @@ static void chv_rps_init(struct intel_rps *rps)
i915->mem_freq = 1600;
break;
}
- DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", i915->mem_freq);
+ drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
rps->max_freq = chv_rps_max_freq(rps);
rps->rp0_freq = rps->max_freq;
- DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->max_freq),
- rps->max_freq);
+ drm_dbg(&i915->drm, "max GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->max_freq), rps->max_freq);
rps->efficient_freq = chv_rps_rpe_freq(rps);
- DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->efficient_freq),
- rps->efficient_freq);
+ drm_dbg(&i915->drm, "RPe GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->efficient_freq), rps->efficient_freq);
rps->rp1_freq = chv_rps_guar_freq(rps);
- DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->rp1_freq),
- rps->rp1_freq);
+ drm_dbg(&i915->drm, "RP1(Guar) GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->rp1_freq), rps->rp1_freq);
rps->min_freq = chv_rps_min_freq(rps);
- DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
- intel_gpu_freq(rps, rps->min_freq),
- rps->min_freq);
+ drm_dbg(&i915->drm, "min GPU freq: %d MHz (%u)\n",
+ intel_gpu_freq(rps, rps->min_freq), rps->min_freq);
vlv_iosf_sb_put(i915,
BIT(VLV_IOSF_SB_PUNIT) |
@@ -1641,9 +1634,10 @@ void intel_rps_init(struct intel_rps *rps)
sandybridge_pcode_read(i915, GEN6_READ_OC_PARAMS,
¶ms, NULL);
if (params & BIT(31)) { /* OC supported */
- DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
- (rps->max_freq & 0xff) * 50,
- (params & 0xff) * 50);
+ drm_dbg(&i915->drm,
+ "Overclocking supported, max: %dMHz, overclock: %dMHz\n",
+ (rps->max_freq & 0xff) * 50,
+ (params & 0xff) * 50);
rps->max_freq = params & 0xff;
}
}
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..b4942083593c 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -815,7 +815,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
intel_uncore_read(&i915->uncore, GEN10_MIRROR_FUSE3) &
GEN10_L3BANK_MASK;
- DRM_DEBUG_DRIVER("L3 fuse = %x\n", l3_fuse);
+ drm_dbg(&i915->drm, "L3 fuse = %x\n", l3_fuse);
l3_en = ~(l3_fuse << GEN10_L3BANK_PAIR_COUNT | l3_fuse);
} else {
l3_en = ~0;
@@ -824,7 +824,8 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
slice = fls(sseu->slice_mask) - 1;
subslice = fls(l3_en & intel_sseu_get_subslices(sseu, slice));
if (!subslice) {
- DRM_WARN("No common index found between subslice mask %x and L3 bank mask %x!\n",
+ drm_warn(&i915->drm,
+ "No common index found between subslice mask %x and L3 bank mask %x!\n",
intel_sseu_get_subslices(sseu, slice), l3_en);
subslice = fls(l3_en);
drm_WARN_ON(&i915->drm, !subslice);
@@ -839,7 +840,7 @@ wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
mcr_mask = GEN8_MCR_SLICE_MASK | GEN8_MCR_SUBSLICE_MASK;
}
- DRM_DEBUG_DRIVER("MCR slice/subslice = %x\n", mcr);
+ drm_dbg(&i915->drm, "MCR slice/subslice = %x\n", mcr);
wa_write_masked_or(wal, GEN8_MCR_SELECTOR, mcr_mask, mcr);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
index caed0d57e704..d6a8e1e93983 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_log.c
@@ -391,7 +391,8 @@ static int guc_log_relay_create(struct intel_guc_log *log)
subbuf_size, n_subbufs,
&relay_callbacks, dev_priv);
if (!guc_log_relay_chan) {
- DRM_ERROR("Couldn't create relay chan for GuC logging\n");
+ drm_err(&dev_priv->drm,
+ "Couldn't create relay chan for GuC logging\n");
ret = -ENOMEM;
return ret;
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_uc.c b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
index 64934a876a50..d2bdd74466f2 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_uc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_uc.c
@@ -224,7 +224,7 @@ static int guc_enable_communication(struct intel_guc *guc)
intel_guc_ct_event_handler(&guc->ct);
spin_unlock_irq(&i915->irq_lock);
- DRM_INFO("GuC communication enabled\n");
+ drm_info(&i915->drm, "GuC communication enabled\n");
return 0;
}
@@ -441,7 +441,7 @@ static int __uc_init_hw(struct intel_uc *uc)
if (ret == 0)
break;
- DRM_DEBUG_DRIVER("GuC fw load failed: %d; will reset and "
+ drm_dbg(&i915->drm, "GuC fw load failed: %d; will reset and "
"retry %d more time(s)\n", ret, attempts);
}
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 2/8] drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 1/8] drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 3/8] drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c Wambui Karuga
` (8 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
Manual conversion of the printk based logging macros to the new struct
drm_based logging macros in drm/i915/gt/intel_ggtt.c.
Also includes extracting the struct drm_i915_private device from various
intel types to use in the new macros.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_ggtt.c | 25 ++++++++++++++++---------
1 file changed, 16 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index d938cf8db460..09f4aa37bf2d 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -472,7 +472,8 @@ static int ggtt_reserve_guc_top(struct i915_ggtt *ggtt)
GUC_GGTT_TOP, I915_COLOR_UNEVICTABLE,
PIN_NOEVICT);
if (ret)
- DRM_DEBUG_DRIVER("Failed to reserve top of GGTT for GuC\n");
+ drm_dbg(&ggtt->vm.i915->drm,
+ "Failed to reserve top of GGTT for GuC\n");
return ret;
}
@@ -544,8 +545,9 @@ static int init_ggtt(struct i915_ggtt *ggtt)
/* Clear any non-preallocated blocks */
drm_mm_for_each_hole(entry, &ggtt->vm.mm, hole_start, hole_end) {
- DRM_DEBUG_KMS("clearing unused GTT space: [%lx, %lx]\n",
- hole_start, hole_end);
+ drm_dbg_kms(&ggtt->vm.i915->drm,
+ "clearing unused GTT space: [%lx, %lx]\n",
+ hole_start, hole_end);
ggtt->vm.clear_range(&ggtt->vm, hole_start,
hole_end - hole_start);
}
@@ -1273,6 +1275,7 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
struct drm_i915_gem_object *obj)
{
unsigned int size = intel_rotation_info_size(rot_info);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct sg_table *st;
struct scatterlist *sg;
int ret = -ENOMEM;
@@ -1302,8 +1305,9 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
kfree(st);
err_st_alloc:
- DRM_DEBUG_DRIVER("Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
- obj->base.size, rot_info->plane[0].width, rot_info->plane[0].height, size);
+ drm_dbg(&i915->drm, "Failed to create rotated mapping for object size %zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rot_info->plane[0].width,
+ rot_info->plane[0].height, size);
return ERR_PTR(ret);
}
@@ -1355,6 +1359,7 @@ intel_remap_pages(struct intel_remapped_info *rem_info,
struct drm_i915_gem_object *obj)
{
unsigned int size = intel_remapped_info_size(rem_info);
+ struct drm_i915_private *i915 = to_i915(obj->base.dev);
struct sg_table *st;
struct scatterlist *sg;
int ret = -ENOMEM;
@@ -1386,8 +1391,9 @@ intel_remap_pages(struct intel_remapped_info *rem_info,
kfree(st);
err_st_alloc:
- DRM_DEBUG_DRIVER("Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
- obj->base.size, rem_info->plane[0].width, rem_info->plane[0].height, size);
+ drm_dbg(&i915->drm, "Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rem_info->plane[0].width,
+ rem_info->plane[0].height, size);
return ERR_PTR(ret);
}
@@ -1485,8 +1491,9 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
if (IS_ERR(vma->pages)) {
ret = PTR_ERR(vma->pages);
vma->pages = NULL;
- DRM_ERROR("Failed to get pages for VMA view type %u (%d)!\n",
- vma->ggtt_view.type, ret);
+ drm_err(&vma->vm->i915->drm,
+ "Failed to get pages for VMA view type %u (%d)!\n",
+ vma->ggtt_view.type, ret);
}
return ret;
}
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 3/8] drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 1/8] drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 2/8] drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 4/8] drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c Wambui Karuga
` (7 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
This converts most instances of the printk based drm logging macros in
i915/gt/intel_resect.c to the new struct drm_based logging macros.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_reset.c | 48 +++++++++++++++------------
1 file changed, 26 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index beee0cf89bce..df8240324714 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -72,9 +72,10 @@ static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
if (score) {
atomic_add(score, &file_priv->ban_score);
- DRM_DEBUG_DRIVER("client %s: gained %u ban score, now %u\n",
- ctx->name, score,
- atomic_read(&file_priv->ban_score));
+ drm_dbg(&ctx->i915->drm,
+ "client %s: gained %u ban score, now %u\n",
+ ctx->name, score,
+ atomic_read(&file_priv->ban_score));
}
}
@@ -122,8 +123,8 @@ static bool mark_guilty(struct i915_request *rq)
if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
banned = true;
if (banned) {
- DRM_DEBUG_DRIVER("context %s: guilty %d, banned\n",
- ctx->name, atomic_read(&ctx->guilty_count));
+ drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
+ ctx->name, atomic_read(&ctx->guilty_count));
intel_context_set_banned(rq->context);
}
@@ -226,7 +227,7 @@ static int g4x_do_reset(struct intel_gt *gt,
GRDOM_MEDIA | GRDOM_RESET_ENABLE);
ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for media reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for media reset failed\n");
goto out;
}
@@ -234,7 +235,7 @@ static int g4x_do_reset(struct intel_gt *gt,
GRDOM_RENDER | GRDOM_RESET_ENABLE);
ret = wait_for_atomic(g4x_reset_complete(pdev), 50);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for render reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for render reset failed\n");
goto out;
}
@@ -260,7 +261,7 @@ static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
5000, 0,
NULL);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for render reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for render reset failed\n");
goto out;
}
@@ -271,7 +272,7 @@ static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
5000, 0,
NULL);
if (ret) {
- DRM_DEBUG_DRIVER("Wait for media reset failed\n");
+ drm_dbg(>->i915->drm, "Wait for media reset failed\n");
goto out;
}
@@ -300,8 +301,9 @@ static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
500, 0,
NULL);
if (err)
- DRM_DEBUG_DRIVER("Wait for 0x%08x engines reset failed\n",
- hw_domain_mask);
+ drm_dbg(>->i915->drm,
+ "Wait for 0x%08x engines reset failed\n",
+ hw_domain_mask);
return err;
}
@@ -401,7 +403,8 @@ static int gen11_lock_sfc(struct intel_engine_cs *engine, u32 *hw_mask)
return 0;
if (ret) {
- DRM_DEBUG_DRIVER("Wait for SFC forced lock ack failed\n");
+ drm_dbg(&engine->i915->drm,
+ "Wait for SFC forced lock ack failed\n");
return ret;
}
@@ -515,9 +518,10 @@ static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
700, 0, NULL);
if (ret)
- DRM_ERROR("%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
- engine->name, request,
- intel_uncore_read_fw(uncore, reg));
+ drm_err(&engine->i915->drm,
+ "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
+ engine->name, request,
+ intel_uncore_read_fw(uncore, reg));
return ret;
}
@@ -1022,7 +1026,7 @@ void intel_gt_reset(struct intel_gt *gt,
if (i915_modparams.reset)
dev_err(gt->i915->drm.dev, "GPU reset not supported\n");
else
- DRM_DEBUG_DRIVER("GPU reset disabled\n");
+ drm_dbg(>->i915->drm, "GPU reset disabled\n");
goto error;
}
@@ -1049,8 +1053,9 @@ void intel_gt_reset(struct intel_gt *gt,
*/
ret = intel_gt_init_hw(gt);
if (ret) {
- DRM_ERROR("Failed to initialise HW following reset (%d)\n",
- ret);
+ drm_err(>->i915->drm,
+ "Failed to initialise HW following reset (%d)\n",
+ ret);
goto taint;
}
@@ -1126,9 +1131,8 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
ret = intel_guc_reset_engine(&engine->gt->uc.guc, engine);
if (ret) {
/* If we fail here, we expect to fallback to a global reset */
- DRM_DEBUG_DRIVER("%sFailed to reset %s, ret=%d\n",
- uses_guc ? "GuC " : "",
- engine->name, ret);
+ drm_dbg(>->i915->drm, "%sFailed to reset %s, ret=%d\n",
+ uses_guc ? "GuC " : "", engine->name, ret);
goto out;
}
@@ -1165,7 +1169,7 @@ static void intel_gt_reset_global(struct intel_gt *gt,
kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
- DRM_DEBUG_DRIVER("resetting chip\n");
+ drm_dbg(>->i915->drm, "resetting chip\n");
kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
/* Use a watchdog to ensure that our reset completes */
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 4/8] drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (2 preceding siblings ...)
2020-01-28 7:14 ` [Intel-gfx] [PATCH 3/8] drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 5/8] drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c Wambui Karuga
` (6 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
Conversion of the remaining printk based drm logging macros to the new
struct drm_device based logging macros in i915/gt/intel_engine_cs.c.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 084abc577b14..b9511e045eee 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -200,10 +200,10 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
* out in the wash.
*/
cxt_size = intel_uncore_read(uncore, CXT_SIZE) + 1;
- DRM_DEBUG_DRIVER("gen%d CXT_SIZE = %d bytes [0x%08x]\n",
- INTEL_GEN(gt->i915),
- cxt_size * 64,
- cxt_size - 1);
+ drm_dbg(>->i915->drm,
+ "gen%d CXT_SIZE = %d bytes [0x%08x]\n",
+ INTEL_GEN(gt->i915), cxt_size * 64,
+ cxt_size - 1);
return round_up(cxt_size * 64, PAGE_SIZE);
case 3:
case 2:
@@ -562,7 +562,8 @@ static int init_status_page(struct intel_engine_cs *engine)
*/
obj = i915_gem_object_create_internal(engine->i915, PAGE_SIZE);
if (IS_ERR(obj)) {
- DRM_ERROR("Failed to allocate status page\n");
+ drm_err(&engine->i915->drm,
+ "Failed to allocate status page\n");
return PTR_ERR(obj);
}
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 5/8] drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (3 preceding siblings ...)
2020-01-28 7:14 ` [Intel-gfx] [PATCH 4/8] drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 6/8] drm/i915/gt: convert to new logging macros in gt/intel_gt.c Wambui Karuga
` (5 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
Converts most instances of the printk based drm logging macros in
i915/gt/intel_lrc.c to the new struct drm_device based logging macros.
In some instances, extracts the struct drm_i915_private device for use
in the logging macros.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 22 ++++++++++++++--------
1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 5003c2e84786..57bd77120b5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3310,7 +3310,8 @@ static int intel_init_workaround_bb(struct intel_engine_cs *engine)
ret = lrc_setup_wa_ctx(engine);
if (ret) {
- DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret);
+ drm_dbg(&engine->i915->drm,
+ "Failed to setup context WA page: %d\n", ret);
return ret;
}
@@ -3372,7 +3373,8 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
bool unexpected = false;
if (ENGINE_READ_FW(engine, RING_MI_MODE) & STOP_RING) {
- DRM_DEBUG_DRIVER("STOP_RING still set in RING_MI_MODE\n");
+ drm_dbg(&engine->i915->drm,
+ "STOP_RING still set in RING_MI_MODE\n");
unexpected = true;
}
@@ -4502,6 +4504,7 @@ populate_lr_context(struct intel_context *ce,
struct intel_engine_cs *engine,
struct intel_ring *ring)
{
+ struct drm_i915_private *i915 = to_i915(ctx_obj->base.dev);
bool inhibit = true;
void *vaddr;
int ret;
@@ -4509,7 +4512,7 @@ populate_lr_context(struct intel_context *ce,
vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB);
if (IS_ERR(vaddr)) {
ret = PTR_ERR(vaddr);
- DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret);
+ drm_dbg(&i915->drm, "Could not map object pages! (%d)\n", ret);
return ret;
}
@@ -4588,7 +4591,8 @@ static int __execlists_context_alloc(struct intel_context *ce,
ret = populate_lr_context(ce, ctx_obj, engine, ring);
if (ret) {
- DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret);
+ drm_dbg(&engine->i915->drm,
+ "Failed to populate LRC: %d\n", ret);
goto error_ring_free;
}
@@ -4975,8 +4979,9 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
GEM_BUG_ON(!is_power_of_2(sibling->mask));
if (sibling->mask & ve->base.mask) {
- DRM_DEBUG("duplicate %s entry in load balancer\n",
- sibling->name);
+ drm_dbg(&sibling->i915->drm,
+ "duplicate %s entry in load balancer\n",
+ sibling->name);
err = -EINVAL;
goto err_put;
}
@@ -5009,8 +5014,9 @@ intel_execlists_create_virtual(struct intel_engine_cs **siblings,
*/
if (ve->base.class != OTHER_CLASS) {
if (ve->base.class != sibling->class) {
- DRM_DEBUG("invalid mixing of engine class, sibling %d, already %d\n",
- sibling->class, ve->base.class);
+ drm_dbg(&sibling->i915->drm,
+ "invalid mixing of engine class, sibling %d, already %d\n",
+ sibling->class, ve->base.class);
err = -EINVAL;
goto err_put;
}
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 6/8] drm/i915/gt: convert to new logging macros in gt/intel_gt.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (4 preceding siblings ...)
2020-01-28 7:14 ` [Intel-gfx] [PATCH 5/8] drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 7/8] drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c Wambui Karuga
` (4 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
Convert remaining instances of the printk based logging macros in
i915/gt/intel_gt to the struct drm_device based logging macros.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 43 +++++++++++++++---------------
1 file changed, 21 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index a1ba0097117e..448afdcf40ab 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -198,16 +198,16 @@ static void gen6_check_faults(struct intel_gt *gt)
for_each_engine(engine, gt, id) {
fault = GEN6_RING_FAULT_REG_READ(engine);
if (fault & RING_FAULT_VALID) {
- DRM_DEBUG_DRIVER("Unexpected fault\n"
- "\tAddr: 0x%08lx\n"
- "\tAddress space: %s\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- fault & PAGE_MASK,
- fault & RING_FAULT_GTTSEL_MASK ?
- "GGTT" : "PPGTT",
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ drm_dbg(&engine->i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08lx\n"
+ "\tAddress space: %s\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ fault & PAGE_MASK,
+ fault & RING_FAULT_GTTSEL_MASK ?
+ "GGTT" : "PPGTT",
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
}
@@ -239,18 +239,17 @@ static void gen8_check_faults(struct intel_gt *gt)
fault_addr = ((u64)(fault_data1 & FAULT_VA_HIGH_BITS) << 44) |
((u64)fault_data0 << 12);
- DRM_DEBUG_DRIVER("Unexpected fault\n"
- "\tAddr: 0x%08x_%08x\n"
- "\tAddress space: %s\n"
- "\tEngine ID: %d\n"
- "\tSource ID: %d\n"
- "\tType: %d\n",
- upper_32_bits(fault_addr),
- lower_32_bits(fault_addr),
- fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
- GEN8_RING_FAULT_ENGINE_ID(fault),
- RING_FAULT_SRCID(fault),
- RING_FAULT_FAULT_TYPE(fault));
+ drm_dbg(&uncore->i915->drm, "Unexpected fault\n"
+ "\tAddr: 0x%08x_%08x\n"
+ "\tAddress space: %s\n"
+ "\tEngine ID: %d\n"
+ "\tSource ID: %d\n"
+ "\tType: %d\n",
+ upper_32_bits(fault_addr), lower_32_bits(fault_addr),
+ fault_data1 & FAULT_GTT_SEL ? "GGTT" : "PPGTT",
+ GEN8_RING_FAULT_ENGINE_ID(fault),
+ RING_FAULT_SRCID(fault),
+ RING_FAULT_FAULT_TYPE(fault));
}
}
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 7/8] drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (5 preceding siblings ...)
2020-01-28 7:14 ` [Intel-gfx] [PATCH 6/8] drm/i915/gt: convert to new logging macros in gt/intel_gt.c Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 8/8] drm/i915/rps: move to new drm logging macros in gt/intel_rps.c Wambui Karuga
` (3 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
Manually convert the remaining instance of the printk based drm logging
macros to the struct drm_device based logging macros in
i915/gt/intel_ring_submission.c
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 964a8d8d28b5..0f2e8a010794 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -1666,7 +1666,8 @@ static void gen6_bsd_submit_request(struct i915_request *request)
GEN6_BSD_SLEEP_INDICATOR,
0,
1000, 0, NULL))
- DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
+ drm_err(&uncore->i915->drm,
+ "timed out waiting for the BSD ring to wake up\n");
/* Now that the ring is fully powered up, update the tail */
i9xx_submit_request(request);
--
2.25.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH 8/8] drm/i915/rps: move to new drm logging macros in gt/intel_rps.c
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (6 preceding siblings ...)
2020-01-28 7:14 ` [Intel-gfx] [PATCH 7/8] drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c Wambui Karuga
@ 2020-01-28 7:14 ` Wambui Karuga
2020-01-28 7:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt conversion to new drm logging macros Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 12+ messages in thread
From: Wambui Karuga @ 2020-01-28 7:14 UTC (permalink / raw)
To: jani.nikula, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
Convert various instances of the printk based drm logging macros to the
new struct drm_device based logging macros in i915/gt/intel_rps.c.
Signed-off-by: Wambui Karuga <wambui.karugax@gmail.com>
---
drivers/gpu/drm/i915/gt/intel_rps.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_rps.c b/drivers/gpu/drm/i915/gt/intel_rps.c
index 54e63435ccfe..9771d5f64b94 100644
--- a/drivers/gpu/drm/i915/gt/intel_rps.c
+++ b/drivers/gpu/drm/i915/gt/intel_rps.c
@@ -306,7 +306,7 @@ static bool gen5_rps_set(struct intel_rps *rps, u8 val)
rgvswctl = intel_uncore_read16(uncore, MEMSWCTL);
if (rgvswctl & MEMCTL_CMD_STS) {
- DRM_DEBUG("gpu busy, RCS change rejected\n");
+ drm_dbg(&uncore->i915->drm, "gpu busy, RCS change rejected\n");
return false; /* still busy with another command */
}
@@ -450,7 +450,8 @@ static bool gen5_rps_enable(struct intel_rps *rps)
if (wait_for_atomic((intel_uncore_read(uncore, MEMSWCTL) &
MEMCTL_CMD_STS) == 0, 10))
- DRM_ERROR("stuck trying to change perf mode\n");
+ drm_err(&uncore->i915->drm,
+ "stuck trying to change perf mode\n");
mdelay(1);
gen5_rps_set(rps, rps->cur_freq);
@@ -873,12 +874,13 @@ static void gen6_rps_init(struct intel_rps *rps)
static bool rps_reset(struct intel_rps *rps)
{
+ struct drm_i915_private *i915 = rps_to_i915(rps);
/* force a reset */
rps->power.mode = -1;
rps->last_freq = -1;
if (rps_set(rps, rps->min_freq, true)) {
- DRM_ERROR("Failed to reset RPS to initial values\n");
+ drm_err(&i915->drm, "Failed to reset RPS to initial values\n");
return false;
}
@@ -1441,6 +1443,7 @@ static void rps_work(struct work_struct *work)
{
struct intel_rps *rps = container_of(work, typeof(*rps), work);
struct intel_gt *gt = rps_to_gt(rps);
+ struct drm_i915_private *i915 = rps_to_i915(rps);
bool client_boost = false;
int new_freq, adj, min, max;
u32 pm_iir = 0;
@@ -1516,7 +1519,7 @@ static void rps_work(struct work_struct *work)
new_freq = clamp_t(int, new_freq, min, max);
if (intel_rps_set(rps, new_freq)) {
- DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n");
+ drm_dbg(&i915->drm, "Failed to set new GPU frequency\n");
rps->last_adj = 0;
}
@@ -1547,6 +1550,7 @@ void gen11_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
{
struct intel_gt *gt = rps_to_gt(rps);
+ struct drm_i915_private *i915 = rps_to_i915(rps);
if (pm_iir & rps->pm_events) {
spin_lock(>->irq_lock);
@@ -1563,7 +1567,8 @@ void gen6_rps_irq_handler(struct intel_rps *rps, u32 pm_iir)
intel_engine_signal_breadcrumbs(gt->engine[VECS0]);
if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
- DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
+ drm_dbg(&i915->drm,
+ "Command parser error, pm_iir 0x%08x\n", pm_iir);
}
void gen5_rps_irq_handler(struct intel_rps *rps)
--
2.25.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt conversion to new drm logging macros.
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (7 preceding siblings ...)
2020-01-28 7:14 ` [Intel-gfx] [PATCH 8/8] drm/i915/rps: move to new drm logging macros in gt/intel_rps.c Wambui Karuga
@ 2020-01-28 7:42 ` Patchwork
2020-01-29 6:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-01-30 14:07 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-01-28 7:42 UTC (permalink / raw)
To: Wambui Karuga; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt conversion to new drm logging macros.
URL : https://patchwork.freedesktop.org/series/72643/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7827 -> Patchwork_16290
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/index.html
Known issues
------------
Here are the changes found in Patchwork_16290 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_close_race@basic-threads:
- fi-byt-j1900: [PASS][1] -> [INCOMPLETE][2] ([i915#45])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-byt-j1900/igt@gem_close_race@basic-threads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-byt-j1900/igt@gem_close_race@basic-threads.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-guc: [PASS][3] -> [DMESG-FAIL][4] ([i915#623])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-cfl-guc/igt@i915_selftest@live_gem_contexts.html
#### Possible fixes ####
* igt@i915_selftest@live_blt:
- fi-hsw-4770: [DMESG-FAIL][5] ([i915#553] / [i915#725]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-hsw-4770/igt@i915_selftest@live_blt.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-hsw-4770/igt@i915_selftest@live_blt.html
* igt@i915_selftest@live_hangcheck:
- fi-icl-u3: [INCOMPLETE][7] ([fdo#108569] / [i915#140]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/fi-icl-u3/igt@i915_selftest@live_hangcheck.html
[fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#623]: https://gitlab.freedesktop.org/drm/intel/issues/623
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
Participating hosts (46 -> 39)
------------------------------
Additional (5): fi-bsw-n3050 fi-gdg-551 fi-cfl-8109u fi-ivb-3770 fi-skl-6600u
Missing (12): fi-ilk-m540 fi-bdw-samus fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ctg-p8600 fi-whl-u fi-kbl-7560u fi-byt-n2820 fi-byt-clapper fi-skl-6700k2 fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7827 -> Patchwork_16290
CI-20190529: 20190529
CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16290: 5b110e05162bff7e512f9a4f8133c5d3b1a315c5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
5b110e05162b drm/i915/rps: move to new drm logging macros in gt/intel_rps.c
28139438c616 drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c
d9d8777b20a6 drm/i915/gt: convert to new logging macros in gt/intel_gt.c
5ed3964d97b2 drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c
cf7f41aa28b5 drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c
b7d1e0802827 drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c
52132978d32c drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c
31cfe64d2d7f drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/gt conversion to new drm logging macros.
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (8 preceding siblings ...)
2020-01-28 7:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt conversion to new drm logging macros Patchwork
@ 2020-01-29 6:57 ` Patchwork
2020-01-30 14:07 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
10 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-01-29 6:57 UTC (permalink / raw)
To: Wambui Karuga; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt conversion to new drm logging macros.
URL : https://patchwork.freedesktop.org/series/72643/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_7827_full -> Patchwork_16290_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_16290_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_caching@reads:
- shard-hsw: [PASS][1] -> [FAIL][2] ([i915#694])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw4/igt@gem_caching@reads.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-hsw6/igt@gem_caching@reads.html
* igt@gem_ctx_isolation@vcs1-clean:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [fdo#112080]) +2 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@gem_ctx_isolation@vcs1-clean.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb8/igt@gem_ctx_isolation@vcs1-clean.html
* igt@gem_eio@kms:
- shard-snb: [PASS][5] -> [INCOMPLETE][6] ([i915#82])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-snb1/igt@gem_eio@kms.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-snb2/igt@gem_eio@kms.html
* igt@gem_exec_schedule@preempt-other-chain-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +5 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb7/igt@gem_exec_schedule@preempt-other-chain-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb1/igt@gem_exec_schedule@preempt-other-chain-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +13 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-apl: [PASS][11] -> [DMESG-WARN][12] ([i915#180]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-apl4/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +3 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-skl: [PASS][15] -> [INCOMPLETE][16] ([i915#69])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-skl6/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl1/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][19] -> [FAIL][20] ([fdo#108145] / [i915#265]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-skl2/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_psr@psr2_no_drrs:
- shard-iclb: [PASS][21] -> [SKIP][22] ([fdo#109441]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb1/igt@kms_psr@psr2_no_drrs.html
* igt@kms_setmode@basic:
- shard-glk: [PASS][23] -> [FAIL][24] ([i915#31])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-glk6/igt@kms_setmode@basic.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-glk2/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-b-accuracy-idle:
- shard-glk: [PASS][25] -> [FAIL][26] ([i915#43])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-glk5/igt@kms_vblank@pipe-b-accuracy-idle.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-glk9/igt@kms_vblank@pipe-b-accuracy-idle.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][27] -> [SKIP][28] ([fdo#112080]) +4 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@perf_pmu@busy-no-semaphores-vcs1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb8/igt@perf_pmu@busy-no-semaphores-vcs1.html
* igt@prime_mmap_coherency@ioctl-errors:
- shard-hsw: [PASS][29] -> [FAIL][30] ([i915#831])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw1/igt@prime_mmap_coherency@ioctl-errors.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-hsw2/igt@prime_mmap_coherency@ioctl-errors.html
#### Possible fixes ####
* igt@gem_ctx_persistence@vcs1-mixed:
- shard-iclb: [SKIP][31] ([fdo#109276] / [fdo#112080]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb7/igt@gem_ctx_persistence@vcs1-mixed.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb1/igt@gem_ctx_persistence@vcs1-mixed.html
* igt@gem_eio@in-flight-suspend:
- shard-skl: [INCOMPLETE][33] ([i915#69]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl5/igt@gem_eio@in-flight-suspend.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-skl7/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [SKIP][35] ([fdo#109276]) -> [PASS][36] +10 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb7/igt@gem_exec_schedule@fifo-bsd1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [SKIP][37] ([i915#677]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb8/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@wide-bsd:
- shard-iclb: [SKIP][39] ([fdo#112146]) -> [PASS][40] +3 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb2/igt@gem_exec_schedule@wide-bsd.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb3/igt@gem_exec_schedule@wide-bsd.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [DMESG-WARN][41] ([i915#180]) -> [PASS][42] +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-kbl4/igt@gem_exec_suspend@basic-s3.html
* igt@gem_softpin@noreloc-s3:
- shard-apl: [DMESG-WARN][43] ([i915#180]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-apl8/igt@gem_softpin@noreloc-s3.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-apl1/igt@gem_softpin@noreloc-s3.html
* igt@i915_pm_dc@dc5-dpms:
- shard-iclb: [FAIL][45] ([i915#447]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb1/igt@i915_pm_dc@dc5-dpms.html
* igt@i915_selftest@live_blt:
- shard-hsw: [DMESG-FAIL][47] ([i915#553] / [i915#725]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw1/igt@i915_selftest@live_blt.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-hsw1/igt@i915_selftest@live_blt.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-skl: [INCOMPLETE][49] ([i915#300]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-skl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [INCOMPLETE][51] ([i915#221]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-skl3/igt@kms_flip@flip-vs-suspend-interruptible.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-skl8/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_psr@psr2_cursor_mmap_cpu:
- shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +3 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb6/igt@kms_psr@psr2_cursor_mmap_cpu.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb2/igt@kms_psr@psr2_cursor_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][55] ([i915#31]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-apl3/igt@kms_setmode@basic.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-apl4/igt@kms_setmode@basic.html
- shard-kbl: [FAIL][57] ([i915#31]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-kbl7/igt@kms_setmode@basic.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-kbl2/igt@kms_setmode@basic.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [SKIP][59] ([fdo#112080]) -> [PASS][60] +7 similar issues
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb8/igt@perf_pmu@init-busy-vcs1.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb2/igt@perf_pmu@init-busy-vcs1.html
#### Warnings ####
* igt@gem_ctx_isolation@vcs1-nonpriv:
- shard-iclb: [SKIP][61] ([fdo#109276] / [fdo#112080]) -> [FAIL][62] ([IGT#28])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb3/igt@gem_ctx_isolation@vcs1-nonpriv.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb1/igt@gem_ctx_isolation@vcs1-nonpriv.html
* igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive:
- shard-hsw: [FAIL][63] ([i915#1045]) -> [DMESG-FAIL][64] ([i915#1045])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-hsw1/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-hsw5/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][65] ([fdo#109349]) -> [DMESG-WARN][66] ([fdo#107724])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7827/shard-iclb6/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[IGT#28]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/28
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1045]: https://gitlab.freedesktop.org/drm/intel/issues/1045
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#43]: https://gitlab.freedesktop.org/drm/intel/issues/43
[i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447
[i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#831]: https://gitlab.freedesktop.org/drm/intel/issues/831
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7827 -> Patchwork_16290
CI-20190529: 20190529
CI_DRM_7827: c8969aeacfff681c83a800e82b0f18a6ab3e77ea @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5389: 966c58649dee31bb5bf2fad92f75ffd365968b81 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16290: 5b110e05162bff7e512f9a4f8133c5d3b1a315c5 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16290/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros.
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
` (9 preceding siblings ...)
2020-01-29 6:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-01-30 14:07 ` Jani Nikula
10 siblings, 0 replies; 12+ messages in thread
From: Jani Nikula @ 2020-01-30 14:07 UTC (permalink / raw)
To: Wambui Karuga, joonas.lahtinen, rodrigo.vivi, airlied, daniel; +Cc: intel-gfx
On Tue, 28 Jan 2020, Wambui Karuga <wambui.karugax@gmail.com> wrote:
> This series continues the conversion to the new drm logging macros
> focused on the drm/i915/gt folder. This was done both manually and using
> coccinelle.
Thanks for the patches, for now pushed only the non-contentions ones
that don't convert DRM_DEBUG() -> drm_dbg().
BR,
Jani.
>
> Wambui Karuga (8):
> drm/i915/gt: conversion to struct drm_device macros when struct
> drm_i915_private is available.
> drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c
> drm/i915/reset: conversion to new drm logging macros in
> gt/intel_reset.c
> drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c
> drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c
> drm/i915/gt: convert to new logging macros in gt/intel_gt.c
> drm/i915/ring: convert to new logging macros in
> gt/intel_ring_submission.c
> drm/i915/rps: move to new drm logging macros in gt/intel_rps.c
>
> drivers/gpu/drm/i915/gt/intel_engine_cs.c | 11 +--
> drivers/gpu/drm/i915/gt/intel_engine_user.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_ggtt.c | 63 +++++++++------
> drivers/gpu/drm/i915/gt/intel_gt.c | 49 ++++++-----
> drivers/gpu/drm/i915/gt/intel_lrc.c | 24 +++---
> drivers/gpu/drm/i915/gt/intel_rc6.c | 30 ++++---
> drivers/gpu/drm/i915/gt/intel_renderstate.c | 2 +-
> drivers/gpu/drm/i915/gt/intel_reset.c | 48 ++++++-----
> .../gpu/drm/i915/gt/intel_ring_submission.c | 36 +++++----
> drivers/gpu/drm/i915/gt/intel_rps.c | 81 +++++++++----------
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 7 +-
> drivers/gpu/drm/i915/gt/uc/intel_guc_log.c | 3 +-
> drivers/gpu/drm/i915/gt/uc/intel_uc.c | 4 +-
> 13 files changed, 196 insertions(+), 164 deletions(-)
--
Jani Nikula, Intel Open Source Graphics Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-01-30 14:07 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-01-28 7:14 [Intel-gfx] [PATCH 0/8] drm/i915/gt conversion to new drm logging macros Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 1/8] drm/i915/gt: conversion to struct drm_device macros when struct drm_i915_private is available Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 2/8] drm/i915/ggtt: use new drm logging macros in gt/intel_ggtt.c Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 3/8] drm/i915/reset: conversion to new drm logging macros in gt/intel_reset.c Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 4/8] drm/i915/engine_cs: use new drm logging macros in gt/intel_engine_cs.c Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 5/8] drm/i915/lrc: conversion to new drm logging macros in gt/intel_lrc.c Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 6/8] drm/i915/gt: convert to new logging macros in gt/intel_gt.c Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 7/8] drm/i915/ring: convert to new logging macros in gt/intel_ring_submission.c Wambui Karuga
2020-01-28 7:14 ` [Intel-gfx] [PATCH 8/8] drm/i915/rps: move to new drm logging macros in gt/intel_rps.c Wambui Karuga
2020-01-28 7:42 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/gt conversion to new drm logging macros Patchwork
2020-01-29 6:57 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-01-30 14:07 ` [Intel-gfx] [PATCH 0/8] " Jani Nikula
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