[cip-dev] [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral support

[cip-dev] [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral support

[Biju Das]

This patch series adds support for following peripherals supported by RZ
G2N,
1: SDHI
2: Watchdog
3: MSIOF
4: PCIE

Please note this patch series is based on top of the series [1].

[1] https://patchwork.kernel.org/project/cip-dev/list/?series=233689&submitter=&state=*&q=&archive=both&delegate=

Biju Das (3):
  mmc: renesas_sdhi_internal_dmac: Add r8a774b1 support
  arm64: dts: renesas: r8a774b1: Add SDHI support
  arm64: dts: renesas: r8a774b1-hihope-rzg2n: Enable HS400 mode

Fabrizio Castro (7):
  dt-bindings: spi: sh-msiof: Add r8a774b1 support
  dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support
  arm64: dts: renesas: r8a774b1: Add RWDT node
  arm64: dts: renesas: r8a774b1: Add all MSIOF nodes
  arm64: dts: renesas: r8a774b1: Add PCIe device nodes
  arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide
    about pciec1
  arm64: dts: renesas: r8a774b1: Add INTC-EX device node

Lad Prabhakar (1):
  dt-bindings: mmc: renesas_sdhi: Add r8a774b1 support

Simon Horman (1):
  dt-bindings: watchdog: Rename bindings documentation file

 Documentation/devicetree/bindings/mmc/tmio_mmc.txt |   1 +
 Documentation/devicetree/bindings/spi/sh-msiof.txt |   1 +
 .../devicetree/bindings/watchdog/renesas,wdt.txt   |  46 ++++++
 .../devicetree/bindings/watchdog/renesas-wdt.txt   |  45 ------
 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi    |   4 -
 .../boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts  |   4 +
 .../boot/dts/renesas/r8a774b1-hihope-rzg2n.dts     |   4 +
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi          | 163 ++++++++++++++++++++-
 drivers/mmc/host/renesas_sdhi_internal_dmac.c      |   1 +
 9 files changed, 213 insertions(+), 56 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
 delete mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt

-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 01/12] dt-bindings: spi: sh-msiof: Add r8a774b1 support

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 97f41c68b83ea5216dbf3ac51fd86b0fbd399a97 upstream.

Document RZ/G2N (R8A774B1) SoC bindings.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1570178133-21532-3-git-send-email-fabrizio.castro at bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
(patched text version of bindings file)
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/spi/sh-msiof.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/spi/sh-msiof.txt b/Documentation/devicetree/bindings/spi/sh-msiof.txt
index 4dd4455..5d6360d 100644
--- a/Documentation/devicetree/bindings/spi/sh-msiof.txt
+++ b/Documentation/devicetree/bindings/spi/sh-msiof.txt
@@ -4,6 +4,7 @@ Required properties:
 - compatible           : "renesas,msiof-r8a7743" (RZ/G1M)
 			 "renesas,msiof-r8a7745" (RZ/G1E)
 			 "renesas,msiof-r8a774a1" (RZ/G2M)
+			 "renesas,msiof-r8a774b1" (RZ/G2N)
 			 "renesas,msiof-r8a774c0" (RZ/G2E)
 			 "renesas,msiof-r8a7790" (R-Car H2)
 			 "renesas,msiof-r8a7791" (R-Car M2-W)
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 02/12] dt-bindings: watchdog: Rename bindings documentation file

[Biju Das]

From: Simon Horman <horms+renesas@verge.net.au>

commit 3265c3d8f70f0cb98dc7a7a3865200a7b19f654b upstream.

For consistency with the naming of (most) other documentation files for DT
bindings for Renesas IP blocks rename the Renesas WDT documentation file
from renesas-wdt.txt to renesas,wdt.txt.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Niklas S?derlund <niklas.soderlund+renesas@ragnatech.se>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
(dropped compatible strings which didnt exist)
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 .../devicetree/bindings/watchdog/renesas,wdt.txt   | 45 ++++++++++++++++++++++
 .../devicetree/bindings/watchdog/renesas-wdt.txt   | 45 ----------------------
 2 files changed, 45 insertions(+), 45 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
 delete mode 100644 Documentation/devicetree/bindings/watchdog/renesas-wdt.txt

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
new file mode 100644
index 0000000..2c0b03a
--- /dev/null
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -0,0 +1,45 @@
+Renesas Watchdog Timer (WDT) Controller
+
+Required properties:
+ - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
+		fallback compatible string when compatible with the generic
+		version.
+	       Examples with soctypes are:
+		 - "renesas,r8a7743-wdt" (RZ/G1M)
+		 - "renesas,r8a7745-wdt" (RZ/G1E)
+		 - "renesas,r8a774a1-wdt" (RZ/G2M)
+		 - "renesas,r8a774c0-wdt" (RZ/G2E)
+	         - "renesas,r8a7790-wdt" (R-Car H2)
+	         - "renesas,r8a7791-wdt" (R-Car M2-W)
+	         - "renesas,r8a7792-wdt" (R-Car V2H)
+	         - "renesas,r8a7793-wdt" (R-Car M2-N)
+	         - "renesas,r8a7794-wdt" (R-Car E2)
+	         - "renesas,r8a7795-wdt" (R-Car H3)
+	         - "renesas,r8a7796-wdt" (R-Car M3-W)
+		 - "renesas,r8a77965-wdt" (R-Car M3-N)
+	         - "renesas,r8a77970-wdt" (R-Car V3M)
+	         - "renesas,r8a77990-wdt" (R-Car E3)
+	         - "renesas,r8a77995-wdt" (R-Car D3)
+	         - "renesas,r7s72100-wdt" (RZ/A1)
+		The generic compatible string must be:
+		 - "renesas,rza-wdt" for RZ/A
+		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1
+		 - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2
+
+- reg : Should contain WDT registers location and length
+- clocks : the clock feeding the watchdog timer.
+
+Optional properties:
+- timeout-sec : Contains the watchdog timeout in seconds
+- power-domains : the power domain the WDT belongs to
+- interrupts: Some WDTs have an interrupt when used in interval timer mode
+
+Examples:
+
+	wdt0: watchdog at e6020000 {
+		compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
+		reg = <0 0xe6020000 0 0x0c>;
+		clocks = <&cpg CPG_MOD 402>;
+		power-domains = <&cpg>;
+		timeout-sec = <60>;
+	};
diff --git a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
deleted file mode 100644
index 2c0b03a..0000000
--- a/Documentation/devicetree/bindings/watchdog/renesas-wdt.txt
+++ /dev/null
@@ -1,45 +0,0 @@
-Renesas Watchdog Timer (WDT) Controller
-
-Required properties:
- - compatible : Must be "renesas,<soctype>-wdt", followed by a generic
-		fallback compatible string when compatible with the generic
-		version.
-	       Examples with soctypes are:
-		 - "renesas,r8a7743-wdt" (RZ/G1M)
-		 - "renesas,r8a7745-wdt" (RZ/G1E)
-		 - "renesas,r8a774a1-wdt" (RZ/G2M)
-		 - "renesas,r8a774c0-wdt" (RZ/G2E)
-	         - "renesas,r8a7790-wdt" (R-Car H2)
-	         - "renesas,r8a7791-wdt" (R-Car M2-W)
-	         - "renesas,r8a7792-wdt" (R-Car V2H)
-	         - "renesas,r8a7793-wdt" (R-Car M2-N)
-	         - "renesas,r8a7794-wdt" (R-Car E2)
-	         - "renesas,r8a7795-wdt" (R-Car H3)
-	         - "renesas,r8a7796-wdt" (R-Car M3-W)
-		 - "renesas,r8a77965-wdt" (R-Car M3-N)
-	         - "renesas,r8a77970-wdt" (R-Car V3M)
-	         - "renesas,r8a77990-wdt" (R-Car E3)
-	         - "renesas,r8a77995-wdt" (R-Car D3)
-	         - "renesas,r7s72100-wdt" (RZ/A1)
-		The generic compatible string must be:
-		 - "renesas,rza-wdt" for RZ/A
-		 - "renesas,rcar-gen2-wdt" for R-Car Gen2 and RZ/G1
-		 - "renesas,rcar-gen3-wdt" for R-Car Gen3 and RZ/G2
-
-- reg : Should contain WDT registers location and length
-- clocks : the clock feeding the watchdog timer.
-
-Optional properties:
-- timeout-sec : Contains the watchdog timeout in seconds
-- power-domains : the power domain the WDT belongs to
-- interrupts: Some WDTs have an interrupt when used in interval timer mode
-
-Examples:
-
-	wdt0: watchdog at e6020000 {
-		compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
-		reg = <0 0xe6020000 0 0x0c>;
-		clocks = <&cpg CPG_MOD 402>;
-		power-domains = <&cpg>;
-		timeout-sec = <60>;
-	};
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 03/12] dt-bindings: watchdog: renesas-wdt: Document r8a774b1 support

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 758622581489b159286eeb9b9cc8d24382a610ec upstream.

RZ/G2N (a.k.a. R8A774B1) watchdog implementation is compatible
with R-Car Gen3, therefore add the relevant documentation.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/watchdog/renesas,wdt.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
index 2c0b03a..71f419d 100644
--- a/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
+++ b/Documentation/devicetree/bindings/watchdog/renesas,wdt.txt
@@ -8,6 +8,7 @@ Required properties:
 		 - "renesas,r8a7743-wdt" (RZ/G1M)
 		 - "renesas,r8a7745-wdt" (RZ/G1E)
 		 - "renesas,r8a774a1-wdt" (RZ/G2M)
+		 - "renesas,r8a774b1-wdt" (RZ/G2N)
 		 - "renesas,r8a774c0-wdt" (RZ/G2E)
 	         - "renesas,r8a7790-wdt" (R-Car H2)
 	         - "renesas,r8a7791-wdt" (R-Car M2-W)
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 04/12] arm64: dts: renesas: r8a774b1: Add RWDT node

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 7213aea4afad4a0642157fce76eb88736bb9b29f upstream.

Populate the device tree node for the Watchdog Timer (RWDT)
controller on the Renesas RZ/G2N (r8a774b1) SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570178133-21532-5-git-send-email-fabrizio.castro at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index f42f646..de904426 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -127,8 +127,13 @@
 		ranges;
 
 		rwdt: watchdog at e6020000 {
+			compatible = "renesas,r8a774b1-wdt",
+				     "renesas,rcar-gen3-wdt";
 			reg = <0 0xe6020000 0 0x0c>;
-			/* placeholder */
+			clocks = <&cpg CPG_MOD 402>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 402>;
+			status = "disabled";
 		};
 
 		gpio0: gpio at e6050000 {
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream.

Add the device nodes for all MSIOF SPI controllers on the RZ/G2N
SoC (a.k.a. r8a774b1).

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570178133-21532-6-git-send-email-fabrizio.castro at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 62 +++++++++++++++++++++++++++++++
 1 file changed, 62 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index de904426..aede2b3 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -650,6 +650,68 @@
 			status = "disabled";
 		};
 
+		msiof0: spi at e6e90000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 211>;
+			dmas = <&dmac1 0x41>, <&dmac1 0x40>,
+			       <&dmac2 0x41>, <&dmac2 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 211>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi at e6ea0000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 210>;
+			dmas = <&dmac1 0x43>, <&dmac1 0x42>,
+			       <&dmac2 0x43>, <&dmac2 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 210>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi at e6c00000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 209>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 209>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi at e6c10000 {
+			compatible = "renesas,msiof-r8a774b1",
+				     "renesas,rcar-gen3-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 208>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>;
+			dma-names = "tx", "rx";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 208>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		rcar_sound: sound at ec500000 {
 			reg = <0 0xec500000 0 0x1000>, /* SCU */
 			      <0 0xec5a0000 0 0x100>,  /* ADG */
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 06/12] arm64: dts: renesas: r8a774b1: Add PCIe device nodes

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit b3ddadfa28315c6417866eac35a3aee67fc06aa3 upstream.

This patch adds PCIe{0,1} device nodes for R8A774B1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Andrew Murray <andrew.murray@arm.com>
Link: https://lore.kernel.org/r/1570178133-21532-7-git-send-email-fabrizio.castro at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 42 +++++++++++++++++++++++++++++--
 1 file changed, 40 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index aede2b3..2e6bca7 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -811,19 +811,57 @@
 		};
 
 		pciec0: pcie at fe000000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
 			reg = <0 0xfe000000 0 0x80000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
-			/* placeholder */
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000
+				  0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000
+				  0x02000000 0 0x30000000 0 0x30000000 0 0x08000000
+				  0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 319>;
+			status = "disabled";
 		};
 
 		pciec1: pcie at ee800000 {
+			compatible = "renesas,pcie-r8a774b1",
+				     "renesas,pcie-rcar-gen3";
 			reg = <0 0xee800000 0 0x80000>;
 			#address-cells = <3>;
 			#size-cells = <2>;
 			bus-range = <0x00 0xff>;
-			/* placeholder */
+			device_type = "pci";
+			ranges = <0x01000000 0 0x00000000 0 0xee900000 0 0x00100000
+				  0x02000000 0 0xeea00000 0 0xeea00000 0 0x00200000
+				  0x02000000 0 0xc0000000 0 0xc0000000 0 0x08000000
+				  0x42000000 0 0xc8000000 0 0xc8000000 0 0x08000000>;
+			/* Map all possible DDR as inbound ranges */
+			dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>;
+			interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>,
+				     <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+			#interrupt-cells = <1>;
+			interrupt-map-mask = <0 0 0 0>;
+			interrupt-map = <0 0 0 0 &gic GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 318>, <&pcie_bus_clk>;
+			clock-names = "pcie", "pcie_bus";
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 318>;
+			status = "disabled";
 		};
 
 		hdmi0: hdmi at fead0000 {
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 07/12] arm64: dts: renesas: hihope-rzg2-ex: Let the board specific DT decide about pciec1

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 133e6c78c4937ea7449cf8542b14f7b37bf470ac upstream.

The plan for the HiHope RZ/G2N board is to enable pciec0 by default,
and use pciec1 physical interface for SATA (as SATA and PCIE1 share
the same physical interface), therefore move pciec1 enabling away
from hihope-rzg2-ex.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570178133-21532-8-git-send-email-fabrizio.castro at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi          | 4 ----
 arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts | 4 ++++
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
index 4280b19..6870e22 100644
--- a/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
+++ b/arch/arm64/boot/dts/renesas/hihope-rzg2-ex.dtsi
@@ -47,10 +47,6 @@
 	status = "okay";
 };
 
-&pciec1 {
-	status = "okay";
-};
-
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
diff --git a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
index 6e33a3b..c754fca 100644
--- a/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774a1-hihope-rzg2m-ex.dts
@@ -13,3 +13,7 @@
 	compatible = "hoperun,hihope-rzg2-ex", "hoperun,hihope-rzg2m",
 		     "renesas,r8a774a1";
 };
+
+&pciec1 {
+	status = "okay";
+};
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 08/12] arm64: dts: renesas: r8a774b1: Add INTC-EX device node

[Biju Das]

From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>

commit 04360e4112c3e0e35c08b7fd8d0b2f6e68be4935 upstream.

Add support for the Interrupt Controller for External Devices
(INTC-EX) on RZ/G2N.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Link: https://lore.kernel.org/r/1570531132-21856-11-git-send-email-fabrizio.castro at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 2e6bca7..46578de 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -282,6 +282,22 @@
 			#power-domain-cells = <1>;
 		};
 
+		intc_ex: interrupt-controller at e61c0000 {
+			compatible = "renesas,intc-ex-r8a774b1", "renesas,irqc";
+			#interrupt-cells = <2>;
+			interrupt-controller;
+			reg = <0 0xe61c0000 0 0x200>;
+			interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+				      GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 407>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 407>;
+		};
+
 		i2c4: i2c at e66d8000 {
 			#address-cells = <1>;
 			#size-cells = <0>;
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 09/12] dt-bindings: mmc: renesas_sdhi: Add r8a774b1 support

[Biju Das]

From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Document RZ/G2N (R8A774B1) SoC bindings.

This patch is similar to commit 01a5674301fa790d05e1d2c888c9c98370082d45
("dt-bindings: mmc: renesas_sdhi: Add r8a774b1 support") in mainline
kernel, but since tmio_mmc.txt is renamed to renesas,sdhi.txt due to split
of core functionality, DMA and MFD glue in mainline kernel in commit
b6147490e6aa ("mmc: tmio: split core functionality, DMA and MFD glue")

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 Documentation/devicetree/bindings/mmc/tmio_mmc.txt | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
index ac5c93c..d50c6cb 100644
--- a/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
+++ b/Documentation/devicetree/bindings/mmc/tmio_mmc.txt
@@ -18,6 +18,7 @@ Required properties:
 		"renesas,sdhi-r8a7743" - SDHI IP on R8A7743 SoC
 		"renesas,sdhi-r8a7745" - SDHI IP on R8A7745 SoC
 		"renesas,sdhi-r8a774a1" - SDHI IP on R8A774A1 SoC
+		"renesas,sdhi-r8a774b1" - SDHI IP on R8A774B1 SoC
 		"renesas,sdhi-r8a774c0" - SDHI IP on R8A774C0 SoC
 		"renesas,sdhi-r8a77470" - SDHI IP on R8A77470 SoC
 		"renesas,sdhi-mmc-r8a77470" - SDHI/MMC IP on R8A77470 SoC
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 10/12] mmc: renesas_sdhi_internal_dmac: Add r8a774b1 support

[Biju Das]

commit c9af138c42f07a0d6d8554a9bed85ca395ed0511 upstream.

This patch adds SDHI support for RZ/G2N (R8A774B1) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 drivers/mmc/host/renesas_sdhi_internal_dmac.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/drivers/mmc/host/renesas_sdhi_internal_dmac.c b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
index 7b0bc15..d156158 100644
--- a/drivers/mmc/host/renesas_sdhi_internal_dmac.c
+++ b/drivers/mmc/host/renesas_sdhi_internal_dmac.c
@@ -300,6 +300,7 @@ static const struct soc_device_attribute gen3_soc_whitelist[] = {
 	  .data = (void *)BIT(SDHI_INTERNAL_DMAC_ONE_RX_ONLY) },
 	/* generic ones */
 	{ .soc_id = "r8a774a1" },
+	{ .soc_id = "r8a774b1" },
 	{ .soc_id = "r8a774c0" },
 	{ .soc_id = "r8a7795" },
 	{ .soc_id = "r8a7796" },
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 11/12] arm64: dts: renesas: r8a774b1: Add SDHI support

[Biju Das]

commit 6317736729acbdb5bd58cb5ee0ba5f354bd51830 upstream.

Add SDHI support for the r8a774b1 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569313375-53428-2-git-send-email-biju.das at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1.dtsi | 36 +++++++++++++++++++++++++++----
 1 file changed, 32 insertions(+), 4 deletions(-)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 46578de..08f98b6 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -790,23 +790,51 @@
 		};
 
 		sdhi0: sd at ee100000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee100000 0 0x2000>;
-			/* placeholder */
+			interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 314>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 314>;
+			status = "disabled";
 		};
 
 		sdhi1: sd at ee120000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee120000 0 0x2000>;
-			/* placeholder */
+			interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 313>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 313>;
+			status = "disabled";
 		};
 
 		sdhi2: sd at ee140000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee140000 0 0x2000>;
-			/* placeholder */
+			interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 312>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 312>;
+			status = "disabled";
 		};
 
 		sdhi3: sd at ee160000 {
+			compatible = "renesas,sdhi-r8a774b1",
+				     "renesas,rcar-gen3-sdhi";
 			reg = <0 0xee160000 0 0x2000>;
-			/* placeholder */
+			interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 311>;
+			max-frequency = <200000000>;
+			power-domains = <&sysc R8A774B1_PD_ALWAYS_ON>;
+			resets = <&cpg 311>;
+			status = "disabled";
 		};
 
 		gic: interrupt-controller at f1010000 {
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 12/12] arm64: dts: renesas: r8a774b1-hihope-rzg2n: Enable HS400 mode

[Biju Das]

commit 048b39fae795c713c465b6e1d55089334535d862 upstream.

This patch enables HS400 mode on HiHope RZ/G2N board.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569837778-55874-1-git-send-email-biju.das at bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
 arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts
index 094b5ef..c9e2119 100644
--- a/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts
+++ b/arch/arm64/boot/dts/renesas/r8a774b1-hihope-rzg2n.dts
@@ -24,3 +24,7 @@
 		reg = <0x4 0x80000000 0x0 0x80000000>;
 	};
 };
+
+&sdhi3 {
+	mmc-hs400-1_8v;
+};
-- 
2.7.4

[cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Pavel Machek]

On Wed 2020-01-29 14:29:58, Biju Das wrote:
> From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> 
> commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream.
> 
> Add the device nodes for all MSIOF SPI controllers on the RZ/G2N
> SoC (a.k.a. r8a774b1).

I googled a bit, and MSIOF SPI seems to be "slave" controller on
SPI. But I still don't know what "MSIOF" stands for, if anything.

Best regards,
								Pavel
								
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Prabhakar Mahadev Lad]

Hi Pavel,

> -----Original Message-----
> From: cip-dev <cip-dev-bounces@lists.cip-project.org> On Behalf Of Pavel
> Machek
> Sent: 30 January 2020 19:27
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: cip-dev at lists.cip-project.org
> Subject: Re: [cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas:
> r8a774b1: Add all MSIOF nodes
>
> On Wed 2020-01-29 14:29:58, Biju Das wrote:
> > From: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
> >
> > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream.
> >
> > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N SoC
> > (a.k.a. r8a774b1).
>
> I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I still
> don't know what "MSIOF" stands for, if anything.
>
"MSIOF" stands for clock-synchronized serial interface with FIFO, this interface supports IIS and
SPI serial formats (master and slave mode). ATM only SPI master mode is supported in mainline
Kernel.

Cheers,
--Prabhakar

> Best regards,
> Pavel
>
> --
> DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

[cip-dev] [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral support

[Pavel Machek]

Hi!

> This patch series adds support for following peripherals supported by RZ
> G2N,
> 1: SDHI
> 2: Watchdog
> 3: MSIOF
> 4: PCIE
> 
> Please note this patch series is based on top of the series [1].
> 
> [1] https://patchwork.kernel.org/project/cip-dev/list/?series=233689&submitter=&state=*&q=&archive=both&delegate=

Series looks good to me, thanks. I guess Iwamatsu-san can apply both
series if there are no objections, alternatively I can apply one or
both of series.

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[cip-dev] [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral support

[nobuhiro1.iwamatsu at toshiba.co.jp]

Hi,

> -----Original Message-----
> From: Pavel Machek [mailto:pavel at denx.de]
> Sent: Friday, January 31, 2020 7:45 AM
> To: Biju Das <biju.das@bp.renesas.com>
> Cc: cip-dev at lists.cip-project.org; iwamatsu nobuhiro(?? ?? ???
> ?????) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> <pavel@denx.de>; Chris Paterson <chris.paterson2@renesas.com>
> Subject: Re: [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral
> support
> 
> Hi!
> 
> > This patch series adds support for following peripherals supported by
> > RZ G2N,
> > 1: SDHI
> > 2: Watchdog
> > 3: MSIOF
> > 4: PCIE
> >
> > Please note this patch series is based on top of the series [1].
> >
> > [1]
> >
> https://patchwork.kernel.org/project/cip-dev/list/?series=233689&sub
> mi
> > tter=&state=*&q=&archive=both&delegate=
> 
> Series looks good to me, thanks. I guess Iwamatsu-san can apply both series
> if there are no objections, alternatively I can apply one or both of
> series.

This series looks good to me too.
And sorry, I had applied the previous series but had not contacted.

I applied and pushed this.

Best regards,
  Nobuhiro

[cip-dev] [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral support

[Prabhakar Mahadev Lad]

Hi,

> -----Original Message-----
> From: cip-dev <cip-dev-bounces@lists.cip-project.org> On Behalf Of
> nobuhiro1.iwamatsu at toshiba.co.jp
> Sent: 31 January 2020 03:55
> To: pavel at denx.de; biju.das at bp.renesas.com
> Cc: cip-dev at lists.cip-project.org
> Subject: Re: [cip-dev] [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend
> peripheral support
>
> Hi,
>
> > -----Original Message-----
> > From: Pavel Machek [mailto:pavel at denx.de]
> > Sent: Friday, January 31, 2020 7:45 AM
> > To: Biju Das <biju.das@bp.renesas.com>
> > Cc: cip-dev at lists.cip-project.org; iwamatsu nobuhiro(?? ?? ???
> > ?????) <nobuhiro1.iwamatsu@toshiba.co.jp>; Pavel Machek
> > <pavel@denx.de>; Chris Paterson <chris.paterson2@renesas.com>
> > Subject: Re: [PATCH 4.19.y-cip 00/12] Renesas RZ/G2N extend peripheral
> > support
> >
> > Hi!
> >
> > > This patch series adds support for following peripherals supported
> > > by RZ G2N,
> > > 1: SDHI
> > > 2: Watchdog
> > > 3: MSIOF
> > > 4: PCIE
> > >
> > > Please note this patch series is based on top of the series [1].
> > >
> > > [1]
> > >
> > https://patchwork.kernel.org/project/cip-dev/list/?series=233689&sub
> > mi
> > > tter=&state=*&q=&archive=both&delegate=
> >
> > Series looks good to me, thanks. I guess Iwamatsu-san can apply both
> > series if there are no objections, alternatively I can apply one or
> > both of series.
>
> This series looks good to me too.
> And sorry, I had applied the previous series but had not contacted.
>
> I applied and pushed this.
>
Thank you for the review and acceptance.

Cheers,
--Prabhakar

> Best regards,
>   Nobuhiro
>
> _______________________________________________
> cip-dev mailing list
> cip-dev at lists.cip-project.org
> https://lists.cip-project.org/mailman/listinfo/cip-dev


Renesas Electronics Europe GmbH, Geschaeftsfuehrer/President: Carsten Jauch, Sitz der Gesellschaft/Registered office: Duesseldorf, Arcadiastrasse 10, 40472 Duesseldorf, Germany, Handelsregister/Commercial Register: Duesseldorf, HRB 3708 USt-IDNr./Tax identification no.: DE 119353406 WEEE-Reg.-Nr./WEEE reg. no.: DE 14978647

[cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Pavel Machek]

Hi!

> > > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream.
> > >
> > > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N SoC
> > > (a.k.a. r8a774b1).
> >
> > I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I still
> > don't know what "MSIOF" stands for, if anything.
> >
> "MSIOF" stands for clock-synchronized serial interface with FIFO, this interface supports IIS and
> SPI serial formats (master and slave mode). ATM only SPI master mode is supported in mainline
> Kernel.

Ok, I can imagine that. But is "MSIOF" an acronym, and if so, what
does it stand for?

Best regards,
								Pavel
-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
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[cip-dev] [PATCH 4.19.y-cip 05/12] arm64: dts: renesas: r8a774b1: Add all MSIOF nodes

[Chris Paterson]

Hello Pavel,

> From: cip-dev <cip-dev-bounces@lists.cip-project.org> On Behalf Of Pavel
> Machek
> Sent: 02 February 2020 18:01
>
> Hi!
>
> > > > commit c88657c4a1ead900cf59d87511d7deee41ed92a5 upstream.
> > > >
> > > > Add the device nodes for all MSIOF SPI controllers on the RZ/G2N SoC
> > > > (a.k.a. r8a774b1).
> > >
> > > I googled a bit, and MSIOF SPI seems to be "slave" controller on SPI. But I
> still
> > > don't know what "MSIOF" stands for, if anything.
> > >
> > "MSIOF" stands for clock-synchronized serial interface with FIFO, this
> interface supports IIS and
> > SPI serial formats (master and slave mode). ATM only SPI master mode is
> supported in mainline
> > Kernel.
>
> Ok, I can imagine that. But is "MSIOF" an acronym, and if so, what
> does it stand for?

To be honest, even I'm not sure what the acronym is meant to mean (or even if there is a direct meaning), but the 'long' name for the IP block is "Clock-Synchronized Serial Interface with FIFO".

Kind regards, Chris

>
> Best regards,
> ????? ??????? ??????? ??????? ??????? ??????? ??????? ??????? Pavel
> --
> DENX Software Engineering GmbH,????? Managing Director: Wolfgang Denk
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany