[PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV

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* [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV
@ 2020-02-18  2:54 Monk Liu
  2020-02-18  2:54 ` [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test Monk Liu
                   ` (2 more replies)
  0 siblings, 3 replies; 16+ messages in thread
From: Monk Liu @ 2020-02-18  2:54 UTC (permalink / raw)
  To: amd-gfx; +Cc: Monk Liu

SWDEV-220810 - some register access from VF is wrong

1)
we shouldn't load PSP kdb and sys/sos for VF, they are
supposed to be handled by hypervisor

2)
ih reroute doesn't work on VF thus we should avoid calling
it, besides VF should not use those PSP register sets for PF

3)
shouldn't load SMU ucode under SRIOV, otherwise PSP would report
error

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--
 drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index a16c810..3494966 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1081,7 +1081,7 @@ static int psp_hw_start(struct psp_context *psp)
 	struct amdgpu_device *adev = psp->adev;
 	int ret;
 
-	if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
+	if (!amdgpu_sriov_vf(adev) && !adev->in_gpu_reset) {
 		if (psp->kdb_bin_size &&
 		    (psp->funcs->bootloader_load_kdb != NULL)) {
 			ret = psp_bootloader_load_kdb(psp);
@@ -1318,7 +1318,7 @@ static int psp_np_fw_load(struct psp_context *psp)
 
 	if (psp->autoload_supported) {
 		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
-		if (!ucode->fw)
+		if (!ucode->fw || amdgpu_sriov_vf(adev))
 			goto out;
 
 		ret = psp_execute_np_fw_load(psp, ucode);
diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0829188..8ab3bf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -420,7 +420,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
 	struct psp_ring *ring;
 	struct amdgpu_device *adev = psp->adev;
 
-	psp_v11_0_reroute_ih(psp);
+	if (!amdgpu_sriov_vf(adev))
+		psp_v11_0_reroute_ih(psp);
 
 	ring = &psp->km_ring;
 
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test
  2020-02-18  2:54 [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Monk Liu
@ 2020-02-18  2:54 ` Monk Liu
  2020-02-18 11:10   ` Zhang, Hawking
  2020-02-18  2:54 ` [PATCH 3/3] drm/amdgpu: fix colliding of preemption Monk Liu
  2020-02-18 11:08 ` [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Zhang, Hawking
  2 siblings, 1 reply; 16+ messages in thread
From: Monk Liu @ 2020-02-18  2:54 UTC (permalink / raw)
  To: amd-gfx; +Cc: Monk Liu

fix system memory leak regression introduced
by this previous change of 201331 - Single VF Mode Test

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9d15acf..3363f1c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -978,8 +978,12 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 	int ret = 0;
 
-	max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
+	if (smu->smu_table.max_sustainable_clocks == NULL)
+		max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
 					 GFP_KERNEL);
+	else
+		max_sustainable_clocks = smu->smu_table.max_sustainable_clocks;
+
 	smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 
 	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18  2:54 [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Monk Liu
  2020-02-18  2:54 ` [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test Monk Liu
@ 2020-02-18  2:54 ` Monk Liu
  2020-02-18 11:32   ` Zhang, Hawking
  2020-02-18 11:08 ` [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Zhang, Hawking
  2 siblings, 1 reply; 16+ messages in thread
From: Monk Liu @ 2020-02-18  2:54 UTC (permalink / raw)
  To: amd-gfx; +Cc: Monk Liu

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but
there is still UMD side issues not resovlved yet, so this patch
cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index);
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
 {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
-- 
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* RE: [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV
  2020-02-18  2:54 [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Monk Liu
  2020-02-18  2:54 ` [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test Monk Liu
  2020-02-18  2:54 ` [PATCH 3/3] drm/amdgpu: fix colliding of preemption Monk Liu
@ 2020-02-18 11:08 ` Zhang, Hawking
  2 siblings, 0 replies; 16+ messages in thread
From: Zhang, Hawking @ 2020-02-18 11:08 UTC (permalink / raw)
  To: Liu, Monk, amd-gfx; +Cc: Liu, Monk

[AMD Official Use Only - Internal Distribution Only]

Please remove the ticket number from the commit description. With that fixed, the patch is

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV

SWDEV-220810 - some register access from VF is wrong

1)
we shouldn't load PSP kdb and sys/sos for VF, they are supposed to be handled by hypervisor

2)
ih reroute doesn't work on VF thus we should avoid calling it, besides VF should not use those PSP register sets for PF

3)
shouldn't load SMU ucode under SRIOV, otherwise PSP would report error

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c | 4 ++--  drivers/gpu/drm/amd/amdgpu/psp_v11_0.c  | 3 ++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index a16c810..3494966 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1081,7 +1081,7 @@ static int psp_hw_start(struct psp_context *psp)
 	struct amdgpu_device *adev = psp->adev;
 	int ret;
 
-	if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
+	if (!amdgpu_sriov_vf(adev) && !adev->in_gpu_reset) {
 		if (psp->kdb_bin_size &&
 		    (psp->funcs->bootloader_load_kdb != NULL)) {
 			ret = psp_bootloader_load_kdb(psp);
@@ -1318,7 +1318,7 @@ static int psp_np_fw_load(struct psp_context *psp)
 
 	if (psp->autoload_supported) {
 		ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
-		if (!ucode->fw)
+		if (!ucode->fw || amdgpu_sriov_vf(adev))
 			goto out;
 
 		ret = psp_execute_np_fw_load(psp, ucode); diff --git a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
index 0829188..8ab3bf3 100644
--- a/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/psp_v11_0.c
@@ -420,7 +420,8 @@ static int psp_v11_0_ring_init(struct psp_context *psp,
 	struct psp_ring *ring;
 	struct amdgpu_device *adev = psp->adev;
 
-	psp_v11_0_reroute_ih(psp);
+	if (!amdgpu_sriov_vf(adev))
+		psp_v11_0_reroute_ih(psp);
 
 	ring = &psp->km_ring;
 
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* RE: [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test
  2020-02-18  2:54 ` [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test Monk Liu
@ 2020-02-18 11:10   ` Zhang, Hawking
  0 siblings, 0 replies; 16+ messages in thread
From: Zhang, Hawking @ 2020-02-18 11:10 UTC (permalink / raw)
  To: Liu, Monk, amd-gfx; +Cc: Liu, Monk

[AMD Official Use Only - Internal Distribution Only]

! smu->smu_table.max_sustainable_clocks is the preferred coding style. And please also remove internal changelist no from commit description.

With above addressed, the patch is

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>

Regards,
Hawking
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test

fix system memory leak regression introduced by this previous change of 201331 - Single VF Mode Test

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/powerplay/smu_v11_0.c | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
index 9d15acf..3363f1c 100644
--- a/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
+++ b/drivers/gpu/drm/amd/powerplay/smu_v11_0.c
@@ -978,8 +978,12 @@ int smu_v11_0_init_max_sustainable_clocks(struct smu_context *smu)
 	struct smu_11_0_max_sustainable_clocks *max_sustainable_clocks;
 	int ret = 0;
 
-	max_sustainable_clocks = kzalloc(sizeof(struct smu_11_0_max_sustainable_clocks),
+	if (smu->smu_table.max_sustainable_clocks == NULL)
+		max_sustainable_clocks = kzalloc(sizeof(struct 
+smu_11_0_max_sustainable_clocks),
 					 GFP_KERNEL);
+	else
+		max_sustainable_clocks = smu->smu_table.max_sustainable_clocks;
+
 	smu->smu_table.max_sustainable_clocks = (void *)max_sustainable_clocks;
 
 	max_sustainable_clocks->uclock = smu->smu_table.boot_values.uclk / 100;
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18  2:54 ` [PATCH 3/3] drm/amdgpu: fix colliding of preemption Monk Liu
@ 2020-02-18 11:32   ` Zhang, Hawking
  2020-02-18 11:48     ` Zhang, Hawking
  2020-02-18 12:19     ` Liu, Monk
  0 siblings, 2 replies; 16+ messages in thread
From: Zhang, Hawking @ 2020-02-18 11:32 UTC (permalink / raw)
  To: Liu, Monk, amd-gfx; +Cc: Liu, Monk

[AMD Official Use Only - Internal Distribution Only]

It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.

I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & 
+AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 11:32   ` Zhang, Hawking
@ 2020-02-18 11:48     ` Zhang, Hawking
  2020-02-18 12:29       ` 回复: " Liu, Monk
  2020-02-18 12:19     ` Liu, Monk
  1 sibling, 1 reply; 16+ messages in thread
From: Zhang, Hawking @ 2020-02-18 11:48 UTC (permalink / raw)
  To: Zhang, Hawking, Liu, Monk, amd-gfx; +Cc: Liu, Monk

[AMD Official Use Only - Internal Distribution Only]

Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking
Sent: Tuesday, February 18, 2020 19:32
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.

I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & 
+AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 11:32   ` Zhang, Hawking
  2020-02-18 11:48     ` Zhang, Hawking
@ 2020-02-18 12:19     ` Liu, Monk
  1 sibling, 0 replies; 16+ messages in thread
From: Liu, Monk @ 2020-02-18 12:19 UTC (permalink / raw)
  To: Zhang, Hawking, amd-gfx

Hi Hawking

The problem is amdgpu_mcbp only controls OS preemption feature, and OS preemption cannot enabled together with world switch MCBP 
That's why we still need to differentiate them separately

Besides, there are some logic handling different between them, you can check the details in my patch:

@@ -4522,9 +4522,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
 {
        uint32_t dw2 = 0;

-       if (amdgpu_mcbp)
+       if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
                gfx_v10_0_ring_emit_ce_meta(ring,
-                                   flags & AMDGPU_IB_PREEMPTED ? true : false);
+                                   (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);



@@ -4369,7 +4369,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,

                if (!(ib->flags & AMDGPU_IB_FLAG_CE))
                        gfx_v10_0_ring_emit_de_meta(ring,
-                                   flags & AMDGPU_IB_PREEMPTED ? true : false);
+                                   (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);



-       if (vmid == 0 || !amdgpu_mcbp)
+       /* don't enable OS preemption on SDMA under SRIOV */
+       if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
                return 0;


see that above three part need different handling for OS preemption and world switch preemption 

BTW: the OS preemption implement in our driver is actually not too perfect to me, e.g.: the CSA buffer is static (which is what SRIOV want), and static CSA buffer cannot handle double preemption case sequence like :
MCBP in IB-A --> run IB-B --> and MCBP in IB-B, since we are using static CSA, so the MCBP on IB-B will overwrite CSA content which is left by MCBP in IB-A, so IB-A resume will not work. But it is not my interest currently so I didn’t touch OS preemption path

thanks !


-----邮件原件-----
发件人: Zhang, Hawking <Hawking.Zhang@amd.com> 
发送时间: 2020年2月18日 19:32
收件人: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
抄送: Liu, Monk <Monk.Liu@amd.com>
主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.

I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & 
+AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 11:48     ` Zhang, Hawking
@ 2020-02-18 12:29       ` Liu, Monk
  2020-02-18 12:39         ` Christian König
  2020-02-18 14:54         ` Zhang, Hawking
  0 siblings, 2 replies; 16+ messages in thread
From: Liu, Monk @ 2020-02-18 12:29 UTC (permalink / raw)
  To: Zhang, Hawking, amd-gfx

Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.: 
In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, and we do the same thing under that condition,
But we cannot do that thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV case. Because that will let OS preemption work, which will trigger mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such colliding)

So we always need to disable OS preemption behavior for SRIOV (don't to preempt an IB by touch vmid_preempt register, and no IB resume happen)

Thanks 


-----邮件原件-----
发件人: Zhang, Hawking <Hawking.Zhang@amd.com> 
发送时间: 2020年2月18日 19:48
收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
抄送: Liu, Monk <Monk.Liu@amd.com>
主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking
Sent: Tuesday, February 18, 2020 19:32
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.

I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & 
+AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* Re: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 12:29       ` 回复: " Liu, Monk
@ 2020-02-18 12:39         ` Christian König
  2020-02-18 12:53           ` 回复: " Liu, Monk
  2020-02-18 14:54         ` Zhang, Hawking
  1 sibling, 1 reply; 16+ messages in thread
From: Christian König @ 2020-02-18 12:39 UTC (permalink / raw)
  To: Liu, Monk, Zhang, Hawking, amd-gfx

Hawking is right here. We could just check amdgpu_mcbp during device 
initialization and forcefully clear it under SRIOV.

But why is MCBP and SRIOV mutual exclusive? We are certainly getting the 
requirement for this sooner or later.

Regards,
Christian.

Am 18.02.20 um 13:29 schrieb Liu, Monk:
> Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.:
> In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, and we do the same thing under that condition,
> But we cannot do that thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV case. Because that will let OS preemption work, which will trigger mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such colliding)
>
> So we always need to disable OS preemption behavior for SRIOV (don't to preempt an IB by touch vmid_preempt register, and no IB resume happen)
>
> Thanks
>
>
> -----邮件原件-----
> 发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
> 发送时间: 2020年2月18日 19:48
> 收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> 抄送: Liu, Monk <Monk.Liu@amd.com>
> 主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking
> Sent: Tuesday, February 18, 2020 19:32
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.
>
> I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
> Sent: Tuesday, February 18, 2020 10:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> what:
> some os preemption path is messed up with world switch preemption
>
> fix:
> cleanup those logics so os preemption not mixed with world switch
>
> this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
>   2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index a2ee30b..7854c05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
>   	uint32_t index = 0;
>   	int r;
>   
> -	if (vmid == 0 || !amdgpu_mcbp)
> +	/* don't enable OS preemption on SDMA under SRIOV */
> +	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
>   		return 0;
>   
>   	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 5e9fb09..7b61583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   
>   	control |= ib->length_dw | (vmid << 24);
>   
> -	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
> +	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
> +AMDGPU_IB_FLAG_PREEMPT)) {
>   		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
>   		if (flags & AMDGPU_IB_PREEMPTED)
> @@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
>   
>   		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
>   			gfx_v10_0_ring_emit_de_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   	}
>   
>   	amdgpu_ring_write(ring, header);
> @@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
>   	uint32_t dw2 = 0;
>   
> -	if (amdgpu_mcbp)
> +	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
>   		gfx_v10_0_ring_emit_ce_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Chawking.zhang%40amd.com%7Ca7e465ef5e31462f53bb08d7b4663103%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637176223323017983&amp;sdata=wE%2FWt31a6tCmc9Tt0uHMC1S5XePnAgUFNSlXRDP1oSE%3D&amp;reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flists.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7Chawking.zhang%40amd.com%7Ca7e465ef5e31462f53bb08d7b4663103%7C3dd8961fe4884e608e11a82d994e183d%7C0%7C0%7C637176223323017983&amp;sdata=wE%2FWt31a6tCmc9Tt0uHMC1S5XePnAgUFNSlXRDP1oSE%3D&amp;reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

_______________________________________________
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amd-gfx@lists.freedesktop.org
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^ permalink raw reply	[flat|nested] 16+ messages in thread

* 回复: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 12:39         ` Christian König
@ 2020-02-18 12:53           ` Liu, Monk
  2020-02-18 14:48             ` Fernlund, Hans
  0 siblings, 1 reply; 16+ messages in thread
From: Liu, Monk @ 2020-02-18 12:53 UTC (permalink / raw)
  To: Koenig, Christian, Zhang, Hawking, amd-gfx, Fernlund, Hans

If OS preemption can work with SRIOV world switch I won't provide such patch, I would already clean up those MCBP checking ... 

To your question: I don't know details, but my guess is that CP use the same interface with KMD (e.g. CE/DE meta) to handle two MCBP type: world switch and OS preempt,
But some implementation is different inside CP firmware by the given interface, that need @Fernlund, Hans to provide the details if you want an expertise, he is the author of CP preemption 

Thanks 

-----邮件原件-----
发件人: Christian König <ckoenig.leichtzumerken@gmail.com> 
发送时间: 2020年2月18日 20:40
收件人: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
主题: Re: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

Hawking is right here. We could just check amdgpu_mcbp during device initialization and forcefully clear it under SRIOV.

But why is MCBP and SRIOV mutual exclusive? We are certainly getting the requirement for this sooner or later.

Regards,
Christian.

Am 18.02.20 um 13:29 schrieb Liu, Monk:
> Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.:
> In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, 
> and we do the same thing under that condition, But we cannot do that 
> thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV 
> case. Because that will let OS preemption work, which will trigger 
> mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such 
> colliding)
>
> So we always need to disable OS preemption behavior for SRIOV (don't 
> to preempt an IB by touch vmid_preempt register, and no IB resume 
> happen)
>
> Thanks
>
>
> -----邮件原件-----
> 发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
> 发送时间: 2020年2月18日 19:48
> 收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk 
> <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> 抄送: Liu, Monk <Monk.Liu@amd.com>
> 主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of 
> Zhang, Hawking
> Sent: Tuesday, February 18, 2020 19:32
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.
>
> I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of 
> Monk Liu
> Sent: Tuesday, February 18, 2020 10:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> what:
> some os preemption path is messed up with world switch preemption
>
> fix:
> cleanup those logics so os preemption not mixed with world switch
>
> this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
>   2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c 
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index a2ee30b..7854c05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
>   	uint32_t index = 0;
>   	int r;
>   
> -	if (vmid == 0 || !amdgpu_mcbp)
> +	/* don't enable OS preemption on SDMA under SRIOV */
> +	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
>   		return 0;
>   
>   	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git 
> a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 5e9fb09..7b61583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   
>   	control |= ib->length_dw | (vmid << 24);
>   
> -	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
> +	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
> +AMDGPU_IB_FLAG_PREEMPT)) {
>   		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
>   		if (flags & AMDGPU_IB_PREEMPTED)
> @@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   
>   		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
>   			gfx_v10_0_ring_emit_de_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   	}
>   
>   	amdgpu_ring_write(ring, header);
> @@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
>   	uint32_t dw2 = 0;
>   
> -	if (amdgpu_mcbp)
> +	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
>   		gfx_v10_0_ring_emit_ce_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CMo
> nk.Liu%40amd.com%7C86ae6b396abe40ba179608d7b46facf3%7C3dd8961fe4884e60
> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
> uYuOQ1pdp1IL6QlTA30i8By27iDhg%3D&amp;reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CMo
> nk.Liu%40amd.com%7C86ae6b396abe40ba179608d7b46facf3%7C3dd8961fe4884e60
> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
> uYuOQ1pdp1IL6QlTA30i8By27iDhg%3D&amp;reserved=0
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-gfx&amp;data=02%7C01%7CMo
> nk.Liu%40amd.com%7C86ae6b396abe40ba179608d7b46facf3%7C3dd8961fe4884e60
> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
> uYuOQ1pdp1IL6QlTA30i8By27iDhg%3D&amp;reserved=0

_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx

^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 12:53           ` 回复: " Liu, Monk
@ 2020-02-18 14:48             ` Fernlund, Hans
  2020-02-19  5:04               ` 回复: " Liu, Monk
  0 siblings, 1 reply; 16+ messages in thread
From: Fernlund, Hans @ 2020-02-18 14:48 UTC (permalink / raw)
  To: Liu, Monk, Koenig, Christian, Zhang, Hawking, amd-gfx

[AMD Official Use Only - Internal Distribution Only]

At CP level, MCBP and SRIOV are not mutually exclusive. They are used together in some environments.

/Hans


-----Original Message-----
From: Liu, Monk <Monk.Liu@amd.com> 
Sent: Tuesday, February 18, 2020 7:53 AM
To: Koenig, Christian <Christian.Koenig@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org; Fernlund, Hans <Hans.Fernlund@amd.com>
Subject: 回复: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

If OS preemption can work with SRIOV world switch I won't provide such patch, I would already clean up those MCBP checking ... 

To your question: I don't know details, but my guess is that CP use the same interface with KMD (e.g. CE/DE meta) to handle two MCBP type: world switch and OS preempt, But some implementation is different inside CP firmware by the given interface, that need @Fernlund, Hans to provide the details if you want an expertise, he is the author of CP preemption 

Thanks 

-----邮件原件-----
发件人: Christian König <ckoenig.leichtzumerken@gmail.com>
发送时间: 2020年2月18日 20:40
收件人: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
主题: Re: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

Hawking is right here. We could just check amdgpu_mcbp during device initialization and forcefully clear it under SRIOV.

But why is MCBP and SRIOV mutual exclusive? We are certainly getting the requirement for this sooner or later.

Regards,
Christian.

Am 18.02.20 um 13:29 schrieb Liu, Monk:
> Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.:
> In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, 
> and we do the same thing under that condition, But we cannot do that 
> thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV 
> case. Because that will let OS preemption work, which will trigger 
> mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such
> colliding)
>
> So we always need to disable OS preemption behavior for SRIOV (don't 
> to preempt an IB by touch vmid_preempt register, and no IB resume
> happen)
>
> Thanks
>
>
> -----邮件原件-----
> 发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
> 发送时间: 2020年2月18日 19:48
> 收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk 
> <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> 抄送: Liu, Monk <Monk.Liu@amd.com>
> 主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of 
> Zhang, Hawking
> Sent: Tuesday, February 18, 2020 19:32
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.
>
> I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of 
> Monk Liu
> Sent: Tuesday, February 18, 2020 10:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> what:
> some os preemption path is messed up with world switch preemption
>
> fix:
> cleanup those logics so os preemption not mixed with world switch
>
> this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
>   2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index a2ee30b..7854c05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
>   	uint32_t index = 0;
>   	int r;
>   
> -	if (vmid == 0 || !amdgpu_mcbp)
> +	/* don't enable OS preemption on SDMA under SRIOV */
> +	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
>   		return 0;
>   
>   	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git 
> a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 5e9fb09..7b61583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   
>   	control |= ib->length_dw | (vmid << 24);
>   
> -	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
> +	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
> +AMDGPU_IB_FLAG_PREEMPT)) {
>   		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
>   		if (flags & AMDGPU_IB_PREEMPTED)
> @@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   
>   		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
>   			gfx_v10_0_ring_emit_de_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   	}
>   
>   	amdgpu_ring_write(ring, header);
> @@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
>   	uint32_t dw2 = 0;
>   
> -	if (amdgpu_mcbp)
> +	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
>   		gfx_v10_0_ring_emit_ce_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
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> nk.Liu%40amd.com%7C86ae6b396abe40ba179608d7b46facf3%7C3dd8961fe4884e60
> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
> uYuOQ1pdp1IL6QlTA30i8By27iDhg%3D&amp;reserved=0
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> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
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> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
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> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
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^ permalink raw reply	[flat|nested] 16+ messages in thread

* RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 12:29       ` 回复: " Liu, Monk
  2020-02-18 12:39         ` Christian König
@ 2020-02-18 14:54         ` Zhang, Hawking
  2020-02-19  5:05           ` 回复: " Liu, Monk
  1 sibling, 1 reply; 16+ messages in thread
From: Zhang, Hawking @ 2020-02-18 14:54 UTC (permalink / raw)
  To: Liu, Monk, amd-gfx

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,

I don't want to mix os preemption with world switch here. I'm just trying to see whether we can leverage the code path as much as possible, i.e. CSA related code path. 

Specific for the sriov check in your patch, as I mentioned before, they are fair enough. You can have my ACK for patch #3. But I'd like to take another chance to review all the existing mcbp code with Jack and you to see any room for improvement. 

Regards,
Hawking
-----Original Message-----
From: Liu, Monk <Monk.Liu@amd.com> 
Sent: Tuesday, February 18, 2020 20:30
To: Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
Subject: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.: 
In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, and we do the same thing under that condition, But we cannot do that thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV case. Because that will let OS preemption work, which will trigger mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such colliding)

So we always need to disable OS preemption behavior for SRIOV (don't to preempt an IB by touch vmid_preempt register, and no IB resume happen)

Thanks 


-----邮件原件-----
发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
发送时间: 2020年2月18日 19:48
收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
抄送: Liu, Monk <Monk.Liu@amd.com>
主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking
Sent: Tuesday, February 18, 2020 19:32
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.

I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
+AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* 回复: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 14:48             ` Fernlund, Hans
@ 2020-02-19  5:04               ` Liu, Monk
  2020-02-19  8:27                 ` Christian König
  0 siblings, 1 reply; 16+ messages in thread
From: Liu, Monk @ 2020-02-19  5:04 UTC (permalink / raw)
  To: Fernlund, Hans, Koenig, Christian, Zhang, Hawking, amd-gfx

Hi Hans

For CE/DE meta data, OS preemption would write those credential to a dynamically allocated CSA buffer (one per process), but for SRIOV we only write them to static CSA (one per VF) 
In windows KMD, the OS Preemption is forced to disabled when SRIOV is enabled

Based on above two reason I stated that if we are under SRIOV, we should not allow an OS preemption triggered.

Are you saying that we can still support OS preemption even for VF ? 

Thanks 

-----邮件原件-----
发件人: Fernlund, Hans <Hans.Fernlund@amd.com> 
发送时间: 2020年2月18日 22:49
收件人: Liu, Monk <Monk.Liu@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
主题: RE: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

At CP level, MCBP and SRIOV are not mutually exclusive. They are used together in some environments.

/Hans


-----Original Message-----
From: Liu, Monk <Monk.Liu@amd.com>
Sent: Tuesday, February 18, 2020 7:53 AM
To: Koenig, Christian <Christian.Koenig@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org; Fernlund, Hans <Hans.Fernlund@amd.com>
Subject: 回复: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

If OS preemption can work with SRIOV world switch I won't provide such patch, I would already clean up those MCBP checking ... 

To your question: I don't know details, but my guess is that CP use the same interface with KMD (e.g. CE/DE meta) to handle two MCBP type: world switch and OS preempt, But some implementation is different inside CP firmware by the given interface, that need @Fernlund, Hans to provide the details if you want an expertise, he is the author of CP preemption 

Thanks 

-----邮件原件-----
发件人: Christian König <ckoenig.leichtzumerken@gmail.com>
发送时间: 2020年2月18日 20:40
收件人: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
主题: Re: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

Hawking is right here. We could just check amdgpu_mcbp during device initialization and forcefully clear it under SRIOV.

But why is MCBP and SRIOV mutual exclusive? We are certainly getting the requirement for this sooner or later.

Regards,
Christian.

Am 18.02.20 um 13:29 schrieb Liu, Monk:
> Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.:
> In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, 
> and we do the same thing under that condition, But we cannot do that 
> thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV 
> case. Because that will let OS preemption work, which will trigger 
> mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such
> colliding)
>
> So we always need to disable OS preemption behavior for SRIOV (don't 
> to preempt an IB by touch vmid_preempt register, and no IB resume
> happen)
>
> Thanks
>
>
> -----邮件原件-----
> 发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
> 发送时间: 2020年2月18日 19:48
> 收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk 
> <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> 抄送: Liu, Monk <Monk.Liu@amd.com>
> 主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of 
> Zhang, Hawking
> Sent: Tuesday, February 18, 2020 19:32
> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.
>
> I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.
>
> Regards,
> Hawking
>
> -----Original Message-----
> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of 
> Monk Liu
> Sent: Tuesday, February 18, 2020 10:54
> To: amd-gfx@lists.freedesktop.org
> Cc: Liu, Monk <Monk.Liu@amd.com>
> Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> what:
> some os preemption path is messed up with world switch preemption
>
> fix:
> cleanup those logics so os preemption not mixed with world switch
>
> this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.
>
> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
>   drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
>   2 files changed, 6 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> index a2ee30b..7854c05 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
> @@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
>   	uint32_t index = 0;
>   	int r;
>   
> -	if (vmid == 0 || !amdgpu_mcbp)
> +	/* don't enable OS preemption on SDMA under SRIOV */
> +	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
>   		return 0;
>   
>   	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git 
> a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> index 5e9fb09..7b61583 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
> @@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   
>   	control |= ib->length_dw | (vmid << 24);
>   
> -	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
> +	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
> +AMDGPU_IB_FLAG_PREEMPT)) {
>   		control |= INDIRECT_BUFFER_PRE_ENB(1);
>   
>   		if (flags & AMDGPU_IB_PREEMPTED)
> @@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct 
> amdgpu_ring *ring,
>   
>   		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
>   			gfx_v10_0_ring_emit_de_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   	}
>   
>   	amdgpu_ring_write(ring, header);
> @@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
>   	uint32_t dw2 = 0;
>   
> -	if (amdgpu_mcbp)
> +	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
>   		gfx_v10_0_ring_emit_ce_meta(ring,
> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
> +true : false);
>   
>   	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>   	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
> --
> 2.7.4
>
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^ permalink raw reply	[flat|nested] 16+ messages in thread

* 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-18 14:54         ` Zhang, Hawking
@ 2020-02-19  5:05           ` Liu, Monk
  0 siblings, 0 replies; 16+ messages in thread
From: Liu, Monk @ 2020-02-19  5:05 UTC (permalink / raw)
  To: Zhang, Hawking, amd-gfx

>> I don't want to mix os preemption with world switch here. I'm just trying to see whether we can leverage the code path as much as possible, i.e. CSA related code path.

Yeah, I agree with that 

>> But I'd like to take another chance to review all the existing mcbp code with Jack and you to see any room for improvement

Sure, let me know when you want to do this, we can discuss together on the MCBP topic 

Thanks !

-----邮件原件-----
发件人: Zhang, Hawking <Hawking.Zhang@amd.com> 
发送时间: 2020年2月18日 22:55
收件人: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

Hi Monk,

I don't want to mix os preemption with world switch here. I'm just trying to see whether we can leverage the code path as much as possible, i.e. CSA related code path. 

Specific for the sriov check in your patch, as I mentioned before, they are fair enough. You can have my ACK for patch #3. But I'd like to take another chance to review all the existing mcbp code with Jack and you to see any room for improvement. 

Regards,
Hawking
-----Original Message-----
From: Liu, Monk <Monk.Liu@amd.com> 
Sent: Tuesday, February 18, 2020 20:30
To: Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
Subject: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.: 
In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check, and we do the same thing under that condition, But we cannot do that thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV case. Because that will let OS preemption work, which will trigger mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such colliding)

So we always need to disable OS preemption behavior for SRIOV (don't to preempt an IB by touch vmid_preempt register, and no IB resume happen)

Thanks 


-----邮件原件-----
发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
发送时间: 2020年2月18日 19:48
收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
抄送: Liu, Monk <Monk.Liu@amd.com>
主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Zhang, Hawking
Sent: Tuesday, February 18, 2020 19:32
To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

[AMD Official Use Only - Internal Distribution Only]

It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.

I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.

Regards,
Hawking

-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Monk Liu
Sent: Tuesday, February 18, 2020 10:54
To: amd-gfx@lists.freedesktop.org
Cc: Liu, Monk <Monk.Liu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption

what:
some os preemption path is messed up with world switch preemption

fix:
cleanup those logics so os preemption not mixed with world switch

this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.

Signed-off-by: Monk Liu <Monk.Liu@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
index a2ee30b..7854c05 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
@@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
 	uint32_t index = 0;
 	int r;
 
-	if (vmid == 0 || !amdgpu_mcbp)
+	/* don't enable OS preemption on SDMA under SRIOV */
+	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
 		return 0;
 
 	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 5e9fb09..7b61583 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 	control |= ib->length_dw | (vmid << 24);
 
-	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
+	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
+AMDGPU_IB_FLAG_PREEMPT)) {
 		control |= INDIRECT_BUFFER_PRE_ENB(1);
 
 		if (flags & AMDGPU_IB_PREEMPTED)
@@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
 			gfx_v10_0_ring_emit_de_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 	}
 
 	amdgpu_ring_write(ring, header);
@@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
 	uint32_t dw2 = 0;
 
-	if (amdgpu_mcbp)
+	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
 		gfx_v10_0_ring_emit_ce_meta(ring,
-				    flags & AMDGPU_IB_PREEMPTED ? true : false);
+				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? 
+true : false);
 
 	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
 	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
--
2.7.4

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^ permalink raw reply related	[flat|nested] 16+ messages in thread

* Re: 回复: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
  2020-02-19  5:04               ` 回复: " Liu, Monk
@ 2020-02-19  8:27                 ` Christian König
  0 siblings, 0 replies; 16+ messages in thread
From: Christian König @ 2020-02-19  8:27 UTC (permalink / raw)
  To: Liu, Monk, Fernlund, Hans, Zhang, Hawking, amd-gfx

Hi Monk,

oh, I've miss interpreted Hans response. It indeed sounds like that 
could work.

We don't even need full preemption under VF, it would also make things 
easier if we just have the same CSA handling for both.

Regards,
Christian.

Am 19.02.20 um 06:04 schrieb Liu, Monk:
> Hi Hans
>
> For CE/DE meta data, OS preemption would write those credential to a dynamically allocated CSA buffer (one per process), but for SRIOV we only write them to static CSA (one per VF)
> In windows KMD, the OS Preemption is forced to disabled when SRIOV is enabled
>
> Based on above two reason I stated that if we are under SRIOV, we should not allow an OS preemption triggered.
>
> Are you saying that we can still support OS preemption even for VF ?
>
> Thanks
>
> -----邮件原件-----
> 发件人: Fernlund, Hans <Hans.Fernlund@amd.com>
> 发送时间: 2020年2月18日 22:49
> 收件人: Liu, Monk <Monk.Liu@amd.com>; Koenig, Christian <Christian.Koenig@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
> 主题: RE: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> [AMD Official Use Only - Internal Distribution Only]
>
> At CP level, MCBP and SRIOV are not mutually exclusive. They are used together in some environments.
>
> /Hans
>
>
> -----Original Message-----
> From: Liu, Monk <Monk.Liu@amd.com>
> Sent: Tuesday, February 18, 2020 7:53 AM
> To: Koenig, Christian <Christian.Koenig@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org; Fernlund, Hans <Hans.Fernlund@amd.com>
> Subject: 回复: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> If OS preemption can work with SRIOV world switch I won't provide such patch, I would already clean up those MCBP checking ...
>
> To your question: I don't know details, but my guess is that CP use the same interface with KMD (e.g. CE/DE meta) to handle two MCBP type: world switch and OS preempt, But some implementation is different inside CP firmware by the given interface, that need @Fernlund, Hans to provide the details if you want an expertise, he is the author of CP preemption
>
> Thanks
>
> -----邮件原件-----
> 发件人: Christian König <ckoenig.leichtzumerken@gmail.com>
> 发送时间: 2020年2月18日 20:40
> 收件人: Liu, Monk <Monk.Liu@amd.com>; Zhang, Hawking <Hawking.Zhang@amd.com>; amd-gfx@lists.freedesktop.org
> 主题: Re: 回复: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>
> Hawking is right here. We could just check amdgpu_mcbp during device initialization and forcefully clear it under SRIOV.
>
> But why is MCBP and SRIOV mutual exclusive? We are certainly getting the requirement for this sooner or later.
>
> Regards,
> Christian.
>
> Am 18.02.20 um 13:29 schrieb Liu, Monk:
>> Even not talking about CE/DE meta and SDMA CS, we still cannot share amdgpu_mcbp with SRIOV case,  e.g.:
>> In some place we use "if (amdgpu_mcbp || amdgpu_sriov_vf()" to check,
>> and we do the same thing under that condition, But we cannot do that
>> thing by "if (amdgpu_mcbp)" and set "amdgpu_mcbp" to true under SRIOV
>> case. Because that will let OS preemption work, which will trigger
>> mismatch/crush in CPG side during the MCBP. (not sure if CWSR has such
>> colliding)
>>
>> So we always need to disable OS preemption behavior for SRIOV (don't
>> to preempt an IB by touch vmid_preempt register, and no IB resume
>> happen)
>>
>> Thanks
>>
>>
>> -----邮件原件-----
>> 发件人: Zhang, Hawking <Hawking.Zhang@amd.com>
>> 发送时间: 2020年2月18日 19:48
>> 收件人: Zhang, Hawking <Hawking.Zhang@amd.com>; Liu, Monk
>> <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
>> 抄送: Liu, Monk <Monk.Liu@amd.com>
>> 主题: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> Ahhh.... Send it too quickly. Of course, we still need to apply vf check for ce/de-meta, but I think in such way, we can dramatically reduce the amdgpu_sirov_vf check in every mcbp code path.
>>
>> Regards,
>> Hawking
>>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>> Zhang, Hawking
>> Sent: Tuesday, February 18, 2020 19:32
>> To: Liu, Monk <Monk.Liu@amd.com>; amd-gfx@lists.freedesktop.org
>> Cc: Liu, Monk <Monk.Liu@amd.com>
>> Subject: RE: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>>
>> [AMD Official Use Only - Internal Distribution Only]
>>
>> It's some kind of annoying to check vf in every place that is required for mcbp until amdgpu_mcbp is enabled by default. What's more, when amdgpu_mcbp is enabled by default, there will be many unnecessary vf check that can be removed as most of mcbp function actually can be shared between world switch preemption and os preemption.
>>
>> I'd prefer to enable amdgpu_mcbp for sriov in amdgpu_device_check_arguments to reduce the vf specific check everywhere.
>>
>> Regards,
>> Hawking
>>
>> -----Original Message-----
>> From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of
>> Monk Liu
>> Sent: Tuesday, February 18, 2020 10:54
>> To: amd-gfx@lists.freedesktop.org
>> Cc: Liu, Monk <Monk.Liu@amd.com>
>> Subject: [PATCH 3/3] drm/amdgpu: fix colliding of preemption
>>
>> what:
>> some os preemption path is messed up with world switch preemption
>>
>> fix:
>> cleanup those logics so os preemption not mixed with world switch
>>
>> this patch is a general fix for issues comes from SRIOV MCBP, but there is still UMD side issues not resovlved yet, so this patch cannot fix all world switch bug.
>>
>> Signed-off-by: Monk Liu <Monk.Liu@amd.com>
>> ---
>>    drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c | 3 ++-
>>    drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c   | 8 ++++----
>>    2 files changed, 6 insertions(+), 5 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>> index a2ee30b..7854c05 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.c
>> @@ -70,7 +70,8 @@ uint64_t amdgpu_sdma_get_csa_mc_addr(struct amdgpu_ring *ring,
>>    	uint32_t index = 0;
>>    	int r;
>>    
>> -	if (vmid == 0 || !amdgpu_mcbp)
>> +	/* don't enable OS preemption on SDMA under SRIOV */
>> +	if (amdgpu_sriov_vf(adev) || vmid == 0 || !amdgpu_mcbp)
>>    		return 0;
>>    
>>    	r = amdgpu_sdma_get_index_from_ring(ring, &index); diff --git
>> a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> index 5e9fb09..7b61583 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
>> @@ -4413,7 +4413,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct
>> amdgpu_ring *ring,
>>    
>>    	control |= ib->length_dw | (vmid << 24);
>>    
>> -	if (amdgpu_mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
>> +	if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags &
>> +AMDGPU_IB_FLAG_PREEMPT)) {
>>    		control |= INDIRECT_BUFFER_PRE_ENB(1);
>>    
>>    		if (flags & AMDGPU_IB_PREEMPTED)
>> @@ -4421,7 +4421,7 @@ static void gfx_v10_0_ring_emit_ib_gfx(struct
>> amdgpu_ring *ring,
>>    
>>    		if (!(ib->flags & AMDGPU_IB_FLAG_CE))
>>    			gfx_v10_0_ring_emit_de_meta(ring,
>> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
>> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
>> +true : false);
>>    	}
>>    
>>    	amdgpu_ring_write(ring, header);
>> @@ -4569,9 +4569,9 @@ static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,  {
>>    	uint32_t dw2 = 0;
>>    
>> -	if (amdgpu_mcbp)
>> +	if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
>>    		gfx_v10_0_ring_emit_ce_meta(ring,
>> -				    flags & AMDGPU_IB_PREEMPTED ? true : false);
>> +				    (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ?
>> +true : false);
>>    
>>    	dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
>>    	if (flags & AMDGPU_HAVE_CTX_SWITCH) {
>> --
>> 2.7.4
>>
>> _______________________________________________
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>> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
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>> 8e11a82d994e183d%7C0%7C0%7C637176264049018414&amp;sdata=LYwxBmSyfmH3ep
>> uYuOQ1pdp1IL6QlTA30i8By27iDhg%3D&amp;reserved=0
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^ permalink raw reply	[flat|nested] 16+ messages in thread

end of thread, other threads:[~2020-02-19  8:27 UTC | newest]

Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-18  2:54 [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Monk Liu
2020-02-18  2:54 ` [PATCH 2/3] drm/amdgpu: fix memory leak during TDR test Monk Liu
2020-02-18 11:10   ` Zhang, Hawking
2020-02-18  2:54 ` [PATCH 3/3] drm/amdgpu: fix colliding of preemption Monk Liu
2020-02-18 11:32   ` Zhang, Hawking
2020-02-18 11:48     ` Zhang, Hawking
2020-02-18 12:29       ` 回复: " Liu, Monk
2020-02-18 12:39         ` Christian König
2020-02-18 12:53           ` 回复: " Liu, Monk
2020-02-18 14:48             ` Fernlund, Hans
2020-02-19  5:04               ` 回复: " Liu, Monk
2020-02-19  8:27                 ` Christian König
2020-02-18 14:54         ` Zhang, Hawking
2020-02-19  5:05           ` 回复: " Liu, Monk
2020-02-18 12:19     ` Liu, Monk
2020-02-18 11:08 ` [PATCH 1/3] drm/amdgpu: cleanup some incorrect reg access for SRIOV Zhang, Hawking

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