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From: no-reply@patchew.org
To: david@gibson.dropbear.id.au
Cc: lvivier@redhat.com, aik@ozlabs.ru, mark.cave-ayland@ilande.co.uk,
	groug@kaod.org, qemu-devel@nongnu.org, paulus@samba.org,
	clg@kaod.org, qemu-ppc@nongnu.org, philmd@redhat.com,
	david@gibson.dropbear.id.au
Subject: Re: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling
Date: Tue, 18 Feb 2020 17:21:37 -0800 (PST)	[thread overview]
Message-ID: <158207529589.20350.13094839224352717874@a1bbccc8075a> (raw)
In-Reply-To: <20200219005414.15635-1-david@gibson.dropbear.id.au>

Patchew URL: https://patchew.org/QEMU/20200219005414.15635-1-david@gibson.dropbear.id.au/



Hi,

This series seems to have some coding style problems. See output below for
more information:

Subject: [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling
Message-id: 20200219005414.15635-1-david@gibson.dropbear.id.au
Type: series

=== TEST SCRIPT BEGIN ===
#!/bin/bash
git rev-parse base > /dev/null || exit 0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
./scripts/checkpatch.pl --mailback base..
=== TEST SCRIPT END ===

From https://github.com/patchew-project/qemu
 * [new tag]         patchew/20200219005414.15635-1-david@gibson.dropbear.id.au -> patchew/20200219005414.15635-1-david@gibson.dropbear.id.au
Switched to a new branch 'test'
275db2f target/ppc: Don't store VRMA SLBE persistently
8f4ef78 target/ppc: Streamline construction of VRMA SLB entry
5329f3b target/ppc: Only calculate RMLS derived RMA limit on demand
656a372 target/ppc: Correct RMLS table
6432e7f target/ppc: Streamline calculation of RMA limit from LPCR[RMLS]
00f78cd target/ppc: Use class fields to simplify LPCR masking
c6f6cea target/ppc: Remove RMOR register from POWER9 & POWER10
c6daae6 spapr, ppc: Remove VPM0/RMLS hacks for POWER9
3374197 target/ppc: Introduce ppc_hash64_use_vrma() helper
7e14e97 target/ppc: Correct handling of real mode accesses with vhyp on hash MMU
7c298cb ppc: Remove stub of PPC970 HID4 implementation
4525879 ppc: Remove stub support for 32-bit hypervisor mode

=== OUTPUT BEGIN ===
1/12 Checking commit 4525879e6fae (ppc: Remove stub support for 32-bit hypervisor mode)
2/12 Checking commit 7c298cb58821 (ppc: Remove stub of PPC970 HID4 implementation)
WARNING: Block comments use a leading /* on a separate line
#98: FILE: target/ppc/translate_init.inc.c:7904:
+    /* PPC970: HID4 covers things later controlled by the LPCR and

WARNING: Block comments use a trailing */ on a separate line
#102: FILE: target/ppc/translate_init.inc.c:7908:
+     * ignore it */

total: 0 errors, 2 warnings, 71 lines checked

Patch 2/12 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
3/12 Checking commit 7e14e97fa725 (target/ppc: Correct handling of real mode accesses with vhyp on hash MMU)
4/12 Checking commit 337419739ee8 (target/ppc: Introduce ppc_hash64_use_vrma() helper)
WARNING: Block comments use a leading /* on a separate line
#41: FILE: target/ppc/mmu-hash64.c:675:
+        /* ISAv3.0 (POWER9) always uses VRMA, the VPM0 field and RMOR

WARNING: Block comments use a trailing */ on a separate line
#42: FILE: target/ppc/mmu-hash64.c:676:
+         * register no longer exist */

total: 0 errors, 2 warnings, 83 lines checked

Patch 4/12 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
5/12 Checking commit c6daae6e9b06 (spapr, ppc: Remove VPM0/RMLS hacks for POWER9)
6/12 Checking commit c6f6ceaa43fc (target/ppc: Remove RMOR register from POWER9 & POWER10)
7/12 Checking commit 00f78cdfebbd (target/ppc: Use class fields to simplify LPCR masking)
8/12 Checking commit 6432e7fe864f (target/ppc: Streamline calculation of RMA limit from LPCR[RMLS])
9/12 Checking commit 656a372f677c (target/ppc: Correct RMLS table)
10/12 Checking commit 5329f3b07fba (target/ppc: Only calculate RMLS derived RMA limit on demand)
11/12 Checking commit 8f4ef78a4af3 (target/ppc: Streamline construction of VRMA SLB entry)
ERROR: braces {} are necessary for all arms of this statement
#80: FILE: target/ppc/mmu-hash64.c:1084:
+        if (build_vrma_slbe(cpu, slb) == 0)
[...]

total: 1 errors, 0 warnings, 97 lines checked

Patch 11/12 has style problems, please review.  If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.

12/12 Checking commit 275db2fe2a84 (target/ppc: Don't store VRMA SLBE persistently)
=== OUTPUT END ===

Test command exited with code: 1


The full log is available at
http://patchew.org/logs/20200219005414.15635-1-david@gibson.dropbear.id.au/testing.checkpatch/?type=message.
---
Email generated automatically by Patchew [https://patchew.org/].
Please send your feedback to patchew-devel@redhat.com

  parent reply	other threads:[~2020-02-19  1:22 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-19  0:54 [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling David Gibson
2020-02-19  0:54 ` [PATCH v3 01/12] ppc: Remove stub support for 32-bit hypervisor mode David Gibson
2020-02-19 14:15   ` Fabiano Rosas
2020-02-19  0:54 ` [PATCH v3 02/12] ppc: Remove stub of PPC970 HID4 implementation David Gibson
2020-02-19 11:18   ` BALATON Zoltan
2020-02-20  0:36     ` David Gibson
2020-02-19  0:54 ` [PATCH v3 03/12] target/ppc: Correct handling of real mode accesses with vhyp on hash MMU David Gibson
2020-02-19  0:54 ` [PATCH v3 04/12] target/ppc: Introduce ppc_hash64_use_vrma() helper David Gibson
2020-02-19 14:06   ` Fabiano Rosas
2020-02-20  2:41     ` Paul Mackerras
2020-02-20  3:10     ` David Gibson
2020-02-19  0:54 ` [PATCH v3 05/12] spapr, ppc: Remove VPM0/RMLS hacks for POWER9 David Gibson
2020-02-19  0:54 ` [PATCH v3 06/12] target/ppc: Remove RMOR register from POWER9 & POWER10 David Gibson
2020-02-19  0:54 ` [PATCH v3 07/12] target/ppc: Use class fields to simplify LPCR masking David Gibson
2020-02-19  0:54 ` [PATCH v3 08/12] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] David Gibson
2020-02-19  0:54 ` [PATCH v3 09/12] target/ppc: Correct RMLS table David Gibson
2020-02-19  0:54 ` [PATCH v3 10/12] target/ppc: Only calculate RMLS derived RMA limit on demand David Gibson
2020-02-19  0:54 ` [PATCH v3 11/12] target/ppc: Streamline construction of VRMA SLB entry David Gibson
2020-02-19 14:34   ` Fabiano Rosas
2020-02-20  3:13     ` David Gibson
2020-02-19  0:54 ` [PATCH v3 12/12] target/ppc: Don't store VRMA SLBE persistently David Gibson
2020-02-19  1:21 ` no-reply [this message]
2020-02-19  2:11 ` [PATCH v3 00/12] target/ppc: Correct some errors with real mode handling David Gibson

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