* [Intel-gfx] [PATCH] drm/i915/gt/tgl: implement Wa_1409085225
@ 2020-02-18 19:47 Matt Atwood
2020-02-18 23:44 ` Rafael Antognolli
2020-02-19 4:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
0 siblings, 2 replies; 4+ messages in thread
From: Matt Atwood @ 2020-02-18 19:47 UTC (permalink / raw)
To: intel-gfx
Disable Push Constant buffer addition for A0, which can cause FIFO
underruns.
Fix a minor white space issue while we're here.
Bspec: 52890
Cc: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++
drivers/gpu/drm/i915/i915_reg.h | 3 +++
2 files changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 887e0dc701f7..9bbd28aa9bde 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -580,6 +580,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
struct i915_wa_list *wal)
{
+ struct drm_i915_private *i915 = engine->i915;
u32 val;
/* Wa_1409142259:tgl */
@@ -590,6 +591,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
val = intel_uncore_read(engine->uncore, FF_MODE2);
val &= ~FF_MODE2_TDS_TIMER_MASK;
val |= FF_MODE2_TDS_TIMER_128;
+
/*
* FIXME: FF_MODE2 register is not readable till TGL B0. We can
* enable verification of WA from the later steppings, which enables
@@ -598,6 +600,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
FF_MODE2_TDS_TIMER_MASK);
+
+ /* Wa_1409085225:tgl
+ *
+ * Push Constant Buffer can case FIFO underruns on A0
+ */
+ if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
+ WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4,
+ GEN12_DISABLE_TDL_PUSH);
}
static void
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index b09c1d6dc0aa..a75a27ed63ce 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9153,6 +9153,9 @@ enum {
#define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
#define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
+#define GEN9_ROW_CHICKEN4 _MMIO(0x48c)
+#define GEN12_DISABLE_TDL_PUSH (1 << 9)
+
#define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
#define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
--
2.21.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt/tgl: implement Wa_1409085225
2020-02-18 19:47 [Intel-gfx] [PATCH] drm/i915/gt/tgl: implement Wa_1409085225 Matt Atwood
@ 2020-02-18 23:44 ` Rafael Antognolli
2020-02-19 0:16 ` Rafael Antognolli
2020-02-19 4:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
1 sibling, 1 reply; 4+ messages in thread
From: Rafael Antognolli @ 2020-02-18 23:44 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
On Tue, Feb 18, 2020 at 02:47:10PM -0500, Matt Atwood wrote:
> Disable Push Constant buffer addition for A0, which can cause FIFO
> underruns.
>
> Fix a minor white space issue while we're here.
>
> Bspec: 52890
> Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 3 +++
> 2 files changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> index 887e0dc701f7..9bbd28aa9bde 100644
> --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> @@ -580,6 +580,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> struct i915_wa_list *wal)
> {
> + struct drm_i915_private *i915 = engine->i915;
> u32 val;
>
> /* Wa_1409142259:tgl */
> @@ -590,6 +591,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> val = intel_uncore_read(engine->uncore, FF_MODE2);
> val &= ~FF_MODE2_TDS_TIMER_MASK;
> val |= FF_MODE2_TDS_TIMER_128;
> +
> /*
> * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> * enable verification of WA from the later steppings, which enables
> @@ -598,6 +600,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> FF_MODE2_TDS_TIMER_MASK);
> +
> + /* Wa_1409085225:tgl
> + *
> + * Push Constant Buffer can case FIFO underruns on A0
> + */
> + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
Is this really only applicable to A stepping?
> + WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4,
> + GEN12_DISABLE_TDL_PUSH);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index b09c1d6dc0aa..a75a27ed63ce 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -9153,6 +9153,9 @@ enum {
> #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
>
> +#define GEN9_ROW_CHICKEN4 _MMIO(0x48c)
s/0x48c/0xe48c/ ?
> +#define GEN12_DISABLE_TDL_PUSH (1 << 9)
> +
> #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
>
> --
> 2.21.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/gt/tgl: implement Wa_1409085225
2020-02-18 23:44 ` Rafael Antognolli
@ 2020-02-19 0:16 ` Rafael Antognolli
0 siblings, 0 replies; 4+ messages in thread
From: Rafael Antognolli @ 2020-02-19 0:16 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
On Tue, Feb 18, 2020 at 03:44:49PM -0800, Rafael Antognolli wrote:
> On Tue, Feb 18, 2020 at 02:47:10PM -0500, Matt Atwood wrote:
> > Disable Push Constant buffer addition for A0, which can cause FIFO
> > underruns.
> >
> > Fix a minor white space issue while we're here.
> >
> > Bspec: 52890
> > Cc: Rafael Antognolli <rafael.antognolli@intel.com>
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_workarounds.c | 10 ++++++++++
> > drivers/gpu/drm/i915/i915_reg.h | 3 +++
> > 2 files changed, 13 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > index 887e0dc701f7..9bbd28aa9bde 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
> > @@ -580,6 +580,7 @@ static void icl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > struct i915_wa_list *wal)
> > {
> > + struct drm_i915_private *i915 = engine->i915;
> > u32 val;
> >
> > /* Wa_1409142259:tgl */
> > @@ -590,6 +591,7 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > val = intel_uncore_read(engine->uncore, FF_MODE2);
> > val &= ~FF_MODE2_TDS_TIMER_MASK;
> > val |= FF_MODE2_TDS_TIMER_128;
> > +
> > /*
> > * FIXME: FF_MODE2 register is not readable till TGL B0. We can
> > * enable verification of WA from the later steppings, which enables
> > @@ -598,6 +600,14 @@ static void tgl_ctx_workarounds_init(struct intel_engine_cs *engine,
> > wa_add(wal, FF_MODE2, FF_MODE2_TDS_TIMER_MASK, val,
> > IS_TGL_REVID(engine->i915, TGL_REVID_A0, TGL_REVID_A0) ? 0 :
> > FF_MODE2_TDS_TIMER_MASK);
> > +
> > + /* Wa_1409085225:tgl
> > + *
> > + * Push Constant Buffer can case FIFO underruns on A0
> > + */
> > + if (IS_TGL_REVID(i915, TGL_REVID_A0, TGL_REVID_A0))
>
> Is this really only applicable to A stepping?
Hmmm... it looks like there is another workaround that's almost the
same: 14010229206 <-- this one seems to be permanent.
The one you implemented is indeed only A stepping. I'm not sure which
one is right, though.
> > + WA_SET_BIT_MASKED(GEN9_ROW_CHICKEN4,
> > + GEN12_DISABLE_TDL_PUSH);
> > }
> >
> > static void
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index b09c1d6dc0aa..a75a27ed63ce 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -9153,6 +9153,9 @@ enum {
> > #define PUSH_CONSTANT_DEREF_DISABLE (1 << 8)
> > #define GEN11_TDL_CLOCK_GATING_FIX_DISABLE (1 << 1)
> >
> > +#define GEN9_ROW_CHICKEN4 _MMIO(0x48c)
>
> s/0x48c/0xe48c/ ?
>
> > +#define GEN12_DISABLE_TDL_PUSH (1 << 9)
> > +
> > #define HSW_ROW_CHICKEN3 _MMIO(0xe49c)
> > #define HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE (1 << 6)
> >
> > --
> > 2.21.1
> >
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/gt/tgl: implement Wa_1409085225
2020-02-18 19:47 [Intel-gfx] [PATCH] drm/i915/gt/tgl: implement Wa_1409085225 Matt Atwood
2020-02-18 23:44 ` Rafael Antognolli
@ 2020-02-19 4:49 ` Patchwork
1 sibling, 0 replies; 4+ messages in thread
From: Patchwork @ 2020-02-19 4:49 UTC (permalink / raw)
To: Matt Atwood; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/gt/tgl: implement Wa_1409085225
URL : https://patchwork.freedesktop.org/series/73611/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_7963 -> Patchwork_16612
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_16612 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_16612, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_16612:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live_workarounds:
- fi-icl-guc: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-guc/igt@i915_selftest@live_workarounds.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-icl-guc/igt@i915_selftest@live_workarounds.html
Known issues
------------
Here are the changes found in Patchwork_16612 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_sanitycheck:
- fi-icl-u3: [PASS][3] -> [DMESG-WARN][4] ([i915#585]) +39 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-icl-u3/igt@i915_selftest@live_sanitycheck.html
#### Possible fixes ####
* igt@gem_close_race@basic-threads:
- fi-hsw-peppy: [INCOMPLETE][5] ([i915#694] / [i915#816]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
- fi-byt-n2820: [INCOMPLETE][7] ([i915#45]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-byt-n2820/igt@gem_close_race@basic-threads.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-byt-n2820/igt@gem_close_race@basic-threads.html
* igt@gem_exec_parallel@contexts:
- {fi-ehl-1}: [INCOMPLETE][9] ([i915#937]) -> [PASS][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-ehl-1/igt@gem_exec_parallel@contexts.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-ehl-1/igt@gem_exec_parallel@contexts.html
* igt@i915_selftest@live_active:
- fi-icl-dsi: [DMESG-FAIL][11] ([i915#765]) -> [PASS][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-dsi/igt@i915_selftest@live_active.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-icl-dsi/igt@i915_selftest@live_active.html
* igt@i915_selftest@live_gem_contexts:
- fi-cfl-8700k: [INCOMPLETE][13] ([i915#424]) -> [PASS][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-cfl-8700k/igt@i915_selftest@live_gem_contexts.html
- fi-cml-s: [DMESG-FAIL][15] ([i915#877]) -> [PASS][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-cml-s/igt@i915_selftest@live_gem_contexts.html
* igt@i915_selftest@live_gt_heartbeat:
- fi-kbl-7500u: [DMESG-FAIL][17] ([fdo#112406]) -> [PASS][18]
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-kbl-7500u/igt@i915_selftest@live_gt_heartbeat.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- fi-bsw-n3050: [FAIL][19] ([i915#34]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-bsw-n3050/igt@kms_flip@basic-flip-vs-wf_vblank.html
#### Warnings ####
* igt@amdgpu/amd_prime@amd-to-i915:
- fi-icl-u3: [SKIP][21] ([fdo#109315]) -> [SKIP][22] ([fdo#109315] / [i915#585])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@amdgpu/amd_prime@amd-to-i915.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-icl-u3/igt@amdgpu/amd_prime@amd-to-i915.html
* igt@i915_pm_rpm@basic-rte:
- fi-kbl-guc: [FAIL][23] ([i915#579]) -> [SKIP][24] ([fdo#109271])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-icl-u3: [SKIP][25] ([fdo#109284] / [fdo#111827]) -> [SKIP][26] ([fdo#109284] / [fdo#111827] / [i915#585])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@kms_chamelium@dp-hpd-fast.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-icl-u3/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-u3: [SKIP][27] ([fdo#109285]) -> [SKIP][28] ([fdo#109285] / [i915#585])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7963/fi-icl-u3/igt@kms_force_connector_basic@force-load-detect.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/fi-icl-u3/igt@kms_force_connector_basic@force-load-detect.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112406]: https://bugs.freedesktop.org/show_bug.cgi?id=112406
[i915#1169]: https://gitlab.freedesktop.org/drm/intel/issues/1169
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#424]: https://gitlab.freedesktop.org/drm/intel/issues/424
[i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#585]: https://gitlab.freedesktop.org/drm/intel/issues/585
[i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
[i915#765]: https://gitlab.freedesktop.org/drm/intel/issues/765
[i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
[i915#937]: https://gitlab.freedesktop.org/drm/intel/issues/937
Participating hosts (50 -> 39)
------------------------------
Missing (11): fi-ilk-m540 fi-hsw-4200u fi-glk-dsi fi-bsw-cyan fi-ctg-p8600 fi-gdg-551 fi-ivb-3770 fi-bsw-kefka fi-bdw-samus fi-skl-6700k2 fi-snb-2600
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_7963 -> Patchwork_16612
CI-20190529: 20190529
CI_DRM_7963: e0d737598eb749378a5dc4ed3dfafc6f79d512cb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5448: 116020b1f83c1b3994c76882df7f77b6731d78ba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_16612: 80f68b98697d1377b6537fdae1601f61e5a65149 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
80f68b98697d drm/i915/gt/tgl: implement Wa_1409085225
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16612/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2020-02-19 4:49 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-02-18 19:47 [Intel-gfx] [PATCH] drm/i915/gt/tgl: implement Wa_1409085225 Matt Atwood
2020-02-18 23:44 ` Rafael Antognolli
2020-02-19 0:16 ` Rafael Antognolli
2020-02-19 4:49 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for " Patchwork
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