* [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
@ 2020-02-26 4:34 Emily Deng
2020-02-26 11:06 ` Liu, Monk
2020-02-26 14:29 ` Alex Deucher
0 siblings, 2 replies; 5+ messages in thread
From: Emily Deng @ 2020-02-26 4:34 UTC (permalink / raw)
To: amd-gfx; +Cc: Emily Deng
For vega10 sriov, the register is blocked, use
copy data command to fix the issue.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68 +++++++++++++++++++++++++++++------
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1c7a16b..71df0d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3963,6 +3963,63 @@ static int gfx_v9_0_soft_reset(void *handle)
return 0;
}
+static uint64_t amdgpu_kiq_read_clock(struct amdgpu_device *adev)
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+ struct amdgpu_ring *ring = &kiq->ring;
+
+ BUG_ON(!ring->funcs->emit_rreg);
+
+ spin_lock_irqsave(&kiq->ring_lock, flags);
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
+ amdgpu_ring_write(ring, 9 | /* src: register*/
+ (5 << 8) | /* dst: memory */
+ (1 << 16) | /* count sel */
+ (1 << 20)); /* write confirm */
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
+ kiq->reg_val_offs * 4));
+ amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
+ kiq->reg_val_offs * 4));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+ * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+ * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+ * never return if we keep waiting in virt_kiq_rreg, which cause
+ * gpu_recover() hang there.
+ *
+ * also don't wait anymore for IRQ context
+ * */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq_read;
+
+ might_sleep();
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+ msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+ }
+
+ if (cnt > MAX_KIQ_REG_TRY)
+ goto failed_kiq_read;
+
+ return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
+ (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL;
+
+failed_kiq_read:
+ pr_err("failed to read gpu clock\n");
+ return ~0;
+}
+
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
{
uint64_t clock;
@@ -3970,16 +4027,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex);
if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
- uint32_t tmp, lsb, msb, i = 0;
- do {
- if (i != 0)
- udelay(1);
- tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
- lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
- msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
- i++;
- } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
- clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
+ clock = amdgpu_kiq_read_clock(adev);
} else {
WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
--
2.7.4
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
2020-02-26 4:34 [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock Emily Deng
@ 2020-02-26 11:06 ` Liu, Monk
2020-02-26 14:29 ` Alex Deucher
1 sibling, 0 replies; 5+ messages in thread
From: Liu, Monk @ 2020-02-26 11:06 UTC (permalink / raw)
To: Deng, Emily, amd-gfx; +Cc: Deng, Emily
Reviewed-by: Monk Liu <monk.liu@amd.com>
_____________________________________
Monk Liu|GPU Virtualization Team |AMD
-----Original Message-----
From: amd-gfx <amd-gfx-bounces@lists.freedesktop.org> On Behalf Of Emily Deng
Sent: Wednesday, February 26, 2020 12:34 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deng, Emily <Emily.Deng@amd.com>
Subject: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
For vega10 sriov, the register is blocked, use copy data command to fix the issue.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68 +++++++++++++++++++++++++++++------
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 1c7a16b..71df0d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3963,6 +3963,63 @@ static int gfx_v9_0_soft_reset(void *handle)
return 0;
}
+static uint64_t amdgpu_kiq_read_clock(struct amdgpu_device *adev) {
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+ struct amdgpu_ring *ring = &kiq->ring;
+
+ BUG_ON(!ring->funcs->emit_rreg);
+
+ spin_lock_irqsave(&kiq->ring_lock, flags);
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
+ amdgpu_ring_write(ring, 9 | /* src: register*/
+ (5 << 8) | /* dst: memory */
+ (1 << 16) | /* count sel */
+ (1 << 20)); /* write confirm */
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
+ kiq->reg_val_offs * 4));
+ amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
+ kiq->reg_val_offs * 4));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+ * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+ * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+ * never return if we keep waiting in virt_kiq_rreg, which cause
+ * gpu_recover() hang there.
+ *
+ * also don't wait anymore for IRQ context
+ * */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq_read;
+
+ might_sleep();
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+ msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+ }
+
+ if (cnt > MAX_KIQ_REG_TRY)
+ goto failed_kiq_read;
+
+ return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
+ (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL;
+
+failed_kiq_read:
+ pr_err("failed to read gpu clock\n");
+ return ~0;
+}
+
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev) {
uint64_t clock;
@@ -3970,16 +4027,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex);
if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
- uint32_t tmp, lsb, msb, i = 0;
- do {
- if (i != 0)
- udelay(1);
- tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
- lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
- msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
- i++;
- } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
- clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
+ clock = amdgpu_kiq_read_clock(adev);
} else {
WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
--
2.7.4
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
2020-02-26 4:34 [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock Emily Deng
2020-02-26 11:06 ` Liu, Monk
@ 2020-02-26 14:29 ` Alex Deucher
2020-02-26 16:18 ` Christian König
2020-02-27 2:03 ` Deng, Emily
1 sibling, 2 replies; 5+ messages in thread
From: Alex Deucher @ 2020-02-26 14:29 UTC (permalink / raw)
To: Emily Deng; +Cc: amd-gfx list
On Tue, Feb 25, 2020 at 11:34 PM Emily Deng <Emily.Deng@amd.com> wrote:
>
> For vega10 sriov, the register is blocked, use
> copy data command to fix the issue.
>
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68 +++++++++++++++++++++++++++++------
> 1 file changed, 58 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> index 1c7a16b..71df0d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
> @@ -3963,6 +3963,63 @@ static int gfx_v9_0_soft_reset(void *handle)
> return 0;
> }
>
> +static uint64_t amdgpu_kiq_read_clock(struct amdgpu_device *adev)
Please name this function gfx_v9_0_kiq_read_clock for consistency.
> +{
> + signed long r, cnt = 0;
> + unsigned long flags;
> + uint32_t seq;
> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
> + struct amdgpu_ring *ring = &kiq->ring;
> +
> + BUG_ON(!ring->funcs->emit_rreg);
> +
> + spin_lock_irqsave(&kiq->ring_lock, flags);
> + amdgpu_ring_alloc(ring, 32);
> + amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
> + amdgpu_ring_write(ring, 9 | /* src: register*/
Is src 9 the counter?
Assuming that is correct, with the naming fixed:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> + (5 << 8) | /* dst: memory */
> + (1 << 16) | /* count sel */
> + (1 << 20)); /* write confirm */
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
> + kiq->reg_val_offs * 4));
> + amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
> + kiq->reg_val_offs * 4));
> + amdgpu_fence_emit_polling(ring, &seq);
> + amdgpu_ring_commit(ring);
> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
> +
> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> +
> + /* don't wait anymore for gpu reset case because this way may
> + * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
> + * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
> + * never return if we keep waiting in virt_kiq_rreg, which cause
> + * gpu_recover() hang there.
> + *
> + * also don't wait anymore for IRQ context
> + * */
> + if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
> + goto failed_kiq_read;
> +
> + might_sleep();
> + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
> + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
> + }
> +
> + if (cnt > MAX_KIQ_REG_TRY)
> + goto failed_kiq_read;
> +
> + return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
> + (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL;
> +
> +failed_kiq_read:
> + pr_err("failed to read gpu clock\n");
> + return ~0;
> +}
> +
> static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> {
> uint64_t clock;
> @@ -3970,16 +4027,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
> amdgpu_gfx_off_ctrl(adev, false);
> mutex_lock(&adev->gfx.gpu_clock_mutex);
> if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
> - uint32_t tmp, lsb, msb, i = 0;
> - do {
> - if (i != 0)
> - udelay(1);
> - tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
> - lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
> - msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
> - i++;
> - } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
> - clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
> + clock = amdgpu_kiq_read_clock(adev);
> } else {
> WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
> clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
2020-02-26 14:29 ` Alex Deucher
@ 2020-02-26 16:18 ` Christian König
2020-02-27 2:03 ` Deng, Emily
1 sibling, 0 replies; 5+ messages in thread
From: Christian König @ 2020-02-26 16:18 UTC (permalink / raw)
To: Alex Deucher, Emily Deng; +Cc: amd-gfx list
Am 26.02.20 um 15:29 schrieb Alex Deucher:
> On Tue, Feb 25, 2020 at 11:34 PM Emily Deng <Emily.Deng@amd.com> wrote:
>> For vega10 sriov, the register is blocked, use
>> copy data command to fix the issue.
>>
>> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68 +++++++++++++++++++++++++++++------
>> 1 file changed, 58 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 1c7a16b..71df0d9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3963,6 +3963,63 @@ static int gfx_v9_0_soft_reset(void *handle)
>> return 0;
>> }
>>
>> +static uint64_t amdgpu_kiq_read_clock(struct amdgpu_device *adev)
> Please name this function gfx_v9_0_kiq_read_clock for consistency.
Alternatively it might also be a good idea to move this in amdgpu_kiq.c.
But depends on you what you think makes more sense.
Regards,
Christian.
>
>
>> +{
>> + signed long r, cnt = 0;
>> + unsigned long flags;
>> + uint32_t seq;
>> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>> + struct amdgpu_ring *ring = &kiq->ring;
>> +
>> + BUG_ON(!ring->funcs->emit_rreg);
>> +
>> + spin_lock_irqsave(&kiq->ring_lock, flags);
>> + amdgpu_ring_alloc(ring, 32);
>> + amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
>> + amdgpu_ring_write(ring, 9 | /* src: register*/
> Is src 9 the counter?
>
> Assuming that is correct, with the naming fixed:
> Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> + (5 << 8) | /* dst: memory */
>> + (1 << 16) | /* count sel */
>> + (1 << 20)); /* write confirm */
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
>> + kiq->reg_val_offs * 4));
>> + amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
>> + kiq->reg_val_offs * 4));
>> + amdgpu_fence_emit_polling(ring, &seq);
>> + amdgpu_ring_commit(ring);
>> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
>> +
>> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
>> +
>> + /* don't wait anymore for gpu reset case because this way may
>> + * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
>> + * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
>> + * never return if we keep waiting in virt_kiq_rreg, which cause
>> + * gpu_recover() hang there.
>> + *
>> + * also don't wait anymore for IRQ context
>> + * */
>> + if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
>> + goto failed_kiq_read;
>> +
>> + might_sleep();
>> + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
>> + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
>> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
>> + }
>> +
>> + if (cnt > MAX_KIQ_REG_TRY)
>> + goto failed_kiq_read;
>> +
>> + return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
>> + (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL;
>> +
>> +failed_kiq_read:
>> + pr_err("failed to read gpu clock\n");
>> + return ~0;
>> +}
>> +
>> static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>> {
>> uint64_t clock;
>> @@ -3970,16 +4027,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>> amdgpu_gfx_off_ctrl(adev, false);
>> mutex_lock(&adev->gfx.gpu_clock_mutex);
>> if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
>> - uint32_t tmp, lsb, msb, i = 0;
>> - do {
>> - if (i != 0)
>> - udelay(1);
>> - tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
>> - lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
>> - msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
>> - i++;
>> - } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
>> - clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
>> + clock = amdgpu_kiq_read_clock(adev);
>> } else {
>> WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
>> clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
2020-02-26 14:29 ` Alex Deucher
2020-02-26 16:18 ` Christian König
@ 2020-02-27 2:03 ` Deng, Emily
1 sibling, 0 replies; 5+ messages in thread
From: Deng, Emily @ 2020-02-27 2:03 UTC (permalink / raw)
To: Alex Deucher; +Cc: amd-gfx list
[-- Attachment #1: Type: text/plain, Size: 5648 bytes --]
[AMD Official Use Only - Internal Distribution Only]
Thanks Alex and Christian. Already renamed it according your request. Please help review.
Best wishes
Emily Deng
>-----Original Message-----
>From: Alex Deucher <alexdeucher@gmail.com>
>Sent: Wednesday, February 26, 2020 10:30 PM
>To: Deng, Emily <Emily.Deng@amd.com>
>Cc: amd-gfx list <amd-gfx@lists.freedesktop.org>
>Subject: Re: [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock
>
>On Tue, Feb 25, 2020 at 11:34 PM Emily Deng <Emily.Deng@amd.com> wrote:
>>
>> For vega10 sriov, the register is blocked, use copy data command to
>> fix the issue.
>>
>> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
>> ---
>> drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68
>> +++++++++++++++++++++++++++++------
>> 1 file changed, 58 insertions(+), 10 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> index 1c7a16b..71df0d9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
>> @@ -3963,6 +3963,63 @@ static int gfx_v9_0_soft_reset(void *handle)
>> return 0;
>> }
>>
>> +static uint64_t amdgpu_kiq_read_clock(struct amdgpu_device *adev)
>
>Please name this function gfx_v9_0_kiq_read_clock for consistency.
>
>
>> +{
>> + signed long r, cnt = 0;
>> + unsigned long flags;
>> + uint32_t seq;
>> + struct amdgpu_kiq *kiq = &adev->gfx.kiq;
>> + struct amdgpu_ring *ring = &kiq->ring;
>> +
>> + BUG_ON(!ring->funcs->emit_rreg);
>> +
>> + spin_lock_irqsave(&kiq->ring_lock, flags);
>> + amdgpu_ring_alloc(ring, 32);
>> + amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
>> + amdgpu_ring_write(ring, 9 | /* src: register*/
>
>Is src 9 the counter?
Yes, it is gpu counter.
>
>Assuming that is correct, with the naming fixed:
>Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
>
>> + (5 << 8) | /* dst: memory */
>> + (1 << 16) | /* count sel */
>> + (1 << 20)); /* write confirm */
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, 0);
>> + amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
>> + kiq->reg_val_offs * 4));
>> + amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
>> + kiq->reg_val_offs * 4));
>> + amdgpu_fence_emit_polling(ring, &seq);
>> + amdgpu_ring_commit(ring);
>> + spin_unlock_irqrestore(&kiq->ring_lock, flags);
>> +
>> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
>> +
>> + /* don't wait anymore for gpu reset case because this way may
>> + * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
>> + * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
>> + * never return if we keep waiting in virt_kiq_rreg, which cause
>> + * gpu_recover() hang there.
>> + *
>> + * also don't wait anymore for IRQ context
>> + * */
>> + if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
>> + goto failed_kiq_read;
>> +
>> + might_sleep();
>> + while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
>> + msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
>> + r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
>> + }
>> +
>> + if (cnt > MAX_KIQ_REG_TRY)
>> + goto failed_kiq_read;
>> +
>> + return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
>> + (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] <<
>> + 32ULL;
>> +
>> +failed_kiq_read:
>> + pr_err("failed to read gpu clock\n");
>> + return ~0;
>> +}
>> +
>> static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device
>> *adev) {
>> uint64_t clock;
>> @@ -3970,16 +4027,7 @@ static uint64_t
>gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
>> amdgpu_gfx_off_ctrl(adev, false);
>> mutex_lock(&adev->gfx.gpu_clock_mutex);
>> if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
>> - uint32_t tmp, lsb, msb, i = 0;
>> - do {
>> - if (i != 0)
>> - udelay(1);
>> - tmp = RREG32_SOC15(GC, 0,
>mmRLC_REFCLOCK_TIMESTAMP_MSB);
>> - lsb = RREG32_SOC15(GC, 0,
>mmRLC_REFCLOCK_TIMESTAMP_LSB);
>> - msb = RREG32_SOC15(GC, 0,
>mmRLC_REFCLOCK_TIMESTAMP_MSB);
>> - i++;
>> - } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
>> - clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
>> + clock = amdgpu_kiq_read_clock(adev);
>> } else {
>> WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
>> clock = (uint64_t)RREG32_SOC15(GC, 0,
>> mmRLC_GPU_CLOCK_COUNT_LSB) |
>> --
>> 2.7.4
>>
>> _______________________________________________
>> amd-gfx mailing list
>> amd-gfx@lists.freedesktop.org
>> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Flist
>> s.freedesktop.org%2Fmailman%2Flistinfo%2Famd-
>gfx&data=02%7C01%7CEm
>>
>ily.Deng%40amd.com%7C9ebe490f88644de35b9a08d7bac85d1c%7C3dd8961fe4
>884e
>>
>608e11a82d994e183d%7C0%7C0%7C637183242027868417&sdata=6mdbo
>Q%2BeeH
>> KeQXnEm%2B6lFfMuBnMSfGhxpWXHjfg6Vso%3D&reserved=0
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From: "Deng, Emily" <Emily.Deng@amd.com>
To: "amd-gfx@lists.freedesktop.org" <amd-gfx@lists.freedesktop.org>
Cc: "Deng, Emily" <Emily.Deng@amd.com>
Subject: [PATCH v2] drm/amdgpu/sriov: Use kiq to copy the gpu clock
Date: Thu, 27 Feb 2020 01:48:15 +0000
Message-ID: <1582768095-7917-1-git-send-email-Emily.Deng@amd.com>
For vega10 sriov, the register is blocked, use
copy data command to fix the issue.
v2: Rename amdgpu_kiq_read_clock to gfx_v9_0_kiq_read_clock.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c | 68 +++++++++++++++++++++++++++++------
1 file changed, 58 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index edd5501..5f7336a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3978,6 +3978,63 @@ static int gfx_v9_0_soft_reset(void *handle)
return 0;
}
+static uint64_t gfx_v9_0_kiq_read_clock(struct amdgpu_device *adev)
+{
+ signed long r, cnt = 0;
+ unsigned long flags;
+ uint32_t seq;
+ struct amdgpu_kiq *kiq = &adev->gfx.kiq;
+ struct amdgpu_ring *ring = &kiq->ring;
+
+ BUG_ON(!ring->funcs->emit_rreg);
+
+ spin_lock_irqsave(&kiq->ring_lock, flags);
+ amdgpu_ring_alloc(ring, 32);
+ amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
+ amdgpu_ring_write(ring, 9 | /* src: register*/
+ (5 << 8) | /* dst: memory */
+ (1 << 16) | /* count sel */
+ (1 << 20)); /* write confirm */
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, 0);
+ amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
+ kiq->reg_val_offs * 4));
+ amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
+ kiq->reg_val_offs * 4));
+ amdgpu_fence_emit_polling(ring, &seq);
+ amdgpu_ring_commit(ring);
+ spin_unlock_irqrestore(&kiq->ring_lock, flags);
+
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+
+ /* don't wait anymore for gpu reset case because this way may
+ * block gpu_recover() routine forever, e.g. this virt_kiq_rreg
+ * is triggered in TTM and ttm_bo_lock_delayed_workqueue() will
+ * never return if we keep waiting in virt_kiq_rreg, which cause
+ * gpu_recover() hang there.
+ *
+ * also don't wait anymore for IRQ context
+ * */
+ if (r < 1 && (adev->in_gpu_reset || in_interrupt()))
+ goto failed_kiq_read;
+
+ might_sleep();
+ while (r < 1 && cnt++ < MAX_KIQ_REG_TRY) {
+ msleep(MAX_KIQ_REG_BAILOUT_INTERVAL);
+ r = amdgpu_fence_wait_polling(ring, seq, MAX_KIQ_REG_WAIT);
+ }
+
+ if (cnt > MAX_KIQ_REG_TRY)
+ goto failed_kiq_read;
+
+ return (uint64_t)adev->wb.wb[kiq->reg_val_offs] |
+ (uint64_t)adev->wb.wb[kiq->reg_val_offs + 1 ] << 32ULL;
+
+failed_kiq_read:
+ pr_err("failed to read gpu clock\n");
+ return ~0;
+}
+
static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
{
uint64_t clock;
@@ -3985,16 +4042,7 @@ static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
amdgpu_gfx_off_ctrl(adev, false);
mutex_lock(&adev->gfx.gpu_clock_mutex);
if (adev->asic_type == CHIP_VEGA10 && amdgpu_sriov_runtime(adev)) {
- uint32_t tmp, lsb, msb, i = 0;
- do {
- if (i != 0)
- udelay(1);
- tmp = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
- lsb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_LSB);
- msb = RREG32_SOC15(GC, 0, mmRLC_REFCLOCK_TIMESTAMP_MSB);
- i++;
- } while (unlikely(tmp != msb) && (i < adev->usec_timeout));
- clock = (uint64_t)lsb | ((uint64_t)msb << 32ULL);
+ clock = gfx_v9_0_kiq_read_clock(adev);
} else {
WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
--
2.7.4
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-- links below jump to the message on this page --
2020-02-26 4:34 [PATCH] drm/amdgpu/sriov: Use kiq to copy the gpu clock Emily Deng
2020-02-26 11:06 ` Liu, Monk
2020-02-26 14:29 ` Alex Deucher
2020-02-26 16:18 ` Christian König
2020-02-27 2:03 ` Deng, Emily
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