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* [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups
@ 2020-03-03 17:33 Ville Syrjala
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
                   ` (18 more replies)
  0 siblings, 19 replies; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Remainder of my earlier gamma cleanups, rebased due to
hw vs. uapi split and intel_de_{read,write}().

Ville Syrjälä (9):
  drm/i915: Polish CHV CGM CSC loading
  drm/i915: Clean up i9xx_load_luts_internal()
  drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  drm/i915: s/blob_data/lut/
  drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  drm/i915: Clean up integer types in color code
  drm/i915: Refactor LUT read functions
  drm/i915: Fix readout of PIPEGCMAX
  drm/i915: Pass the crtc to the low level read_lut() funcs

 drivers/gpu/drm/i915/display/intel_color.c | 407 ++++++++++++---------
 drivers/gpu/drm/i915/i915_reg.h            |   1 -
 2 files changed, 225 insertions(+), 183 deletions(-)

-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06  8:44   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
                   ` (17 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Only load the CGM CSC based on the cgm_mode bit like we
do with the gamma/degamma LUTs. And make the function
naming and arguments consistent as well.

TODO: the code to convert the coefficients look totally
bogus. IIRC CHV uses two's complement format but the code
certainly doesn't generate that, so probably negative
coefficients are totally busted.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 69 +++++++++++-----------
 1 file changed, 35 insertions(+), 34 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 98aefeebda28..444980fdeda6 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -348,48 +348,43 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
 		       crtc_state->csc_mode);
 }
 
-/*
- * Set up the pipe CSC unit on CherryView.
- */
-static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
+static void chv_load_cgm_csc(struct intel_crtc *crtc,
+			     const struct drm_property_blob *blob)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_ctm *ctm = blob->data;
 	enum pipe pipe = crtc->pipe;
+	u16 coeffs[9];
+	int i;
 
-	if (crtc_state->hw.ctm) {
-		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
-		u16 coeffs[9] = {};
-		int i;
+	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
+		u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
 
-		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
-			u64 abs_coeff =
-				((1ULL << 63) - 1) & ctm->matrix[i];
+		/* Round coefficient. */
+		abs_coeff += 1 << (32 - 13);
+		/* Clamp to hardware limits. */
+		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
 
-			/* Round coefficient. */
-			abs_coeff += 1 << (32 - 13);
-			/* Clamp to hardware limits. */
-			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
+		coeffs[i] = 0;
 
-			/* Write coefficients in S3.12 format. */
-			if (ctm->matrix[i] & (1ULL << 63))
-				coeffs[i] = 1 << 15;
-			coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
-			coeffs[i] |= (abs_coeff >> 20) & 0xfff;
-		}
+		/* Write coefficients in S3.12 format. */
+		if (ctm->matrix[i] & (1ULL << 63))
+			coeffs[i] |= 1 << 15;
 
-		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
-			       coeffs[1] << 16 | coeffs[0]);
-		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
-			       coeffs[3] << 16 | coeffs[2]);
-		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
-			       coeffs[5] << 16 | coeffs[4]);
-		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
-			       coeffs[7] << 16 | coeffs[6]);
-		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
+		coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
+		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
 	}
 
-	intel_de_write(dev_priv, CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
+	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
+		       coeffs[1] << 16 | coeffs[0]);
+	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
+		       coeffs[3] << 16 | coeffs[2]);
+	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
+		       coeffs[5] << 16 | coeffs[4]);
+	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
+		       coeffs[7] << 16 | coeffs[6]);
+	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
+		       coeffs[8]);
 }
 
 static u32 i9xx_lut_8(const struct drm_color_lut *color)
@@ -1020,10 +1015,13 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
 static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
 
-	cherryview_load_csc_matrix(crtc_state);
+	if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
+		chv_load_cgm_csc(crtc, ctm);
 
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
 		chv_load_cgm_degamma(crtc, degamma_lut);
@@ -1032,6 +1030,9 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
 		chv_load_cgm_gamma(crtc, gamma_lut);
 	else
 		i965_load_luts(crtc_state);
+
+	intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
+		       crtc_state->cgm_mode);
 }
 
 void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal()
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06 14:42   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
                   ` (16 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Split i9xx_load_luts_internal() into neat gmch vs. ilk+ chunks.
Avoids at least one branch in the inner loop, and makes life
a bit less confusing.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 104 ++++++++++++---------
 1 file changed, 60 insertions(+), 44 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 444980fdeda6..cf8ed4e2ae13 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -417,43 +417,6 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
-/* Loads the legacy palette/gamma unit for the CRTC. */
-static void i9xx_load_luts_internal(const struct intel_crtc_state *crtc_state,
-				    const struct drm_property_blob *blob)
-{
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	enum pipe pipe = crtc->pipe;
-	int i;
-
-	if (HAS_GMCH(dev_priv)) {
-		if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
-			assert_dsi_pll_enabled(dev_priv);
-		else
-			assert_pll_enabled(dev_priv, pipe);
-	}
-
-	if (blob) {
-		const struct drm_color_lut *lut = blob->data;
-
-		for (i = 0; i < 256; i++) {
-			u32 word = i9xx_lut_8(&lut[i]);
-
-			if (HAS_GMCH(dev_priv))
-				intel_de_write(dev_priv, PALETTE(pipe, i),
-					       word);
-			else
-				intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
-					       word);
-		}
-	}
-}
-
-static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
-{
-	i9xx_load_luts_internal(crtc_state, crtc_state->hw.gamma_lut);
-}
-
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -520,6 +483,35 @@ static void skl_color_commit(const struct intel_crtc_state *crtc_state)
 		ilk_load_csc_matrix(crtc_state);
 }
 
+static void i9xx_load_lut_8(struct intel_crtc *crtc,
+			    const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		intel_de_write(dev_priv, PALETTE(pipe, i),
+			       i9xx_lut_8(&lut[i]));
+}
+
+static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
+
+	assert_pll_enabled(dev_priv, crtc->pipe);
+
+	i9xx_load_lut_8(crtc, gamma_lut);
+}
+
 static void i965_load_lut_10p6(struct intel_crtc *crtc,
 			       const struct drm_property_blob *blob)
 {
@@ -543,14 +535,38 @@ static void i965_load_lut_10p6(struct intel_crtc *crtc,
 static void i965_load_luts(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
+	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
+		assert_dsi_pll_enabled(dev_priv);
+	else
+		assert_pll_enabled(dev_priv, crtc->pipe);
+
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		i9xx_load_lut_8(crtc, gamma_lut);
 	else
 		i965_load_lut_10p6(crtc, gamma_lut);
 }
 
+static void ilk_load_lut_8(struct intel_crtc *crtc,
+			   const struct drm_property_blob *blob)
+{
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	const struct drm_color_lut *lut;
+	enum pipe pipe = crtc->pipe;
+	int i;
+
+	if (!blob)
+		return;
+
+	lut = blob->data;
+
+	for (i = 0; i < 256; i++)
+		intel_de_write(dev_priv, LGC_PALETTE(pipe, i),
+			       i9xx_lut_8(&lut[i]));
+}
+
 static void ilk_load_lut_10(struct intel_crtc *crtc,
 			    const struct drm_property_blob *blob)
 {
@@ -561,7 +577,7 @@ static void ilk_load_lut_10(struct intel_crtc *crtc,
 
 	for (i = 0; i < lut_size; i++)
 		intel_de_write(dev_priv, PREC_PALETTE(pipe, i),
-		               ilk_lut_10(&lut[i]));
+			       ilk_lut_10(&lut[i]));
 }
 
 static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
@@ -570,7 +586,7 @@ static void ilk_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	else
 		ilk_load_lut_10(crtc, gamma_lut);
 }
@@ -680,7 +696,7 @@ static void ivb_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		ivb_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -703,7 +719,7 @@ static void bdw_load_luts(const struct intel_crtc_state *crtc_state)
 	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else if (crtc_state->gamma_mode == GAMMA_MODE_MODE_SPLIT) {
 		bdw_load_lut_10(crtc, degamma_lut, PAL_PREC_SPLIT_MODE |
 				PAL_PREC_INDEX_VALUE(0));
@@ -807,7 +823,7 @@ static void glk_load_luts(const struct intel_crtc_state *crtc_state)
 		glk_load_degamma_lut_linear(crtc_state);
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT) {
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 	} else {
 		bdw_load_lut_10(crtc, gamma_lut, PAL_PREC_INDEX_VALUE(0));
 		ivb_load_lut_ext_max(crtc);
@@ -943,7 +959,7 @@ static void icl_load_luts(const struct intel_crtc_state *crtc_state)
 
 	switch (crtc_state->gamma_mode & GAMMA_MODE_MODE_MASK) {
 	case GAMMA_MODE_MODE_8BIT:
-		i9xx_load_luts(crtc_state);
+		ilk_load_lut_8(crtc, gamma_lut);
 		break;
 	case GAMMA_MODE_MODE_12BIT_MULTI_SEGMENTED:
 		icl_program_gamma_superfine_segment(crtc_state);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-04  2:54     ` kbuild test robot
  2020-03-06 15:00   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/ Ville Syrjala
                   ` (15 subsequent siblings)
  18 siblings, 2 replies; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

To mirror the load_luts path let's clone an ilk+ version
from i9xx_read_lut_8(). I guess the extra branch isn't a huge
issue but feels better to make a clean split.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 41 ++++++++++++++++++----
 1 file changed, 35 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index cf8ed4e2ae13..e3abaa1908a9 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1706,10 +1706,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	blob_data = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		if (HAS_GMCH(dev_priv))
-			val = intel_de_read(dev_priv, PALETTE(pipe, i));
-		else
-			val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
+		val = intel_de_read(dev_priv, PALETTE(pipe, i));
 
 		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1824,6 +1821,38 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
 		i965_read_luts(crtc_state);
 }
 
+static struct drm_property_blob *
+ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+{
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+	enum pipe pipe = crtc->pipe;
+	struct drm_property_blob *blob;
+	struct drm_color_lut *blob_data;
+	u32 i, val;
+
+	blob = drm_property_create_blob(&dev_priv->drm,
+					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
+					NULL);
+	if (IS_ERR(blob))
+		return NULL;
+
+	blob_data = blob->data;
+
+	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
+		val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
+
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+							LGC_PALETTE_RED_MASK, val), 8);
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+							  LGC_PALETTE_GREEN_MASK, val), 8);
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+							 LGC_PALETTE_BLUE_MASK, val), 8);
+	}
+
+	return blob;
+}
+
 static struct drm_property_blob *
 ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
@@ -1866,7 +1895,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
 }
@@ -1915,7 +1944,7 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
 	else
 		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
 }
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (2 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06 15:03   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
                   ` (14 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

We're talking about LUT contents here so let's call the thing
'lut' rather than 'blob_data'. This is the name the load_lut()
code used before already.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++-----------
 1 file changed, 33 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index e3abaa1908a9..f90f113355bc 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1694,7 +1694,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1703,16 +1703,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = intel_de_read(dev_priv, PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1735,7 +1735,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1744,25 +1744,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
 		val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
 		val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
 
-		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
+		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
+		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
 						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
+		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
 						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
 	}
 
-	blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
-	blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
-	blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
 
 	return blob;
@@ -1787,7 +1787,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1796,17 +1796,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
 
 		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							CGM_PIPE_GAMMA_RED_MASK, val), 10);
 	}
 
@@ -1828,7 +1828,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1837,16 +1837,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  LGC_PALETTE_GREEN_MASK, val), 8);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 LGC_PALETTE_BLUE_MASK, val), 8);
 	}
 
@@ -1861,7 +1861,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1870,16 +1870,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
 		val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  PREC_PALETTE_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							 PREC_PALETTE_BLUE_MASK, val), 10);
 	}
 
@@ -1908,7 +1908,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	int hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
-	struct drm_color_lut *blob_data;
+	struct drm_color_lut *lut;
 	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
@@ -1917,7 +1917,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	if (IS_ERR(blob))
 		return NULL;
 
-	blob_data = blob->data;
+	lut = blob->data;
 
 	intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
 		       prec_index | PAL_PREC_AUTO_INCREMENT);
@@ -1925,11 +1925,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	for (i = 0; i < hw_lut_size; i++) {
 		val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
 
-		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_BLUE_MASK, val), 10);
 	}
 
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (3 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/ Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06 15:18   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code Ville Syrjala
                   ` (13 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so
let's rename it to reflect that fact. This also mirrors
the other direction's chv_load_cgm_gamma().

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index f90f113355bc..ab23b24e7be3 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1780,7 +1780,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
 }
 
 static struct drm_property_blob *
-chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
+chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
@@ -1816,7 +1816,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
 	else
 		i965_read_luts(crtc_state);
 }
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (4 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06 15:24   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions Ville Syrjala
                   ` (12 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A variable called 'i' having an unsigned type is just looking for
trouble, and using a sized type generally makes no sense either.
Change all of them to just plain old int. And do the same for some
'lut_size' variables which generally provide the loop end codition
for 'i'.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 43 ++++++++++------------
 1 file changed, 19 insertions(+), 24 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ab23b24e7be3..934f00817c5c 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -740,9 +740,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
-	u32 i;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -781,8 +780,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
-	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
-	u32 i;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
 
 	/*
 	 * When setting the auto-increment bit, the hardware seems to
@@ -867,7 +865,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *lut = blob->data;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Super Fine segment (let's call it seg1)...
@@ -900,7 +898,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
 	const struct drm_color_lut *entry;
 	struct intel_dsb *dsb = intel_dsb_get(crtc);
 	enum pipe pipe = crtc->pipe;
-	u32 i;
+	int i;
 
 	/*
 	 * Program Fine segment (let's call it seg2)...
@@ -1675,7 +1673,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 }
 
 /* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
 {
 	u32 max = 0xffff >> (16 - bit_precision);
 
@@ -1695,7 +1693,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1706,7 +1704,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = intel_de_read(dev_priv, PALETTE(pipe, i));
+		u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1732,11 +1730,10 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val1, val2;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1747,8 +1744,8 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
-		val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
+		u32 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
+		u32 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
 
 		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
 						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
@@ -1784,11 +1781,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1799,7 +1795,8 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
+		u32 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
+
 		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
 							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
 		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
@@ -1829,7 +1826,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
+	int i;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
@@ -1840,7 +1837,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
-		val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
+		u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							LGC_PALETTE_RED_MASK, val), 8);
@@ -1858,11 +1855,10 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
+	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * lut_size,
@@ -1873,7 +1869,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
+		u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PALETTE_RED_MASK, val), 10);
@@ -1905,11 +1901,10 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-	int hw_lut_size = ivb_lut_10_size(prec_index);
+	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
 	struct drm_color_lut *lut;
-	u32 i, val;
 
 	blob = drm_property_create_blob(&dev_priv->drm,
 					sizeof(struct drm_color_lut) * hw_lut_size,
@@ -1923,7 +1918,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 		       prec_index | PAL_PREC_AUTO_INCREMENT);
 
 	for (i = 0; i < hw_lut_size; i++) {
-		val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
+		u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
 
 		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
 							PREC_PAL_DATA_RED_MASK, val), 10);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (5 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06 15:28   ` Sharma, Swati2
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix readout of PIPEGCMAX Ville Syrjala
                   ` (11 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Extract all the 'hw value -> LUT entry' stuff into small helpers
to make the main 'read out the entire LUT' loop less bogged down
by such mundane details.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 122 +++++++++++----------
 1 file changed, 62 insertions(+), 60 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 934f00817c5c..8796f04e23a8 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -387,6 +387,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
 		       coeffs[8]);
 }
 
+/* convert hw value with given bit_precision to lut property val */
+static u32 intel_color_lut_pack(u32 val, int bit_precision)
+{
+	u32 max = 0xffff >> (16 - bit_precision);
+
+	val = clamp_val(val, 0, max);
+
+	if (bit_precision < 16)
+		val <<= 16 - bit_precision;
+
+	return val;
+}
+
 static u32 i9xx_lut_8(const struct drm_color_lut *color)
 {
 	return drm_color_lut_extract(color->red, 8) << 16 |
@@ -394,6 +407,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 8);
 }
 
+static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
+{
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
+}
+
 /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
 static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
 {
@@ -410,6 +430,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
 		(color->blue >> 8);
 }
 
+static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_RED_MASK, ldw);
+	entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
+	entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
+		REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
+}
+
+static u16 i965_lut_11p6_max_pack(u32 val)
+{
+	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+}
+
 static u32 ilk_lut_10(const struct drm_color_lut *color)
 {
 	return drm_color_lut_extract(color->red, 10) << 20 |
@@ -417,6 +452,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
 		drm_color_lut_extract(color->blue, 10);
 }
 
+static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
+{
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
+}
+
 static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
 {
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
@@ -983,6 +1025,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
 	return drm_color_lut_extract(color->red, 14);
 }
 
+static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
+{
+	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
+	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
+	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
+}
+
 static void chv_load_cgm_degamma(struct intel_crtc *crtc,
 				 const struct drm_property_blob *blob)
 {
@@ -1672,19 +1721,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-/* convert hw value with given bit_precision to lut property val */
-static u32 intel_color_lut_pack(u32 val, int bit_precision)
-{
-	u32 max = 0xffff >> (16 - bit_precision);
-
-	val = clamp_val(val, 0, max);
-
-	if (bit_precision < 16)
-		val <<= 16 - bit_precision;
-
-	return val;
-}
-
 static struct drm_property_blob *
 i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 {
@@ -1706,12 +1742,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							LGC_PALETTE_RED_MASK, val), 8);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  LGC_PALETTE_GREEN_MASK, val), 8);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 LGC_PALETTE_BLUE_MASK, val), 8);
+		i9xx_lut_8_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1744,23 +1775,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size - 1; i++) {
-		u32 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
-		u32 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
+		u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
+		u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
 
-		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
-						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
-		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
-						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
-		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
-						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
+		i965_lut_10p6_pack(&lut[i], ldw, udw);
 	}
 
-	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
-	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					   intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
-	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
-					  intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
+	lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
+	lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
+	lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
 
 	return blob;
 }
@@ -1795,16 +1818,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 	lut = blob->data;
 
 	for (i = 0; i < lut_size; i++) {
-		u32 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
+		u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
+		u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
 
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
-
-		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							CGM_PIPE_GAMMA_RED_MASK, val), 10);
+		chv_cgm_gamma_pack(&lut[i], ldw, udw);
 	}
 
 	return blob;
@@ -1839,12 +1856,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
 		u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							LGC_PALETTE_RED_MASK, val), 8);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  LGC_PALETTE_GREEN_MASK, val), 8);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 LGC_PALETTE_BLUE_MASK, val), 8);
+		i9xx_lut_8_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1871,12 +1883,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 	for (i = 0; i < lut_size; i++) {
 		u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PALETTE_RED_MASK, val), 10);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							  PREC_PALETTE_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							 PREC_PALETTE_BLUE_MASK, val), 10);
+		ilk_lut_10_pack(&lut[i], val);
 	}
 
 	return blob;
@@ -1920,12 +1927,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 	for (i = 0; i < hw_lut_size; i++) {
 		u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
 
-		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_RED_MASK, val), 10);
-		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_GREEN_MASK, val), 10);
-		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
-							PREC_PAL_DATA_BLUE_MASK, val), 10);
+		ilk_lut_10_pack(&lut[i], val);
 	}
 
 	intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix readout of PIPEGCMAX
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (6 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
                   ` (10 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

PIPEGCMAX is a 11.6 (or 1.16 if you will) value. Ie. it can
represent a value of 1.0 when the maximum we can store in the
software LUT is 0.ffff. Clamp the value so that it gets
saturated to the max the uapi supports.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 3 ++-
 drivers/gpu/drm/i915/i915_reg.h            | 1 -
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index 8796f04e23a8..ed9996aacafd 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -442,7 +442,8 @@ static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
 
 static u16 i965_lut_11p6_max_pack(u32 val)
 {
-	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
+	/* PIPEGCMAX is 11.6, clamp to 10.6 */
+	return clamp_val(val, 0, 0xffff);
 }
 
 static u32 ilk_lut_10(const struct drm_color_lut *color)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 80cf02a6eec1..79ae9654dac9 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5870,7 +5870,6 @@ enum {
 
 #define  _PIPEAGCMAX           0x70010
 #define  _PIPEBGCMAX           0x71010
-#define PIPEGCMAX_RGB_MASK     REG_GENMASK(15, 0)
 #define PIPEGCMAX(pipe, i)     _MMIO_PIPE2(pipe, _PIPEAGCMAX + (i) * 4)
 
 #define _PIPE_MISC_A			0x70030
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (7 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix readout of PIPEGCMAX Ville Syrjala
@ 2020-03-03 17:33 ` Ville Syrjala
  2020-03-06 15:36   ` Sharma, Swati2
  2020-03-03 19:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev3) Patchwork
                   ` (9 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Ville Syrjala @ 2020-03-03 17:33 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

The low level read_lut() functions don't need the entire crtc state
as they know exactly what they're reading. Just need to pass in the
crtc to get at the pipe. This now neatly mirrors the load_lut()
direction.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/display/intel_color.c | 51 +++++++++++-----------
 1 file changed, 25 insertions(+), 26 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index ed9996aacafd..c1cce93a1c25 100644
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -1722,10 +1722,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
 	return true;
 }
 
-static struct drm_property_blob *
-i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1751,16 +1749,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
 
 static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
-	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 }
 
-static struct drm_property_blob *
-i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1791,19 +1789,19 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
 
 static void i965_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
+		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
 }
 
-static struct drm_property_blob *
-chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1830,16 +1828,16 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
 
 static void chv_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
-		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
+		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
 	else
 		i965_read_luts(crtc_state);
 }
 
-static struct drm_property_blob *
-ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	struct drm_property_blob *blob;
@@ -1863,10 +1861,8 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
 	return blob;
 }
 
-static struct drm_property_blob *
-ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
+static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
 	enum pipe pipe = crtc->pipe;
@@ -1892,6 +1888,8 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
 
 static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
@@ -1899,15 +1897,14 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
 }
 
-static struct drm_property_blob *
-glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
+static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
+						 u32 prec_index)
 {
-	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 	int i, hw_lut_size = ivb_lut_10_size(prec_index);
 	enum pipe pipe = crtc->pipe;
@@ -1938,13 +1935,15 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
 
 static void glk_read_luts(struct intel_crtc_state *crtc_state)
 {
+	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+
 	if (!crtc_state->gamma_enable)
 		return;
 
 	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
-		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
+		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
 	else
-		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
+		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
 }
 
 void intel_color_init(struct intel_crtc *crtc)
-- 
2.24.1

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev3)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (8 preceding siblings ...)
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
@ 2020-03-03 19:21 ` Patchwork
  2020-03-03 19:38 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
                   ` (8 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-03 19:21 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev3)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
a80ba6cf6eef drm/i915: Polish CHV CGM CSC loading
68f1bc86f1b8 drm/i915: Clean up i9xx_load_luts_internal()
11ff682dafcd drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:56: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#56: FILE: drivers/gpu/drm/i915/display/intel_color.c:1845:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1847:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1849:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
2bd70fc18de0 drm/i915: s/blob_data/lut/
-:39: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#39: FILE: drivers/gpu/drm/i915/display/intel_color.c:1711:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:42: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#42: FILE: drivers/gpu/drm/i915/display/intel_color.c:1713:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:45: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#45: FILE: drivers/gpu/drm/i915/display/intel_color.c:1715:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:82: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#82: FILE: drivers/gpu/drm/i915/display/intel_color.c:1762:
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));

-:85: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#85: FILE: drivers/gpu/drm/i915/display/intel_color.c:1764:
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));

-:88: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#88: FILE: drivers/gpu/drm/i915/display/intel_color.c:1766:
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));

-:110: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#110: FILE: drivers/gpu/drm/i915/display/intel_color.c:1803:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:113: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#113: FILE: drivers/gpu/drm/i915/display/intel_color.c:1805:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:118: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#118: FILE: drivers/gpu/drm/i915/display/intel_color.c:1809:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:142: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#142: FILE: drivers/gpu/drm/i915/display/intel_color.c:1845:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:145: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#145: FILE: drivers/gpu/drm/i915/display/intel_color.c:1847:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:148: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#148: FILE: drivers/gpu/drm/i915/display/intel_color.c:1849:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:172: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#172: FILE: drivers/gpu/drm/i915/display/intel_color.c:1878:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:175: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#175: FILE: drivers/gpu/drm/i915/display/intel_color.c:1880:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:178: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#178: FILE: drivers/gpu/drm/i915/display/intel_color.c:1882:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:205: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#205: FILE: drivers/gpu/drm/i915/display/intel_color.c:1928:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:208: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#208: FILE: drivers/gpu/drm/i915/display/intel_color.c:1930:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:211: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#211: FILE: drivers/gpu/drm/i915/display/intel_color.c:1932:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
5d0116537847 drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
0608422e4221 drm/i915: Clean up integer types in color code
32017c748224 drm/i915: Refactor LUT read functions
4dbbf6bed479 drm/i915: Fix readout of PIPEGCMAX
1be5c304ba4b drm/i915: Pass the crtc to the low level read_lut() funcs

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Gamma cleanups (rev3)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (9 preceding siblings ...)
  2020-03-03 19:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev3) Patchwork
@ 2020-03-03 19:38 ` Patchwork
  2020-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
                   ` (7 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-03 19:38 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev3)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs'

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Gamma cleanups (rev3)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (10 preceding siblings ...)
  2020-03-03 19:38 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2020-03-03 20:00 ` Patchwork
  2020-03-06 15:40 ` [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Sharma, Swati2
                   ` (6 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-03 20:00 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev3)
URL   : https://patchwork.freedesktop.org/series/69136/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8057 -> Patchwork_16801
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16801 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16801, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16801/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16801:

### IGT changes ###

#### Possible regressions ####

  * igt@runner@aborted:
    - fi-kbl-guc:         NOTRUN -> [FAIL][1]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16801/fi-kbl-guc/igt@runner@aborted.html

  
Known issues
------------

  Here are the changes found in Patchwork_16801 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@execlists:
    - fi-kbl-guc:         [PASS][2] -> [INCOMPLETE][3] ([fdo#112175] / [fdo#112259])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8057/fi-kbl-guc/igt@i915_selftest@live@execlists.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16801/fi-kbl-guc/igt@i915_selftest@live@execlists.html

  * igt@kms_addfb_basic@addfb25-x-tiled:
    - fi-tgl-y:           [PASS][4] -> [DMESG-WARN][5] ([CI#94] / [i915#402])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8057/fi-tgl-y/igt@kms_addfb_basic@addfb25-x-tiled.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16801/fi-tgl-y/igt@kms_addfb_basic@addfb25-x-tiled.html

  
#### Possible fixes ####

  * igt@vgem_basic@mmap:
    - fi-tgl-y:           [DMESG-WARN][6] ([CI#94] / [i915#402]) -> [PASS][7] +1 similar issue
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8057/fi-tgl-y/igt@vgem_basic@mmap.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16801/fi-tgl-y/igt@vgem_basic@mmap.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [fdo#112175]: https://bugs.freedesktop.org/show_bug.cgi?id=112175
  [fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Participating hosts (43 -> 37)
------------------------------

  Additional (3): fi-bsw-kefka fi-kbl-7500u fi-snb-2600 
  Missing    (9): fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-snb-2520m fi-elk-e7500 fi-blb-e6850 fi-byt-clapper fi-bsw-nick fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8057 -> Patchwork_16801

  CI-20190529: 20190529
  CI_DRM_8057: 45ca41e870e508bf9040b308d9ff1ccf7ab779e2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5488: 5b6930b4d267f7002c2e9442262e21a725941db5 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16801: 1be5c304ba4b3c4fca354a0a55acfe648bd25a6c @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1be5c304ba4b drm/i915: Pass the crtc to the low level read_lut() funcs
4dbbf6bed479 drm/i915: Fix readout of PIPEGCMAX
32017c748224 drm/i915: Refactor LUT read functions
0608422e4221 drm/i915: Clean up integer types in color code
5d0116537847 drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
2bd70fc18de0 drm/i915: s/blob_data/lut/
11ff682dafcd drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
68f1bc86f1b8 drm/i915: Clean up i9xx_load_luts_internal()
a80ba6cf6eef drm/i915: Polish CHV CGM CSC loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16801/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
@ 2020-03-04  2:54     ` kbuild test robot
  2020-03-06 15:00   ` Sharma, Swati2
  1 sibling, 0 replies; 36+ messages in thread
From: kbuild test robot @ 2020-03-04  2:54 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx, kbuild-all

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to v5.6-rc4 next-20200303]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Gamma-cleanups/20200304-043847
base:   git://anongit.freedesktop.org/drm-intel for-linux-next

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

New smatch warnings:
drivers/gpu/drm/i915/display/intel_color.c:1840 ilk_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)

Old smatch warnings:
drivers/gpu/drm/i915/display/intel_color.c:1706 i9xx_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1747 i965_read_lut_10p6() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1799 chv_read_cgm_lut() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1873 ilk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1920 glk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)

vim +/blob +1840 drivers/gpu/drm/i915/display/intel_color.c

  1823	
  1824	static struct drm_property_blob *
  1825	ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
  1826	{
  1827		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
  1828		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  1829		enum pipe pipe = crtc->pipe;
  1830		struct drm_property_blob *blob;
  1831		struct drm_color_lut *blob_data;
  1832		u32 i, val;
  1833	
  1834		blob = drm_property_create_blob(&dev_priv->drm,
  1835						sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
  1836						NULL);
  1837		if (IS_ERR(blob))
  1838			return NULL;
  1839	
> 1840		blob_data = blob->data;
  1841	
  1842		for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
  1843			val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
  1844	
  1845			blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
  1846								LGC_PALETTE_RED_MASK, val), 8);
  1847			blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
  1848								  LGC_PALETTE_GREEN_MASK, val), 8);
  1849			blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
  1850								 LGC_PALETTE_BLUE_MASK, val), 8);
  1851		}
  1852	
  1853		return blob;
  1854	}
  1855	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
@ 2020-03-04  2:54     ` kbuild test robot
  0 siblings, 0 replies; 36+ messages in thread
From: kbuild test robot @ 2020-03-04  2:54 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 3046 bytes --]

Hi Ville,

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm-intel/for-linux-next]
[also build test WARNING on drm-tip/drm-tip]
[cannot apply to v5.6-rc4 next-20200303]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Gamma-cleanups/20200304-043847
base:   git://anongit.freedesktop.org/drm-intel for-linux-next

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

New smatch warnings:
drivers/gpu/drm/i915/display/intel_color.c:1840 ilk_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)

Old smatch warnings:
drivers/gpu/drm/i915/display/intel_color.c:1706 i9xx_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1747 i965_read_lut_10p6() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1799 chv_read_cgm_lut() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1873 ilk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
drivers/gpu/drm/i915/display/intel_color.c:1920 glk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)

vim +/blob +1840 drivers/gpu/drm/i915/display/intel_color.c

  1823	
  1824	static struct drm_property_blob *
  1825	ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
  1826	{
  1827		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
  1828		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
  1829		enum pipe pipe = crtc->pipe;
  1830		struct drm_property_blob *blob;
  1831		struct drm_color_lut *blob_data;
  1832		u32 i, val;
  1833	
  1834		blob = drm_property_create_blob(&dev_priv->drm,
  1835						sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
  1836						NULL);
  1837		if (IS_ERR(blob))
  1838			return NULL;
  1839	
> 1840		blob_data = blob->data;
  1841	
  1842		for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
  1843			val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
  1844	
  1845			blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
  1846								LGC_PALETTE_RED_MASK, val), 8);
  1847			blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
  1848								  LGC_PALETTE_GREEN_MASK, val), 8);
  1849			blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
  1850								 LGC_PALETTE_BLUE_MASK, val), 8);
  1851		}
  1852	
  1853		return blob;
  1854	}
  1855	

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  2020-03-04  2:54     ` kbuild test robot
@ 2020-03-04 11:51       ` Ville Syrjälä
  -1 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2020-03-04 11:51 UTC (permalink / raw)
  To: kbuild test robot; +Cc: intel-gfx, kbuild-all

On Wed, Mar 04, 2020 at 10:54:44AM +0800, kbuild test robot wrote:
> Hi Ville,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm-intel/for-linux-next]
> [also build test WARNING on drm-tip/drm-tip]
> [cannot apply to v5.6-rc4 next-20200303]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system. BTW, we also suggest to use '--base' option to specify the
> base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
> 
> url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Gamma-cleanups/20200304-043847
> base:   git://anongit.freedesktop.org/drm-intel for-linux-next
> 
> If you fix the issue, kindly add following tag
> Reported-by: kbuild test robot <lkp@intel.com>
> 
> New smatch warnings:
> drivers/gpu/drm/i915/display/intel_color.c:1840 ilk_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)

drm_property_create_blob() does _not_ return NULL. Why does this thing
think it does?

> 
> Old smatch warnings:
> drivers/gpu/drm/i915/display/intel_color.c:1706 i9xx_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1747 i965_read_lut_10p6() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1799 chv_read_cgm_lut() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1873 ilk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1920 glk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> 
> vim +/blob +1840 drivers/gpu/drm/i915/display/intel_color.c
> 
>   1823	
>   1824	static struct drm_property_blob *
>   1825	ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   1826	{
>   1827		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   1828		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   1829		enum pipe pipe = crtc->pipe;
>   1830		struct drm_property_blob *blob;
>   1831		struct drm_color_lut *blob_data;
>   1832		u32 i, val;
>   1833	
>   1834		blob = drm_property_create_blob(&dev_priv->drm,
>   1835						sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
>   1836						NULL);
>   1837		if (IS_ERR(blob))
>   1838			return NULL;
>   1839	
> > 1840		blob_data = blob->data;
>   1841	
>   1842		for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
>   1843			val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
>   1844	
>   1845			blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   1846								LGC_PALETTE_RED_MASK, val), 8);
>   1847			blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   1848								  LGC_PALETTE_GREEN_MASK, val), 8);
>   1849			blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   1850								 LGC_PALETTE_BLUE_MASK, val), 8);
>   1851		}
>   1852	
>   1853		return blob;
>   1854	}
>   1855	
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
@ 2020-03-04 11:51       ` Ville Syrjälä
  0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2020-03-04 11:51 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 3371 bytes --]

On Wed, Mar 04, 2020 at 10:54:44AM +0800, kbuild test robot wrote:
> Hi Ville,
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm-intel/for-linux-next]
> [also build test WARNING on drm-tip/drm-tip]
> [cannot apply to v5.6-rc4 next-20200303]
> [if your patch is applied to the wrong git tree, please drop us a note to help
> improve the system. BTW, we also suggest to use '--base' option to specify the
> base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
> 
> url:    https://github.com/0day-ci/linux/commits/Ville-Syrjala/drm-i915-Gamma-cleanups/20200304-043847
> base:   git://anongit.freedesktop.org/drm-intel for-linux-next
> 
> If you fix the issue, kindly add following tag
> Reported-by: kbuild test robot <lkp@intel.com>
> 
> New smatch warnings:
> drivers/gpu/drm/i915/display/intel_color.c:1840 ilk_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)

drm_property_create_blob() does _not_ return NULL. Why does this thing
think it does?

> 
> Old smatch warnings:
> drivers/gpu/drm/i915/display/intel_color.c:1706 i9xx_read_lut_8() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1747 i965_read_lut_10p6() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1799 chv_read_cgm_lut() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1873 ilk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> drivers/gpu/drm/i915/display/intel_color.c:1920 glk_read_lut_10() error: potential null dereference 'blob'.  (drm_property_create_blob returns null)
> 
> vim +/blob +1840 drivers/gpu/drm/i915/display/intel_color.c
> 
>   1823	
>   1824	static struct drm_property_blob *
>   1825	ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   1826	{
>   1827		struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   1828		struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   1829		enum pipe pipe = crtc->pipe;
>   1830		struct drm_property_blob *blob;
>   1831		struct drm_color_lut *blob_data;
>   1832		u32 i, val;
>   1833	
>   1834		blob = drm_property_create_blob(&dev_priv->drm,
>   1835						sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
>   1836						NULL);
>   1837		if (IS_ERR(blob))
>   1838			return NULL;
>   1839	
> > 1840		blob_data = blob->data;
>   1841	
>   1842		for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
>   1843			val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
>   1844	
>   1845			blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   1846								LGC_PALETTE_RED_MASK, val), 8);
>   1847			blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   1848								  LGC_PALETTE_GREEN_MASK, val), 8);
>   1849			blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   1850								 LGC_PALETTE_BLUE_MASK, val), 8);
>   1851		}
>   1852	
>   1853		return blob;
>   1854	}
>   1855	
> 
> ---
> 0-DAY CI Kernel Test Service, Intel Corporation
> https://lists.01.org/hyperkitty/list/kbuild-all(a)lists.01.org

-- 
Ville Syrjälä
Intel

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
@ 2020-03-06  8:44   ` Sharma, Swati2
  2020-03-06 11:49     ` Ville Syrjälä
  0 siblings, 1 reply; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06  8:44 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Only load the CGM CSC based on the cgm_mode bit like we
> do with the gamma/degamma LUTs. And make the function
> naming and arguments consistent as well.
> 
> TODO: the code to convert the coefficients look totally
> bogus. IIRC CHV uses two's complement format but the code
> certainly doesn't generate that, so probably negative
> coefficients are totally busted.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 69 +++++++++++-----------
>   1 file changed, 35 insertions(+), 34 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 98aefeebda28..444980fdeda6 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -348,48 +348,43 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
>   		       crtc_state->csc_mode);
>   }
>   
> -/*
> - * Set up the pipe CSC unit on CherryView.
> - */
> -static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> +static void chv_load_cgm_csc(struct intel_crtc *crtc,
> +			     const struct drm_property_blob *blob)
Nitpick: Spacing?
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct drm_color_ctm *ctm = blob->data;
>   	enum pipe pipe = crtc->pipe;
> +	u16 coeffs[9];
> +	int i;
>   
> -	if (crtc_state->hw.ctm) {
> -		const struct drm_color_ctm *ctm = crtc_state->hw.ctm->data;
> -		u16 coeffs[9] = {};
> -		int i;
> +	for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
> +		u64 abs_coeff = ((1ULL << 63) - 1) & ctm->matrix[i];
>   
> -		for (i = 0; i < ARRAY_SIZE(coeffs); i++) {
> -			u64 abs_coeff =
> -				((1ULL << 63) - 1) & ctm->matrix[i];
> +		/* Round coefficient. */
> +		abs_coeff += 1 << (32 - 13);
> +		/* Clamp to hardware limits. */
> +		abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
>   
> -			/* Round coefficient. */
> -			abs_coeff += 1 << (32 - 13);
> -			/* Clamp to hardware limits. */
> -			abs_coeff = clamp_val(abs_coeff, 0, CTM_COEFF_8_0 - 1);
> +		coeffs[i] = 0;
>   
> -			/* Write coefficients in S3.12 format. */
> -			if (ctm->matrix[i] & (1ULL << 63))
> -				coeffs[i] = 1 << 15;
> -			coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
> -			coeffs[i] |= (abs_coeff >> 20) & 0xfff;
> -		}
> +		/* Write coefficients in S3.12 format. */
> +		if (ctm->matrix[i] & (1ULL << 63))
> +			coeffs[i] |= 1 << 15;
>   
> -		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
> -			       coeffs[1] << 16 | coeffs[0]);
> -		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
> -			       coeffs[3] << 16 | coeffs[2]);
> -		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
> -			       coeffs[5] << 16 | coeffs[4]);
> -		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
> -			       coeffs[7] << 16 | coeffs[6]);
> -		intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe), coeffs[8]);
> +		coeffs[i] |= ((abs_coeff >> 32) & 7) << 12;
> +		coeffs[i] |= (abs_coeff >> 20) & 0xfff;
>   	}
>   
> -	intel_de_write(dev_priv, CGM_PIPE_MODE(pipe), crtc_state->cgm_mode);
> +	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF01(pipe),
> +		       coeffs[1] << 16 | coeffs[0]);
> +	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF23(pipe),
> +		       coeffs[3] << 16 | coeffs[2]);
> +	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF45(pipe),
> +		       coeffs[5] << 16 | coeffs[4]);
> +	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF67(pipe),
> +		       coeffs[7] << 16 | coeffs[6]);
> +	intel_de_write(dev_priv, CGM_PIPE_CSC_COEFF8(pipe),
> +		       coeffs[8]);
>   }
>   
>   static u32 i9xx_lut_8(const struct drm_color_lut *color)
> @@ -1020,10 +1015,13 @@ static void chv_load_cgm_gamma(struct intel_crtc *crtc,
>   static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	const struct drm_property_blob *degamma_lut = crtc_state->hw.degamma_lut;
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +	const struct drm_property_blob *ctm = crtc_state->hw.ctm;
>   
> -	cherryview_load_csc_matrix(crtc_state);
> +	if (crtc_state->cgm_mode & CGM_PIPE_MODE_CSC)
> +		chv_load_cgm_csc(crtc, ctm);
>   
>   	if (crtc_state->cgm_mode & CGM_PIPE_MODE_DEGAMMA)
>   		chv_load_cgm_degamma(crtc, degamma_lut);
> @@ -1032,6 +1030,9 @@ static void chv_load_luts(const struct intel_crtc_state *crtc_state)
>   		chv_load_cgm_gamma(crtc, gamma_lut);
>   	else
>   		i965_load_luts(crtc_state);
> +
> +	intel_de_write(dev_priv, CGM_PIPE_MODE(crtc->pipe),
> +		       crtc_state->cgm_mode);
>   }
>   
>   void intel_color_load_luts(const struct intel_crtc_state *crtc_state)
> 

With that fixed

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading
  2020-03-06  8:44   ` Sharma, Swati2
@ 2020-03-06 11:49     ` Ville Syrjälä
  0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2020-03-06 11:49 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

On Fri, Mar 06, 2020 at 02:14:15PM +0530, Sharma, Swati2 wrote:
> 
> 
> On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Only load the CGM CSC based on the cgm_mode bit like we
> > do with the gamma/degamma LUTs. And make the function
> > naming and arguments consistent as well.
> > 
> > TODO: the code to convert the coefficients look totally
> > bogus. IIRC CHV uses two's complement format but the code
> > certainly doesn't generate that, so probably negative
> > coefficients are totally busted.
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_color.c | 69 +++++++++++-----------
> >   1 file changed, 35 insertions(+), 34 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index 98aefeebda28..444980fdeda6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -348,48 +348,43 @@ static void icl_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> >   		       crtc_state->csc_mode);
> >   }
> >   
> > -/*
> > - * Set up the pipe CSC unit on CherryView.
> > - */
> > -static void cherryview_load_csc_matrix(const struct intel_crtc_state *crtc_state)
> > +static void chv_load_cgm_csc(struct intel_crtc *crtc,
> > +			     const struct drm_property_blob *blob)
> Nitpick: Spacing?

I think it's just the use of tabs and the diff's '+' making it look off.

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal()
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
@ 2020-03-06 14:42   ` Sharma, Swati2
  2020-03-06 14:46     ` Ville Syrjälä
  0 siblings, 1 reply; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 14:42 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> +static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> +
> +	assert_pll_enabled(dev_priv, crtc->pipe);
Just a query:
Why won't we have following condition here?
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
		assert_dsi_pll_enabled(dev_priv);
or is it applicable only for i965_load_luts() and not for i9xx_load_luts()?

> +
> +	i9xx_load_lut_8(crtc, gamma_lut);
> +}
> +
The patch looks good to me.

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal()
  2020-03-06 14:42   ` Sharma, Swati2
@ 2020-03-06 14:46     ` Ville Syrjälä
  0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2020-03-06 14:46 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

On Fri, Mar 06, 2020 at 08:12:22PM +0530, Sharma, Swati2 wrote:
> 
> 
> On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> > +static void i9xx_load_luts(const struct intel_crtc_state *crtc_state)
> > +{
> > +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > +	const struct drm_property_blob *gamma_lut = crtc_state->hw.gamma_lut;
> > +
> > +	assert_pll_enabled(dev_priv, crtc->pipe);
> Just a query:
> Why won't we have following condition here?
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
> 		assert_dsi_pll_enabled(dev_priv);
> or is it applicable only for i965_load_luts() and not for i9xx_load_luts()?

No DSI on these platforms. Only VLV/CHV can have it, and they use
i965_load_luts().

> 
> > +
> > +	i9xx_load_lut_8(crtc, gamma_lut);
> > +}
> > +
> The patch looks good to me.
> 
> Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
> 
> -- 
> ~Swati Sharma

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
  2020-03-04  2:54     ` kbuild test robot
@ 2020-03-06 15:00   ` Sharma, Swati2
  1 sibling, 0 replies; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:00 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> To mirror the load_luts path let's clone an ilk+ version
> from i9xx_read_lut_8(). I guess the extra branch isn't a huge
> issue but feels better to make a clean split.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 41 ++++++++++++++++++----
>   1 file changed, 35 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index cf8ed4e2ae13..e3abaa1908a9 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1706,10 +1706,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	blob_data = blob->data;
>   
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> -		if (HAS_GMCH(dev_priv))
> -			val = intel_de_read(dev_priv, PALETTE(pipe, i));
> -		else
> -			val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
> +		val = intel_de_read(dev_priv, PALETTE(pipe, i));
>   
>   		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							LGC_PALETTE_RED_MASK, val), 8);
> @@ -1824,6 +1821,38 @@ static void chv_read_luts(struct intel_crtc_state *crtc_state)
>   		i965_read_luts(crtc_state);
>   }
>   
> +static struct drm_property_blob *
> +ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
> +{
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> +	enum pipe pipe = crtc->pipe;
> +	struct drm_property_blob *blob;
> +	struct drm_color_lut *blob_data;
> +	u32 i, val;
> +
> +	blob = drm_property_create_blob(&dev_priv->drm,
> +					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
> +					NULL);
> +	if (IS_ERR(blob))
> +		return NULL;
> +
> +	blob_data = blob->data;
> +
> +	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> +		val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
> +
> +		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +							LGC_PALETTE_RED_MASK, val), 8);
> +		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +							  LGC_PALETTE_GREEN_MASK, val), 8);
> +		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +							 LGC_PALETTE_BLUE_MASK, val), 8);
> +	}
> +
> +	return blob;
> +}
> +
>   static struct drm_property_blob *
>   ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   {
> @@ -1866,7 +1895,7 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
>   	else
>   		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
>   }
> @@ -1915,7 +1944,7 @@ static void glk_read_luts(struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
>   	else
>   		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
>   }
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/ Ville Syrjala
@ 2020-03-06 15:03   ` Sharma, Swati2
  0 siblings, 0 replies; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:03 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> We're talking about LUT contents here so let's call the thing
> 'lut' rather than 'blob_data'. This is the name the load_lut()
> code used before already.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 66 +++++++++++-----------
>   1 file changed, 33 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index e3abaa1908a9..f90f113355bc 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1694,7 +1694,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> +	struct drm_color_lut *lut;
>   	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> @@ -1703,16 +1703,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	if (IS_ERR(blob))
>   		return NULL;
>   
> -	blob_data = blob->data;
> +	lut = blob->data;
>   
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
>   		val = intel_de_read(dev_priv, PALETTE(pipe, i));
>   
> -		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							LGC_PALETTE_RED_MASK, val), 8);
> -		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   							  LGC_PALETTE_GREEN_MASK, val), 8);
> -		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   							 LGC_PALETTE_BLUE_MASK, val), 8);
>   	}
>   
> @@ -1735,7 +1735,7 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>   	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> +	struct drm_color_lut *lut;
>   	u32 i, val1, val2;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> @@ -1744,25 +1744,25 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>   	if (IS_ERR(blob))
>   		return NULL;
>   
> -	blob_data = blob->data;
> +	lut = blob->data;
>   
>   	for (i = 0; i < lut_size - 1; i++) {
>   		val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
>   		val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
>   
> -		blob_data[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
> +		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
>   						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
> -		blob_data[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
> +		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
>   						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
> -		blob_data[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
> +		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
>   						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
>   	}
>   
> -	blob_data[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> +	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
>   					 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
> -	blob_data[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> +	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
>   					   intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
> -	blob_data[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> +	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
>   					  intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
>   
>   	return blob;
> @@ -1787,7 +1787,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
>   	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> +	struct drm_color_lut *lut;
>   	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> @@ -1796,17 +1796,17 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
>   	if (IS_ERR(blob))
>   		return NULL;
>   
> -	blob_data = blob->data;
> +	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
>   		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> -		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
> -		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
>   
>   		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
> -		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							CGM_PIPE_GAMMA_RED_MASK, val), 10);
>   	}
>   
> @@ -1828,7 +1828,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> +	struct drm_color_lut *lut;
>   	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> @@ -1837,16 +1837,16 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	if (IS_ERR(blob))
>   		return NULL;
>   
> -	blob_data = blob->data;
> +	lut = blob->data;
>   
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
>   		val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
>   
> -		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							LGC_PALETTE_RED_MASK, val), 8);
> -		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   							  LGC_PALETTE_GREEN_MASK, val), 8);
> -		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   							 LGC_PALETTE_BLUE_MASK, val), 8);
>   	}
>   
> @@ -1861,7 +1861,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> +	struct drm_color_lut *lut;
>   	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> @@ -1870,16 +1870,16 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   	if (IS_ERR(blob))
>   		return NULL;
>   
> -	blob_data = blob->data;
> +	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
>   		val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
>   
> -		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							PREC_PALETTE_RED_MASK, val), 10);
> -		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   							  PREC_PALETTE_GREEN_MASK, val), 10);
> -		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   							 PREC_PALETTE_BLUE_MASK, val), 10);
>   	}
>   
> @@ -1908,7 +1908,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   	int hw_lut_size = ivb_lut_10_size(prec_index);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> -	struct drm_color_lut *blob_data;
> +	struct drm_color_lut *lut;
>   	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
> @@ -1917,7 +1917,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   	if (IS_ERR(blob))
>   		return NULL;
>   
> -	blob_data = blob->data;
> +	lut = blob->data;
>   
>   	intel_de_write(dev_priv, PREC_PAL_INDEX(pipe),
>   		       prec_index | PAL_PREC_AUTO_INCREMENT);
> @@ -1925,11 +1925,11 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   	for (i = 0; i < hw_lut_size; i++) {
>   		val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
>   
> -		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							PREC_PAL_DATA_RED_MASK, val), 10);
> -		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   							PREC_PAL_DATA_GREEN_MASK, val), 10);
> -		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> +		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
>   							PREC_PAL_DATA_BLUE_MASK, val), 10);
>   	}
>   
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
@ 2020-03-06 15:18   ` Sharma, Swati2
  2020-03-06 15:32     ` Ville Syrjälä
  0 siblings, 1 reply; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:18 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so
> let's rename it to reflect that fact. This also mirrors
> the other direction's chv_load_cgm_gamma().

At present, since all the readouts are only gamma luts so should we 
rename all the readouts like chv_read_gamma_lut()?

> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index f90f113355bc..ab23b24e7be3 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1780,7 +1780,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
>   }
>   
>   static struct drm_property_blob *
> -chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> +chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> @@ -1816,7 +1816,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
>   static void chv_read_luts(struct intel_crtc_state *crtc_state)
>   {
>   	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> -		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
> +		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
>   	else
>   		i965_read_luts(crtc_state);
>   }
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code Ville Syrjala
@ 2020-03-06 15:24   ` Sharma, Swati2
  0 siblings, 0 replies; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:24 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> A variable called 'i' having an unsigned type is just looking for
> trouble, and using a sized type generally makes no sense either.
> Change all of them to just plain old int. And do the same for some
> 'lut_size' variables which generally provide the loop end codition
> for 'i'.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 43 ++++++++++------------
>   1 file changed, 19 insertions(+), 24 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index ab23b24e7be3..934f00817c5c 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -740,9 +740,8 @@ static void glk_load_degamma_lut(const struct intel_crtc_state *crtc_state)
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
> -	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>   	const struct drm_color_lut *lut = crtc_state->hw.degamma_lut->data;
> -	u32 i;
>   
>   	/*
>   	 * When setting the auto-increment bit, the hardware seems to
> @@ -781,8 +780,7 @@ static void glk_load_degamma_lut_linear(const struct intel_crtc_state *crtc_stat
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
> -	const u32 lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
> -	u32 i;
> +	int i, lut_size = INTEL_INFO(dev_priv)->color.degamma_lut_size;
>   
>   	/*
>   	 * When setting the auto-increment bit, the hardware seems to
> @@ -867,7 +865,7 @@ icl_program_gamma_superfine_segment(const struct intel_crtc_state *crtc_state)
>   	const struct drm_color_lut *lut = blob->data;
>   	struct intel_dsb *dsb = intel_dsb_get(crtc);
>   	enum pipe pipe = crtc->pipe;
> -	u32 i;
> +	int i;
>   
>   	/*
>   	 * Program Super Fine segment (let's call it seg1)...
> @@ -900,7 +898,7 @@ icl_program_gamma_multi_segment(const struct intel_crtc_state *crtc_state)
>   	const struct drm_color_lut *entry;
>   	struct intel_dsb *dsb = intel_dsb_get(crtc);
>   	enum pipe pipe = crtc->pipe;
> -	u32 i;
> +	int i;
>   
>   	/*
>   	 * Program Fine segment (let's call it seg2)...
> @@ -1675,7 +1673,7 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>   }
>   
>   /* convert hw value with given bit_precision to lut property val */
> -static u32 intel_color_lut_pack(u32 val, u32 bit_precision)
> +static u32 intel_color_lut_pack(u32 val, int bit_precision)
>   {
>   	u32 max = 0xffff >> (16 - bit_precision);
>   
> @@ -1695,7 +1693,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> -	u32 i, val;
> +	int i;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
>   					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
> @@ -1706,7 +1704,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> -		val = intel_de_read(dev_priv, PALETTE(pipe, i));
> +		u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
>   
>   		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							LGC_PALETTE_RED_MASK, val), 8);
> @@ -1732,11 +1730,10 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> -	u32 i, val1, val2;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
>   					sizeof(struct drm_color_lut) * lut_size,
> @@ -1747,8 +1744,8 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size - 1; i++) {
> -		val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
> -		val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
> +		u32 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
> +		u32 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
>   
>   		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
>   						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
> @@ -1784,11 +1781,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> -	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
>   					sizeof(struct drm_color_lut) * lut_size,
> @@ -1799,7 +1795,8 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> +		u32 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> +
>   		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
>   							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
>   		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> @@ -1829,7 +1826,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> -	u32 i, val;
> +	int i;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
>   					sizeof(struct drm_color_lut) * LEGACY_LUT_LENGTH,
> @@ -1840,7 +1837,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
> -		val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
> +		u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
>   
>   		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							LGC_PALETTE_RED_MASK, val), 8);
> @@ -1858,11 +1855,10 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	u32 lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
> +	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> -	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
>   					sizeof(struct drm_color_lut) * lut_size,
> @@ -1873,7 +1869,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
> +		u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
>   
>   		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							PREC_PALETTE_RED_MASK, val), 10);
> @@ -1905,11 +1901,10 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> -	int hw_lut_size = ivb_lut_10_size(prec_index);
> +	int i, hw_lut_size = ivb_lut_10_size(prec_index);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
>   	struct drm_color_lut *lut;
> -	u32 i, val;
>   
>   	blob = drm_property_create_blob(&dev_priv->drm,
>   					sizeof(struct drm_color_lut) * hw_lut_size,
> @@ -1923,7 +1918,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   		       prec_index | PAL_PREC_AUTO_INCREMENT);
>   
>   	for (i = 0; i < hw_lut_size; i++) {
> -		val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
> +		u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
>   
>   		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
>   							PREC_PAL_DATA_RED_MASK, val), 10);
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions Ville Syrjala
@ 2020-03-06 15:28   ` Sharma, Swati2
  0 siblings, 0 replies; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:28 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Extract all the 'hw value -> LUT entry' stuff into small helpers
> to make the main 'read out the entire LUT' loop less bogged down
> by such mundane details.
> 
Wow!

> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 122 +++++++++++----------
>   1 file changed, 62 insertions(+), 60 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index 934f00817c5c..8796f04e23a8 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -387,6 +387,19 @@ static void chv_load_cgm_csc(struct intel_crtc *crtc,
>   		       coeffs[8]);
>   }
>   
> +/* convert hw value with given bit_precision to lut property val */
> +static u32 intel_color_lut_pack(u32 val, int bit_precision)
> +{
> +	u32 max = 0xffff >> (16 - bit_precision);
> +
> +	val = clamp_val(val, 0, max);
> +
> +	if (bit_precision < 16)
> +		val <<= 16 - bit_precision;
> +
> +	return val;
> +}
> +
>   static u32 i9xx_lut_8(const struct drm_color_lut *color)
>   {
>   	return drm_color_lut_extract(color->red, 8) << 16 |
> @@ -394,6 +407,13 @@ static u32 i9xx_lut_8(const struct drm_color_lut *color)
>   		drm_color_lut_extract(color->blue, 8);
>   }
>   
> +static void i9xx_lut_8_pack(struct drm_color_lut *entry, u32 val)
> +{
> +	entry->red = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_RED_MASK, val), 8);
> +	entry->green = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_GREEN_MASK, val), 8);
> +	entry->blue = intel_color_lut_pack(REG_FIELD_GET(LGC_PALETTE_BLUE_MASK, val), 8);
> +}
> +
>   /* i965+ "10.6" bit interpolated format "even DW" (low 8 bits) */
>   static u32 i965_lut_10p6_ldw(const struct drm_color_lut *color)
>   {
> @@ -410,6 +430,21 @@ static u32 i965_lut_10p6_udw(const struct drm_color_lut *color)
>   		(color->blue >> 8);
>   }
>   
> +static void i965_lut_10p6_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> +{
> +	entry->red = REG_FIELD_GET(PALETTE_RED_MASK, udw) << 8 |
> +		REG_FIELD_GET(PALETTE_RED_MASK, ldw);
> +	entry->green = REG_FIELD_GET(PALETTE_GREEN_MASK, udw) << 8 |
> +		REG_FIELD_GET(PALETTE_GREEN_MASK, ldw);
> +	entry->blue = REG_FIELD_GET(PALETTE_BLUE_MASK, udw) << 8 |
> +		REG_FIELD_GET(PALETTE_BLUE_MASK, ldw);
> +}
> +
> +static u16 i965_lut_11p6_max_pack(u32 val)
> +{
> +	return REG_FIELD_GET(PIPEGCMAX_RGB_MASK, val);
> +}
> +
>   static u32 ilk_lut_10(const struct drm_color_lut *color)
>   {
>   	return drm_color_lut_extract(color->red, 10) << 20 |
> @@ -417,6 +452,13 @@ static u32 ilk_lut_10(const struct drm_color_lut *color)
>   		drm_color_lut_extract(color->blue, 10);
>   }
>   
> +static void ilk_lut_10_pack(struct drm_color_lut *entry, u32 val)
> +{
> +	entry->red = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_RED_MASK, val), 10);
> +	entry->green = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_GREEN_MASK, val), 10);
> +	entry->blue = intel_color_lut_pack(REG_FIELD_GET(PREC_PALETTE_BLUE_MASK, val), 10);
> +}
> +
>   static void i9xx_color_commit(const struct intel_crtc_state *crtc_state)
>   {
>   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> @@ -983,6 +1025,13 @@ static u32 chv_cgm_degamma_udw(const struct drm_color_lut *color)
>   	return drm_color_lut_extract(color->red, 14);
>   }
>   
> +static void chv_cgm_gamma_pack(struct drm_color_lut *entry, u32 ldw, u32 udw)
> +{
> +	entry->green = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_GREEN_MASK, ldw), 10);
> +	entry->blue = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_BLUE_MASK, ldw), 10);
> +	entry->red = intel_color_lut_pack(REG_FIELD_GET(CGM_PIPE_GAMMA_RED_MASK, udw), 10);
> +}
> +
>   static void chv_load_cgm_degamma(struct intel_crtc *crtc,
>   				 const struct drm_property_blob *blob)
>   {
> @@ -1672,19 +1721,6 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>   	return true;
>   }
>   
> -/* convert hw value with given bit_precision to lut property val */
> -static u32 intel_color_lut_pack(u32 val, int bit_precision)
> -{
> -	u32 max = 0xffff >> (16 - bit_precision);
> -
> -	val = clamp_val(val, 0, max);
> -
> -	if (bit_precision < 16)
> -		val <<= 16 - bit_precision;
> -
> -	return val;
> -}
> -
>   static struct drm_property_blob *
>   i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   {
> @@ -1706,12 +1742,7 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
>   		u32 val = intel_de_read(dev_priv, PALETTE(pipe, i));
>   
> -		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> -							LGC_PALETTE_RED_MASK, val), 8);
> -		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> -							  LGC_PALETTE_GREEN_MASK, val), 8);
> -		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> -							 LGC_PALETTE_BLUE_MASK, val), 8);
> +		i9xx_lut_8_pack(&lut[i], val);
>   	}
>   
>   	return blob;
> @@ -1744,23 +1775,15 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size - 1; i++) {
> -		u32 val1 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
> -		u32 val2 = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
> +		u32 ldw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 0));
> +		u32 udw = intel_de_read(dev_priv, PALETTE(pipe, 2 * i + 1));
>   
> -		lut[i].red = REG_FIELD_GET(PALETTE_RED_MASK, val2) << 8 |
> -						 REG_FIELD_GET(PALETTE_RED_MASK, val1);
> -		lut[i].green = REG_FIELD_GET(PALETTE_GREEN_MASK, val2) << 8 |
> -						   REG_FIELD_GET(PALETTE_GREEN_MASK, val1);
> -		lut[i].blue = REG_FIELD_GET(PALETTE_BLUE_MASK, val2) << 8 |
> -						  REG_FIELD_GET(PALETTE_BLUE_MASK, val1);
> +		i965_lut_10p6_pack(&lut[i], ldw, udw);
>   	}
>   
> -	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> -					 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
> -	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> -					   intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
> -	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
> -					  intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
> +	lut[i].red = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));
> +	lut[i].green = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));
> +	lut[i].blue = i965_lut_11p6_max_pack(intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));
>   
>   	return blob;
>   }
> @@ -1795,16 +1818,10 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
>   	lut = blob->data;
>   
>   	for (i = 0; i < lut_size; i++) {
> -		u32 val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> +		u32 ldw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 0));
> +		u32 udw = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
>   
> -		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> -							  CGM_PIPE_GAMMA_GREEN_MASK, val), 10);
> -		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> -							 CGM_PIPE_GAMMA_BLUE_MASK, val), 10);
> -
> -		val = intel_de_read(dev_priv, CGM_PIPE_GAMMA(pipe, i, 1));
> -		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> -							CGM_PIPE_GAMMA_RED_MASK, val), 10);
> +		chv_cgm_gamma_pack(&lut[i], ldw, udw);
>   	}
>   
>   	return blob;
> @@ -1839,12 +1856,7 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	for (i = 0; i < LEGACY_LUT_LENGTH; i++) {
>   		u32 val = intel_de_read(dev_priv, LGC_PALETTE(pipe, i));
>   
> -		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> -							LGC_PALETTE_RED_MASK, val), 8);
> -		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> -							  LGC_PALETTE_GREEN_MASK, val), 8);
> -		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> -							 LGC_PALETTE_BLUE_MASK, val), 8);
> +		i9xx_lut_8_pack(&lut[i], val);
>   	}
>   
>   	return blob;
> @@ -1871,12 +1883,7 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   	for (i = 0; i < lut_size; i++) {
>   		u32 val = intel_de_read(dev_priv, PREC_PALETTE(pipe, i));
>   
> -		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> -							PREC_PALETTE_RED_MASK, val), 10);
> -		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> -							  PREC_PALETTE_GREEN_MASK, val), 10);
> -		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> -							 PREC_PALETTE_BLUE_MASK, val), 10);
> +		ilk_lut_10_pack(&lut[i], val);
>   	}
>   
>   	return blob;
> @@ -1920,12 +1927,7 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   	for (i = 0; i < hw_lut_size; i++) {
>   		u32 val = intel_de_read(dev_priv, PREC_PAL_DATA(pipe));
>   
> -		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(
> -							PREC_PAL_DATA_RED_MASK, val), 10);
> -		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(
> -							PREC_PAL_DATA_GREEN_MASK, val), 10);
> -		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(
> -							PREC_PAL_DATA_BLUE_MASK, val), 10);
> +		ilk_lut_10_pack(&lut[i], val);
>   	}
>   
>   	intel_de_write(dev_priv, PREC_PAL_INDEX(pipe), 0);
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
  2020-03-06 15:18   ` Sharma, Swati2
@ 2020-03-06 15:32     ` Ville Syrjälä
  0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2020-03-06 15:32 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

On Fri, Mar 06, 2020 at 08:48:42PM +0530, Sharma, Swati2 wrote:
> 
> 
> On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > chv_read_cgm_lut() specifically reads the CGM _gamma_ LUT so
> > let's rename it to reflect that fact. This also mirrors
> > the other direction's chv_load_cgm_gamma().
> 
> At present, since all the readouts are only gamma luts so should we 
> rename all the readouts like chv_read_gamma_lut()?

No, the names are chosen based on the HW LUT we read not the SW LUT.

> 
> > 
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >   drivers/gpu/drm/i915/display/intel_color.c | 4 ++--
> >   1 file changed, 2 insertions(+), 2 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> > index f90f113355bc..ab23b24e7be3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -1780,7 +1780,7 @@ static void i965_read_luts(struct intel_crtc_state *crtc_state)
> >   }
> >   
> >   static struct drm_property_blob *
> > -chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> > +chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
> >   {
> >   	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> >   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > @@ -1816,7 +1816,7 @@ chv_read_cgm_lut(const struct intel_crtc_state *crtc_state)
> >   static void chv_read_luts(struct intel_crtc_state *crtc_state)
> >   {
> >   	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> > -		crtc_state->hw.gamma_lut = chv_read_cgm_lut(crtc_state);
> > +		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
> >   	else
> >   		i965_read_luts(crtc_state);
> >   }
> > 
> 
> -- 
> ~Swati Sharma

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs
  2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
@ 2020-03-06 15:36   ` Sharma, Swati2
  0 siblings, 0 replies; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:36 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> The low level read_lut() functions don't need the entire crtc state
> as they know exactly what they're reading. Just need to pass in the
> crtc to get at the pipe. This now neatly mirrors the load_lut()
> direction.
> 
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_color.c | 51 +++++++++++-----------
>   1 file changed, 25 insertions(+), 26 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
> index ed9996aacafd..c1cce93a1c25 100644
> --- a/drivers/gpu/drm/i915/display/intel_color.c
> +++ b/drivers/gpu/drm/i915/display/intel_color.c
> @@ -1722,10 +1722,8 @@ bool intel_color_lut_equal(struct drm_property_blob *blob1,
>   	return true;
>   }
>   
> -static struct drm_property_blob *
> -i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
> +static struct drm_property_blob *i9xx_read_lut_8(struct intel_crtc *crtc)
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> @@ -1751,16 +1749,16 @@ i9xx_read_lut_8(const struct intel_crtc_state *crtc_state)
>   
>   static void i9xx_read_luts(struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
>   	if (!crtc_state->gamma_enable)
>   		return;
>   
> -	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> +	crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
>   }
>   
> -static struct drm_property_blob *
> -i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
> +static struct drm_property_blob *i965_read_lut_10p6(struct intel_crtc *crtc)
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
> @@ -1791,19 +1789,19 @@ i965_read_lut_10p6(const struct intel_crtc_state *crtc_state)
>   
>   static void i965_read_luts(struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
>   	if (!crtc_state->gamma_enable)
>   		return;
>   
>   	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = i9xx_read_lut_8(crtc);
>   	else
> -		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc_state);
> +		crtc_state->hw.gamma_lut = i965_read_lut_10p6(crtc);
>   }
>   
> -static struct drm_property_blob *
> -chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
> +static struct drm_property_blob *chv_read_cgm_gamma(struct intel_crtc *crtc)
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
> @@ -1830,16 +1828,16 @@ chv_read_cgm_gamma(const struct intel_crtc_state *crtc_state)
>   
>   static void chv_read_luts(struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
>   	if (crtc_state->cgm_mode & CGM_PIPE_MODE_GAMMA)
> -		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc_state);
> +		crtc_state->hw.gamma_lut = chv_read_cgm_gamma(crtc);
>   	else
>   		i965_read_luts(crtc_state);
>   }
>   
> -static struct drm_property_blob *
> -ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
> +static struct drm_property_blob *ilk_read_lut_8(struct intel_crtc *crtc)
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	enum pipe pipe = crtc->pipe;
>   	struct drm_property_blob *blob;
> @@ -1863,10 +1861,8 @@ ilk_read_lut_8(const struct intel_crtc_state *crtc_state)
>   	return blob;
>   }
>   
> -static struct drm_property_blob *
> -ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
> +static struct drm_property_blob *ilk_read_lut_10(struct intel_crtc *crtc)
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	int i, lut_size = INTEL_INFO(dev_priv)->color.gamma_lut_size;
>   	enum pipe pipe = crtc->pipe;
> @@ -1892,6 +1888,8 @@ ilk_read_lut_10(const struct intel_crtc_state *crtc_state)
>   
>   static void ilk_read_luts(struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
>   	if (!crtc_state->gamma_enable)
>   		return;
>   
> @@ -1899,15 +1897,14 @@ static void ilk_read_luts(struct intel_crtc_state *crtc_state)
>   		return;
>   
>   	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
>   	else
> -		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc_state);
> +		crtc_state->hw.gamma_lut = ilk_read_lut_10(crtc);
>   }
>   
> -static struct drm_property_blob *
> -glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
> +static struct drm_property_blob *glk_read_lut_10(struct intel_crtc *crtc,
> +						 u32 prec_index)
>   {
> -	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
>   	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
>   	int i, hw_lut_size = ivb_lut_10_size(prec_index);
>   	enum pipe pipe = crtc->pipe;
> @@ -1938,13 +1935,15 @@ glk_read_lut_10(const struct intel_crtc_state *crtc_state, u32 prec_index)
>   
>   static void glk_read_luts(struct intel_crtc_state *crtc_state)
>   {
> +	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> +
>   	if (!crtc_state->gamma_enable)
>   		return;
>   
>   	if (crtc_state->gamma_mode == GAMMA_MODE_MODE_8BIT)
> -		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc_state);
> +		crtc_state->hw.gamma_lut = ilk_read_lut_8(crtc);
>   	else
> -		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc_state, PAL_PREC_INDEX_VALUE(0));
> +		crtc_state->hw.gamma_lut = glk_read_lut_10(crtc, PAL_PREC_INDEX_VALUE(0));
>   }
>   
>   void intel_color_init(struct intel_crtc *crtc)
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (11 preceding siblings ...)
  2020-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-03-06 15:40 ` Sharma, Swati2
  2020-03-09 20:26   ` Ville Syrjälä
  2020-03-07  0:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev4) Patchwork
                   ` (5 subsequent siblings)
  18 siblings, 1 reply; 36+ messages in thread
From: Sharma, Swati2 @ 2020-03-06 15:40 UTC (permalink / raw)
  To: Ville Syrjala, intel-gfx



On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Remainder of my earlier gamma cleanups, rebased due to
> hw vs. uapi split and intel_de_{read,write}().

I didn't get patch#8. Everything looks good to me.
There is BAT failure https://patchwork.freedesktop.org/series/69136/
Please check that.

Reviewed-by: Swati Sharma <swati2.sharma@intel.com>
> 
> Ville Syrjälä (9):
>    drm/i915: Polish CHV CGM CSC loading
>    drm/i915: Clean up i9xx_load_luts_internal()
>    drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
>    drm/i915: s/blob_data/lut/
>    drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
>    drm/i915: Clean up integer types in color code
>    drm/i915: Refactor LUT read functions
>    drm/i915: Fix readout of PIPEGCMAX
>    drm/i915: Pass the crtc to the low level read_lut() funcs
> 
>   drivers/gpu/drm/i915/display/intel_color.c | 407 ++++++++++++---------
>   drivers/gpu/drm/i915/i915_reg.h            |   1 -
>   2 files changed, 225 insertions(+), 183 deletions(-)
> 

-- 
~Swati Sharma
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev4)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (12 preceding siblings ...)
  2020-03-06 15:40 ` [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Sharma, Swati2
@ 2020-03-07  0:09 ` Patchwork
  2020-03-07  0:27 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
                   ` (4 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-07  0:09 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev4)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
ca6d5d42a01b drm/i915: Polish CHV CGM CSC loading
97e95a526dd1 drm/i915: Clean up i9xx_load_luts_internal()
cce1fed1d2dd drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
-:58: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#58: FILE: drivers/gpu/drm/i915/display/intel_color.c:1845:
+		blob_data[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:60: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#60: FILE: drivers/gpu/drm/i915/display/intel_color.c:1847:
+		blob_data[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:62: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#62: FILE: drivers/gpu/drm/i915/display/intel_color.c:1849:
+		blob_data[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 3 checks, 65 lines checked
319ef1a13f77 drm/i915: s/blob_data/lut/
-:40: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#40: FILE: drivers/gpu/drm/i915/display/intel_color.c:1711:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:43: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#43: FILE: drivers/gpu/drm/i915/display/intel_color.c:1713:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:46: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#46: FILE: drivers/gpu/drm/i915/display/intel_color.c:1715:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:83: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#83: FILE: drivers/gpu/drm/i915/display/intel_color.c:1762:
+	lut[i].red = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					 intel_de_read(dev_priv, PIPEGCMAX(pipe, 0)));

-:86: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#86: FILE: drivers/gpu/drm/i915/display/intel_color.c:1764:
+	lut[i].green = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					   intel_de_read(dev_priv, PIPEGCMAX(pipe, 1)));

-:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#89: FILE: drivers/gpu/drm/i915/display/intel_color.c:1766:
+	lut[i].blue = REG_FIELD_GET(PIPEGCMAX_RGB_MASK,
 					  intel_de_read(dev_priv, PIPEGCMAX(pipe, 2)));

-:111: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#111: FILE: drivers/gpu/drm/i915/display/intel_color.c:1803:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/drm/i915/display/intel_color.c:1805:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:119: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#119: FILE: drivers/gpu/drm/i915/display/intel_color.c:1809:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:143: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#143: FILE: drivers/gpu/drm/i915/display/intel_color.c:1845:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:146: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#146: FILE: drivers/gpu/drm/i915/display/intel_color.c:1847:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:149: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#149: FILE: drivers/gpu/drm/i915/display/intel_color.c:1849:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:173: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#173: FILE: drivers/gpu/drm/i915/display/intel_color.c:1878:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:176: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#176: FILE: drivers/gpu/drm/i915/display/intel_color.c:1880:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:179: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#179: FILE: drivers/gpu/drm/i915/display/intel_color.c:1882:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

-:206: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#206: FILE: drivers/gpu/drm/i915/display/intel_color.c:1928:
+		lut[i].red = intel_color_lut_pack(REG_FIELD_GET(

-:209: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#209: FILE: drivers/gpu/drm/i915/display/intel_color.c:1930:
+		lut[i].green = intel_color_lut_pack(REG_FIELD_GET(

-:212: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#212: FILE: drivers/gpu/drm/i915/display/intel_color.c:1932:
+		lut[i].blue = intel_color_lut_pack(REG_FIELD_GET(

total: 0 errors, 0 warnings, 18 checks, 183 lines checked
d4f1fa52704c drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
ef770588c959 drm/i915: Clean up integer types in color code
8973bf85659e drm/i915: Refactor LUT read functions
406986ee9efc drm/i915: Fix readout of PIPEGCMAX
3da0fd12387c drm/i915: Pass the crtc to the low level read_lut() funcs

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Gamma cleanups (rev4)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (13 preceding siblings ...)
  2020-03-07  0:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev4) Patchwork
@ 2020-03-07  0:27 ` Patchwork
  2020-03-07  0:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
                   ` (3 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-07  0:27 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev4)
URL   : https://patchwork.freedesktop.org/series/69136/
State : warning

== Summary ==

$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_dpll_mgr.h:285: warning: Function parameter or member 'get_freq' not described in 'intel_shared_dpll_funcs'

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Gamma cleanups (rev4)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (14 preceding siblings ...)
  2020-03-07  0:27 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2020-03-07  0:45 ` Patchwork
  2020-03-09 13:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-07  0:45 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev4)
URL   : https://patchwork.freedesktop.org/series/69136/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_8087 -> Patchwork_16866
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16866 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16866, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16866:

### IGT changes ###

#### Possible regressions ####

  * igt@gem_exec_parallel@fds:
    - fi-cfl-8700k:       [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-cfl-8700k/igt@gem_exec_parallel@fds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-cfl-8700k/igt@gem_exec_parallel@fds.html

  
Known issues
------------

  Here are the changes found in Patchwork_16866 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live@gem_contexts:
    - fi-cml-s:           [PASS][3] -> [DMESG-FAIL][4] ([i915#877])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-icl-u2:          [PASS][5] -> [FAIL][6] ([fdo#109635] / [i915#217])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-tgl-y:           [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@prime_vgem@basic-sync-default:
    - fi-tgl-y:           [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-tgl-y/igt@prime_vgem@basic-sync-default.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-tgl-y/igt@prime_vgem@basic-sync-default.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u2:          [TIMEOUT][11] -> [DMESG-WARN][12] ([i915#289])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-icl-u2/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-icl-u2/igt@i915_pm_rpm@module-reload.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (49 -> 40)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (10): fi-hsw-4200u fi-byt-j1900 fi-bsw-n3050 fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ivb-3770 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8087 -> Patchwork_16866

  CI-20190529: 20190529
  CI_DRM_8087: 2eecd3619f1f227c890414a0730a723f1c5a3a60 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5498: 1bb7a25a09fe3e653d310e8bdfbdde4a1934b326 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16866: 3da0fd12387c4ea1e49870f9119bd70c9e1fceb2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3da0fd12387c drm/i915: Pass the crtc to the low level read_lut() funcs
406986ee9efc drm/i915: Fix readout of PIPEGCMAX
8973bf85659e drm/i915: Refactor LUT read functions
ef770588c959 drm/i915: Clean up integer types in color code
d4f1fa52704c drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
319ef1a13f77 drm/i915: s/blob_data/lut/
cce1fed1d2dd drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
97e95a526dd1 drm/i915: Clean up i9xx_load_luts_internal()
ca6d5d42a01b drm/i915: Polish CHV CGM CSC loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Gamma cleanups (rev4)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (15 preceding siblings ...)
  2020-03-07  0:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2020-03-09 13:54 ` Patchwork
  2020-03-09 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
  2020-03-09 19:46 ` Patchwork
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-09 13:54 UTC (permalink / raw)
  To: Ville Syrjala; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev4)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8087 -> Patchwork_16866
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/index.html

Known issues
------------

  Here are the changes found in Patchwork_16866 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_parallel@fds:
    - fi-cfl-8700k:       [PASS][1] -> [INCOMPLETE][2] ([i915#1147])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-cfl-8700k/igt@gem_exec_parallel@fds.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-cfl-8700k/igt@gem_exec_parallel@fds.html

  * igt@i915_selftest@live@gem_contexts:
    - fi-cml-s:           [PASS][3] -> [DMESG-FAIL][4] ([i915#877])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-cml-s/igt@i915_selftest@live@gem_contexts.html

  * igt@kms_chamelium@hdmi-crc-fast:
    - fi-icl-u2:          [PASS][5] -> [FAIL][6] ([fdo#109635] / [i915#217])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-icl-u2/igt@kms_chamelium@hdmi-crc-fast.html

  * igt@prime_vgem@basic-fence-flip:
    - fi-tgl-y:           [PASS][7] -> [DMESG-WARN][8] ([CI#94] / [i915#402]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-tgl-y/igt@prime_vgem@basic-fence-flip.html

  
#### Possible fixes ####

  * igt@prime_vgem@basic-sync-default:
    - fi-tgl-y:           [DMESG-WARN][9] ([CI#94] / [i915#402]) -> [PASS][10] +1 similar issue
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-tgl-y/igt@prime_vgem@basic-sync-default.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-tgl-y/igt@prime_vgem@basic-sync-default.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-icl-u2:          [TIMEOUT][11] -> [DMESG-WARN][12] ([i915#289])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/fi-icl-u2/igt@i915_pm_rpm@module-reload.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/fi-icl-u2/igt@i915_pm_rpm@module-reload.html

  
  [CI#94]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/94
  [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
  [i915#1147]: https://gitlab.freedesktop.org/drm/intel/issues/1147
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
  [i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877


Participating hosts (49 -> 40)
------------------------------

  Additional (1): fi-icl-y 
  Missing    (10): fi-hsw-4200u fi-byt-j1900 fi-bsw-n3050 fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-kbl-7500u fi-ivb-3770 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8087 -> Patchwork_16866

  CI-20190529: 20190529
  CI_DRM_8087: 2eecd3619f1f227c890414a0730a723f1c5a3a60 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5498: 1bb7a25a09fe3e653d310e8bdfbdde4a1934b326 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16866: 3da0fd12387c4ea1e49870f9119bd70c9e1fceb2 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

3da0fd12387c drm/i915: Pass the crtc to the low level read_lut() funcs
406986ee9efc drm/i915: Fix readout of PIPEGCMAX
8973bf85659e drm/i915: Refactor LUT read functions
ef770588c959 drm/i915: Clean up integer types in color code
d4f1fa52704c drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
319ef1a13f77 drm/i915: s/blob_data/lut/
cce1fed1d2dd drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
97e95a526dd1 drm/i915: Clean up i9xx_load_luts_internal()
ca6d5d42a01b drm/i915: Polish CHV CGM CSC loading

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Gamma cleanups (rev4)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (16 preceding siblings ...)
  2020-03-09 13:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-03-09 19:27 ` Patchwork
  2020-03-09 19:46 ` Patchwork
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-09 19:27 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev4)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8087_full -> Patchwork_16866_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_16866_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16866_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16866_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-kbl:          [INCOMPLETE][1] ([fdo#103665]) -> [INCOMPLETE][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  
Known issues
------------

  Here are the changes found in Patchwork_16866_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-kbl:          [PASS][3] -> [INCOMPLETE][4] ([i915#1402])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl1/igt@gem_ctx_persistence@close-replace-race.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@gem_ctx_persistence@close-replace-race.html
    - shard-iclb:         [PASS][5] -> [INCOMPLETE][6] ([i915#1402])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb4/igt@gem_ctx_persistence@close-replace-race.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb6/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_exec_schedule@implicit-both-bsd1:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html

  * igt@gem_exec_schedule@independent-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +23 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html

  * igt@gem_exec_schedule@pi-userfault-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb8/igt@gem_exec_schedule@pi-userfault-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@gem_exec_schedule@pi-userfault-bsd.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb3/igt@gem_exec_schedule@preempt-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl2/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-hsw:          [PASS][17] -> [INCOMPLETE][18] ([i915#61])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-hsw6/igt@gem_exec_whisper@basic-contexts-forked.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-hsw7/igt@gem_exec_whisper@basic-contexts-forked.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_atomic_transition@2x-modeset-transitions-fencing:
    - shard-hsw:          [PASS][21] -> [DMESG-FAIL][22] ([i915#44])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-hsw8/igt@kms_atomic_transition@2x-modeset-transitions-fencing.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-hsw5/igt@kms_atomic_transition@2x-modeset-transitions-fencing.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#1188])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb1/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][29] -> [INCOMPLETE][30] ([i915#198])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl9/igt@kms_psr@suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl5/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#31])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@kms_setmode@basic.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl10/igt@kms_setmode@basic.html
    - shard-kbl:          [PASS][33] -> [FAIL][34] ([i915#31])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl7/igt@kms_setmode@basic.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl4/igt@kms_setmode@basic.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#112080]) +16 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@perf_pmu@busy-vcs1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb3/igt@perf_pmu@busy-vcs1.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][37] ([fdo#112080]) -> [PASS][38] +18 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb6/igt@gem_busy@busy-vcs1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@gem_busy@busy-vcs1.html

  * {igt@gem_ctx_ringsize@active@bcs0}:
    - shard-skl:          [FAIL][39] ([i915#1407]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl5/igt@gem_ctx_ringsize@active@bcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl10/igt@gem_ctx_ringsize@active@bcs0.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][41] ([fdo#110841]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_parallel@vcs0-contexts:
    - shard-kbl:          [INCOMPLETE][43] ([fdo#103665]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl3/igt@gem_exec_parallel@vcs0-contexts.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl4/igt@gem_exec_parallel@vcs0-contexts.html

  * igt@gem_exec_schedule@implicit-write-read-bsd1:
    - shard-iclb:         [SKIP][45] ([fdo#109276] / [i915#677]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb8/igt@gem_exec_schedule@implicit-write-read-bsd1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@gem_exec_schedule@implicit-write-read-bsd1.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [SKIP][47] ([i915#677]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][49] ([fdo#112146]) -> [PASS][50] +9 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl7/igt@gem_exec_whisper@basic-contexts-forked.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl7/igt@gem_exec_whisper@basic-contexts-forked.html

  * igt@gem_exec_whisper@basic-fds-priority:
    - shard-iclb:         [INCOMPLETE][53] ([i915#1394]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb8/igt@gem_exec_whisper@basic-fds-priority.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@gem_exec_whisper@basic-fds-priority.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [FAIL][55] ([i915#644]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-skl:          [INCOMPLETE][57] ([i915#151] / [i915#69]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl8/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         [FAIL][59] ([i915#370]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@i915_pm_rps@min-max-config-loaded.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb1/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][61] ([i915#79]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][63] ([i915#79]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-apl:          [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl8/igt@kms_flip@flip-vs-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-skl:          [DMESG-WARN][67] ([IGT#6]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl6/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][69] ([fdo#109642] / [fdo#111068]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [SKIP][71] ([fdo#109441]) -> [PASS][72] +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][73] ([i915#31]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl3/igt@kms_setmode@basic.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl3/igt@kms_setmode@basic.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][75] ([fdo#109276]) -> [PASS][76] +24 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-glk:          [INCOMPLETE][77] ([i915#58] / [k.org#198133]) -> [INCOMPLETE][78] ([i915#1402] / [i915#58] / [k.org#198133])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk3/igt@gem_ctx_persistence@close-replace-race.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_linear_blits@normal:
    - shard-apl:          [TIMEOUT][79] ([fdo#111732]) -> [TIMEOUT][80] ([fdo#111732] / [i915#1322])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl1/igt@gem_linear_blits@normal.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl1/igt@gem_linear_blits@normal.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][81] ([i915#716]) -> [INCOMPLETE][82] ([i915#58] / [k.org#198133])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk9/igt@gen9_exec_parse@allowed-all.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk3/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-kbl:          [INCOMPLETE][83] ([fdo#103665] / [i915#879]) -> [INCOMPLETE][84] ([i915#879])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl2/igt@i915_module_load@reload-with-fault-injection.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][85] ([i915#468]) -> [FAIL][86] ([i915#454])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-tglb8/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-snb:          [INCOMPLETE][87] ([i915#82]) -> [SKIP][88] ([fdo#109271])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-snb5/igt@i915_pm_rpm@system-suspend-execbuf.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-snb5/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][89], [FAIL][90]) ([fdo#111012] / [i915#92]) -> ([FAIL][91], [FAIL][92]) ([i915#1389] / [i915#1402] / [i915#92])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl3/igt@runner@aborted.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl2/igt@runner@aborted.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@runner@aborted.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@runner@aborted.html
    - shard-apl:          ([FAIL][93], [FAIL][94]) ([fdo#103927] / [i915#1402]) -> [FAIL][95] ([fdo#103927])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl4/igt@runner@aborted.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl6/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl3/igt@runner@aborted.html
    - shard-glk:          ([FAIL][96], [FAIL][97]) ([k.org#202321]) -> ([FAIL][98], [FAIL][99]) ([i915#1402] / [k.org#202321])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk3/igt@runner@aborted.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk9/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk8/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk3/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1322]: https://gitlab.freedesktop.org/drm/intel/issues/1322
  [i915#1389]: https://gitlab.freedesktop.org/drm/intel/issues/1389
  [i915#1394]: https://gitlab.freedesktop.org/drm/intel/issues/1394
  [i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
  [i915#1407]: https://gitlab.freedesktop.org/drm/intel/issues/1407
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#370]: https://gitlab.freedesktop.org/drm/intel/issues/370
  [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#879]: https://gitlab.freedesktop.org/drm/intel/issues/879
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8087 -> Patchwork_16866

  CI-20190529: 20190529
  CI_DRM_8087: 2eecd3619f1f227c890414a0730a723f1c5a3a60 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5498: 1bb7a25a09fe3e653d310e8bdfbdde4a1934b326 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16866: 3da0fd12387c4ea1e49870f9119bd70c9e1fceb2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Gamma cleanups (rev4)
  2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
                   ` (17 preceding siblings ...)
  2020-03-09 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
@ 2020-03-09 19:46 ` Patchwork
  18 siblings, 0 replies; 36+ messages in thread
From: Patchwork @ 2020-03-09 19:46 UTC (permalink / raw)
  To: Ville Syrjälä; +Cc: intel-gfx

== Series Details ==

Series: drm/i915: Gamma cleanups (rev4)
URL   : https://patchwork.freedesktop.org/series/69136/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8087_full -> Patchwork_16866_full
====================================================

Summary
-------

  **WARNING**

  Minor unknown changes coming with Patchwork_16866_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16866_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16866_full:

### IGT changes ###

#### Warnings ####

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-kbl:          [INCOMPLETE][1] ([fdo#103665]) -> [INCOMPLETE][2] +1 similar issue
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  
Known issues
------------

  Here are the changes found in Patchwork_16866_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-kbl:          [PASS][3] -> [INCOMPLETE][4] ([i915#1402])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl1/igt@gem_ctx_persistence@close-replace-race.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@gem_ctx_persistence@close-replace-race.html
    - shard-iclb:         [PASS][5] -> [INCOMPLETE][6] ([i915#1402])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb4/igt@gem_ctx_persistence@close-replace-race.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb6/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_exec_schedule@implicit-both-bsd1:
    - shard-iclb:         [PASS][7] -> [SKIP][8] ([fdo#109276] / [i915#677]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd1.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html

  * igt@gem_exec_schedule@independent-bsd2:
    - shard-iclb:         [PASS][9] -> [SKIP][10] ([fdo#109276]) +23 similar issues
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb4/igt@gem_exec_schedule@independent-bsd2.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb6/igt@gem_exec_schedule@independent-bsd2.html

  * igt@gem_exec_schedule@pi-userfault-bsd:
    - shard-iclb:         [PASS][11] -> [SKIP][12] ([i915#677]) +1 similar issue
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb8/igt@gem_exec_schedule@pi-userfault-bsd.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@gem_exec_schedule@pi-userfault-bsd.html

  * igt@gem_exec_schedule@preempt-bsd:
    - shard-iclb:         [PASS][13] -> [SKIP][14] ([fdo#112146]) +3 similar issues
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb3/igt@gem_exec_schedule@preempt-bsd.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@gem_exec_schedule@preempt-bsd.html

  * igt@gem_exec_suspend@basic-s3:
    - shard-kbl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +3 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl3/igt@gem_exec_suspend@basic-s3.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl2/igt@gem_exec_suspend@basic-s3.html

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-hsw:          [PASS][17] -> [INCOMPLETE][18] ([i915#61])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-hsw6/igt@gem_exec_whisper@basic-contexts-forked.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-hsw7/igt@gem_exec_whisper@basic-contexts-forked.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl3/igt@i915_suspend@fence-restore-tiled2untiled.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_atomic_transition@2x-modeset-transitions-fencing:
    - shard-hsw:          [PASS][21] -> [DMESG-FAIL][22] ([i915#44])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-hsw8/igt@kms_atomic_transition@2x-modeset-transitions-fencing.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-hsw5/igt@kms_atomic_transition@2x-modeset-transitions-fencing.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#1188])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl9/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min:
    - shard-skl:          [PASS][25] -> [FAIL][26] ([fdo#108145])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-min.html

  * igt@kms_psr@psr2_cursor_plane_onoff:
    - shard-iclb:         [PASS][27] -> [SKIP][28] ([fdo#109441]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@kms_psr@psr2_cursor_plane_onoff.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb1/igt@kms_psr@psr2_cursor_plane_onoff.html

  * igt@kms_psr@suspend:
    - shard-skl:          [PASS][29] -> [INCOMPLETE][30] ([i915#198])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl9/igt@kms_psr@suspend.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl5/igt@kms_psr@suspend.html

  * igt@kms_setmode@basic:
    - shard-skl:          [PASS][31] -> [FAIL][32] ([i915#31])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@kms_setmode@basic.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl10/igt@kms_setmode@basic.html
    - shard-kbl:          [PASS][33] -> [FAIL][34] ([i915#31])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl7/igt@kms_setmode@basic.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl4/igt@kms_setmode@basic.html

  * igt@perf_pmu@busy-vcs1:
    - shard-iclb:         [PASS][35] -> [SKIP][36] ([fdo#112080]) +16 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@perf_pmu@busy-vcs1.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb3/igt@perf_pmu@busy-vcs1.html

  
#### Possible fixes ####

  * igt@gem_busy@busy-vcs1:
    - shard-iclb:         [SKIP][37] ([fdo#112080]) -> [PASS][38] +18 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb6/igt@gem_busy@busy-vcs1.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@gem_busy@busy-vcs1.html

  * {igt@gem_ctx_ringsize@active@bcs0}:
    - shard-skl:          [FAIL][39] ([i915#1407]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl5/igt@gem_ctx_ringsize@active@bcs0.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl10/igt@gem_ctx_ringsize@active@bcs0.html

  * igt@gem_ctx_shared@exec-single-timeline-bsd:
    - shard-iclb:         [SKIP][41] ([fdo#110841]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb4/igt@gem_ctx_shared@exec-single-timeline-bsd.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb6/igt@gem_ctx_shared@exec-single-timeline-bsd.html

  * igt@gem_exec_parallel@vcs0-contexts:
    - shard-kbl:          [INCOMPLETE][43] ([fdo#103665]) -> [PASS][44]
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl3/igt@gem_exec_parallel@vcs0-contexts.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl4/igt@gem_exec_parallel@vcs0-contexts.html

  * igt@gem_exec_schedule@implicit-write-read-bsd1:
    - shard-iclb:         [SKIP][45] ([fdo#109276] / [i915#677]) -> [PASS][46] +1 similar issue
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb8/igt@gem_exec_schedule@implicit-write-read-bsd1.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@gem_exec_schedule@implicit-write-read-bsd1.html

  * igt@gem_exec_schedule@pi-common-bsd:
    - shard-iclb:         [SKIP][47] ([i915#677]) -> [PASS][48] +1 similar issue
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb1/igt@gem_exec_schedule@pi-common-bsd.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb8/igt@gem_exec_schedule@pi-common-bsd.html

  * igt@gem_exec_schedule@preempt-other-chain-bsd:
    - shard-iclb:         [SKIP][49] ([fdo#112146]) -> [PASS][50] +9 similar issues
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@gem_exec_schedule@preempt-other-chain-bsd.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb3/igt@gem_exec_schedule@preempt-other-chain-bsd.html

  * igt@gem_exec_whisper@basic-contexts-forked:
    - shard-apl:          [INCOMPLETE][51] ([fdo#103927]) -> [PASS][52] +1 similar issue
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl7/igt@gem_exec_whisper@basic-contexts-forked.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl7/igt@gem_exec_whisper@basic-contexts-forked.html

  * igt@gem_exec_whisper@basic-fds-priority:
    - shard-iclb:         [INCOMPLETE][53] ([i915#1394]) -> [PASS][54]
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb8/igt@gem_exec_whisper@basic-fds-priority.html
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@gem_exec_whisper@basic-fds-priority.html

  * igt@gem_ppgtt@flink-and-close-vma-leak:
    - shard-apl:          [FAIL][55] ([i915#644]) -> [PASS][56]
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl4/igt@gem_ppgtt@flink-and-close-vma-leak.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-skl:          [INCOMPLETE][57] ([i915#151] / [i915#69]) -> [PASS][58]
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@i915_pm_rpm@system-suspend-execbuf.html
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl8/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@i915_pm_rps@min-max-config-loaded:
    - shard-iclb:         [FAIL][59] ([i915#370]) -> [PASS][60]
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb2/igt@i915_pm_rps@min-max-config-loaded.html
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb1/igt@i915_pm_rps@min-max-config-loaded.html

  * igt@kms_flip@2x-flip-vs-expired-vblank:
    - shard-glk:          [FAIL][61] ([i915#79]) -> [PASS][62]
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk3/igt@kms_flip@2x-flip-vs-expired-vblank.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk8/igt@kms_flip@2x-flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-skl:          [FAIL][63] ([i915#79]) -> [PASS][64]
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl2/igt@kms_flip@flip-vs-expired-vblank.html
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl5/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-apl:          [DMESG-WARN][65] ([i915#180]) -> [PASS][66]
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl8/igt@kms_flip@flip-vs-suspend.html
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl1/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_plane_multiple@atomic-pipe-b-tiling-yf:
    - shard-skl:          [DMESG-WARN][67] ([IGT#6]) -> [PASS][68]
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-skl6/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-skl9/igt@kms_plane_multiple@atomic-pipe-b-tiling-yf.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][69] ([fdo#109642] / [fdo#111068]) -> [PASS][70]
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb5/igt@kms_psr2_su@frontbuffer.html
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [SKIP][71] ([fdo#109441]) -> [PASS][72] +2 similar issues
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb5/igt@kms_psr@psr2_primary_page_flip.html
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_setmode@basic:
    - shard-apl:          [FAIL][73] ([i915#31]) -> [PASS][74]
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl3/igt@kms_setmode@basic.html
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl3/igt@kms_setmode@basic.html

  * igt@prime_busy@hang-bsd2:
    - shard-iclb:         [SKIP][75] ([fdo#109276]) -> [PASS][76] +24 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-iclb6/igt@prime_busy@hang-bsd2.html
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-iclb4/igt@prime_busy@hang-bsd2.html

  
#### Warnings ####

  * igt@gem_ctx_persistence@close-replace-race:
    - shard-glk:          [INCOMPLETE][77] ([i915#58] / [k.org#198133]) -> [INCOMPLETE][78] ([i915#1402] / [i915#58] / [k.org#198133])
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk3/igt@gem_ctx_persistence@close-replace-race.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk8/igt@gem_ctx_persistence@close-replace-race.html

  * igt@gem_linear_blits@normal:
    - shard-apl:          [TIMEOUT][79] ([fdo#111732]) -> [TIMEOUT][80] ([fdo#111732] / [i915#1322])
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl1/igt@gem_linear_blits@normal.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl1/igt@gem_linear_blits@normal.html

  * igt@gen9_exec_parse@allowed-all:
    - shard-glk:          [DMESG-WARN][81] ([i915#716]) -> [INCOMPLETE][82] ([i915#58] / [k.org#198133])
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk9/igt@gen9_exec_parse@allowed-all.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk3/igt@gen9_exec_parse@allowed-all.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-kbl:          [INCOMPLETE][83] ([fdo#103665] / [i915#879]) -> [INCOMPLETE][84] ([i915#879])
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl2/igt@i915_module_load@reload-with-fault-injection.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][85] ([i915#468]) -> [FAIL][86] ([i915#454])
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-tglb8/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@system-suspend-execbuf:
    - shard-snb:          [INCOMPLETE][87] ([i915#82]) -> [SKIP][88] ([fdo#109271])
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-snb5/igt@i915_pm_rpm@system-suspend-execbuf.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-snb5/igt@i915_pm_rpm@system-suspend-execbuf.html

  * igt@runner@aborted:
    - shard-kbl:          ([FAIL][89], [FAIL][90]) ([fdo#111012] / [i915#92]) -> ([FAIL][91], [FAIL][92]) ([i915#1389] / [i915#1402] / [i915#92])
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl3/igt@runner@aborted.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-kbl2/igt@runner@aborted.html
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@runner@aborted.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-kbl6/igt@runner@aborted.html
    - shard-apl:          ([FAIL][93], [FAIL][94]) ([fdo#103927] / [i915#1402]) -> [FAIL][95] ([fdo#103927])
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl4/igt@runner@aborted.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-apl6/igt@runner@aborted.html
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-apl3/igt@runner@aborted.html
    - shard-glk:          ([FAIL][96], [FAIL][97]) ([k.org#202321]) -> ([FAIL][98], [FAIL][99]) ([i915#1402] / [k.org#202321])
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk3/igt@runner@aborted.html
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8087/shard-glk9/igt@runner@aborted.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk3/igt@runner@aborted.html
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/shard-glk8/igt@runner@aborted.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [IGT#6]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/6
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110841]: https://bugs.freedesktop.org/show_bug.cgi?id=110841
  [fdo#111012]: https://bugs.freedesktop.org/show_bug.cgi?id=111012
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [fdo#111732]: https://bugs.freedesktop.org/show_bug.cgi?id=111732
  [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
  [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#1322]: https://gitlab.freedesktop.org/drm/intel/issues/1322
  [i915#1389]: https://gitlab.freedesktop.org/drm/intel/issues/1389
  [i915#1394]: https://gitlab.freedesktop.org/drm/intel/issues/1394
  [i915#1402]: https://gitlab.freedesktop.org/drm/intel/issues/1402
  [i915#1407]: https://gitlab.freedesktop.org/drm/intel/issues/1407
  [i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
  [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
  [i915#370]: https://gitlab.freedesktop.org/drm/intel/issues/370
  [i915#44]: https://gitlab.freedesktop.org/drm/intel/issues/44
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#58]: https://gitlab.freedesktop.org/drm/intel/issues/58
  [i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
  [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644
  [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
  [i915#879]: https://gitlab.freedesktop.org/drm/intel/issues/879
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
  [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8087 -> Patchwork_16866

  CI-20190529: 20190529
  CI_DRM_8087: 2eecd3619f1f227c890414a0730a723f1c5a3a60 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5498: 1bb7a25a09fe3e653d310e8bdfbdde4a1934b326 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16866: 3da0fd12387c4ea1e49870f9119bd70c9e1fceb2 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16866/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 36+ messages in thread
* Re: [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups
  2020-03-06 15:40 ` [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Sharma, Swati2
@ 2020-03-09 20:26   ` Ville Syrjälä
  0 siblings, 0 replies; 36+ messages in thread
From: Ville Syrjälä @ 2020-03-09 20:26 UTC (permalink / raw)
  To: Sharma, Swati2; +Cc: intel-gfx

On Fri, Mar 06, 2020 at 09:10:56PM +0530, Sharma, Swati2 wrote:
> 
> 
> On 03-Mar-20 11:03 PM, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Remainder of my earlier gamma cleanups, rebased due to
> > hw vs. uapi split and intel_de_{read,write}().
> 
> I didn't get patch#8. Everything looks good to me.
> There is BAT failure https://patchwork.freedesktop.org/series/69136/
> Please check that.
> 
> Reviewed-by: Swati Sharma <swati2.sharma@intel.com>

Series pushed to dinq. Thanks for the review.

> > 
> > Ville Syrjälä (9):
> >    drm/i915: Polish CHV CGM CSC loading
> >    drm/i915: Clean up i9xx_load_luts_internal()
> >    drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants
> >    drm/i915: s/blob_data/lut/
> >    drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/
> >    drm/i915: Clean up integer types in color code
> >    drm/i915: Refactor LUT read functions
> >    drm/i915: Fix readout of PIPEGCMAX
> >    drm/i915: Pass the crtc to the low level read_lut() funcs
> > 
> >   drivers/gpu/drm/i915/display/intel_color.c | 407 ++++++++++++---------
> >   drivers/gpu/drm/i915/i915_reg.h            |   1 -
> >   2 files changed, 225 insertions(+), 183 deletions(-)
> > 
> 
> -- 
> ~Swati Sharma

-- 
Ville Syrjälä
Intel
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^ permalink raw reply	[flat|nested] 36+ messages in thread
end of thread, other threads:[~2020-03-09 20:26 UTC | newest]

Thread overview: 36+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-03 17:33 [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Ville Syrjala
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 1/9] drm/i915: Polish CHV CGM CSC loading Ville Syrjala
2020-03-06  8:44   ` Sharma, Swati2
2020-03-06 11:49     ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 2/9] drm/i915: Clean up i9xx_load_luts_internal() Ville Syrjala
2020-03-06 14:42   ` Sharma, Swati2
2020-03-06 14:46     ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 3/9] drm/i915: Split i9xx_read_lut_8() to gmch vs. ilk variants Ville Syrjala
2020-03-04  2:54   ` kbuild test robot
2020-03-04  2:54     ` kbuild test robot
2020-03-04 11:51     ` Ville Syrjälä
2020-03-04 11:51       ` Ville Syrjälä
2020-03-06 15:00   ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 4/9] drm/i915: s/blob_data/lut/ Ville Syrjala
2020-03-06 15:03   ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 5/9] drm/i915: s/chv_read_cgm_lut/chv_read_cgm_gamma/ Ville Syrjala
2020-03-06 15:18   ` Sharma, Swati2
2020-03-06 15:32     ` Ville Syrjälä
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 6/9] drm/i915: Clean up integer types in color code Ville Syrjala
2020-03-06 15:24   ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 7/9] drm/i915: Refactor LUT read functions Ville Syrjala
2020-03-06 15:28   ` Sharma, Swati2
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 8/9] drm/i915: Fix readout of PIPEGCMAX Ville Syrjala
2020-03-03 17:33 ` [Intel-gfx] [PATCH v2 9/9] drm/i915: Pass the crtc to the low level read_lut() funcs Ville Syrjala
2020-03-06 15:36   ` Sharma, Swati2
2020-03-03 19:21 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev3) Patchwork
2020-03-03 19:38 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-03 20:00 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-06 15:40 ` [Intel-gfx] [PATCH v2 0/9] drm/i915: Gamma cleanups Sharma, Swati2
2020-03-09 20:26   ` Ville Syrjälä
2020-03-07  0:09 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Gamma cleanups (rev4) Patchwork
2020-03-07  0:27 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
2020-03-07  0:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-03-09 13:54 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-09 19:27 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
2020-03-09 19:46 ` Patchwork

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