From: Jolly Shah <jolly.shah@xilinx.com> To: olof@lixom.net, mturquette@baylibre.com, sboyd@kernel.org, michal.simek@xilinx.com, arm@kernel.org, linux-clk@vger.kernel.org Cc: rajanv@xilinx.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Tejas Patel <tejas.patel@xilinx.com>, Rajan Vaja <rajan.vaja@xilinx.com>, Jolly Shah <jolly.shah@xilinx.com> Subject: [PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags Date: Thu, 12 Mar 2020 14:31:39 -0700 [thread overview] Message-ID: <1584048699-24186-3-git-send-email-jolly.shah@xilinx.com> (raw) In-Reply-To: <1584048699-24186-1-git-send-email-jolly.shah@xilinx.com> From: Tejas Patel <tejas.patel@xilinx.com> Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support both old and new firmware version, consider BIT(13) from clkflag and BIT(4) from type_flag to check if divider is fractional or not. To maintain compatibility BIT(13) of clkflag in firmware will not be used in future for any purpose and will be marked as unused. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> --- drivers/clk/zynqmp/divider.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 8eed715..efe2ed6 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -25,7 +25,8 @@ #define to_zynqmp_clk_divider(_hw) \ container_of(_hw, struct zynqmp_clk_divider, hw) -#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */ /** * struct zynqmp_clk_divider - adjustable divider clock @@ -307,7 +308,8 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, init.num_parents = 1; /* struct clk_divider assignments */ - div->is_frac = !!(nodes->flag & CLK_FRAC); + div->is_frac = !!((nodes->flag & CLK_FRAC) | + (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); div->flags = nodes->type_flag; div->hw.init = &init; div->clk_id = clk_id; -- 2.7.4
WARNING: multiple messages have this Message-ID (diff)
From: Jolly Shah <jolly.shah@xilinx.com> To: olof@lixom.net, mturquette@baylibre.com, sboyd@kernel.org, michal.simek@xilinx.com, arm@kernel.org, linux-clk@vger.kernel.org Cc: Tejas Patel <tejas.patel@xilinx.com>, Rajan Vaja <rajan.vaja@xilinx.com>, linux-kernel@vger.kernel.org, rajanv@xilinx.com, Jolly Shah <jolly.shah@xilinx.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags Date: Thu, 12 Mar 2020 14:31:39 -0700 [thread overview] Message-ID: <1584048699-24186-3-git-send-email-jolly.shah@xilinx.com> (raw) In-Reply-To: <1584048699-24186-1-git-send-email-jolly.shah@xilinx.com> From: Tejas Patel <tejas.patel@xilinx.com> Older firmware version sets BIT(13) in clkflag to mark a divider as fractional divider. Updated firmware version sets BIT(4) in type flags to mark a divider as fractional divider since BIT(13) is defined as CLK_DUTY_CYCLE_PARENT in the common clk framework flags. To support both old and new firmware version, consider BIT(13) from clkflag and BIT(4) from type_flag to check if divider is fractional or not. To maintain compatibility BIT(13) of clkflag in firmware will not be used in future for any purpose and will be marked as unused. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Jolly Shah <jolly.shah@xilinx.com> --- drivers/clk/zynqmp/divider.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/zynqmp/divider.c b/drivers/clk/zynqmp/divider.c index 8eed715..efe2ed6 100644 --- a/drivers/clk/zynqmp/divider.c +++ b/drivers/clk/zynqmp/divider.c @@ -25,7 +25,8 @@ #define to_zynqmp_clk_divider(_hw) \ container_of(_hw, struct zynqmp_clk_divider, hw) -#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CLK_FRAC BIT(13) /* has a fractional parent */ +#define CUSTOM_FLAG_CLK_FRAC BIT(0) /* has a fractional parent in custom type flag */ /** * struct zynqmp_clk_divider - adjustable divider clock @@ -307,7 +308,8 @@ struct clk_hw *zynqmp_clk_register_divider(const char *name, init.num_parents = 1; /* struct clk_divider assignments */ - div->is_frac = !!(nodes->flag & CLK_FRAC); + div->is_frac = !!((nodes->flag & CLK_FRAC) | + (nodes->custom_type_flag & CUSTOM_FLAG_CLK_FRAC)); div->flags = nodes->type_flag; div->hw.init = &init; div->clk_id = clk_id; -- 2.7.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-03-12 21:32 UTC|newest] Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-03-12 21:31 [PATCH v2 0/2] drivers: clk: zynqmp: Update fraction clock check from custom type flags Jolly Shah 2020-03-12 21:31 ` Jolly Shah 2020-03-12 21:31 ` [PATCH v2 1/2] drivers: clk: zynqmp: Add support for " Jolly Shah 2020-03-12 21:31 ` Jolly Shah 2020-05-27 1:01 ` Stephen Boyd 2020-05-27 1:01 ` Stephen Boyd 2020-03-12 21:31 ` Jolly Shah [this message] 2020-03-12 21:31 ` [PATCH v2 2/2] drivers: clk: zynqmp: Update fraction clock check from " Jolly Shah 2020-05-27 1:01 ` Stephen Boyd 2020-05-27 1:01 ` Stephen Boyd 2020-05-27 1:08 ` Stephen Boyd 2020-05-27 1:08 ` Stephen Boyd 2020-05-28 17:44 ` Jolly Shah 2020-05-28 17:44 ` Jolly Shah 2020-05-28 23:12 ` Stephen Boyd 2020-05-28 23:12 ` Stephen Boyd 2020-05-29 21:20 ` Jolly Shah 2020-05-29 21:20 ` Jolly Shah 2020-03-23 21:15 ` [PATCH v2 0/2] " Jolly Shah 2020-03-23 21:15 ` Jolly Shah 2020-04-09 20:48 ` Jolly Shah 2020-04-09 20:48 ` Jolly Shah
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