* [PATCH v2 1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
@ 2020-03-25 1:22 ` Manasi Navare
0 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2020-03-25 1:22 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Nicholas Kazlauskas
DP sink device sets the Ignore MSA bit in its
DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
ignore the MSA video timing paramaters and its ability to support
seamless video timing change over a range of timing exposed by
DisplayID and EDID.
This is required for the sink to indicate that it is Adaptive sync
capable.
v2:
* Rename to describe what the function does (Jani Nikula)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/drm_dp_helper.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 9d87cdf2740a..36655f3c83f8 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_ALTERNATE_SCRAMBLER_RESET_CAP;
}
+/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
+static inline bool
+drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
+ DP_MSA_TIMING_PAR_IGNORED;
+}
+
/*
* DisplayPort AUX channel
*/
--
2.19.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v2 1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
@ 2020-03-25 1:22 ` Manasi Navare
0 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2020-03-25 1:22 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Harry Wentland, Nicholas Kazlauskas
DP sink device sets the Ignore MSA bit in its
DP_DOWNSTREAM_PORT_COUNT register to indicate its ability to
ignore the MSA video timing paramaters and its ability to support
seamless video timing change over a range of timing exposed by
DisplayID and EDID.
This is required for the sink to indicate that it is Adaptive sync
capable.
v2:
* Rename to describe what the function does (Jani Nikula)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
---
include/drm/drm_dp_helper.h | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index 9d87cdf2740a..36655f3c83f8 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -1315,6 +1315,14 @@ drm_dp_alternate_scrambler_reset_cap(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
DP_ALTERNATE_SCRAMBLER_RESET_CAP;
}
+/* Ignore MSA timing for Adaptive Sync support on DP 1.4 */
+static inline bool
+drm_dp_sink_can_do_video_without_timing_msa(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
+{
+ return dpcd[DP_DOWN_STREAM_PORT_COUNT] &
+ DP_MSA_TIMING_PAR_IGNORED;
+}
+
/*
* DisplayPort AUX channel
*/
--
2.19.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/2] drm/i915/dp: Attach and set drm connector VRR property
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
@ 2020-03-25 1:22 ` Manasi Navare
-1 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2020-03-25 1:22 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Manasi Navare, Aditya Swarup
From: Aditya Swarup <aditya.swarup@intel.com>
This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.
v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ef2e06e292d5..95db4e783893 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5843,6 +5843,23 @@ intel_dp_force(struct drm_connector *connector)
intel_display_power_put(dev_priv, aux_domain, wakeref);
}
+static bool intel_dp_is_vrr_capable(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
+ const struct drm_display_info *info = &connector->display_info;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+ /*
+ * DP Sink is capable of Variable refresh video timings if
+ * Ignore MSA bit is set in DPCD.
+ * EDID monitor range also should be atleast 10 for reasonable
+ * Adaptive sync/ VRR end user experience.
+ */
+ return INTEL_GEN(dev_priv) >= 12 &&
+ drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
+ info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+}
+
static int intel_dp_get_modes(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -5853,6 +5870,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
int ret = intel_connector_update_modes(connector, edid);
if (ret)
return ret;
+
+ if (intel_dp_is_vrr_capable(connector))
+ drm_connector_set_vrr_capable_property(connector,
+ true);
}
/* if eDP has no EDID, fall back to fixed mode */
@@ -6880,6 +6901,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
}
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ drm_connector_attach_vrr_capable_property(connector);
}
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
--
2.19.1
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^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Attach and set drm connector VRR property
@ 2020-03-25 1:22 ` Manasi Navare
0 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2020-03-25 1:22 UTC (permalink / raw)
To: intel-gfx, dri-devel
From: Aditya Swarup <aditya.swarup@intel.com>
This function sets the VRR property for connector based
on the platform support, EDID monitor range and DP sink
DPCD capability of outputing video without msa
timing information.
v2:
* Just set this in intel_dp_get_modes instead of new hook (Jani)
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ef2e06e292d5..95db4e783893 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -5843,6 +5843,23 @@ intel_dp_force(struct drm_connector *connector)
intel_display_power_put(dev_priv, aux_domain, wakeref);
}
+static bool intel_dp_is_vrr_capable(struct drm_connector *connector)
+{
+ struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
+ const struct drm_display_info *info = &connector->display_info;
+ struct drm_i915_private *dev_priv = to_i915(connector->dev);
+
+ /*
+ * DP Sink is capable of Variable refresh video timings if
+ * Ignore MSA bit is set in DPCD.
+ * EDID monitor range also should be atleast 10 for reasonable
+ * Adaptive sync/ VRR end user experience.
+ */
+ return INTEL_GEN(dev_priv) >= 12 &&
+ drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
+ info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
+}
+
static int intel_dp_get_modes(struct drm_connector *connector)
{
struct intel_connector *intel_connector = to_intel_connector(connector);
@@ -5853,6 +5870,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
int ret = intel_connector_update_modes(connector, edid);
if (ret)
return ret;
+
+ if (intel_dp_is_vrr_capable(connector))
+ drm_connector_set_vrr_capable_property(connector,
+ true);
}
/* if eDP has no EDID, fall back to fixed mode */
@@ -6880,6 +6901,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
}
+
+ if (INTEL_GEN(dev_priv) >= 12)
+ drm_connector_attach_vrr_capable_property(connector);
}
static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
--
2.19.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
(?)
(?)
@ 2020-03-25 1:33 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-03-25 1:33 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
URL : https://patchwork.freedesktop.org/series/75042/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b3e66fa48b38 drm/dp: DRM DP helper for reading Ignore MSA from DPCD
-:11: WARNING:TYPO_SPELLING: 'paramaters' may be misspelled - perhaps 'parameters'?
#11:
ignore the MSA video timing paramaters and its ability to support
total: 0 errors, 1 warnings, 0 checks, 14 lines checked
f456eddc0f15 drm/i915/dp: Attach and set drm connector VRR property
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
` (2 preceding siblings ...)
(?)
@ 2020-03-25 1:59 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-03-25 1:59 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
URL : https://patchwork.freedesktop.org/series/75042/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8184 -> Patchwork_17077
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/index.html
Known issues
------------
Here are the changes found in Patchwork_17077 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_suspend@basic-s3:
- fi-snb-2600: [PASS][1] -> [DMESG-WARN][2] ([i915#42])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/fi-snb-2600/igt@gem_exec_suspend@basic-s3.html
#### Possible fixes ####
* igt@i915_selftest@live@gem_contexts:
- fi-cml-s: [DMESG-FAIL][3] ([i915#877]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/fi-cml-s/igt@i915_selftest@live@gem_contexts.html
[i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42
[i915#877]: https://gitlab.freedesktop.org/drm/intel/issues/877
Participating hosts (40 -> 39)
------------------------------
Additional (6): fi-kbl-soraka fi-hsw-4770r fi-bsw-n3050 fi-byt-j1900 fi-kbl-7500u fi-cfl-8109u
Missing (7): fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-bdw-samus fi-bsw-nick fi-skl-6600u
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8184 -> Patchwork_17077
CI-20190529: 20190529
CI_DRM_8184: 1a72c9d9d3140e92190485d766b9d165932c5b86 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5535: d1dcf40cc6869ac858586c5ad9f09af6617ce2ee @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17077: f456eddc0f150e1234121f0c65f91d7b47ceeb7c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f456eddc0f15 drm/i915/dp: Attach and set drm connector VRR property
b3e66fa48b38 drm/dp: DRM DP helper for reading Ignore MSA from DPCD
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/index.html
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
` (3 preceding siblings ...)
(?)
@ 2020-03-25 4:08 ` Patchwork
-1 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2020-03-25 4:08 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD
URL : https://patchwork.freedesktop.org/series/75042/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8184_full -> Patchwork_17077_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17077_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@kms:
- shard-glk: [PASS][1] -> [TIMEOUT][2] ([i915#1383])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-glk9/igt@gem_eio@kms.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-glk5/igt@gem_eio@kms.html
* igt@gem_exec_schedule@implicit-both-bsd1:
- shard-iclb: [PASS][3] -> [SKIP][4] ([fdo#109276] / [i915#677])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb4/igt@gem_exec_schedule@implicit-both-bsd1.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@gem_exec_schedule@implicit-both-bsd1.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][5] -> [SKIP][6] ([i915#677])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb6/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb6/igt@gem_exec_schedule@preempt-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb1/igt@gem_exec_schedule@preempt-bsd.html
* igt@gem_exec_schedule@promotion-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +11 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@gem_exec_schedule@promotion-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@gem_exec_schedule@promotion-bsd1.html
* igt@gem_exec_store@cachelines-vcs1:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112080]) +7 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@gem_exec_store@cachelines-vcs1.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@gem_exec_store@cachelines-vcs1.html
* igt@i915_suspend@sysfs-reader:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-kbl3/igt@i915_suspend@sysfs-reader.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-kbl1/igt@i915_suspend@sysfs-reader.html
* igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding:
- shard-skl: [PASS][15] -> [FAIL][16] ([i915#54])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl6/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x85-sliding.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#52] / [i915#54])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-apl: [PASS][19] -> [DMESG-WARN][20] ([i915#180] / [i915#95])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-apl4/igt@kms_fbcon_fbt@fbc-suspend.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-skl: [PASS][21] -> [INCOMPLETE][22] ([i915#221])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl5/igt@kms_flip@flip-vs-suspend-interruptible.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible.html
- shard-apl: [PASS][23] -> [DMESG-WARN][24] ([i915#180]) +1 similar issue
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [PASS][25] -> [FAIL][26] ([fdo#108145]) +1 similar issue
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl6/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr2_su@frontbuffer:
- shard-iclb: [PASS][29] -> [SKIP][30] ([fdo#109642] / [fdo#111068])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@kms_psr2_su@frontbuffer.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@kms_psr2_su@frontbuffer.html
* igt@kms_psr@psr2_dpms:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@kms_psr@psr2_dpms.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb4/igt@kms_psr@psr2_dpms.html
#### Possible fixes ####
* igt@gem_ctx_isolation@vcs1-dirty-create:
- shard-iclb: [SKIP][33] ([fdo#112080]) -> [PASS][34] +7 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb6/igt@gem_ctx_isolation@vcs1-dirty-create.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb1/igt@gem_ctx_isolation@vcs1-dirty-create.html
* igt@gem_eio@in-flight-suspend:
- shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36] +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-kbl1/igt@gem_eio@in-flight-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-kbl3/igt@gem_eio@in-flight-suspend.html
* igt@gem_exec_async@concurrent-writes-bsd:
- shard-iclb: [SKIP][37] ([fdo#112146]) -> [PASS][38] +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@gem_exec_async@concurrent-writes-bsd.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@gem_exec_async@concurrent-writes-bsd.html
* igt@gem_exec_schedule@implicit-read-write-bsd:
- shard-iclb: [SKIP][39] ([i915#677]) -> [PASS][40] +1 similar issue
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@gem_exec_schedule@implicit-read-write-bsd.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@gem_exec_schedule@implicit-read-write-bsd.html
* igt@gem_exec_schedule@pi-shared-iova-bsd2:
- shard-iclb: [SKIP][41] ([fdo#109276]) -> [PASS][42] +3 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb6/igt@gem_exec_schedule@pi-shared-iova-bsd2.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb1/igt@gem_exec_schedule@pi-shared-iova-bsd2.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-skl: [INCOMPLETE][43] ([i915#300]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl6/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_cursor_crc@pipe-b-cursor-suspend:
- shard-iclb: [INCOMPLETE][45] ([i915#1185] / [i915#1237]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb3/igt@kms_cursor_crc@pipe-b-cursor-suspend.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [SKIP][47] ([fdo#109349]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb1/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_flip@plain-flip-fb-recreate:
- shard-skl: [FAIL][49] ([i915#34]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-skl7/igt@kms_flip@plain-flip-fb-recreate.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-skl6/igt@kms_flip@plain-flip-fb-recreate.html
* igt@kms_psr@no_drrs:
- shard-iclb: [FAIL][51] ([i915#173]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb1/igt@kms_psr@no_drrs.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb2/igt@kms_psr@no_drrs.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-iclb: [SKIP][53] ([fdo#109441]) -> [PASS][54] +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb1/igt@kms_psr@psr2_primary_mmap_gtt.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb2/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-apl: [DMESG-WARN][55] ([i915#180]) -> [PASS][56]
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-apl4/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-apl8/igt@kms_vblank@pipe-b-ts-continuation-suspend.html
#### Warnings ####
* igt@i915_pm_dc@dc6-dpms:
- shard-tglb: [SKIP][57] ([i915#468]) -> [FAIL][58] ([i915#454])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][59] ([i915#1515]) -> [FAIL][60] ([i915#1515])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-iclb2/igt@i915_pm_rc6_residency@rc6-idle.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_pm_rpm@gem-idle:
- shard-snb: [SKIP][61] ([fdo#109271]) -> [INCOMPLETE][62] ([i915#82])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8184/shard-snb1/igt@i915_pm_rpm@gem-idle.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/shard-snb4/igt@i915_pm_rpm@gem-idle.html
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
[i915#1237]: https://gitlab.freedesktop.org/drm/intel/issues/1237
[i915#1383]: https://gitlab.freedesktop.org/drm/intel/issues/1383
[i915#1515]: https://gitlab.freedesktop.org/drm/intel/issues/1515
[i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#221]: https://gitlab.freedesktop.org/drm/intel/issues/221
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#300]: https://gitlab.freedesktop.org/drm/intel/issues/300
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8184 -> Patchwork_17077
CI-20190529: 20190529
CI_DRM_8184: 1a72c9d9d3140e92190485d766b9d165932c5b86 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5535: d1dcf40cc6869ac858586c5ad9f09af6617ce2ee @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17077: f456eddc0f150e1234121f0c65f91d7b47ceeb7c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17077/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/2] drm/i915/dp: Attach and set drm connector VRR property
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
@ 2020-03-31 0:26 ` Manasi Navare
-1 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2020-03-31 0:26 UTC (permalink / raw)
To: intel-gfx, dri-devel; +Cc: Aditya Swarup
@Jani @Ville, this is the one we had discussed on IRC, could you
take a look at this patch?
Manasi
On Tue, Mar 24, 2020 at 06:22:01PM -0700, Manasi Navare wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
>
> This function sets the VRR property for connector based
> on the platform support, EDID monitor range and DP sink
> DPCD capability of outputing video without msa
> timing information.
>
> v2:
> * Just set this in intel_dp_get_modes instead of new hook (Jani)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ef2e06e292d5..95db4e783893 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5843,6 +5843,23 @@ intel_dp_force(struct drm_connector *connector)
> intel_display_power_put(dev_priv, aux_domain, wakeref);
> }
>
> +static bool intel_dp_is_vrr_capable(struct drm_connector *connector)
> +{
> + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> + const struct drm_display_info *info = &connector->display_info;
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> + /*
> + * DP Sink is capable of Variable refresh video timings if
> + * Ignore MSA bit is set in DPCD.
> + * EDID monitor range also should be atleast 10 for reasonable
> + * Adaptive sync/ VRR end user experience.
> + */
> + return INTEL_GEN(dev_priv) >= 12 &&
> + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
> + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> +}
> +
> static int intel_dp_get_modes(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -5853,6 +5870,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
> int ret = intel_connector_update_modes(connector, edid);
> if (ret)
> return ret;
> +
> + if (intel_dp_is_vrr_capable(connector))
> + drm_connector_set_vrr_capable_property(connector,
> + true);
> }
>
> /* if eDP has no EDID, fall back to fixed mode */
> @@ -6880,6 +6901,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
> connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
>
> }
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + drm_connector_attach_vrr_capable_property(connector);
> }
>
> static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> --
> 2.19.1
>
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/2] drm/i915/dp: Attach and set drm connector VRR property
@ 2020-03-31 0:26 ` Manasi Navare
0 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2020-03-31 0:26 UTC (permalink / raw)
To: intel-gfx, dri-devel
@Jani @Ville, this is the one we had discussed on IRC, could you
take a look at this patch?
Manasi
On Tue, Mar 24, 2020 at 06:22:01PM -0700, Manasi Navare wrote:
> From: Aditya Swarup <aditya.swarup@intel.com>
>
> This function sets the VRR property for connector based
> on the platform support, EDID monitor range and DP sink
> DPCD capability of outputing video without msa
> timing information.
>
> v2:
> * Just set this in intel_dp_get_modes instead of new hook (Jani)
>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Aditya Swarup <aditya.swarup@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 24 ++++++++++++++++++++++++
> 1 file changed, 24 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index ef2e06e292d5..95db4e783893 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -5843,6 +5843,23 @@ intel_dp_force(struct drm_connector *connector)
> intel_display_power_put(dev_priv, aux_domain, wakeref);
> }
>
> +static bool intel_dp_is_vrr_capable(struct drm_connector *connector)
> +{
> + struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector));
> + const struct drm_display_info *info = &connector->display_info;
> + struct drm_i915_private *dev_priv = to_i915(connector->dev);
> +
> + /*
> + * DP Sink is capable of Variable refresh video timings if
> + * Ignore MSA bit is set in DPCD.
> + * EDID monitor range also should be atleast 10 for reasonable
> + * Adaptive sync/ VRR end user experience.
> + */
> + return INTEL_GEN(dev_priv) >= 12 &&
> + drm_dp_sink_can_do_video_without_timing_msa(intel_dp->dpcd) &&
> + info->monitor_range.max_vfreq - info->monitor_range.min_vfreq > 10;
> +}
> +
> static int intel_dp_get_modes(struct drm_connector *connector)
> {
> struct intel_connector *intel_connector = to_intel_connector(connector);
> @@ -5853,6 +5870,10 @@ static int intel_dp_get_modes(struct drm_connector *connector)
> int ret = intel_connector_update_modes(connector, edid);
> if (ret)
> return ret;
> +
> + if (intel_dp_is_vrr_capable(connector))
> + drm_connector_set_vrr_capable_property(connector,
> + true);
> }
>
> /* if eDP has no EDID, fall back to fixed mode */
> @@ -6880,6 +6901,9 @@ intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connect
> connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
>
> }
> +
> + if (INTEL_GEN(dev_priv) >= 12)
> + drm_connector_attach_vrr_capable_property(connector);
> }
>
> static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
> --
> 2.19.1
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2020-03-31 0:25 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-25 1:22 [PATCH v2 1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Manasi Navare
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
2020-03-25 1:22 ` [PATCH v2 2/2] drm/i915/dp: Attach and set drm connector VRR property Manasi Navare
2020-03-25 1:22 ` [Intel-gfx] " Manasi Navare
2020-03-31 0:26 ` Manasi Navare
2020-03-31 0:26 ` [Intel-gfx] " Manasi Navare
2020-03-25 1:33 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [v2,1/2] drm/dp: DRM DP helper for reading Ignore MSA from DPCD Patchwork
2020-03-25 1:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-25 4:08 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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