* [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
@ 2020-03-27 11:26 Chris Wilson
2020-03-27 11:47 ` [Intel-gfx] [PATCH] " Chris Wilson
` (5 more replies)
0 siblings, 6 replies; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 11:26 UTC (permalink / raw)
To: intel-gfx
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
drivers/gpu/drm/i915/gt/intel_lrc.c | 72 +++++++++++++-------------
2 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..be3817d99908 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,8 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
{
bool tasklet = false;
+ ENGINE_TRACE(engine, "iir: %04x\n", iir);
+
if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
u32 eir;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..53650b452bc9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
- * Don't let the RING_HEAD advance past the breadcrumb
- * as we unwind (and until we resubmit) so that we do
- * not accidentally tell it to go backwards.
- */
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(&ve->base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
+ *port = execlists_schedule_in(last, port - execlists->pending);
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
- /*
- * Skip if we ended up with exactly the same set of requests,
- * e.g. trying to timeslice a pair of ordered contexts
- */
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
-
- goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+ /*
+ * Skip if we ended up with exactly the same set of requests,
+ * e.g. trying to timeslice a pair of ordered contexts
+ */
+ if (!memcmp(active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+ execlists_schedule_out(fetch_and_zero(port));
+ while (port-- != execlists->pending);
- execlists_submit_ports(engine);
- set_preempt_timeout(engine, *active);
- } else {
-skip_submit:
- ring_set_paused(engine, 0);
+ return false;
}
+ clear_ports(port + 1, last_port - port);
+
+ execlists_submit_ports(engine);
+ set_preempt_timeout(engine, *active);
+ tasklet_hi_schedule(&execlists->tasklet); /* lost interrupt */
+ return true;
}
static void
@@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
lockdep_assert_held(&engine->active.lock);
if (!READ_ONCE(engine->execlists.pending[0])) {
rcu_read_lock(); /* protect peeking at execlists->active */
- execlists_dequeue(engine);
+
+ /*
+ * Don't let the RING_HEAD advance past the breadcrumb
+ * as we unwind (and until we resubmit) so that we do
+ * not accidentally tell it to go backwards.
+ */
+ ring_set_paused(engine, 1);
+ if (!execlists_dequeue(engine))
+ ring_set_paused(engine, 0);
+
rcu_read_unlock();
}
}
@@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
ring_set_paused(engine, 1); /* Freeze the current request in place */
if (execlists_capture(engine))
intel_engine_reset(engine, msg);
- else
- ring_set_paused(engine, 0);
+ ring_set_paused(engine, 0);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(bit, lock);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
@ 2020-03-27 11:47 ` Chris Wilson
2020-03-27 11:53 ` Chris Wilson
` (4 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 11:47 UTC (permalink / raw)
To: intel-gfx
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 71 +++++++++++++-------------
2 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..06bdc48c60d5 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,9 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
{
bool tasklet = false;
+ if (engine)
+ ENGINE_TRACE(engine, "iir: %04x\n", iir);
+
if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
u32 eir;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..9e24ff7451a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
- * Don't let the RING_HEAD advance past the breadcrumb
- * as we unwind (and until we resubmit) so that we do
- * not accidentally tell it to go backwards.
- */
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(&ve->base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
+ *port = execlists_schedule_in(last, port - execlists->pending);
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
- /*
- * Skip if we ended up with exactly the same set of requests,
- * e.g. trying to timeslice a pair of ordered contexts
- */
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
-
- goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+ /*
+ * Skip if we ended up with exactly the same set of requests,
+ * e.g. trying to timeslice a pair of ordered contexts
+ */
+ if (!memcmp(active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+ execlists_schedule_out(fetch_and_zero(port));
+ while (port-- != execlists->pending);
- execlists_submit_ports(engine);
- set_preempt_timeout(engine, *active);
- } else {
-skip_submit:
- ring_set_paused(engine, 0);
+ return false;
}
+ clear_ports(port + 1, last_port - port);
+
+ execlists_submit_ports(engine);
+ set_preempt_timeout(engine, *active);
+ return true;
}
static void
@@ -2478,7 +2469,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
lockdep_assert_held(&engine->active.lock);
if (!READ_ONCE(engine->execlists.pending[0])) {
rcu_read_lock(); /* protect peeking at execlists->active */
- execlists_dequeue(engine);
+
+ /*
+ * Don't let the RING_HEAD advance past the breadcrumb
+ * as we unwind (and until we resubmit) so that we do
+ * not accidentally tell it to go backwards.
+ */
+ ring_set_paused(engine, 1);
+ if (!execlists_dequeue(engine))
+ ring_set_paused(engine, 0);
+
rcu_read_unlock();
}
}
@@ -2816,8 +2816,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
ring_set_paused(engine, 1); /* Freeze the current request in place */
if (execlists_capture(engine))
intel_engine_reset(engine, msg);
- else
- ring_set_paused(engine, 0);
+ ring_set_paused(engine, 0);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(bit, lock);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [PATCH] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
2020-03-27 11:47 ` [Intel-gfx] [PATCH] " Chris Wilson
@ 2020-03-27 11:53 ` Chris Wilson
2020-03-27 12:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7) Patchwork
` (3 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 11:53 UTC (permalink / raw)
To: intel-gfx
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt_irq.c | 3 ++
drivers/gpu/drm/i915/gt/intel_lrc.c | 71 +++++++++++++-------------
2 files changed, 38 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
index f0e7fd95165a..3afe05558816 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
@@ -24,6 +24,9 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
{
bool tasklet = false;
+ if (engine && iir & 0xffff)
+ ENGINE_TRACE(engine, "iir: %04x\n", iir);
+
if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
u32 eir;
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..9e24ff7451a9 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
- * Don't let the RING_HEAD advance past the breadcrumb
- * as we unwind (and until we resubmit) so that we do
- * not accidentally tell it to go backwards.
- */
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(&ve->base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,30 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
+ *port = execlists_schedule_in(last, port - execlists->pending);
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
- /*
- * Skip if we ended up with exactly the same set of requests,
- * e.g. trying to timeslice a pair of ordered contexts
- */
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
-
- goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+ /*
+ * Skip if we ended up with exactly the same set of requests,
+ * e.g. trying to timeslice a pair of ordered contexts
+ */
+ if (!memcmp(active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+ execlists_schedule_out(fetch_and_zero(port));
+ while (port-- != execlists->pending);
- execlists_submit_ports(engine);
- set_preempt_timeout(engine, *active);
- } else {
-skip_submit:
- ring_set_paused(engine, 0);
+ return false;
}
+ clear_ports(port + 1, last_port - port);
+
+ execlists_submit_ports(engine);
+ set_preempt_timeout(engine, *active);
+ return true;
}
static void
@@ -2478,7 +2469,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
lockdep_assert_held(&engine->active.lock);
if (!READ_ONCE(engine->execlists.pending[0])) {
rcu_read_lock(); /* protect peeking at execlists->active */
- execlists_dequeue(engine);
+
+ /*
+ * Don't let the RING_HEAD advance past the breadcrumb
+ * as we unwind (and until we resubmit) so that we do
+ * not accidentally tell it to go backwards.
+ */
+ ring_set_paused(engine, 1);
+ if (!execlists_dequeue(engine))
+ ring_set_paused(engine, 0);
+
rcu_read_unlock();
}
}
@@ -2816,8 +2816,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
ring_set_paused(engine, 1); /* Freeze the current request in place */
if (execlists_capture(engine))
intel_engine_reset(engine, msg);
- else
- ring_set_paused(engine, 0);
+ ring_set_paused(engine, 0);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(bit, lock);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7)
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
2020-03-27 11:47 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-03-27 11:53 ` Chris Wilson
@ 2020-03-27 12:43 ` Patchwork
2020-03-27 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-03-27 12:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7)
URL : https://patchwork.freedesktop.org/series/75130/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
ee89d7390a2e drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
-:29: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#29:
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
total: 0 errors, 1 warnings, 0 checks, 134 lines checked
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7)
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
` (2 preceding siblings ...)
2020-03-27 12:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7) Patchwork
@ 2020-03-27 13:19 ` Patchwork
2020-03-27 15:59 ` [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Tvrtko Ursulin
2020-03-28 13:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7) Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-03-27 13:19 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7)
URL : https://patchwork.freedesktop.org/series/75130/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8201 -> Patchwork_17116
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/index.html
Known issues
------------
Here are the changes found in Patchwork_17116 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@execlists:
- fi-icl-dsi: [PASS][1] -> [INCOMPLETE][2] ([i915#140])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/fi-icl-dsi/igt@i915_selftest@live@execlists.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/fi-icl-dsi/igt@i915_selftest@live@execlists.html
- fi-kbl-8809g: [PASS][3] -> [INCOMPLETE][4] ([CI#80] / [fdo#112259])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/fi-kbl-8809g/igt@i915_selftest@live@execlists.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/fi-kbl-8809g/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_pm:
- fi-bwr-2160: [PASS][5] -> [INCOMPLETE][6] ([i915#489])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/fi-bwr-2160/igt@i915_selftest@live@gt_pm.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/fi-bwr-2160/igt@i915_selftest@live@gt_pm.html
#### Possible fixes ####
* igt@i915_pm_rpm@module-reload:
- fi-kbl-guc: [FAIL][7] ([i915#579]) -> [PASS][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/fi-kbl-guc/igt@i915_pm_rpm@module-reload.html
#### Warnings ####
* igt@runner@aborted:
- fi-kbl-8809g: [FAIL][9] ([i915#1209]) -> [FAIL][10] ([i915#656])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/fi-kbl-8809g/igt@runner@aborted.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/fi-kbl-8809g/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[CI#80]: https://gitlab.freedesktop.org/gfx-ci/i915-infra/issues/80
[fdo#112259]: https://bugs.freedesktop.org/show_bug.cgi?id=112259
[i915#1209]: https://gitlab.freedesktop.org/drm/intel/issues/1209
[i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
[i915#579]: https://gitlab.freedesktop.org/drm/intel/issues/579
[i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
[i915#656]: https://gitlab.freedesktop.org/drm/intel/issues/656
Participating hosts (46 -> 40)
------------------------------
Additional (1): fi-byt-n2820
Missing (7): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bsw-nick fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8201 -> Patchwork_17116
CI-20190529: 20190529
CI_DRM_8201: df2dc60809f02d714ddc26136c24d6fc6f5268b6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5541: f3d9a3a5fa9ea281b859a5b81201e6147b9fbad1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17116: ee89d7390a2e05a8cd06631b1838d838b175ba9c @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
ee89d7390a2e drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
` (3 preceding siblings ...)
2020-03-27 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-03-27 15:59 ` Tvrtko Ursulin
2020-03-27 16:47 ` Chris Wilson
2020-03-28 13:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7) Patchwork
5 siblings, 1 reply; 12+ messages in thread
From: Tvrtko Ursulin @ 2020-03-27 15:59 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
On 27/03/2020 11:26, Chris Wilson wrote:
> In what seems remarkably similar to the w/a required to not reload an
> idle context with HEAD==TAIL, it appears we must prevent the HW from
> switching to an idle context in ELSP[1], while simultaneously trying to
> preempt the HW to run another context and a continuation of the idle
> context (which is no longer idle).
>
> process_csb: vecs0: cs-irq head=0, tail=1
> process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
> trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
> trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
> trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
> process_csb: vecs0: cs-irq head=1, tail=2
> process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
> trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
> process_csb: vecs0: cs-irq head=2, tail=5
> process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
> trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
> trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
> process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
> trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
> process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
> trace_ports: vecs0: completed { 8c0:32, 0:0 }
> process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
> process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
> process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
> process_csb: GEM_BUG_ON("context completed before request")
>
> Fortunately, we just so happen to have a semaphore in place to prevent
> the ring HEAD from proceeding past the end of a request that we can use
> to fix the HEAD in position as we reprogram ELSP.
>
> Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
> drivers/gpu/drm/i915/gt/intel_lrc.c | 72 +++++++++++++-------------
> 2 files changed, 38 insertions(+), 36 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> index f0e7fd95165a..be3817d99908 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> @@ -24,6 +24,8 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> {
> bool tasklet = false;
>
> + ENGINE_TRACE(engine, "iir: %04x\n", iir);
> +
> if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> u32 eir;
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> index b12355048501..53650b452bc9 100644
> --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> @@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
> memset_p((void **)ports, NULL, count);
> }
>
> -static void execlists_dequeue(struct intel_engine_cs *engine)
> +static bool execlists_dequeue(struct intel_engine_cs *engine)
> {
> struct intel_engine_execlists * const execlists = &engine->execlists;
> struct i915_request **port = execlists->pending;
> @@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> execlists->queue_priority_hint);
> record_preemption(execlists);
>
> - /*
> - * Don't let the RING_HEAD advance past the breadcrumb
> - * as we unwind (and until we resubmit) so that we do
> - * not accidentally tell it to go backwards.
> - */
> - ring_set_paused(engine, 1);
> -
> /*
> * Note that we have not stopped the GPU at this point,
> * so we are unwinding the incomplete requests as they
> @@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> last->sched.attr.priority,
> execlists->queue_priority_hint);
>
> - ring_set_paused(engine, 1);
> defer_active(engine);
>
> /*
> @@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> * of timeslices, our queue might be.
> */
> start_timeslice(engine);
> - return;
> + return false;
> }
> }
> }
> @@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> }
>
> if (last && !can_merge_rq(last, rq)) {
> + /* leave this for another sibling */
> spin_unlock(&ve->base.active.lock);
> start_timeslice(engine);
> - return; /* leave this for another sibling */
> + return false;
> }
>
> ENGINE_TRACE(engine,
> @@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> * interrupt for secondary ports).
> */
> execlists->queue_priority_hint = queue_prio(execlists);
> + if (!submit)
> + return false;
>
> - if (submit) {
> - *port = execlists_schedule_in(last, port - execlists->pending);
> - execlists->switch_priority_hint =
> - switch_prio(engine, *execlists->pending);
> + *port = execlists_schedule_in(last, port - execlists->pending);
> + execlists->switch_priority_hint =
> + switch_prio(engine, *execlists->pending);
>
> - /*
> - * Skip if we ended up with exactly the same set of requests,
> - * e.g. trying to timeslice a pair of ordered contexts
> - */
> - if (!memcmp(active, execlists->pending,
> - (port - execlists->pending + 1) * sizeof(*port))) {
> - do
> - execlists_schedule_out(fetch_and_zero(port));
> - while (port-- != execlists->pending);
> -
> - goto skip_submit;
> - }
> - clear_ports(port + 1, last_port - port);
> + /*
> + * Skip if we ended up with exactly the same set of requests,
> + * e.g. trying to timeslice a pair of ordered contexts
> + */
> + if (!memcmp(active, execlists->pending,
> + (port - execlists->pending + 1) * sizeof(*port))) {
> + do
> + execlists_schedule_out(fetch_and_zero(port));
> + while (port-- != execlists->pending);
>
> - execlists_submit_ports(engine);
> - set_preempt_timeout(engine, *active);
> - } else {
> -skip_submit:
> - ring_set_paused(engine, 0);
> + return false;
> }
> + clear_ports(port + 1, last_port - port);
> +
> + execlists_submit_ports(engine);
> + set_preempt_timeout(engine, *active);
> + tasklet_hi_schedule(&execlists->tasklet); /* lost interrupt */
> + return true;
> }
>
> static void
> @@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
> lockdep_assert_held(&engine->active.lock);
> if (!READ_ONCE(engine->execlists.pending[0])) {
> rcu_read_lock(); /* protect peeking at execlists->active */
> - execlists_dequeue(engine);
> +
> + /*
> + * Don't let the RING_HEAD advance past the breadcrumb
> + * as we unwind (and until we resubmit) so that we do
> + * not accidentally tell it to go backwards.
> + */
> + ring_set_paused(engine, 1);
> + if (!execlists_dequeue(engine))
> + ring_set_paused(engine, 0);
> +
> rcu_read_unlock();
> }
> }
> @@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
> ring_set_paused(engine, 1); /* Freeze the current request in place */
> if (execlists_capture(engine))
> intel_engine_reset(engine, msg);
> - else
> - ring_set_paused(engine, 0);
> + ring_set_paused(engine, 0);
>
> tasklet_enable(&engine->execlists.tasklet);
> clear_and_wake_up_bit(bit, lock);
>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Regards,
Tvrtko
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
2020-03-27 15:59 ` [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Tvrtko Ursulin
@ 2020-03-27 16:47 ` Chris Wilson
2020-03-27 20:19 ` Mika Kuoppala
0 siblings, 1 reply; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 16:47 UTC (permalink / raw)
To: Tvrtko Ursulin, intel-gfx
Quoting Tvrtko Ursulin (2020-03-27 15:59:45)
>
> On 27/03/2020 11:26, Chris Wilson wrote:
> > In what seems remarkably similar to the w/a required to not reload an
> > idle context with HEAD==TAIL, it appears we must prevent the HW from
> > switching to an idle context in ELSP[1], while simultaneously trying to
> > preempt the HW to run another context and a continuation of the idle
> > context (which is no longer idle).
> >
> > process_csb: vecs0: cs-irq head=0, tail=1
> > process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
> > trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
> > trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
> > trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
> > process_csb: vecs0: cs-irq head=1, tail=2
> > process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
> > trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
> > process_csb: vecs0: cs-irq head=2, tail=5
> > process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
> > trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
> > trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
> > process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
> > trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
> > process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
> > trace_ports: vecs0: completed { 8c0:32, 0:0 }
> > process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
> > process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
> > process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
> > process_csb: GEM_BUG_ON("context completed before request")
> >
> > Fortunately, we just so happen to have a semaphore in place to prevent
> > the ring HEAD from proceeding past the end of a request that we can use
> > to fix the HEAD in position as we reprogram ELSP.
> >
> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
> > drivers/gpu/drm/i915/gt/intel_lrc.c | 72 +++++++++++++-------------
> > 2 files changed, 38 insertions(+), 36 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > index f0e7fd95165a..be3817d99908 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> > @@ -24,6 +24,8 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> > {
> > bool tasklet = false;
> >
> > + ENGINE_TRACE(engine, "iir: %04x\n", iir);
> > +
> > if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> > u32 eir;
> >
> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > index b12355048501..53650b452bc9 100644
> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> > @@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
> > memset_p((void **)ports, NULL, count);
> > }
> >
> > -static void execlists_dequeue(struct intel_engine_cs *engine)
> > +static bool execlists_dequeue(struct intel_engine_cs *engine)
> > {
> > struct intel_engine_execlists * const execlists = &engine->execlists;
> > struct i915_request **port = execlists->pending;
> > @@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> > execlists->queue_priority_hint);
> > record_preemption(execlists);
> >
> > - /*
> > - * Don't let the RING_HEAD advance past the breadcrumb
> > - * as we unwind (and until we resubmit) so that we do
> > - * not accidentally tell it to go backwards.
> > - */
> > - ring_set_paused(engine, 1);
> > -
> > /*
> > * Note that we have not stopped the GPU at this point,
> > * so we are unwinding the incomplete requests as they
> > @@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> > last->sched.attr.priority,
> > execlists->queue_priority_hint);
> >
> > - ring_set_paused(engine, 1);
> > defer_active(engine);
> >
> > /*
> > @@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> > * of timeslices, our queue might be.
> > */
> > start_timeslice(engine);
> > - return;
> > + return false;
> > }
> > }
> > }
> > @@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> > }
> >
> > if (last && !can_merge_rq(last, rq)) {
> > + /* leave this for another sibling */
> > spin_unlock(&ve->base.active.lock);
> > start_timeslice(engine);
> > - return; /* leave this for another sibling */
> > + return false;
> > }
> >
> > ENGINE_TRACE(engine,
> > @@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> > * interrupt for secondary ports).
> > */
> > execlists->queue_priority_hint = queue_prio(execlists);
> > + if (!submit)
> > + return false;
> >
> > - if (submit) {
> > - *port = execlists_schedule_in(last, port - execlists->pending);
> > - execlists->switch_priority_hint =
> > - switch_prio(engine, *execlists->pending);
> > + *port = execlists_schedule_in(last, port - execlists->pending);
> > + execlists->switch_priority_hint =
> > + switch_prio(engine, *execlists->pending);
> >
> > - /*
> > - * Skip if we ended up with exactly the same set of requests,
> > - * e.g. trying to timeslice a pair of ordered contexts
> > - */
> > - if (!memcmp(active, execlists->pending,
> > - (port - execlists->pending + 1) * sizeof(*port))) {
> > - do
> > - execlists_schedule_out(fetch_and_zero(port));
> > - while (port-- != execlists->pending);
> > -
> > - goto skip_submit;
> > - }
> > - clear_ports(port + 1, last_port - port);
> > + /*
> > + * Skip if we ended up with exactly the same set of requests,
> > + * e.g. trying to timeslice a pair of ordered contexts
> > + */
> > + if (!memcmp(active, execlists->pending,
> > + (port - execlists->pending + 1) * sizeof(*port))) {
> > + do
> > + execlists_schedule_out(fetch_and_zero(port));
> > + while (port-- != execlists->pending);
> >
> > - execlists_submit_ports(engine);
> > - set_preempt_timeout(engine, *active);
> > - } else {
> > -skip_submit:
> > - ring_set_paused(engine, 0);
> > + return false;
> > }
> > + clear_ports(port + 1, last_port - port);
> > +
> > + execlists_submit_ports(engine);
> > + set_preempt_timeout(engine, *active);
> > + tasklet_hi_schedule(&execlists->tasklet); /* lost interrupt */
> > + return true;
> > }
> >
> > static void
> > @@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
> > lockdep_assert_held(&engine->active.lock);
> > if (!READ_ONCE(engine->execlists.pending[0])) {
> > rcu_read_lock(); /* protect peeking at execlists->active */
> > - execlists_dequeue(engine);
> > +
> > + /*
> > + * Don't let the RING_HEAD advance past the breadcrumb
> > + * as we unwind (and until we resubmit) so that we do
> > + * not accidentally tell it to go backwards.
> > + */
> > + ring_set_paused(engine, 1);
> > + if (!execlists_dequeue(engine))
> > + ring_set_paused(engine, 0);
> > +
> > rcu_read_unlock();
> > }
> > }
> > @@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
> > ring_set_paused(engine, 1); /* Freeze the current request in place */
> > if (execlists_capture(engine))
> > intel_engine_reset(engine, msg);
> > - else
> > - ring_set_paused(engine, 0);
> > + ring_set_paused(engine, 0);
> >
> > tasklet_enable(&engine->execlists.tasklet);
> > clear_and_wake_up_bit(bit, lock);
> >
>
> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
The problem appears to be that if we lite-restore into a context inside
the semaphore, it doesn't yield an arbitration point and we do not raise
a CSB event.
Out of the frying pan and into the fire.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
2020-03-27 16:47 ` Chris Wilson
@ 2020-03-27 20:19 ` Mika Kuoppala
2020-03-27 20:32 ` Chris Wilson
0 siblings, 1 reply; 12+ messages in thread
From: Mika Kuoppala @ 2020-03-27 20:19 UTC (permalink / raw)
To: Chris Wilson, Tvrtko Ursulin, intel-gfx
Chris Wilson <chris@chris-wilson.co.uk> writes:
> Quoting Tvrtko Ursulin (2020-03-27 15:59:45)
>>
>> On 27/03/2020 11:26, Chris Wilson wrote:
>> > In what seems remarkably similar to the w/a required to not reload an
>> > idle context with HEAD==TAIL, it appears we must prevent the HW from
>> > switching to an idle context in ELSP[1], while simultaneously trying to
>> > preempt the HW to run another context and a continuation of the idle
>> > context (which is no longer idle).
>> >
>> > process_csb: vecs0: cs-irq head=0, tail=1
>> > process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
>> > trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
>> > trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
>> > trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
>> > process_csb: vecs0: cs-irq head=1, tail=2
>> > process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
>> > trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
>> > process_csb: vecs0: cs-irq head=2, tail=5
>> > process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
>> > trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
>> > trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
>> > process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
>> > trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
>> > process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
>> > trace_ports: vecs0: completed { 8c0:32, 0:0 }
>> > process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
>> > process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
>> > process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
>> > process_csb: GEM_BUG_ON("context completed before request")
>> >
>> > Fortunately, we just so happen to have a semaphore in place to prevent
>> > the ring HEAD from proceeding past the end of a request that we can use
>> > to fix the HEAD in position as we reprogram ELSP.
>> >
>> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
>> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
>> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> > ---
>> > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
>> > drivers/gpu/drm/i915/gt/intel_lrc.c | 72 +++++++++++++-------------
>> > 2 files changed, 38 insertions(+), 36 deletions(-)
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > index f0e7fd95165a..be3817d99908 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
>> > @@ -24,6 +24,8 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
>> > {
>> > bool tasklet = false;
>> >
>> > + ENGINE_TRACE(engine, "iir: %04x\n", iir);
>> > +
>> > if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
>> > u32 eir;
>> >
>> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > index b12355048501..53650b452bc9 100644
>> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
>> > @@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
>> > memset_p((void **)ports, NULL, count);
>> > }
>> >
>> > -static void execlists_dequeue(struct intel_engine_cs *engine)
>> > +static bool execlists_dequeue(struct intel_engine_cs *engine)
>> > {
>> > struct intel_engine_execlists * const execlists = &engine->execlists;
>> > struct i915_request **port = execlists->pending;
>> > @@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>> > execlists->queue_priority_hint);
>> > record_preemption(execlists);
>> >
>> > - /*
>> > - * Don't let the RING_HEAD advance past the breadcrumb
>> > - * as we unwind (and until we resubmit) so that we do
>> > - * not accidentally tell it to go backwards.
>> > - */
>> > - ring_set_paused(engine, 1);
>> > -
>> > /*
>> > * Note that we have not stopped the GPU at this point,
>> > * so we are unwinding the incomplete requests as they
>> > @@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>> > last->sched.attr.priority,
>> > execlists->queue_priority_hint);
>> >
>> > - ring_set_paused(engine, 1);
>> > defer_active(engine);
>> >
>> > /*
>> > @@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>> > * of timeslices, our queue might be.
>> > */
>> > start_timeslice(engine);
>> > - return;
>> > + return false;
>> > }
>> > }
>> > }
>> > @@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>> > }
>> >
>> > if (last && !can_merge_rq(last, rq)) {
>> > + /* leave this for another sibling */
>> > spin_unlock(&ve->base.active.lock);
>> > start_timeslice(engine);
>> > - return; /* leave this for another sibling */
>> > + return false;
>> > }
>> >
>> > ENGINE_TRACE(engine,
>> > @@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
>> > * interrupt for secondary ports).
>> > */
>> > execlists->queue_priority_hint = queue_prio(execlists);
>> > + if (!submit)
>> > + return false;
>> >
>> > - if (submit) {
>> > - *port = execlists_schedule_in(last, port - execlists->pending);
>> > - execlists->switch_priority_hint =
>> > - switch_prio(engine, *execlists->pending);
>> > + *port = execlists_schedule_in(last, port - execlists->pending);
>> > + execlists->switch_priority_hint =
>> > + switch_prio(engine, *execlists->pending);
>> >
>> > - /*
>> > - * Skip if we ended up with exactly the same set of requests,
>> > - * e.g. trying to timeslice a pair of ordered contexts
>> > - */
>> > - if (!memcmp(active, execlists->pending,
>> > - (port - execlists->pending + 1) * sizeof(*port))) {
>> > - do
>> > - execlists_schedule_out(fetch_and_zero(port));
>> > - while (port-- != execlists->pending);
>> > -
>> > - goto skip_submit;
>> > - }
>> > - clear_ports(port + 1, last_port - port);
>> > + /*
>> > + * Skip if we ended up with exactly the same set of requests,
>> > + * e.g. trying to timeslice a pair of ordered contexts
>> > + */
>> > + if (!memcmp(active, execlists->pending,
>> > + (port - execlists->pending + 1) * sizeof(*port))) {
>> > + do
>> > + execlists_schedule_out(fetch_and_zero(port));
>> > + while (port-- != execlists->pending);
>> >
>> > - execlists_submit_ports(engine);
>> > - set_preempt_timeout(engine, *active);
>> > - } else {
>> > -skip_submit:
>> > - ring_set_paused(engine, 0);
>> > + return false;
>> > }
>> > + clear_ports(port + 1, last_port - port);
>> > +
>> > + execlists_submit_ports(engine);
>> > + set_preempt_timeout(engine, *active);
>> > + tasklet_hi_schedule(&execlists->tasklet); /* lost interrupt */
>> > + return true;
>> > }
>> >
>> > static void
>> > @@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
>> > lockdep_assert_held(&engine->active.lock);
>> > if (!READ_ONCE(engine->execlists.pending[0])) {
>> > rcu_read_lock(); /* protect peeking at execlists->active */
>> > - execlists_dequeue(engine);
>> > +
>> > + /*
>> > + * Don't let the RING_HEAD advance past the breadcrumb
>> > + * as we unwind (and until we resubmit) so that we do
>> > + * not accidentally tell it to go backwards.
>> > + */
>> > + ring_set_paused(engine, 1);
>> > + if (!execlists_dequeue(engine))
>> > + ring_set_paused(engine, 0);
>> > +
>> > rcu_read_unlock();
>> > }
>> > }
>> > @@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
>> > ring_set_paused(engine, 1); /* Freeze the current request in place */
>> > if (execlists_capture(engine))
>> > intel_engine_reset(engine, msg);
>> > - else
>> > - ring_set_paused(engine, 0);
>> > + ring_set_paused(engine, 0);
>> >
>> > tasklet_enable(&engine->execlists.tasklet);
>> > clear_and_wake_up_bit(bit, lock);
>> >
>>
>> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> The problem appears to be that if we lite-restore into a context inside
> the semaphore, it doesn't yield an arbitration point and we do not raise
> a CSB event.
Trying to make senses of it all...
we do not raise == the hardware does not raise?
So if it is about lite restoring, we can't workaround by always making
sure elsp[1] head != tail?
-Mika
>
> Out of the frying pan and into the fire.
> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
2020-03-27 20:19 ` Mika Kuoppala
@ 2020-03-27 20:32 ` Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 20:32 UTC (permalink / raw)
To: Mika Kuoppala, Tvrtko Ursulin, intel-gfx
Quoting Mika Kuoppala (2020-03-27 20:19:15)
> Chris Wilson <chris@chris-wilson.co.uk> writes:
>
> > Quoting Tvrtko Ursulin (2020-03-27 15:59:45)
> >>
> >> On 27/03/2020 11:26, Chris Wilson wrote:
> >> > In what seems remarkably similar to the w/a required to not reload an
> >> > idle context with HEAD==TAIL, it appears we must prevent the HW from
> >> > switching to an idle context in ELSP[1], while simultaneously trying to
> >> > preempt the HW to run another context and a continuation of the idle
> >> > context (which is no longer idle).
> >> >
> >> > process_csb: vecs0: cs-irq head=0, tail=1
> >> > process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
> >> > trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
> >> > trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
> >> > trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
> >> > process_csb: vecs0: cs-irq head=1, tail=2
> >> > process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
> >> > trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
> >> > process_csb: vecs0: cs-irq head=2, tail=5
> >> > process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
> >> > trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
> >> > trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
> >> > process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
> >> > trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
> >> > process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
> >> > trace_ports: vecs0: completed { 8c0:32, 0:0 }
> >> > process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
> >> > process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
> >> > process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
> >> > process_csb: GEM_BUG_ON("context completed before request")
> >> >
> >> > Fortunately, we just so happen to have a semaphore in place to prevent
> >> > the ring HEAD from proceeding past the end of a request that we can use
> >> > to fix the HEAD in position as we reprogram ELSP.
> >> >
> >> > Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
> >> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> >> > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >> > Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> >> > ---
> >> > drivers/gpu/drm/i915/gt/intel_gt_irq.c | 2 +
> >> > drivers/gpu/drm/i915/gt/intel_lrc.c | 72 +++++++++++++-------------
> >> > 2 files changed, 38 insertions(+), 36 deletions(-)
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gt/intel_gt_irq.c b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> > index f0e7fd95165a..be3817d99908 100644
> >> > --- a/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> > +++ b/drivers/gpu/drm/i915/gt/intel_gt_irq.c
> >> > @@ -24,6 +24,8 @@ cs_irq_handler(struct intel_engine_cs *engine, u32 iir)
> >> > {
> >> > bool tasklet = false;
> >> >
> >> > + ENGINE_TRACE(engine, "iir: %04x\n", iir);
> >> > +
> >> > if (unlikely(iir & GT_CS_MASTER_ERROR_INTERRUPT)) {
> >> > u32 eir;
> >> >
> >> > diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> > index b12355048501..53650b452bc9 100644
> >> > --- a/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> > +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
> >> > @@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
> >> > memset_p((void **)ports, NULL, count);
> >> > }
> >> >
> >> > -static void execlists_dequeue(struct intel_engine_cs *engine)
> >> > +static bool execlists_dequeue(struct intel_engine_cs *engine)
> >> > {
> >> > struct intel_engine_execlists * const execlists = &engine->execlists;
> >> > struct i915_request **port = execlists->pending;
> >> > @@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> >> > execlists->queue_priority_hint);
> >> > record_preemption(execlists);
> >> >
> >> > - /*
> >> > - * Don't let the RING_HEAD advance past the breadcrumb
> >> > - * as we unwind (and until we resubmit) so that we do
> >> > - * not accidentally tell it to go backwards.
> >> > - */
> >> > - ring_set_paused(engine, 1);
> >> > -
> >> > /*
> >> > * Note that we have not stopped the GPU at this point,
> >> > * so we are unwinding the incomplete requests as they
> >> > @@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> >> > last->sched.attr.priority,
> >> > execlists->queue_priority_hint);
> >> >
> >> > - ring_set_paused(engine, 1);
> >> > defer_active(engine);
> >> >
> >> > /*
> >> > @@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> >> > * of timeslices, our queue might be.
> >> > */
> >> > start_timeslice(engine);
> >> > - return;
> >> > + return false;
> >> > }
> >> > }
> >> > }
> >> > @@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> >> > }
> >> >
> >> > if (last && !can_merge_rq(last, rq)) {
> >> > + /* leave this for another sibling */
> >> > spin_unlock(&ve->base.active.lock);
> >> > start_timeslice(engine);
> >> > - return; /* leave this for another sibling */
> >> > + return false;
> >> > }
> >> >
> >> > ENGINE_TRACE(engine,
> >> > @@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
> >> > * interrupt for secondary ports).
> >> > */
> >> > execlists->queue_priority_hint = queue_prio(execlists);
> >> > + if (!submit)
> >> > + return false;
> >> >
> >> > - if (submit) {
> >> > - *port = execlists_schedule_in(last, port - execlists->pending);
> >> > - execlists->switch_priority_hint =
> >> > - switch_prio(engine, *execlists->pending);
> >> > + *port = execlists_schedule_in(last, port - execlists->pending);
> >> > + execlists->switch_priority_hint =
> >> > + switch_prio(engine, *execlists->pending);
> >> >
> >> > - /*
> >> > - * Skip if we ended up with exactly the same set of requests,
> >> > - * e.g. trying to timeslice a pair of ordered contexts
> >> > - */
> >> > - if (!memcmp(active, execlists->pending,
> >> > - (port - execlists->pending + 1) * sizeof(*port))) {
> >> > - do
> >> > - execlists_schedule_out(fetch_and_zero(port));
> >> > - while (port-- != execlists->pending);
> >> > -
> >> > - goto skip_submit;
> >> > - }
> >> > - clear_ports(port + 1, last_port - port);
> >> > + /*
> >> > + * Skip if we ended up with exactly the same set of requests,
> >> > + * e.g. trying to timeslice a pair of ordered contexts
> >> > + */
> >> > + if (!memcmp(active, execlists->pending,
> >> > + (port - execlists->pending + 1) * sizeof(*port))) {
> >> > + do
> >> > + execlists_schedule_out(fetch_and_zero(port));
> >> > + while (port-- != execlists->pending);
> >> >
> >> > - execlists_submit_ports(engine);
> >> > - set_preempt_timeout(engine, *active);
> >> > - } else {
> >> > -skip_submit:
> >> > - ring_set_paused(engine, 0);
> >> > + return false;
> >> > }
> >> > + clear_ports(port + 1, last_port - port);
> >> > +
> >> > + execlists_submit_ports(engine);
> >> > + set_preempt_timeout(engine, *active);
> >> > + tasklet_hi_schedule(&execlists->tasklet); /* lost interrupt */
> >> > + return true;
> >> > }
> >> >
> >> > static void
> >> > @@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
> >> > lockdep_assert_held(&engine->active.lock);
> >> > if (!READ_ONCE(engine->execlists.pending[0])) {
> >> > rcu_read_lock(); /* protect peeking at execlists->active */
> >> > - execlists_dequeue(engine);
> >> > +
> >> > + /*
> >> > + * Don't let the RING_HEAD advance past the breadcrumb
> >> > + * as we unwind (and until we resubmit) so that we do
> >> > + * not accidentally tell it to go backwards.
> >> > + */
> >> > + ring_set_paused(engine, 1);
> >> > + if (!execlists_dequeue(engine))
> >> > + ring_set_paused(engine, 0);
> >> > +
> >> > rcu_read_unlock();
> >> > }
> >> > }
> >> > @@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
> >> > ring_set_paused(engine, 1); /* Freeze the current request in place */
> >> > if (execlists_capture(engine))
> >> > intel_engine_reset(engine, msg);
> >> > - else
> >> > - ring_set_paused(engine, 0);
> >> > + ring_set_paused(engine, 0);
> >> >
> >> > tasklet_enable(&engine->execlists.tasklet);
> >> > clear_and_wake_up_bit(bit, lock);
> >> >
> >>
> >> Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> >
> > The problem appears to be that if we lite-restore into a context inside
> > the semaphore, it doesn't yield an arbitration point and we do not raise
> > a CSB event.
>
> Trying to make senses of it all...
>
> we do not raise == the hardware does not raise?
HW.
> So if it is about lite restoring, we can't workaround by always making
> sure elsp[1] head != tail?
No. The context we enter into ELSP[1] is still executing on the GPU and
hits HEAD==TAIL after we write the register, but before the GPU
processes the register.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7)
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
` (4 preceding siblings ...)
2020-03-27 15:59 ` [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Tvrtko Ursulin
@ 2020-03-28 13:21 ` Patchwork
5 siblings, 0 replies; 12+ messages in thread
From: Patchwork @ 2020-03-28 13:21 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7)
URL : https://patchwork.freedesktop.org/series/75130/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8201_full -> Patchwork_17116_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17116_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@close-replace-race:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2] ([i915#1492])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb1/igt@gem_ctx_persistence@close-replace-race.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb6/igt@gem_ctx_persistence@close-replace-race.html
* igt@gem_ctx_persistence@engines-mixed-process@bcs0:
- shard-skl: [PASS][3] -> [FAIL][4] ([i915#1528])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-skl1/igt@gem_ctx_persistence@engines-mixed-process@bcs0.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-skl6/igt@gem_ctx_persistence@engines-mixed-process@bcs0.html
* igt@gem_exec_schedule@implicit-both-bsd2:
- shard-iclb: [PASS][5] -> [SKIP][6] ([fdo#109276] / [i915#677]) +2 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb1/igt@gem_exec_schedule@implicit-both-bsd2.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb5/igt@gem_exec_schedule@implicit-both-bsd2.html
* igt@gem_exec_schedule@pi-distinct-iova-bsd:
- shard-iclb: [PASS][7] -> [SKIP][8] ([i915#677]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb3/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb4/igt@gem_exec_schedule@pi-distinct-iova-bsd.html
* igt@gem_exec_schedule@preempt-queue-bsd1:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109276]) +11 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb5/igt@gem_exec_schedule@preempt-queue-bsd1.html
* igt@gem_exec_schedule@preempt-self-bsd:
- shard-iclb: [PASS][11] -> [SKIP][12] ([fdo#112146]) +3 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb5/igt@gem_exec_schedule@preempt-self-bsd.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb1/igt@gem_exec_schedule@preempt-self-bsd.html
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: [PASS][13] -> [DMESG-WARN][14] ([i915#180]) +4 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-kbl6/igt@gem_exec_suspend@basic-s3.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-kbl1/igt@gem_exec_suspend@basic-s3.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-hsw: [PASS][15] -> [TIMEOUT][16] ([i915#1526])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw6/igt@i915_pm_rc6_residency@rc6-idle.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw8/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@i915_selftest@live@execlists:
- shard-tglb: [PASS][17] -> [INCOMPLETE][18] ([i915#647])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-tglb8/igt@i915_selftest@live@execlists.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-tglb1/igt@i915_selftest@live@execlists.html
* igt@kms_cursor_crc@pipe-a-cursor-128x128-random:
- shard-kbl: [PASS][19] -> [FAIL][20] ([i915#54] / [i915#93] / [i915#95])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-128x128-random.html
* igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen:
- shard-apl: [PASS][21] -> [FAIL][22] ([i915#54] / [i915#95])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-apl1/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-apl2/igt@kms_cursor_crc@pipe-a-cursor-256x256-offscreen.html
* igt@kms_hdr@bpc-switch-suspend:
- shard-skl: [PASS][23] -> [FAIL][24] ([i915#1188])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-skl4/igt@kms_hdr@bpc-switch-suspend.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-skl10/igt@kms_hdr@bpc-switch-suspend.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-skl: [PASS][25] -> [FAIL][26] ([i915#53])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-skl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-skl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-skl5/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-skl9/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-glk: [PASS][29] -> [FAIL][30] ([i915#899])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-glk3/igt@kms_plane_lowres@pipe-a-tiling-x.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-glk4/igt@kms_plane_lowres@pipe-a-tiling-x.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][31] -> [SKIP][32] ([fdo#109441]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb4/igt@kms_psr@psr2_cursor_plane_move.html
* igt@kms_setmode@basic:
- shard-apl: [PASS][33] -> [FAIL][34] ([i915#31])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-apl6/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-apl6/igt@kms_setmode@basic.html
* igt@perf_pmu@busy-no-semaphores-vcs1:
- shard-iclb: [PASS][35] -> [SKIP][36] ([fdo#112080]) +8 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb1/igt@perf_pmu@busy-no-semaphores-vcs1.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb6/igt@perf_pmu@busy-no-semaphores-vcs1.html
#### Possible fixes ####
* {igt@gem_ctx_isolation@preservation-s3@vcs0}:
- shard-skl: [INCOMPLETE][37] ([i915#198]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-skl7/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-skl4/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_exec_schedule@fifo-bsd1:
- shard-iclb: [SKIP][39] ([fdo#109276]) -> [PASS][40] +7 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb5/igt@gem_exec_schedule@fifo-bsd1.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb1/igt@gem_exec_schedule@fifo-bsd1.html
* igt@gem_exec_schedule@implicit-read-write-bsd1:
- shard-iclb: [SKIP][41] ([fdo#109276] / [i915#677]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb3/igt@gem_exec_schedule@implicit-read-write-bsd1.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb4/igt@gem_exec_schedule@implicit-read-write-bsd1.html
* igt@gem_exec_schedule@in-order-bsd:
- shard-iclb: [SKIP][43] ([fdo#112146]) -> [PASS][44] +6 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb2/igt@gem_exec_schedule@in-order-bsd.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb6/igt@gem_exec_schedule@in-order-bsd.html
* igt@gem_exec_schedule@pi-shared-iova-bsd:
- shard-iclb: [SKIP][45] ([i915#677]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb2/igt@gem_exec_schedule@pi-shared-iova-bsd.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb5/igt@gem_exec_schedule@pi-shared-iova-bsd.html
* igt@gem_workarounds@suspend-resume-fd:
- shard-kbl: [DMESG-WARN][47] ([i915#180]) -> [PASS][48] +1 similar issue
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-kbl1/igt@gem_workarounds@suspend-resume-fd.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html
* igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen:
- shard-apl: [FAIL][49] ([i915#54]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-apl3/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-apl4/igt@kms_cursor_crc@pipe-c-cursor-128x128-offscreen.html
* igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge:
- shard-kbl: [FAIL][51] ([i915#70] / [i915#93] / [i915#95]) -> [PASS][52]
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-kbl1/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-kbl2/igt@kms_cursor_edge_walk@pipe-a-64x64-bottom-edge.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: [FAIL][53] ([IGT#5]) -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled:
- shard-glk: [FAIL][55] ([i915#52] / [i915#54]) -> [PASS][56] +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-glk8/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-glk6/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-ytiled.html
* igt@kms_fbcon_fbt@fbc-suspend:
- shard-kbl: [DMESG-WARN][57] ([i915#180] / [i915#93] / [i915#95]) -> [PASS][58]
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html
* igt@kms_flip@flip-vs-suspend:
- shard-snb: [INCOMPLETE][59] ([i915#82]) -> [PASS][60]
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-snb1/igt@kms_flip@flip-vs-suspend.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-snb4/igt@kms_flip@flip-vs-suspend.html
- shard-hsw: [INCOMPLETE][61] ([i915#61]) -> [PASS][62]
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw6/igt@kms_flip@flip-vs-suspend.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw8/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend-interruptible:
- shard-apl: [DMESG-WARN][63] ([i915#180]) -> [PASS][64] +2 similar issues
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-iclb: [TIMEOUT][65] -> [PASS][66]
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb4/igt@kms_frontbuffer_tracking@fbc-suspend.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb2/igt@kms_frontbuffer_tracking@fbc-suspend.html
- shard-apl: [DMESG-WARN][67] ([i915#180] / [i915#95]) -> [PASS][68]
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-apl6/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][69] ([fdo#109441]) -> [PASS][70] +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb1/igt@kms_psr@psr2_primary_mmap_cpu.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_vblank@pipe-a-ts-continuation-suspend:
- shard-kbl: [INCOMPLETE][71] ([i915#155]) -> [PASS][72]
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-kbl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
* igt@perf_pmu@init-busy-vcs1:
- shard-iclb: [SKIP][73] ([fdo#112080]) -> [PASS][74] +6 similar issues
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb8/igt@perf_pmu@init-busy-vcs1.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb1/igt@perf_pmu@init-busy-vcs1.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][75] ([i915#658]) -> [SKIP][76] ([i915#588])
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-iclb4/igt@i915_pm_dc@dc3co-vpb-simulation.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-apl: [FAIL][77] ([fdo#108145]) -> [FAIL][78] ([fdo#108145] / [i915#95])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-apl2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@runner@aborted:
- shard-hsw: ([FAIL][79], [FAIL][80], [FAIL][81], [FAIL][82], [FAIL][83], [FAIL][84], [FAIL][85], [FAIL][86]) ([fdo#111870] / [i915#1485]) -> ([FAIL][87], [FAIL][88], [FAIL][89], [FAIL][90], [FAIL][91], [FAIL][92], [FAIL][93], [FAIL][94], [FAIL][95]) ([fdo#109271] / [fdo#111870] / [i915#1485])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw4/igt@runner@aborted.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw2/igt@runner@aborted.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw5/igt@runner@aborted.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw8/igt@runner@aborted.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw6/igt@runner@aborted.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw7/igt@runner@aborted.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw8/igt@runner@aborted.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8201/shard-hsw7/igt@runner@aborted.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw7/igt@runner@aborted.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw8/igt@runner@aborted.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw8/igt@runner@aborted.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw5/igt@runner@aborted.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw2/igt@runner@aborted.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw4/igt@runner@aborted.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw5/igt@runner@aborted.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw5/igt@runner@aborted.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/shard-hsw2/igt@runner@aborted.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870
[fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080
[fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1485]: https://gitlab.freedesktop.org/drm/intel/issues/1485
[i915#1492]: https://gitlab.freedesktop.org/drm/intel/issues/1492
[i915#1526]: https://gitlab.freedesktop.org/drm/intel/issues/1526
[i915#1528]: https://gitlab.freedesktop.org/drm/intel/issues/1528
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#198]: https://gitlab.freedesktop.org/drm/intel/issues/198
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#647]: https://gitlab.freedesktop.org/drm/intel/issues/647
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677
[i915#70]: https://gitlab.freedesktop.org/drm/intel/issues/70
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#899]: https://gitlab.freedesktop.org/drm/intel/issues/899
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8201 -> Patchwork_17116
CI-20190529: 20190529
CI_DRM_8201: df2dc60809f02d714ddc26136c24d6fc6f5268b6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5541: f3d9a3a5fa9ea281b859a5b81201e6147b9fbad1 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17116: ee89d7390a2e05a8cd06631b1838d838b175ba9c @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17116/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
@ 2020-03-27 9:29 Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 9:29 UTC (permalink / raw)
To: intel-gfx
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 75 +++++++++++++++--------------
1 file changed, 39 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..26acc4e63a1b 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
- * Don't let the RING_HEAD advance past the breadcrumb
- * as we unwind (and until we resubmit) so that we do
- * not accidentally tell it to go backwards.
- */
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(&ve->base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
-
- /*
- * Skip if we ended up with exactly the same set of requests,
- * e.g. trying to timeslice a pair of ordered contexts
- */
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
+ *port = execlists_schedule_in(last, port - execlists->pending);
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
- goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+ /*
+ * Skip if we ended up with exactly the same set of requests,
+ * e.g. trying to timeslice a pair of ordered contexts
+ */
+ if (!memcmp(active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+ execlists_schedule_out(fetch_and_zero(port));
+ while (port-- != execlists->pending);
- execlists_submit_ports(engine);
- set_preempt_timeout(engine, *active);
- } else {
-skip_submit:
- ring_set_paused(engine, 0);
+ return false;
}
+ clear_ports(port + 1, last_port - port);
+
+ execlists_submit_ports(engine);
+ set_preempt_timeout(engine, *active);
+ tasklet_hi_schedule(&execlists->tasklet); /* lost interrupt */
+ return true;
}
static void
@@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
lockdep_assert_held(&engine->active.lock);
if (!READ_ONCE(engine->execlists.pending[0])) {
rcu_read_lock(); /* protect peeking at execlists->active */
- execlists_dequeue(engine);
+
+ /*
+ * Don't let the RING_HEAD advance past the breadcrumb
+ * as we unwind (and until we resubmit) so that we do
+ * not accidentally tell it to go backwards.
+ */
+ ring_set_paused(engine, 1);
+ if (!execlists_dequeue(engine))
+ ring_set_paused(engine, 0);
+
rcu_read_unlock();
}
}
@@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
ring_set_paused(engine, 1); /* Freeze the current request in place */
if (execlists_capture(engine))
intel_engine_reset(engine, msg);
- else
- ring_set_paused(engine, 0);
+ ring_set_paused(engine, 0);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(bit, lock);
@@ -4203,6 +4203,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
{
+ *cs++ = MI_ARB_CHECK;
+ *cs++ = MI_NOOP;
+
*cs++ = MI_SEMAPHORE_WAIT |
MI_SEMAPHORE_GLOBAL_GTT |
MI_SEMAPHORE_POLL |
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context
@ 2020-03-27 9:24 Chris Wilson
0 siblings, 0 replies; 12+ messages in thread
From: Chris Wilson @ 2020-03-27 9:24 UTC (permalink / raw)
To: intel-gfx
In what seems remarkably similar to the w/a required to not reload an
idle context with HEAD==TAIL, it appears we must prevent the HW from
switching to an idle context in ELSP[1], while simultaneously trying to
preempt the HW to run another context and a continuation of the idle
context (which is no longer idle).
process_csb: vecs0: cs-irq head=0, tail=1
process_csb: vecs0: csb[1]: status=0x00000882:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b2:32!, 8c0:30 }
trace_ports: vecs0: submit { 8b8:32, 8c0:32 }
process_csb: vecs0: cs-irq head=1, tail=2
process_csb: vecs0: csb[2]: status=0x00000814:0x00000040
trace_ports: vecs0: completed { 8b2:32!, 8c0:30 }
process_csb: vecs0: cs-irq head=2, tail=5
process_csb: vecs0: csb[3]: status=0x00000812:0x00000020
trace_ports: vecs0: preempted { 8c0:30!, 0:0 }
trace_ports: vecs0: promote { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[4]: status=0x00000814:0x00000060
trace_ports: vecs0: completed { 8b8:32!, 8c0:32 }
process_csb: vecs0: csb[5]: status=0x00000818:0x00000020
trace_ports: vecs0: completed { 8c0:32, 0:0 }
process_csb: vecs0: ring:{start:0x00021000, head:03f8, tail:03f8, ctl:00000000, mode:00000200}
process_csb: vecs0: rq:{start:00021000, head:03c0, tail:0400, seqno:8c0:32, hwsp:30},
process_csb: vecs0: ctx:{start:00021000, head:03f8, tail:03f8},
process_csb: GEM_BUG_ON("context completed before request")
Fortunately, we just so happen to have a semaphore in place to prevent
the ring HEAD from proceeding past the end of a request that we can use
to fix the HEAD in position as we reprogram ELSP.
Closes: https://gitlab.freedesktop.org/drm/intel/issues/1501
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
drivers/gpu/drm/i915/gt/intel_lrc.c | 75 +++++++++++++++--------------
1 file changed, 39 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index b12355048501..26ece9390954 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -1854,7 +1854,7 @@ static inline void clear_ports(struct i915_request **ports, int count)
memset_p((void **)ports, NULL, count);
}
-static void execlists_dequeue(struct intel_engine_cs *engine)
+static bool execlists_dequeue(struct intel_engine_cs *engine)
{
struct intel_engine_execlists * const execlists = &engine->execlists;
struct i915_request **port = execlists->pending;
@@ -1928,13 +1928,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
execlists->queue_priority_hint);
record_preemption(execlists);
- /*
- * Don't let the RING_HEAD advance past the breadcrumb
- * as we unwind (and until we resubmit) so that we do
- * not accidentally tell it to go backwards.
- */
- ring_set_paused(engine, 1);
-
/*
* Note that we have not stopped the GPU at this point,
* so we are unwinding the incomplete requests as they
@@ -1954,7 +1947,6 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
last->sched.attr.priority,
execlists->queue_priority_hint);
- ring_set_paused(engine, 1);
defer_active(engine);
/*
@@ -1988,7 +1980,7 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* of timeslices, our queue might be.
*/
start_timeslice(engine);
- return;
+ return false;
}
}
}
@@ -2021,9 +2013,10 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
}
if (last && !can_merge_rq(last, rq)) {
+ /* leave this for another sibling */
spin_unlock(&ve->base.active.lock);
start_timeslice(engine);
- return; /* leave this for another sibling */
+ return false;
}
ENGINE_TRACE(engine,
@@ -2193,32 +2186,31 @@ static void execlists_dequeue(struct intel_engine_cs *engine)
* interrupt for secondary ports).
*/
execlists->queue_priority_hint = queue_prio(execlists);
+ if (!submit)
+ return false;
- if (submit) {
- *port = execlists_schedule_in(last, port - execlists->pending);
- execlists->switch_priority_hint =
- switch_prio(engine, *execlists->pending);
-
- /*
- * Skip if we ended up with exactly the same set of requests,
- * e.g. trying to timeslice a pair of ordered contexts
- */
- if (!memcmp(active, execlists->pending,
- (port - execlists->pending + 1) * sizeof(*port))) {
- do
- execlists_schedule_out(fetch_and_zero(port));
- while (port-- != execlists->pending);
+ *port = execlists_schedule_in(last, port - execlists->pending);
+ execlists->switch_priority_hint =
+ switch_prio(engine, *execlists->pending);
- goto skip_submit;
- }
- clear_ports(port + 1, last_port - port);
+ /*
+ * Skip if we ended up with exactly the same set of requests,
+ * e.g. trying to timeslice a pair of ordered contexts
+ */
+ if (!memcmp(active, execlists->pending,
+ (port - execlists->pending + 1) * sizeof(*port))) {
+ do
+ execlists_schedule_out(fetch_and_zero(port));
+ while (port-- != execlists->pending);
- execlists_submit_ports(engine);
- set_preempt_timeout(engine, *active);
- } else {
-skip_submit:
- ring_set_paused(engine, 0);
+ return false;
}
+ clear_ports(port + 1, last_port - port);
+
+ execlists_submit_ports(engine);
+ set_preempt_timeout(engine, *active);
+ tasklet_hi_schedule(&execlists->active); /* paper over lost interrupt */
+ return true;
}
static void
@@ -2478,7 +2470,16 @@ static void __execlists_submission_tasklet(struct intel_engine_cs *const engine)
lockdep_assert_held(&engine->active.lock);
if (!READ_ONCE(engine->execlists.pending[0])) {
rcu_read_lock(); /* protect peeking at execlists->active */
- execlists_dequeue(engine);
+
+ /*
+ * Don't let the RING_HEAD advance past the breadcrumb
+ * as we unwind (and until we resubmit) so that we do
+ * not accidentally tell it to go backwards.
+ */
+ ring_set_paused(engine, 1);
+ if (!execlists_dequeue(engine))
+ ring_set_paused(engine, 0);
+
rcu_read_unlock();
}
}
@@ -2816,8 +2817,7 @@ static void execlists_reset(struct intel_engine_cs *engine, const char *msg)
ring_set_paused(engine, 1); /* Freeze the current request in place */
if (execlists_capture(engine))
intel_engine_reset(engine, msg);
- else
- ring_set_paused(engine, 0);
+ ring_set_paused(engine, 0);
tasklet_enable(&engine->execlists.tasklet);
clear_and_wake_up_bit(bit, lock);
@@ -4203,6 +4203,9 @@ static u32 *gen8_emit_wa_tail(struct i915_request *request, u32 *cs)
static u32 *emit_preempt_busywait(struct i915_request *request, u32 *cs)
{
+ *cs++ = MI_ARB_CHECK;
+ *cs++ = MI_NOOP;
+
*cs++ = MI_SEMAPHORE_WAIT |
MI_SEMAPHORE_GLOBAL_GTT |
MI_SEMAPHORE_POLL |
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2020-03-28 13:21 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-03-27 11:26 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
2020-03-27 11:47 ` [Intel-gfx] [PATCH] " Chris Wilson
2020-03-27 11:53 ` Chris Wilson
2020-03-27 12:43 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7) Patchwork
2020-03-27 13:19 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-03-27 15:59 ` [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Tvrtko Ursulin
2020-03-27 16:47 ` Chris Wilson
2020-03-27 20:19 ` Mika Kuoppala
2020-03-27 20:32 ` Chris Wilson
2020-03-28 13:21 ` [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context (rev7) Patchwork
-- strict thread matches above, loose matches on Subject: below --
2020-03-27 9:29 [Intel-gfx] [CI] drm/i915/execlists: Prevent GPU death on ELSP[1] promotion to idle context Chris Wilson
2020-03-27 9:24 Chris Wilson
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