[Intel-gfx] [PATCH v7 0/2] debugfs cleanup and gt depenencies.

[Intel-gfx] [PATCH v7 0/2] debugfs cleanup and gt depenencies.

[Andi Shyti]

From: Andi Shyti <andi.shyti@intel.com>

Hi,

In this 7th version I removed in a separate patch the sseu
interface which is broken and therefore useless.

Thanks Tvrtko and Chris for the review,
Andi

Changelog
=========
v7:
 - add a preliminary patch that removes completely the
   i915_sseu_status interface.
v6:
 - i915_forcewake_user left intact in in the top level directory
 - improved commit log
v5:
 - renamed from debugfs_gt_sseu.[ch] to debugfs_sseu.[ch]
 - moved i915_rcs_topology from i915_debugfs.c to
   gt/debugfs_sseu.c
 - added Tvrtko's and Chris r-b.
v4:
 - interrupt and sseu debugfs interface are moved to their own
   "debugfs_gt_irq" and "debugfs_gt_sseu" files
 - reset functions are renamed to reset_show/store
v3:
 - better arrangement of what should stay in i915_debugfs and
   what needs to be moved under gt/
 - more use of the local "uncore" and "i915" variables to improve
   readability
v2:
 - dropped changes on "drop_caches", they were indeed irrelevant
 - improved interrupt info function

Andi Shyti (2):
  drm/i915: remove broken i915_sseu_status interface
  drm/i915/gt: move remaining debugfs interfaces into gt

 drivers/gpu/drm/i915/Makefile            |   1 +
 drivers/gpu/drm/i915/gt/debugfs_gt.c     |  48 +++-
 drivers/gpu/drm/i915/gt/debugfs_gt_irq.c | 162 +++++++++++
 drivers/gpu/drm/i915/gt/debugfs_gt_irq.h |  15 +
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c  |  32 +++
 drivers/gpu/drm/i915/i915_debugfs.c      | 339 +----------------------
 6 files changed, 258 insertions(+), 339 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
 create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.h

-- 
2.25.1

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[Intel-gfx] [PATCH v7 1/2] drm/i915: remove broken i915_sseu_status interface

[Andi Shyti]

From: Andi Shyti <andi.shyti@intel.com>

The i915_sseu_status is broken and the tests on this interface
are disabled. There is no reason to drag it along.

Remove it!

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
---
 drivers/gpu/drm/i915/i915_debugfs.c | 257 ----------------------------
 1 file changed, 257 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b22b4e9c3138..4552b958f352 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1558,266 +1558,10 @@ i915_cache_sharing_set(void *data, u64 val)
 	return 0;
 }
 
-static void
-intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
-			  u8 *to_mask)
-{
-	int offset = slice * sseu->ss_stride;
-
-	memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
-}
-
 DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
 			i915_cache_sharing_get, i915_cache_sharing_set,
 			"%llu\n");
 
-static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
-					  struct sseu_dev_info *sseu)
-{
-#define SS_MAX 2
-	const int ss_max = SS_MAX;
-	u32 sig1[SS_MAX], sig2[SS_MAX];
-	int ss;
-
-	sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
-	sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
-	sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
-	sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
-
-	for (ss = 0; ss < ss_max; ss++) {
-		unsigned int eu_cnt;
-
-		if (sig1[ss] & CHV_SS_PG_ENABLE)
-			/* skip disabled subslice */
-			continue;
-
-		sseu->slice_mask = BIT(0);
-		sseu->subslice_mask[0] |= BIT(ss);
-		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
-			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
-			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
-			 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
-		sseu->eu_total += eu_cnt;
-		sseu->eu_per_subslice = max_t(unsigned int,
-					      sseu->eu_per_subslice, eu_cnt);
-	}
-#undef SS_MAX
-}
-
-static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
-				     struct sseu_dev_info *sseu)
-{
-#define SS_MAX 6
-	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
-	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
-	int s, ss;
-
-	for (s = 0; s < info->sseu.max_slices; s++) {
-		/*
-		 * FIXME: Valid SS Mask respects the spec and read
-		 * only valid bits for those registers, excluding reserved
-		 * although this seems wrong because it would leave many
-		 * subslices without ACK.
-		 */
-		s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
-			GEN10_PGCTL_VALID_SS_MASK(s);
-		eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
-		eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
-	}
-
-	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
-		     GEN9_PGCTL_SSA_EU19_ACK |
-		     GEN9_PGCTL_SSA_EU210_ACK |
-		     GEN9_PGCTL_SSA_EU311_ACK;
-	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
-		     GEN9_PGCTL_SSB_EU19_ACK |
-		     GEN9_PGCTL_SSB_EU210_ACK |
-		     GEN9_PGCTL_SSB_EU311_ACK;
-
-	for (s = 0; s < info->sseu.max_slices; s++) {
-		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
-			/* skip disabled slice */
-			continue;
-
-		sseu->slice_mask |= BIT(s);
-		intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
-
-		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
-			unsigned int eu_cnt;
-
-			if (info->sseu.has_subslice_pg &&
-			    !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
-				/* skip disabled subslice */
-				continue;
-
-			eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
-					       eu_mask[ss % 2]);
-			sseu->eu_total += eu_cnt;
-			sseu->eu_per_subslice = max_t(unsigned int,
-						      sseu->eu_per_subslice,
-						      eu_cnt);
-		}
-	}
-#undef SS_MAX
-}
-
-static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
-				    struct sseu_dev_info *sseu)
-{
-#define SS_MAX 3
-	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
-	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
-	int s, ss;
-
-	for (s = 0; s < info->sseu.max_slices; s++) {
-		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
-		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
-		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
-	}
-
-	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
-		     GEN9_PGCTL_SSA_EU19_ACK |
-		     GEN9_PGCTL_SSA_EU210_ACK |
-		     GEN9_PGCTL_SSA_EU311_ACK;
-	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
-		     GEN9_PGCTL_SSB_EU19_ACK |
-		     GEN9_PGCTL_SSB_EU210_ACK |
-		     GEN9_PGCTL_SSB_EU311_ACK;
-
-	for (s = 0; s < info->sseu.max_slices; s++) {
-		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
-			/* skip disabled slice */
-			continue;
-
-		sseu->slice_mask |= BIT(s);
-
-		if (IS_GEN9_BC(dev_priv))
-			intel_sseu_copy_subslices(&info->sseu, s,
-						  sseu->subslice_mask);
-
-		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
-			unsigned int eu_cnt;
-			u8 ss_idx = s * info->sseu.ss_stride +
-				    ss / BITS_PER_BYTE;
-
-			if (IS_GEN9_LP(dev_priv)) {
-				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
-					/* skip disabled subslice */
-					continue;
-
-				sseu->subslice_mask[ss_idx] |=
-					BIT(ss % BITS_PER_BYTE);
-			}
-
-			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
-					       eu_mask[ss%2]);
-			sseu->eu_total += eu_cnt;
-			sseu->eu_per_subslice = max_t(unsigned int,
-						      sseu->eu_per_subslice,
-						      eu_cnt);
-		}
-	}
-#undef SS_MAX
-}
-
-static void bdw_sseu_device_status(struct drm_i915_private *dev_priv,
-				   struct sseu_dev_info *sseu)
-{
-	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
-	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
-	int s;
-
-	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
-
-	if (sseu->slice_mask) {
-		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
-		for (s = 0; s < fls(sseu->slice_mask); s++)
-			intel_sseu_copy_subslices(&info->sseu, s,
-						  sseu->subslice_mask);
-		sseu->eu_total = sseu->eu_per_subslice *
-				 intel_sseu_subslice_total(sseu);
-
-		/* subtract fused off EU(s) from enabled slice(s) */
-		for (s = 0; s < fls(sseu->slice_mask); s++) {
-			u8 subslice_7eu = info->sseu.subslice_7eu[s];
-
-			sseu->eu_total -= hweight8(subslice_7eu);
-		}
-	}
-}
-
-static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
-				 const struct sseu_dev_info *sseu)
-{
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	const char *type = is_available_info ? "Available" : "Enabled";
-	int s;
-
-	seq_printf(m, "  %s Slice Mask: %04x\n", type,
-		   sseu->slice_mask);
-	seq_printf(m, "  %s Slice Total: %u\n", type,
-		   hweight8(sseu->slice_mask));
-	seq_printf(m, "  %s Subslice Total: %u\n", type,
-		   intel_sseu_subslice_total(sseu));
-	for (s = 0; s < fls(sseu->slice_mask); s++) {
-		seq_printf(m, "  %s Slice%i subslices: %u\n", type,
-			   s, intel_sseu_subslices_per_slice(sseu, s));
-	}
-	seq_printf(m, "  %s EU Total: %u\n", type,
-		   sseu->eu_total);
-	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
-		   sseu->eu_per_subslice);
-
-	if (!is_available_info)
-		return;
-
-	seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
-	if (HAS_POOLED_EU(dev_priv))
-		seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
-
-	seq_printf(m, "  Has Slice Power Gating: %s\n",
-		   yesno(sseu->has_slice_pg));
-	seq_printf(m, "  Has Subslice Power Gating: %s\n",
-		   yesno(sseu->has_subslice_pg));
-	seq_printf(m, "  Has EU Power Gating: %s\n",
-		   yesno(sseu->has_eu_pg));
-}
-
-static int i915_sseu_status(struct seq_file *m, void *unused)
-{
-	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
-	struct sseu_dev_info sseu;
-	intel_wakeref_t wakeref;
-
-	if (INTEL_GEN(dev_priv) < 8)
-		return -ENODEV;
-
-	seq_puts(m, "SSEU Device Info\n");
-	i915_print_sseu_info(m, true, &info->sseu);
-
-	seq_puts(m, "SSEU Device Status\n");
-	memset(&sseu, 0, sizeof(sseu));
-	intel_sseu_set_info(&sseu, info->sseu.max_slices,
-			    info->sseu.max_subslices,
-			    info->sseu.max_eus_per_subslice);
-
-	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
-		if (IS_CHERRYVIEW(dev_priv))
-			cherryview_sseu_device_status(dev_priv, &sseu);
-		else if (IS_BROADWELL(dev_priv))
-			bdw_sseu_device_status(dev_priv, &sseu);
-		else if (IS_GEN(dev_priv, 9))
-			gen9_sseu_device_status(dev_priv, &sseu);
-		else if (INTEL_GEN(dev_priv) >= 10)
-			gen10_sseu_device_status(dev_priv, &sseu);
-	}
-
-	i915_print_sseu_info(m, false, &sseu);
-
-	return 0;
-}
-
 static int i915_forcewake_open(struct inode *inode, struct file *file)
 {
 	struct drm_i915_private *i915 = inode->i_private;
@@ -1865,7 +1609,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
 	{"i915_rcs_topology", i915_rcs_topology, 0},
 	{"i915_shrinker_info", i915_shrinker_info, 0},
 	{"i915_wa_registers", i915_wa_registers, 0},
-	{"i915_sseu_status", i915_sseu_status, 0},
 	{"i915_rps_boost_info", i915_rps_boost_info, 0},
 };
 #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
-- 
2.25.1

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[Intel-gfx] [PATCH v7 2/2] drm/i915/gt: move remaining debugfs interfaces into gt

[Andi Shyti]

From: Andi Shyti <andi.shyti@intel.com>

The following interfaces:

  i915_wedged
  i915_forcewake_user
  i915_gem_interrupt
  i915_rcs_topology
  i915_sseu_status

are dependent on gt values. Put them inside gt/ and drop the
"i915_" prefix name. This would be the new structure:

  dri/0/gt
  |
  +-- forcewake_user
  |
  +-- interrupt_info
  |
  \-- reset

For backwards compatibility with existing igt (and the slight
semantic difference between operating on the i915 abi entry
points and the deep gt info):

  dri/0
  |
  +-- i915_wedged
  |
  \-- i915_forcewake_user

remain at the top level.

Signed-off-by: Andi Shyti <andi.shyti@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/Makefile            |   1 +
 drivers/gpu/drm/i915/gt/debugfs_gt.c     |  48 ++++++-
 drivers/gpu/drm/i915/gt/debugfs_gt_irq.c | 162 +++++++++++++++++++++++
 drivers/gpu/drm/i915/gt/debugfs_gt_irq.h |  15 +++
 drivers/gpu/drm/i915/gt/debugfs_gt_pm.c  |  32 +++++
 drivers/gpu/drm/i915/i915_debugfs.c      |  82 +-----------
 6 files changed, 258 insertions(+), 82 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
 create mode 100644 drivers/gpu/drm/i915/gt/debugfs_gt_irq.h

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 2fce8b0040f3..6962c981dd54 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -79,6 +79,7 @@ gt-y += \
 	gt/debugfs_engines.o \
 	gt/debugfs_gt.o \
 	gt/debugfs_gt_pm.o \
+	gt/debugfs_gt_irq.o \
 	gt/gen6_ppgtt.o \
 	gt/gen7_renderclear.o \
 	gt/gen8_ppgtt.o \
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt.c b/drivers/gpu/drm/i915/gt/debugfs_gt.c
index 1de5fbaa1cf9..91ae6d47141b 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt.c
@@ -8,9 +8,52 @@
 
 #include "debugfs_engines.h"
 #include "debugfs_gt.h"
+#include "debugfs_gt_irq.h"
 #include "debugfs_gt_pm.h"
-#include "uc/intel_uc_debugfs.h"
 #include "i915_drv.h"
+#include "intel_gt_pm.h"
+#include "intel_gt_requests.h"
+#include "uc/intel_uc_debugfs.h"
+
+static int reset_show(void *data, u64 *val)
+{
+	struct intel_gt *gt = data;
+	int ret = intel_gt_terminally_wedged(gt);
+
+	switch (ret) {
+	case -EIO:
+		*val = 1;
+		return 0;
+	case 0:
+		*val = 0;
+		return 0;
+	default:
+		return ret;
+	}
+}
+
+static int reset_store(void *data, u64 val)
+{
+	struct intel_gt *gt = data;
+
+	/* Flush any previous reset before applying for a new one */
+	wait_event(gt->reset.queue,
+		   !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
+
+	intel_gt_handle_error(gt, val, I915_ERROR_CAPTURE,
+			      "Manually reset engine mask to %llx", val);
+	return 0;
+}
+DEFINE_SIMPLE_ATTRIBUTE(reset_fops, reset_show, reset_store, "%llu\n");
+
+static void __debugfs_gt_register(struct intel_gt *gt, struct dentry *root)
+{
+	static const struct debugfs_gt_file files[] = {
+		{ "reset", &reset_fops, NULL },
+	};
+
+	intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
 
 void debugfs_gt_register(struct intel_gt *gt)
 {
@@ -23,8 +66,11 @@ void debugfs_gt_register(struct intel_gt *gt)
 	if (IS_ERR(root))
 		return;
 
+	__debugfs_gt_register(gt, root);
+
 	debugfs_engines_register(gt, root);
 	debugfs_gt_pm_register(gt, root);
+	debugfs_gt_register_irq(gt, root);
 
 	intel_uc_debugfs_register(&gt->uc, root);
 }
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
new file mode 100644
index 000000000000..8aaf76dfc573
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.c
@@ -0,0 +1,162 @@
+// SPDX-License-Identifier: MIT
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#include "debugfs_gt.h"
+#include "debugfs_gt_irq.h"
+#include "i915_drv.h"
+
+static int interrupt_info_show(struct seq_file *m, void *data)
+{
+	struct intel_gt *gt = m->private;
+	struct drm_i915_private *i915 = gt->i915;
+	struct intel_uncore *uncore = gt->uncore;
+	struct intel_engine_cs *engine;
+	enum intel_engine_id id;
+	intel_wakeref_t wakeref;
+	int i;
+
+	wakeref = intel_runtime_pm_get(uncore->rpm);
+
+	if (IS_CHERRYVIEW(i915)) {
+		seq_printf(m, "Master Interrupt Control:\t%08x\n",
+			   intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+		for (i = 0; i < 4; i++) {
+			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+				   i, intel_uncore_read(uncore,
+							GEN8_GT_IMR(i)));
+			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+				   i, intel_uncore_read(uncore,
+							GEN8_GT_IIR(i)));
+			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+				   i, intel_uncore_read(uncore,
+							GEN8_GT_IER(i)));
+		}
+
+	} else if (INTEL_GEN(i915) >= 11) {
+		seq_printf(m, "Master Interrupt Control:  %08x\n",
+			   intel_uncore_read(uncore, GEN11_GFX_MSTR_IRQ));
+
+		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_RENDER_COPY_INTR_ENABLE));
+		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_VCS_VECS_INTR_ENABLE));
+		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_GUC_SG_INTR_ENABLE));
+		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_GPM_WGBOXPERF_INTR_ENABLE));
+		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_CRYPTO_RSVD_INTR_ENABLE));
+		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_GUNIT_CSME_INTR_ENABLE));
+
+	} else if (INTEL_GEN(i915) >= 8) {
+		seq_printf(m, "Master Interrupt Control:\t%08x\n",
+			   intel_uncore_read(uncore, GEN8_MASTER_IRQ));
+
+		for (i = 0; i < 4; i++) {
+			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
+				   i, intel_uncore_read(uncore,
+							GEN8_GT_IMR(i)));
+			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
+				   i, intel_uncore_read(uncore,
+							GEN8_GT_IIR(i)));
+			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
+				   i, intel_uncore_read(uncore,
+							GEN8_GT_IER(i)));
+		}
+
+	} else if (IS_VALLEYVIEW(i915)) {
+		seq_printf(m, "Master IER:\t%08x\n",
+			   intel_uncore_read(uncore, VLV_MASTER_IER));
+
+		seq_printf(m, "Render IER:\t%08x\n",
+			   intel_uncore_read(uncore, GTIER));
+		seq_printf(m, "Render IIR:\t%08x\n",
+			   intel_uncore_read(uncore, GTIIR));
+		seq_printf(m, "Render IMR:\t%08x\n",
+			   intel_uncore_read(uncore, GTIMR));
+
+		seq_printf(m, "PM IER:\t\t%08x\n",
+			   intel_uncore_read(uncore, GEN6_PMIER));
+		seq_printf(m, "PM IIR:\t\t%08x\n",
+			   intel_uncore_read(uncore, GEN6_PMIIR));
+		seq_printf(m, "PM IMR:\t\t%08x\n",
+			   intel_uncore_read(uncore, GEN6_PMIMR));
+
+	} else if (!HAS_PCH_SPLIT(i915)) {
+		seq_printf(m, "Interrupt enable:    %08x\n",
+			   intel_uncore_read(uncore, GEN2_IER));
+		seq_printf(m, "Interrupt identity:  %08x\n",
+			   intel_uncore_read(uncore, GEN2_IIR));
+		seq_printf(m, "Interrupt mask:      %08x\n",
+			   intel_uncore_read(uncore, GEN2_IMR));
+	} else {
+		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
+			   intel_uncore_read(uncore, GTIER));
+		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
+			   intel_uncore_read(uncore, GTIIR));
+		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
+			   intel_uncore_read(uncore, GTIMR));
+	}
+
+	if (INTEL_GEN(i915) >= 11) {
+		seq_printf(m, "RCS Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_RCS0_RSVD_INTR_MASK));
+		seq_printf(m, "BCS Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_BCS_RSVD_INTR_MASK));
+		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_VCS0_VCS1_INTR_MASK));
+		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_VCS2_VCS3_INTR_MASK));
+		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_VECS0_VECS1_INTR_MASK));
+		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_GUC_SG_INTR_MASK));
+		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_GPM_WGBOXPERF_INTR_MASK));
+		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_CRYPTO_RSVD_INTR_MASK));
+		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
+			   intel_uncore_read(uncore,
+					     GEN11_GUNIT_CSME_INTR_MASK));
+
+	} else if (INTEL_GEN(i915) >= 6) {
+		for_each_engine(engine, gt, id) {
+			seq_printf(m,
+				   "Graphics Interrupt mask (%s):	%08x\n",
+				   engine->name, ENGINE_READ(engine, RING_IMR));
+		}
+	}
+
+	intel_runtime_pm_put(uncore->rpm, wakeref);
+
+	return 0;
+}
+DEFINE_GT_DEBUGFS_ATTRIBUTE(interrupt_info);
+
+void debugfs_gt_register_irq(struct intel_gt *gt, struct dentry *root)
+{
+	static const struct debugfs_gt_file files[] = {
+		{ "interrupt_info", &interrupt_info_fops, NULL },
+	};
+
+	intel_gt_debugfs_register_files(root, files, ARRAY_SIZE(files), gt);
+}
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_irq.h b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.h
new file mode 100644
index 000000000000..f3d601b3d019
--- /dev/null
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_irq.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: MIT */
+
+/*
+ * Copyright © 2020 Intel Corporation
+ */
+
+#ifndef DEBUGFS_GT_IRQ_H
+#define DEBUGFS_GT_IRQ_H
+
+struct intel_gt;
+struct dentry;
+
+void debugfs_gt_register_irq(struct intel_gt *gt, struct dentry *root);
+
+#endif /* DEBUGFS_GT_IRQ_H */
diff --git a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
index aab30d908072..c94a946e0adb 100644
--- a/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/debugfs_gt_pm.c
@@ -10,6 +10,7 @@
 #include "debugfs_gt_pm.h"
 #include "i915_drv.h"
 #include "intel_gt.h"
+#include "intel_gt_pm.h"
 #include "intel_llc.h"
 #include "intel_rc6.h"
 #include "intel_rps.h"
@@ -17,6 +18,36 @@
 #include "intel_sideband.h"
 #include "intel_uncore.h"
 
+static int forcewake_user_open(struct inode *inode, struct file *file)
+{
+	struct intel_gt *gt = inode->i_private;
+
+	atomic_inc(&gt->user_wakeref);
+	intel_gt_pm_get(gt);
+	if (INTEL_GEN(gt->i915) >= 6)
+		intel_uncore_forcewake_user_get(gt->uncore);
+
+	return 0;
+}
+
+static int forcewake_user_release(struct inode *inode, struct file *file)
+{
+	struct intel_gt *gt = inode->i_private;
+
+	if (INTEL_GEN(gt->i915) >= 6)
+		intel_uncore_forcewake_user_put(gt->uncore);
+	intel_gt_pm_put(gt);
+	atomic_dec(&gt->user_wakeref);
+
+	return 0;
+}
+
+static const struct file_operations forcewake_user_fops = {
+	.owner = THIS_MODULE,
+	.open = forcewake_user_open,
+	.release = forcewake_user_release,
+};
+
 static int fw_domains_show(struct seq_file *m, void *data)
 {
 	struct intel_gt *gt = m->private;
@@ -597,6 +628,7 @@ void debugfs_gt_pm_register(struct intel_gt *gt, struct dentry *root)
 		{ "drpc", &drpc_fops, NULL },
 		{ "frequency", &frequency_fops, NULL },
 		{ "forcewake", &fw_domains_fops, NULL },
+		{ "forcewake_user", &forcewake_user_fops, NULL},
 		{ "llc", &llc_fops, llc_eval },
 		{ "rps_boost", &rps_boost_fops, rps_eval },
 	};
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 4552b958f352..d05de62b4729 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -426,9 +426,8 @@ static void gen8_display_interrupt_info(struct seq_file *m)
 static int i915_interrupt_info(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
-	struct intel_engine_cs *engine;
 	intel_wakeref_t wakeref;
-	int i, pipe;
+	int pipe;
 
 	wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
 
@@ -474,15 +473,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 			   I915_READ(DPINVGTT));
 		intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, pref);
 
-		for (i = 0; i < 4; i++) {
-			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IMR(i)));
-			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IIR(i)));
-			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IER(i)));
-		}
-
 		seq_printf(m, "PCU interrupt mask:\t%08x\n",
 			   I915_READ(GEN8_PCU_IMR));
 		seq_printf(m, "PCU interrupt identity:\t%08x\n",
@@ -493,19 +483,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Master Interrupt Control:  %08x\n",
 			   I915_READ(GEN11_GFX_MSTR_IRQ));
 
-		seq_printf(m, "Render/Copy Intr Enable:   %08x\n",
-			   I915_READ(GEN11_RENDER_COPY_INTR_ENABLE));
-		seq_printf(m, "VCS/VECS Intr Enable:      %08x\n",
-			   I915_READ(GEN11_VCS_VECS_INTR_ENABLE));
-		seq_printf(m, "GUC/SG Intr Enable:\t   %08x\n",
-			   I915_READ(GEN11_GUC_SG_INTR_ENABLE));
-		seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n",
-			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE));
-		seq_printf(m, "Crypto Intr Enable:\t   %08x\n",
-			   I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE));
-		seq_printf(m, "GUnit/CSME Intr Enable:\t   %08x\n",
-			   I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE));
-
 		seq_printf(m, "Display Interrupt Control:\t%08x\n",
 			   I915_READ(GEN11_DISPLAY_INT_CTL));
 
@@ -514,15 +491,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Master Interrupt Control:\t%08x\n",
 			   I915_READ(GEN8_MASTER_IRQ));
 
-		for (i = 0; i < 4; i++) {
-			seq_printf(m, "GT Interrupt IMR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IMR(i)));
-			seq_printf(m, "GT Interrupt IIR %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IIR(i)));
-			seq_printf(m, "GT Interrupt IER %d:\t%08x\n",
-				   i, I915_READ(GEN8_GT_IER(i)));
-		}
-
 		gen8_display_interrupt_info(m);
 	} else if (IS_VALLEYVIEW(dev_priv)) {
 		intel_wakeref_t pref;
@@ -556,20 +524,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 		seq_printf(m, "Master IER:\t%08x\n",
 			   I915_READ(VLV_MASTER_IER));
 
-		seq_printf(m, "Render IER:\t%08x\n",
-			   I915_READ(GTIER));
-		seq_printf(m, "Render IIR:\t%08x\n",
-			   I915_READ(GTIIR));
-		seq_printf(m, "Render IMR:\t%08x\n",
-			   I915_READ(GTIMR));
-
-		seq_printf(m, "PM IER:\t\t%08x\n",
-			   I915_READ(GEN6_PMIER));
-		seq_printf(m, "PM IIR:\t\t%08x\n",
-			   I915_READ(GEN6_PMIIR));
-		seq_printf(m, "PM IMR:\t\t%08x\n",
-			   I915_READ(GEN6_PMIMR));
-
 		pref = intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 		seq_printf(m, "Port hotplug:\t%08x\n",
 			   I915_READ(PORT_HOTPLUG_EN));
@@ -603,40 +557,6 @@ static int i915_interrupt_info(struct seq_file *m, void *data)
 			   I915_READ(SDEIIR));
 		seq_printf(m, "South Display Interrupt mask:		%08x\n",
 			   I915_READ(SDEIMR));
-		seq_printf(m, "Graphics Interrupt enable:		%08x\n",
-			   I915_READ(GTIER));
-		seq_printf(m, "Graphics Interrupt identity:		%08x\n",
-			   I915_READ(GTIIR));
-		seq_printf(m, "Graphics Interrupt mask:		%08x\n",
-			   I915_READ(GTIMR));
-	}
-
-	if (INTEL_GEN(dev_priv) >= 11) {
-		seq_printf(m, "RCS Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_RCS0_RSVD_INTR_MASK));
-		seq_printf(m, "BCS Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_BCS_RSVD_INTR_MASK));
-		seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_VCS0_VCS1_INTR_MASK));
-		seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_VCS2_VCS3_INTR_MASK));
-		seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_VECS0_VECS1_INTR_MASK));
-		seq_printf(m, "GUC/SG Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_GUC_SG_INTR_MASK));
-		seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n",
-			   I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK));
-		seq_printf(m, "Crypto Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK));
-		seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n",
-			   I915_READ(GEN11_GUNIT_CSME_INTR_MASK));
-
-	} else if (INTEL_GEN(dev_priv) >= 6) {
-		for_each_uabi_engine(engine, dev_priv) {
-			seq_printf(m,
-				   "Graphics Interrupt mask (%s):	%08x\n",
-				   engine->name, ENGINE_READ(engine, RING_IMR));
-		}
 	}
 
 	intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
-- 
2.25.1

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[Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for debugfs cleanup and gt depenencies.

[Patchwork]

== Series Details ==

Series: debugfs cleanup and gt depenencies.
URL   : https://patchwork.freedesktop.org/series/75635/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
95bc256f9b08 drm/i915: remove broken i915_sseu_status interface
1e192f84ccd9 drm/i915/gt: move remaining debugfs interfaces into gt
-:124: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#124: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 417 lines checked

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[Intel-gfx] ✓ Fi.CI.BAT: success for debugfs cleanup and gt depenencies.

[Patchwork]

== Series Details ==

Series: debugfs cleanup and gt depenencies.
URL   : https://patchwork.freedesktop.org/series/75635/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8269 -> Patchwork_17243
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/index.html

Known issues
------------

  Here are the changes found in Patchwork_17243 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_chamelium@dp-edid-read:
    - fi-cml-u2:          [PASS][1] -> [FAIL][2] ([i915#976])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [DMESG-WARN][3] ([i915#203]) -> [PASS][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence:
    - fi-skl-6770hq:      [SKIP][5] ([fdo#109271]) -> [PASS][6] +5 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-a-frame-sequence.html

  * igt@kms_pipe_crc_basic@read-crc-pipe-b:
    - fi-skl-6770hq:      [DMESG-WARN][7] ([i915#106]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-skl-6770hq/igt@kms_pipe_crc_basic@read-crc-pipe-b.html

  
#### Warnings ####

  * igt@i915_pm_rpm@module-reload:
    - fi-kbl-x1275:       [DMESG-FAIL][9] ([i915#62] / [i915#95]) -> [SKIP][10] ([fdo#109271])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-kbl-x1275/igt@i915_pm_rpm@module-reload.html

  * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
    - fi-kbl-x1275:       [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +9 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html

  * igt@kms_cursor_legacy@basic-flip-after-cursor-atomic:
    - fi-kbl-x1275:       [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +1 similar issue
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/fi-kbl-x1275/igt@kms_cursor_legacy@basic-flip-after-cursor-atomic.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#106]: https://gitlab.freedesktop.org/drm/intel/issues/106
  [i915#203]: https://gitlab.freedesktop.org/drm/intel/issues/203
  [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
  [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
  [i915#976]: https://gitlab.freedesktop.org/drm/intel/issues/976


Participating hosts (53 -> 47)
------------------------------

  Additional (1): fi-kbl-r 
  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8269 -> Patchwork_17243

  CI-20190529: 20190529
  CI_DRM_8269: 301d0427e2e3108839bf6c36f58dd0b2b5258c25 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5577: 7ee7e86fd79e4dbb6300ef4c23e50cb699216ae2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17243: 1e192f84ccd90d30a5fe711ba72a3e9693f72519 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1e192f84ccd9 drm/i915/gt: move remaining debugfs interfaces into gt
95bc256f9b08 drm/i915: remove broken i915_sseu_status interface

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/index.html
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Re: [Intel-gfx] [PATCH v7 1/2] drm/i915: remove broken i915_sseu_status interface

[Tvrtko Ursulin]

On 07/04/2020 22:45, Andi Shyti wrote:
> From: Andi Shyti <andi.shyti@intel.com>
> 
> The i915_sseu_status is broken and the tests on this interface
> are disabled. There is no reason to drag it along.

Not saying we need it, but can you say how it is broken?

Regards,

Tvrtko

> Remove it!
> 
> Signed-off-by: Andi Shyti <andi.shyti@intel.com>
> ---
>   drivers/gpu/drm/i915/i915_debugfs.c | 257 ----------------------------
>   1 file changed, 257 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index b22b4e9c3138..4552b958f352 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1558,266 +1558,10 @@ i915_cache_sharing_set(void *data, u64 val)
>   	return 0;
>   }
>   
> -static void
> -intel_sseu_copy_subslices(const struct sseu_dev_info *sseu, int slice,
> -			  u8 *to_mask)
> -{
> -	int offset = slice * sseu->ss_stride;
> -
> -	memcpy(&to_mask[offset], &sseu->subslice_mask[offset], sseu->ss_stride);
> -}
> -
>   DEFINE_SIMPLE_ATTRIBUTE(i915_cache_sharing_fops,
>   			i915_cache_sharing_get, i915_cache_sharing_set,
>   			"%llu\n");
>   
> -static void cherryview_sseu_device_status(struct drm_i915_private *dev_priv,
> -					  struct sseu_dev_info *sseu)
> -{
> -#define SS_MAX 2
> -	const int ss_max = SS_MAX;
> -	u32 sig1[SS_MAX], sig2[SS_MAX];
> -	int ss;
> -
> -	sig1[0] = I915_READ(CHV_POWER_SS0_SIG1);
> -	sig1[1] = I915_READ(CHV_POWER_SS1_SIG1);
> -	sig2[0] = I915_READ(CHV_POWER_SS0_SIG2);
> -	sig2[1] = I915_READ(CHV_POWER_SS1_SIG2);
> -
> -	for (ss = 0; ss < ss_max; ss++) {
> -		unsigned int eu_cnt;
> -
> -		if (sig1[ss] & CHV_SS_PG_ENABLE)
> -			/* skip disabled subslice */
> -			continue;
> -
> -		sseu->slice_mask = BIT(0);
> -		sseu->subslice_mask[0] |= BIT(ss);
> -		eu_cnt = ((sig1[ss] & CHV_EU08_PG_ENABLE) ? 0 : 2) +
> -			 ((sig1[ss] & CHV_EU19_PG_ENABLE) ? 0 : 2) +
> -			 ((sig1[ss] & CHV_EU210_PG_ENABLE) ? 0 : 2) +
> -			 ((sig2[ss] & CHV_EU311_PG_ENABLE) ? 0 : 2);
> -		sseu->eu_total += eu_cnt;
> -		sseu->eu_per_subslice = max_t(unsigned int,
> -					      sseu->eu_per_subslice, eu_cnt);
> -	}
> -#undef SS_MAX
> -}
> -
> -static void gen10_sseu_device_status(struct drm_i915_private *dev_priv,
> -				     struct sseu_dev_info *sseu)
> -{
> -#define SS_MAX 6
> -	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> -	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
> -	int s, ss;
> -
> -	for (s = 0; s < info->sseu.max_slices; s++) {
> -		/*
> -		 * FIXME: Valid SS Mask respects the spec and read
> -		 * only valid bits for those registers, excluding reserved
> -		 * although this seems wrong because it would leave many
> -		 * subslices without ACK.
> -		 */
> -		s_reg[s] = I915_READ(GEN10_SLICE_PGCTL_ACK(s)) &
> -			GEN10_PGCTL_VALID_SS_MASK(s);
> -		eu_reg[2 * s] = I915_READ(GEN10_SS01_EU_PGCTL_ACK(s));
> -		eu_reg[2 * s + 1] = I915_READ(GEN10_SS23_EU_PGCTL_ACK(s));
> -	}
> -
> -	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> -		     GEN9_PGCTL_SSA_EU19_ACK |
> -		     GEN9_PGCTL_SSA_EU210_ACK |
> -		     GEN9_PGCTL_SSA_EU311_ACK;
> -	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> -		     GEN9_PGCTL_SSB_EU19_ACK |
> -		     GEN9_PGCTL_SSB_EU210_ACK |
> -		     GEN9_PGCTL_SSB_EU311_ACK;
> -
> -	for (s = 0; s < info->sseu.max_slices; s++) {
> -		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> -			/* skip disabled slice */
> -			continue;
> -
> -		sseu->slice_mask |= BIT(s);
> -		intel_sseu_copy_subslices(&info->sseu, s, sseu->subslice_mask);
> -
> -		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> -			unsigned int eu_cnt;
> -
> -			if (info->sseu.has_subslice_pg &&
> -			    !(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> -				/* skip disabled subslice */
> -				continue;
> -
> -			eu_cnt = 2 * hweight32(eu_reg[2 * s + ss / 2] &
> -					       eu_mask[ss % 2]);
> -			sseu->eu_total += eu_cnt;
> -			sseu->eu_per_subslice = max_t(unsigned int,
> -						      sseu->eu_per_subslice,
> -						      eu_cnt);
> -		}
> -	}
> -#undef SS_MAX
> -}
> -
> -static void gen9_sseu_device_status(struct drm_i915_private *dev_priv,
> -				    struct sseu_dev_info *sseu)
> -{
> -#define SS_MAX 3
> -	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> -	u32 s_reg[SS_MAX], eu_reg[2 * SS_MAX], eu_mask[2];
> -	int s, ss;
> -
> -	for (s = 0; s < info->sseu.max_slices; s++) {
> -		s_reg[s] = I915_READ(GEN9_SLICE_PGCTL_ACK(s));
> -		eu_reg[2*s] = I915_READ(GEN9_SS01_EU_PGCTL_ACK(s));
> -		eu_reg[2*s + 1] = I915_READ(GEN9_SS23_EU_PGCTL_ACK(s));
> -	}
> -
> -	eu_mask[0] = GEN9_PGCTL_SSA_EU08_ACK |
> -		     GEN9_PGCTL_SSA_EU19_ACK |
> -		     GEN9_PGCTL_SSA_EU210_ACK |
> -		     GEN9_PGCTL_SSA_EU311_ACK;
> -	eu_mask[1] = GEN9_PGCTL_SSB_EU08_ACK |
> -		     GEN9_PGCTL_SSB_EU19_ACK |
> -		     GEN9_PGCTL_SSB_EU210_ACK |
> -		     GEN9_PGCTL_SSB_EU311_ACK;
> -
> -	for (s = 0; s < info->sseu.max_slices; s++) {
> -		if ((s_reg[s] & GEN9_PGCTL_SLICE_ACK) == 0)
> -			/* skip disabled slice */
> -			continue;
> -
> -		sseu->slice_mask |= BIT(s);
> -
> -		if (IS_GEN9_BC(dev_priv))
> -			intel_sseu_copy_subslices(&info->sseu, s,
> -						  sseu->subslice_mask);
> -
> -		for (ss = 0; ss < info->sseu.max_subslices; ss++) {
> -			unsigned int eu_cnt;
> -			u8 ss_idx = s * info->sseu.ss_stride +
> -				    ss / BITS_PER_BYTE;
> -
> -			if (IS_GEN9_LP(dev_priv)) {
> -				if (!(s_reg[s] & (GEN9_PGCTL_SS_ACK(ss))))
> -					/* skip disabled subslice */
> -					continue;
> -
> -				sseu->subslice_mask[ss_idx] |=
> -					BIT(ss % BITS_PER_BYTE);
> -			}
> -
> -			eu_cnt = 2 * hweight32(eu_reg[2*s + ss/2] &
> -					       eu_mask[ss%2]);
> -			sseu->eu_total += eu_cnt;
> -			sseu->eu_per_subslice = max_t(unsigned int,
> -						      sseu->eu_per_subslice,
> -						      eu_cnt);
> -		}
> -	}
> -#undef SS_MAX
> -}
> -
> -static void bdw_sseu_device_status(struct drm_i915_private *dev_priv,
> -				   struct sseu_dev_info *sseu)
> -{
> -	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> -	u32 slice_info = I915_READ(GEN8_GT_SLICE_INFO);
> -	int s;
> -
> -	sseu->slice_mask = slice_info & GEN8_LSLICESTAT_MASK;
> -
> -	if (sseu->slice_mask) {
> -		sseu->eu_per_subslice = info->sseu.eu_per_subslice;
> -		for (s = 0; s < fls(sseu->slice_mask); s++)
> -			intel_sseu_copy_subslices(&info->sseu, s,
> -						  sseu->subslice_mask);
> -		sseu->eu_total = sseu->eu_per_subslice *
> -				 intel_sseu_subslice_total(sseu);
> -
> -		/* subtract fused off EU(s) from enabled slice(s) */
> -		for (s = 0; s < fls(sseu->slice_mask); s++) {
> -			u8 subslice_7eu = info->sseu.subslice_7eu[s];
> -
> -			sseu->eu_total -= hweight8(subslice_7eu);
> -		}
> -	}
> -}
> -
> -static void i915_print_sseu_info(struct seq_file *m, bool is_available_info,
> -				 const struct sseu_dev_info *sseu)
> -{
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	const char *type = is_available_info ? "Available" : "Enabled";
> -	int s;
> -
> -	seq_printf(m, "  %s Slice Mask: %04x\n", type,
> -		   sseu->slice_mask);
> -	seq_printf(m, "  %s Slice Total: %u\n", type,
> -		   hweight8(sseu->slice_mask));
> -	seq_printf(m, "  %s Subslice Total: %u\n", type,
> -		   intel_sseu_subslice_total(sseu));
> -	for (s = 0; s < fls(sseu->slice_mask); s++) {
> -		seq_printf(m, "  %s Slice%i subslices: %u\n", type,
> -			   s, intel_sseu_subslices_per_slice(sseu, s));
> -	}
> -	seq_printf(m, "  %s EU Total: %u\n", type,
> -		   sseu->eu_total);
> -	seq_printf(m, "  %s EU Per Subslice: %u\n", type,
> -		   sseu->eu_per_subslice);
> -
> -	if (!is_available_info)
> -		return;
> -
> -	seq_printf(m, "  Has Pooled EU: %s\n", yesno(HAS_POOLED_EU(dev_priv)));
> -	if (HAS_POOLED_EU(dev_priv))
> -		seq_printf(m, "  Min EU in pool: %u\n", sseu->min_eu_in_pool);
> -
> -	seq_printf(m, "  Has Slice Power Gating: %s\n",
> -		   yesno(sseu->has_slice_pg));
> -	seq_printf(m, "  Has Subslice Power Gating: %s\n",
> -		   yesno(sseu->has_subslice_pg));
> -	seq_printf(m, "  Has EU Power Gating: %s\n",
> -		   yesno(sseu->has_eu_pg));
> -}
> -
> -static int i915_sseu_status(struct seq_file *m, void *unused)
> -{
> -	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> -	const struct intel_runtime_info *info = RUNTIME_INFO(dev_priv);
> -	struct sseu_dev_info sseu;
> -	intel_wakeref_t wakeref;
> -
> -	if (INTEL_GEN(dev_priv) < 8)
> -		return -ENODEV;
> -
> -	seq_puts(m, "SSEU Device Info\n");
> -	i915_print_sseu_info(m, true, &info->sseu);
> -
> -	seq_puts(m, "SSEU Device Status\n");
> -	memset(&sseu, 0, sizeof(sseu));
> -	intel_sseu_set_info(&sseu, info->sseu.max_slices,
> -			    info->sseu.max_subslices,
> -			    info->sseu.max_eus_per_subslice);
> -
> -	with_intel_runtime_pm(&dev_priv->runtime_pm, wakeref) {
> -		if (IS_CHERRYVIEW(dev_priv))
> -			cherryview_sseu_device_status(dev_priv, &sseu);
> -		else if (IS_BROADWELL(dev_priv))
> -			bdw_sseu_device_status(dev_priv, &sseu);
> -		else if (IS_GEN(dev_priv, 9))
> -			gen9_sseu_device_status(dev_priv, &sseu);
> -		else if (INTEL_GEN(dev_priv) >= 10)
> -			gen10_sseu_device_status(dev_priv, &sseu);
> -	}
> -
> -	i915_print_sseu_info(m, false, &sseu);
> -
> -	return 0;
> -}
> -
>   static int i915_forcewake_open(struct inode *inode, struct file *file)
>   {
>   	struct drm_i915_private *i915 = inode->i_private;
> @@ -1865,7 +1609,6 @@ static const struct drm_info_list i915_debugfs_list[] = {
>   	{"i915_rcs_topology", i915_rcs_topology, 0},
>   	{"i915_shrinker_info", i915_shrinker_info, 0},
>   	{"i915_wa_registers", i915_wa_registers, 0},
> -	{"i915_sseu_status", i915_sseu_status, 0},
>   	{"i915_rps_boost_info", i915_rps_boost_info, 0},
>   };
>   #define I915_DEBUGFS_ENTRIES ARRAY_SIZE(i915_debugfs_list)
> 
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

[Intel-gfx] ✓ Fi.CI.IGT: success for debugfs cleanup and gt depenencies.

[Patchwork]

== Series Details ==

Series: debugfs cleanup and gt depenencies.
URL   : https://patchwork.freedesktop.org/series/75635/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_8269_full -> Patchwork_17243_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_17243_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@gem_wait@await@vecs0}:
    - shard-skl:          [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl10/igt@gem_wait@await@vecs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl2/igt@gem_wait@await@vecs0.html

  
Known issues
------------

  Here are the changes found in Patchwork_17243_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_exec_params@invalid-bsd-ring:
    - shard-iclb:         [PASS][3] -> [SKIP][4] ([fdo#109276])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb4/igt@gem_exec_params@invalid-bsd-ring.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-iclb6/igt@gem_exec_params@invalid-bsd-ring.html

  * igt@i915_pm_sseu@full-enable:
    - shard-apl:          [PASS][5] -> [SKIP][6] ([fdo#109271])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl8/igt@i915_pm_sseu@full-enable.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-apl4/igt@i915_pm_sseu@full-enable.html
    - shard-kbl:          [PASS][7] -> [SKIP][8] ([fdo#109271])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl7/igt@i915_pm_sseu@full-enable.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-kbl3/igt@i915_pm_sseu@full-enable.html
    - shard-skl:          [PASS][9] -> [SKIP][10] ([fdo#109271])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl9/igt@i915_pm_sseu@full-enable.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl6/igt@i915_pm_sseu@full-enable.html
    - shard-glk:          [PASS][11] -> [SKIP][12] ([fdo#109271])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-glk8/igt@i915_pm_sseu@full-enable.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-glk2/igt@i915_pm_sseu@full-enable.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic:
    - shard-glk:          [PASS][13] -> [FAIL][14] ([i915#72])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-glk7/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-glk5/igt@kms_cursor_legacy@2x-flip-vs-cursor-atomic.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-kbl:          [PASS][15] -> [DMESG-WARN][16] ([i915#180] / [i915#93] / [i915#95])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl4/igt@kms_fbcon_fbt@fbc-suspend.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-suspend-interruptible:
    - shard-apl:          [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-apl1/igt@kms_flip@flip-vs-suspend-interruptible.html
    - shard-kbl:          [PASS][19] -> [DMESG-WARN][20] ([i915#180]) +1 similar issue
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl2/igt@kms_flip@flip-vs-suspend-interruptible.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-kbl6/igt@kms_flip@flip-vs-suspend-interruptible.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible:
    - shard-skl:          [PASS][21] -> [FAIL][22] ([i915#34])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl7/igt@kms_flip@plain-flip-fb-recreate-interruptible.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible.html

  * igt@kms_hdr@bpc-switch-dpms:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([i915#1188])
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl8/igt@kms_hdr@bpc-switch-dpms.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence:
    - shard-kbl:          [PASS][25] -> [DMESG-WARN][26] ([i915#78]) +1 similar issue
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl6/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-kbl2/igt@kms_pipe_crc_basic@nonblocking-crc-pipe-c-frame-sequence.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][27] -> [FAIL][28] ([fdo#108145] / [i915#265]) +1 similar issue
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl8/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_psr@psr2_primary_mmap_cpu:
    - shard-iclb:         [PASS][29] -> [SKIP][30] ([fdo#109441])
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-iclb4/igt@kms_psr@psr2_primary_mmap_cpu.html

  * igt@kms_vblank@pipe-a-query-forked-busy-hang:
    - shard-kbl:          [PASS][31] -> [DMESG-WARN][32] ([i915#165])
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl6/igt@kms_vblank@pipe-a-query-forked-busy-hang.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-kbl2/igt@kms_vblank@pipe-a-query-forked-busy-hang.html

  
#### Possible fixes ####

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [DMESG-WARN][33] ([i915#180]) -> [PASS][34] +2 similar issues
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-kbl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank:
    - shard-glk:          [FAIL][35] ([i915#79]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-glk6/igt@kms_flip@flip-vs-expired-vblank.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [DMESG-WARN][37] ([i915#180] / [i915#95]) -> [PASS][38] +1 similar issue
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_hdr@bpc-switch:
    - shard-skl:          [FAIL][39] ([i915#1188]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl6/igt@kms_hdr@bpc-switch.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl3/igt@kms_hdr@bpc-switch.html

  * igt@kms_psr@no_drrs:
    - shard-iclb:         [FAIL][41] ([i915#173]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb1/igt@kms_psr@no_drrs.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-iclb8/igt@kms_psr@no_drrs.html

  * igt@kms_psr@psr2_sprite_mmap_gtt:
    - shard-iclb:         [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb6/igt@kms_psr@psr2_sprite_mmap_gtt.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-apl:          [DMESG-WARN][45] ([i915#180]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-apl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-apl7/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend:
    - shard-skl:          [INCOMPLETE][47] ([i915#69]) -> [PASS][48]
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-skl6/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-skl1/igt@kms_vblank@pipe-b-ts-continuation-dpms-suspend.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc3co-vpb-simulation:
    - shard-iclb:         [SKIP][49] ([i915#588]) -> [SKIP][50] ([i915#658])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html

  * igt@kms_psr2_su@page_flip:
    - shard-iclb:         [SKIP][51] ([fdo#109642] / [fdo#111068]) -> [FAIL][52] ([i915#608])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8269/shard-iclb3/igt@kms_psr2_su@page_flip.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/shard-iclb2/igt@kms_psr2_su@page_flip.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
  [i915#165]: https://gitlab.freedesktop.org/drm/intel/issues/165
  [i915#173]: https://gitlab.freedesktop.org/drm/intel/issues/173
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
  [i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
  [i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
  [i915#608]: https://gitlab.freedesktop.org/drm/intel/issues/608
  [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
  [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
  [i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
  [i915#78]: https://gitlab.freedesktop.org/drm/intel/issues/78
  [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (10 -> 10)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_8269 -> Patchwork_17243

  CI-20190529: 20190529
  CI_DRM_8269: 301d0427e2e3108839bf6c36f58dd0b2b5258c25 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5577: 7ee7e86fd79e4dbb6300ef4c23e50cb699216ae2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_17243: 1e192f84ccd90d30a5fe711ba72a3e9693f72519 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17243/index.html
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Re: [Intel-gfx] [PATCH v7 1/2] drm/i915: remove broken i915_sseu_status interface

[Andi Shyti]

Hi Tvrtko,

I start by saying that this patch was mainly sent to kickstart a
discussion about cleanups required in debugfs and how debugfs can
be inconsistent and how much it looks to me that we are relying
on its current state.

> > The i915_sseu_status is broken and the tests on this interface
> > are disabled. There is no reason to drag it along.
> 
> Not saying we need it, but can you say how it is broken?

well tests in igt are failing because we don't get the results we
expect, I don't know where it is actually broken but the igt test
looks straight forward to me.

I assume (with some hints I received, though) that the sseu
reads are inconsistent.

Andi
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Re: [Intel-gfx] [PATCH v7 1/2] drm/i915: remove broken i915_sseu_status interface

[Lionel Landwerlin]

On 08/04/2020 14:55, Andi Shyti wrote:
> Hi Tvrtko,
>
> I start by saying that this patch was mainly sent to kickstart a
> discussion about cleanups required in debugfs and how debugfs can
> be inconsistent and how much it looks to me that we are relying
> on its current state.
>
>>> The i915_sseu_status is broken and the tests on this interface
>>> are disabled. There is no reason to drag it along.
>> Not saying we need it, but can you say how it is broken?
> well tests in igt are failing because we don't get the results we
> expect, I don't know where it is actually broken but the igt test
> looks straight forward to me.
>
> I assume (with some hints I received, though) that the sseu
> reads are inconsistent.
>
> Andi

I think it's broken because we're reading an acknowledgement registers.

These registers seems to be populated only after a context is run.

If you read it before a context is run after coming out of power 
management, there is no request to acknowledge and you get 0 values.


-Lionel

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