* [Intel-gfx] [CI 1/3] drm/i915/selftests: Verify frequency scaling with RPS
@ 2020-04-18 15:27 Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 2/3] drm/i915/selftests: Skip energy consumption tests if not controlling freq Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 8+ messages in thread
From: Chris Wilson @ 2020-04-18 15:27 UTC (permalink / raw)
To: intel-gfx
One of the core tenents of reclocking the GPU is that its throughput
scales with the clock frequency. We can observe this by incrementing a
loop counter on the GPU, and compare the different execution rates at
the notional RPS frequencies.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 3 +-
drivers/gpu/drm/i915/gt/selftest_rps.c | 243 +++++++++++++++++++++--
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
3 files changed, 234 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 0141c334f2ac..4b2733967c42 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -53,8 +53,9 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
- SUBTEST(live_rps_interrupt),
+ SUBTEST(live_rps_frequency),
SUBTEST(live_rps_power),
+ SUBTEST(live_rps_interrupt),
SUBTEST(live_gt_resume),
};
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 360f56aa4b82..380a65ca1cae 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -6,6 +6,7 @@
#include <linux/sort.h>
#include "intel_engine_pm.h"
+#include "intel_gpu_commands.h"
#include "intel_gt_pm.h"
#include "intel_rc6.h"
#include "selftest_rps.h"
@@ -17,6 +18,236 @@ static void dummy_rps_work(struct work_struct *wrk)
{
}
+static int cmp_u64(const void *A, const void *B)
+{
+ const u64 *a = A, *b = B;
+
+ if (a < b)
+ return -1;
+ else if (a > b)
+ return 1;
+ else
+ return 0;
+}
+
+static struct i915_vma *
+create_spin_counter(struct intel_engine_cs *engine,
+ struct i915_address_space *vm,
+ u32 **cancel,
+ u32 **counter)
+{
+ enum {
+ COUNT,
+ INC,
+ __NGPR__,
+ };
+#define CS_GPR(x) GEN8_RING_CS_GPR(engine->mmio_base, x)
+ struct drm_i915_gem_object *obj;
+ struct i915_vma *vma;
+ u32 *base, *cs;
+ int loop, i;
+ int err;
+
+ obj = i915_gem_object_create_internal(vm->i915, 4096);
+ if (IS_ERR(obj))
+ return ERR_CAST(obj);
+
+ vma = i915_vma_instance(obj, vm, NULL);
+ if (IS_ERR(vma)) {
+ i915_gem_object_put(obj);
+ return vma;
+ }
+
+ err = i915_vma_pin(vma, 0, 0, PIN_USER);
+ if (err) {
+ i915_vma_put(vma);
+ return ERR_PTR(err);
+ }
+
+ base = i915_gem_object_pin_map(obj, I915_MAP_WC);
+ if (IS_ERR(base)) {
+ i915_gem_object_put(obj);
+ return ERR_CAST(base);
+ }
+ cs = base;
+
+ *cs++ = MI_LOAD_REGISTER_IMM(__NGPR__ * 2);
+ for (i = 0; i < __NGPR__; i++) {
+ *cs++ = i915_mmio_reg_offset(CS_GPR(i));
+ *cs++ = 0;
+ *cs++ = i915_mmio_reg_offset(CS_GPR(i)) + 4;
+ *cs++ = 0;
+ }
+
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(CS_GPR(INC));
+ *cs++ = 1;
+
+ loop = cs - base;
+
+ *cs++ = MI_MATH(4);
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(COUNT));
+ *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(INC));
+ *cs++ = MI_MATH_ADD;
+ *cs++ = MI_MATH_STORE(MI_MATH_REG(COUNT), MI_MATH_REG_ACCU);
+
+ *cs++ = MI_STORE_REGISTER_MEM_GEN8;
+ *cs++ = i915_mmio_reg_offset(CS_GPR(COUNT));
+ *cs++ = lower_32_bits(vma->node.start + 1000 * sizeof(*cs));
+ *cs++ = upper_32_bits(vma->node.start + 1000 * sizeof(*cs));
+
+ *cs++ = MI_BATCH_BUFFER_START_GEN8;
+ *cs++ = lower_32_bits(vma->node.start + loop * sizeof(*cs));
+ *cs++ = upper_32_bits(vma->node.start + loop * sizeof(*cs));
+
+ i915_gem_object_flush_map(obj);
+
+ *cancel = base + loop;
+ *counter = memset32(base + 1000, 0, 1);
+ return vma;
+}
+
+static u64 __measure_frequency(u32 *cntr, int duration_ms)
+{
+ u64 dc, dt;
+
+ dt = ktime_get();
+ dc = READ_ONCE(*cntr);
+ usleep_range(1000 * duration_ms, 2000 * duration_ms);
+ dc = READ_ONCE(*cntr) - dc;
+ dt = ktime_get() - dt;
+
+ return div64_u64(1000 * 1000 * dc, dt);
+}
+
+static u64 measure_frequency_at(struct intel_rps *rps, u32 *cntr, int *freq)
+{
+ u64 x[5];
+ int i;
+
+ mutex_lock(&rps->lock);
+ GEM_BUG_ON(!rps->active);
+ intel_rps_set(rps, *freq);
+ mutex_unlock(&rps->lock);
+
+ msleep(20); /* more than enough time to stabilise! */
+
+ for (i = 0; i < 5; i++)
+ x[i] = __measure_frequency(cntr, 2);
+ *freq = read_cagf(rps);
+
+ /* A simple triangle filter for better result stability */
+ sort(x, 5, sizeof(*x), cmp_u64, NULL);
+ return div_u64(x[1] + 2 * x[2] + x[3], 4);
+}
+
+int live_rps_frequency(void *arg)
+{
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >->rps;
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ int err = 0;
+
+ /*
+ * The premise is that the GPU does change freqency at our behest.
+ * Let's check there is a correspondence between the requested
+ * frequency, the actual frequency, and the observed clock rate.
+ */
+
+ if (!rps->enabled || rps->max_freq <= rps->min_freq)
+ return 0;
+
+ if (INTEL_GEN(gt->i915) < 8) /* for CS simplicity */
+ return 0;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ struct i915_vma *vma;
+ u32 *cancel, *cntr;
+ struct {
+ u64 count;
+ int freq;
+ } min, max;
+
+ vma = create_spin_counter(engine,
+ engine->kernel_context->vm,
+ &cancel, &cntr);
+ if (IS_ERR(vma)) {
+ err = PTR_ERR(vma);
+ break;
+ }
+
+ rq = intel_engine_create_kernel_request(engine);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ goto err_vma;
+ }
+
+ i915_vma_lock(vma);
+ err = i915_request_await_object(rq, vma->obj, false);
+ if (!err)
+ err = i915_vma_move_to_active(vma, rq, 0);
+ if (!err)
+ err = rq->engine->emit_bb_start(rq,
+ vma->node.start,
+ PAGE_SIZE, 0);
+ i915_vma_unlock(vma);
+ i915_request_add(rq);
+ if (err)
+ goto err_vma;
+
+ if (wait_for(READ_ONCE(*cntr), 10)) {
+ pr_err("%s: timed loop did not start\n",
+ engine->name);
+ goto err_vma;
+ }
+
+ min.freq = rps->min_freq;
+ min.count = measure_frequency_at(rps, cntr, &min.freq);
+
+ max.freq = rps->max_freq;
+ max.count = measure_frequency_at(rps, cntr, &max.freq);
+
+ pr_info("%s: min:%lluKHz @ %uMHz, max:%lluKHz @ %uMHz [%d%%]\n",
+ engine->name,
+ min.count, intel_gpu_freq(rps, min.freq),
+ max.count, intel_gpu_freq(rps, max.freq),
+ (int)DIV64_U64_ROUND_CLOSEST(100 * min.freq * max.count,
+ max.freq * min.count));
+
+ if (2 * max.freq * min.count > 3 * min.freq * max.count ||
+ 3 * max.freq * min.count < 2 * min.freq * max.count) {
+ pr_err("%s: CS did not scale with frequency! scaled min:%llu, max:%llu\n",
+ engine->name,
+ max.freq * min.count,
+ min.freq * max.count);
+ err = -EINVAL;
+ }
+
+err_vma:
+ *cancel = MI_BATCH_BUFFER_END;
+ i915_gem_object_unpin_map(vma->obj);
+ i915_vma_unpin(vma);
+ i915_vma_put(vma);
+
+ if (igt_flush_test(gt->i915))
+ err = -EIO;
+ if (err)
+ break;
+ }
+
+ intel_gt_pm_wait_for_idle(gt);
+ rps->work.func = saved_work;
+
+ return err;
+}
+
static void sleep_for_ei(struct intel_rps *rps, int timeout_us)
{
/* Flush any previous EI */
@@ -248,18 +479,6 @@ static u64 __measure_power(int duration_ms)
return div64_u64(1000 * 1000 * dE, dt);
}
-static int cmp_u64(const void *A, const void *B)
-{
- const u64 *a = A, *b = B;
-
- if (a < b)
- return -1;
- else if (a > b)
- return 1;
- else
- return 0;
-}
-
static u64 measure_power_at(struct intel_rps *rps, int freq)
{
u64 x[5];
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.h b/drivers/gpu/drm/i915/gt/selftest_rps.h
index cad515a7f0e5..07c2bddf8899 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.h
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.h
@@ -6,6 +6,7 @@
#ifndef SELFTEST_RPS_H
#define SELFTEST_RPS_H
+int live_rps_frequency(void *arg);
int live_rps_interrupt(void *arg);
int live_rps_power(void *arg);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [CI 2/3] drm/i915/selftests: Skip energy consumption tests if not controlling freq
2020-04-18 15:27 [Intel-gfx] [CI 1/3] drm/i915/selftests: Verify frequency scaling with RPS Chris Wilson
@ 2020-04-18 15:27 ` Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 3/3] drm/i915/selftests: Check RPS controls Chris Wilson
` (2 subsequent siblings)
3 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2020-04-18 15:27 UTC (permalink / raw)
To: intel-gfx
If we can not manipulate the frequency with RPS, then comparing min/max
power consumption is pointless / misleading. We will leave the warning
about not being able to control the frequency selection via RPS to other
tests so as not to confuse this more specialised check.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_rps.c | 37 ++++++++++++++++----------
1 file changed, 23 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 380a65ca1cae..67c287282d38 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -479,26 +479,21 @@ static u64 __measure_power(int duration_ms)
return div64_u64(1000 * 1000 * dE, dt);
}
-static u64 measure_power_at(struct intel_rps *rps, int freq)
+static u64 measure_power_at(struct intel_rps *rps, int *freq)
{
u64 x[5];
int i;
mutex_lock(&rps->lock);
GEM_BUG_ON(!rps->active);
- intel_rps_set(rps, freq);
+ intel_rps_set(rps, *freq);
mutex_unlock(&rps->lock);
msleep(20); /* more than enough time to stabilise! */
- i = read_cagf(rps);
- if (i != freq)
- pr_notice("Running at %x [%uMHz], not target %x [%uMHz]\n",
- i, intel_gpu_freq(rps, i),
- freq, intel_gpu_freq(rps, freq));
-
for (i = 0; i < 5; i++)
x[i] = __measure_power(5);
+ *freq = read_cagf(rps);
/* A simple triangle filter for better result stability */
sort(x, 5, sizeof(*x), cmp_u64, NULL);
@@ -536,7 +531,10 @@ int live_rps_power(void *arg)
for_each_engine(engine, gt, id) {
struct i915_request *rq;
- u64 min, max;
+ struct {
+ u64 power;
+ int freq;
+ } min, max;
if (!intel_engine_can_store_dword(engine))
continue;
@@ -559,16 +557,27 @@ int live_rps_power(void *arg)
break;
}
- max = measure_power_at(rps, rps->max_freq);
- min = measure_power_at(rps, rps->min_freq);
+ max.freq = rps->max_freq;
+ max.power = measure_power_at(rps, &max.freq);
+
+ min.freq = rps->min_freq;
+ min.power = measure_power_at(rps, &min.freq);
igt_spinner_end(&spin);
pr_info("%s: min:%llumW @ %uMHz, max:%llumW @ %uMHz\n",
engine->name,
- min, intel_gpu_freq(rps, rps->min_freq),
- max, intel_gpu_freq(rps, rps->max_freq));
- if (11 * min > 10 * max) {
+ min.power, intel_gpu_freq(rps, min.freq),
+ max.power, intel_gpu_freq(rps, max.freq));
+
+ if (10 * min.freq >= 9 * max.freq) {
+ pr_notice("Could not control frequency, ran at [%d:%uMHz, %d:%uMhz]\n",
+ min.freq, intel_gpu_freq(rps, min.freq),
+ max.freq, intel_gpu_freq(rps, max.freq));
+ continue;
+ }
+
+ if (11 * min.power > 10 * max.power) {
pr_err("%s: did not conserve power when setting lower frequency!\n",
engine->name);
err = -EINVAL;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] [CI 3/3] drm/i915/selftests: Check RPS controls
2020-04-18 15:27 [Intel-gfx] [CI 1/3] drm/i915/selftests: Verify frequency scaling with RPS Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 2/3] drm/i915/selftests: Skip energy consumption tests if not controlling freq Chris Wilson
@ 2020-04-18 15:27 ` Chris Wilson
2020-04-18 16:00 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS Patchwork
2020-04-18 16:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Chris Wilson @ 2020-04-18 15:27 UTC (permalink / raw)
To: intel-gfx
Check that the GPU does respond to our RPS frequency requests by setting
our desired frequency.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/gt/selftest_gt_pm.c | 1 +
drivers/gpu/drm/i915/gt/selftest_rps.c | 192 ++++++++++++++++++++---
drivers/gpu/drm/i915/gt/selftest_rps.h | 1 +
3 files changed, 170 insertions(+), 24 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
index 4b2733967c42..de3eaef40596 100644
--- a/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/selftest_gt_pm.c
@@ -53,6 +53,7 @@ int intel_gt_pm_live_selftests(struct drm_i915_private *i915)
{
static const struct i915_subtest tests[] = {
SUBTEST(live_rc6_manual),
+ SUBTEST(live_rps_control),
SUBTEST(live_rps_frequency),
SUBTEST(live_rps_power),
SUBTEST(live_rps_interrupt),
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.c b/drivers/gpu/drm/i915/gt/selftest_rps.c
index 67c287282d38..5ee693ac9904 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.c
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.c
@@ -107,6 +107,168 @@ create_spin_counter(struct intel_engine_cs *engine,
return vma;
}
+static u8 rps_set_check(struct intel_rps *rps, u8 freq)
+{
+ u8 history[64], i;
+ unsigned long end;
+ int sleep;
+
+ mutex_lock(&rps->lock);
+ GEM_BUG_ON(!rps->active);
+ intel_rps_set(rps, freq);
+ GEM_BUG_ON(rps->last_freq != freq);
+ mutex_unlock(&rps->lock);
+
+ i = 0;
+ memset(history, freq, sizeof(history));
+ sleep = 20;
+
+ /* The PCU does not change instantly, but drifts towards the goal? */
+ end = jiffies + msecs_to_jiffies(50);
+ do {
+ u8 act;
+
+ act = read_cagf(rps);
+ if (time_after(jiffies, end))
+ return act;
+
+ /* Target acquired */
+ if (act == freq)
+ return act;
+
+ /* Any change witin the last N samples? */
+ if (!memchr_inv(history, act, sizeof(history)))
+ return act;
+
+ history[i] = act;
+ i = (i + 1) % ARRAY_SIZE(history);
+
+ usleep_range(sleep, 2 * sleep);
+ sleep *= 2;
+ if (sleep > 1000)
+ sleep = 1000;
+ } while (1);
+}
+
+int live_rps_control(void *arg)
+{
+ struct intel_gt *gt = arg;
+ struct intel_rps *rps = >->rps;
+ void (*saved_work)(struct work_struct *wrk);
+ struct intel_engine_cs *engine;
+ enum intel_engine_id id;
+ struct igt_spinner spin;
+ int err = 0;
+
+ /*
+ * Check that the actual frequency matches our requested frequency,
+ * to verify our control mechanism. We have to be careful that the
+ * PCU may throttle the GPU in which case the actual frequency used
+ * will be lowered than requested.
+ */
+
+ if (!rps->enabled || rps->max_freq <= rps->min_freq)
+ return 0;
+
+ if (igt_spinner_init(&spin, gt))
+ return -ENOMEM;
+
+ intel_gt_pm_wait_for_idle(gt);
+ saved_work = rps->work.func;
+ rps->work.func = dummy_rps_work;
+
+ intel_gt_pm_get(gt);
+ for_each_engine(engine, gt, id) {
+ struct i915_request *rq;
+ ktime_t min_dt, max_dt;
+ int act, f, limit;
+ int min, max;
+
+ if (!intel_engine_can_store_dword(engine))
+ continue;
+
+ rq = igt_spinner_create_request(&spin,
+ engine->kernel_context,
+ MI_NOOP);
+ if (IS_ERR(rq)) {
+ err = PTR_ERR(rq);
+ break;
+ }
+
+ i915_request_add(rq);
+
+ if (!igt_wait_for_spinner(&spin, rq)) {
+ pr_err("%s: RPS spinner did not start\n",
+ engine->name);
+ intel_gt_set_wedged(engine->gt);
+ err = -EIO;
+ break;
+ }
+
+ if (rps_set_check(rps, rps->min_freq) != rps->min_freq) {
+ pr_err("%s: could not set minimum frequency!\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ err = -EINVAL;
+ break;
+ }
+
+ for (f = rps->min_freq + 1; f < rps->max_freq; f++) {
+ act = rps_set_check(rps, f);
+ if (act < f)
+ break;
+ }
+
+ limit = rps_set_check(rps, f);
+
+ if (rps_set_check(rps, rps->min_freq) != rps->min_freq) {
+ pr_err("%s: could not restore minimum frequency!\n",
+ engine->name);
+ igt_spinner_end(&spin);
+ err = -EINVAL;
+ break;
+ }
+
+ max_dt = ktime_get();
+ max = rps_set_check(rps, rps->max_freq);
+ max_dt = ktime_sub(ktime_get(), max_dt);
+
+ min_dt = ktime_get();
+ min = rps_set_check(rps, rps->min_freq);
+ min_dt = ktime_sub(ktime_get(), min_dt);
+
+ igt_spinner_end(&spin);
+
+ pr_info("%s: range:[%x:%uMHz, %x:%uMHz] actual:[ %x:%uMHz, %x:%uMHz], %x:%x response %lluns:%lluns\n",
+ engine->name,
+ rps->min_freq, intel_gpu_freq(rps, rps->min_freq),
+ rps->max_freq, intel_gpu_freq(rps, rps->max_freq),
+ act, intel_gpu_freq(rps, act),
+ limit, intel_gpu_freq(rps, limit),
+ min, max, ktime_to_ns(min_dt), ktime_to_ns(max_dt));
+
+ if (limit == rps->min_freq) {
+ pr_err("%s: GPU throttled to minimum!\n",
+ engine->name);
+ err = -ENODEV;
+ break;
+ }
+
+ if (igt_flush_test(gt->i915)) {
+ err = -EIO;
+ break;
+ }
+ }
+ intel_gt_pm_put(gt);
+
+ igt_spinner_fini(&spin);
+
+ intel_gt_pm_wait_for_idle(gt);
+ rps->work.func = saved_work;
+
+ return err;
+}
+
static u64 __measure_frequency(u32 *cntr, int duration_ms)
{
u64 dc, dt;
@@ -125,16 +287,10 @@ static u64 measure_frequency_at(struct intel_rps *rps, u32 *cntr, int *freq)
u64 x[5];
int i;
- mutex_lock(&rps->lock);
- GEM_BUG_ON(!rps->active);
- intel_rps_set(rps, *freq);
- mutex_unlock(&rps->lock);
-
- msleep(20); /* more than enough time to stabilise! */
-
+ *freq = rps_set_check(rps, *freq);
for (i = 0; i < 5; i++)
x[i] = __measure_frequency(cntr, 2);
- *freq = read_cagf(rps);
+ *freq = (*freq + read_cagf(rps)) / 2;
/* A simple triangle filter for better result stability */
sort(x, 5, sizeof(*x), cmp_u64, NULL);
@@ -273,10 +429,7 @@ static int __rps_up_interrupt(struct intel_rps *rps,
if (!intel_engine_can_store_dword(engine))
return 0;
- mutex_lock(&rps->lock);
- GEM_BUG_ON(!rps->active);
- intel_rps_set(rps, rps->min_freq);
- mutex_unlock(&rps->lock);
+ rps_set_check(rps, rps->min_freq);
rq = igt_spinner_create_request(spin, engine->kernel_context, MI_NOOP);
if (IS_ERR(rq))
@@ -348,10 +501,7 @@ static int __rps_down_interrupt(struct intel_rps *rps,
struct intel_uncore *uncore = engine->uncore;
u32 timeout;
- mutex_lock(&rps->lock);
- GEM_BUG_ON(!rps->active);
- intel_rps_set(rps, rps->max_freq);
- mutex_unlock(&rps->lock);
+ rps_set_check(rps, rps->max_freq);
if (!(rps->pm_events & GEN6_PM_RP_DOWN_THRESHOLD)) {
pr_err("%s: RPS did not register DOWN interrupt\n",
@@ -484,16 +634,10 @@ static u64 measure_power_at(struct intel_rps *rps, int *freq)
u64 x[5];
int i;
- mutex_lock(&rps->lock);
- GEM_BUG_ON(!rps->active);
- intel_rps_set(rps, *freq);
- mutex_unlock(&rps->lock);
-
- msleep(20); /* more than enough time to stabilise! */
-
+ *freq = rps_set_check(rps, *freq);
for (i = 0; i < 5; i++)
x[i] = __measure_power(5);
- *freq = read_cagf(rps);
+ *freq = (*freq + read_cagf(rps)) / 2;
/* A simple triangle filter for better result stability */
sort(x, 5, sizeof(*x), cmp_u64, NULL);
diff --git a/drivers/gpu/drm/i915/gt/selftest_rps.h b/drivers/gpu/drm/i915/gt/selftest_rps.h
index 07c2bddf8899..be0bf8e3f639 100644
--- a/drivers/gpu/drm/i915/gt/selftest_rps.h
+++ b/drivers/gpu/drm/i915/gt/selftest_rps.h
@@ -6,6 +6,7 @@
#ifndef SELFTEST_RPS_H
#define SELFTEST_RPS_H
+int live_rps_control(void *arg);
int live_rps_frequency(void *arg);
int live_rps_interrupt(void *arg);
int live_rps_power(void *arg);
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
2020-04-18 15:27 [Intel-gfx] [CI 1/3] drm/i915/selftests: Verify frequency scaling with RPS Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 2/3] drm/i915/selftests: Skip energy consumption tests if not controlling freq Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 3/3] drm/i915/selftests: Check RPS controls Chris Wilson
@ 2020-04-18 16:00 ` Patchwork
2020-04-18 16:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-04-18 16:00 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
URL : https://patchwork.freedesktop.org/series/76152/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
2020-04-18 15:27 [Intel-gfx] [CI 1/3] drm/i915/selftests: Verify frequency scaling with RPS Chris Wilson
` (2 preceding siblings ...)
2020-04-18 16:00 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS Patchwork
@ 2020-04-18 16:06 ` Patchwork
3 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-04-18 16:06 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
URL : https://patchwork.freedesktop.org/series/76152/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8323 -> Patchwork_17367
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17367 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17367, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/index.html
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17367:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@gt_pm:
- fi-icl-y: [PASS][1] -> [DMESG-FAIL][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-icl-y/igt@i915_selftest@live@gt_pm.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-icl-y/igt@i915_selftest@live@gt_pm.html
- fi-bsw-n3050: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-bsw-n3050/igt@i915_selftest@live@gt_pm.html
- fi-bsw-kefka: [PASS][5] -> [INCOMPLETE][6]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-bsw-kefka/igt@i915_selftest@live@gt_pm.html
- fi-cfl-8109u: [PASS][7] -> [DMESG-FAIL][8]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-cfl-8109u/igt@i915_selftest@live@gt_pm.html
- fi-bsw-nick: [PASS][9] -> [INCOMPLETE][10]
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-bsw-nick/igt@i915_selftest@live@gt_pm.html
#### Warnings ####
* igt@i915_selftest@live@gt_pm:
- fi-tgl-y: [DMESG-FAIL][11] ([i915#1725]) -> [DMESG-FAIL][12]
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-tgl-y/igt@i915_selftest@live@gt_pm.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_pm:
- {fi-tgl-dsi}: [DMESG-FAIL][13] ([i915#1725]) -> [DMESG-FAIL][14]
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-tgl-dsi/igt@i915_selftest@live@gt_pm.html
- {fi-tgl-u}: [DMESG-FAIL][15] ([i915#1725]) -> [DMESG-FAIL][16]
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-tgl-u/igt@i915_selftest@live@gt_pm.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-tgl-u/igt@i915_selftest@live@gt_pm.html
Known issues
------------
Here are the changes found in Patchwork_17367 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@sanitycheck:
- fi-bwr-2160: [PASS][17] -> [INCOMPLETE][18] ([i915#489])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-bwr-2160/igt@i915_selftest@live@sanitycheck.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-bwr-2160/igt@i915_selftest@live@sanitycheck.html
#### Possible fixes ####
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-skl-6770hq: [FAIL][19] ([fdo#103375]) -> [PASS][20]
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8323/fi-skl-6770hq/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/fi-skl-6770hq/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[i915#1725]: https://gitlab.freedesktop.org/drm/intel/issues/1725
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (51 -> 44)
------------------------------
Missing (7): fi-kbl-soraka fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8323 -> Patchwork_17367
CI-20190529: 20190529
CI_DRM_8323: 65545bfa1e4f92bb86462bf7226b8a33d13715a1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5599: cdb07101dda33e2fcb0f4c2aa199c47159d88f35 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17367: e4c40ec617342f1b7a6fb8cdbc3ea5f51f5ab2fe @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
e4c40ec61734 drm/i915/selftests: Check RPS controls
041d5c6f6ca6 drm/i915/selftests: Skip energy consumption tests if not controlling freq
1f71fde93ed2 drm/i915/selftests: Verify frequency scaling with RPS
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17367/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
2020-04-19 9:06 [Intel-gfx] [CI 1/3] " Chris Wilson
@ 2020-04-19 9:31 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-04-19 9:31 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
URL : https://patchwork.freedesktop.org/series/76156/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
2020-04-18 22:23 [Intel-gfx] [CI 1/3] " Chris Wilson
@ 2020-04-18 22:51 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-04-18 22:51 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
URL : https://patchwork.freedesktop.org/series/76154/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
2020-04-18 16:33 [Intel-gfx] [CI 1/3] " Chris Wilson
@ 2020-04-18 17:16 ` Patchwork
0 siblings, 0 replies; 8+ messages in thread
From: Patchwork @ 2020-04-18 17:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS
URL : https://patchwork.freedesktop.org/series/76153/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-04-19 9:31 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-18 15:27 [Intel-gfx] [CI 1/3] drm/i915/selftests: Verify frequency scaling with RPS Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 2/3] drm/i915/selftests: Skip energy consumption tests if not controlling freq Chris Wilson
2020-04-18 15:27 ` [Intel-gfx] [CI 3/3] drm/i915/selftests: Check RPS controls Chris Wilson
2020-04-18 16:00 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] drm/i915/selftests: Verify frequency scaling with RPS Patchwork
2020-04-18 16:06 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2020-04-18 16:33 [Intel-gfx] [CI 1/3] " Chris Wilson
2020-04-18 17:16 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] " Patchwork
2020-04-18 22:23 [Intel-gfx] [CI 1/3] " Chris Wilson
2020-04-18 22:51 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] " Patchwork
2020-04-19 9:06 [Intel-gfx] [CI 1/3] " Chris Wilson
2020-04-19 9:31 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for series starting with [CI,1/3] " Patchwork
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