* [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper
@ 2020-04-17 19:51 Michael J. Ruhl
2020-04-17 19:55 ` Chris Wilson
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Michael J. Ruhl @ 2020-04-17 19:51 UTC (permalink / raw)
To: intel-gfx; +Cc: Chris Wilson
DMA_MASK bit values are different for different generations.
This will become more difficult to manage over time with the open
coded usage of different versions of the device.
Fix by:
disallow setting of dma mask in AGP path (< GEN(5) for i915,
add dma_mask_size to the device info configuration,
updating open code call sequence to the latest interface,
refactoring into a common function for setting the dma segment
and mask info
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
cc: Brian Welty <brian.welty@intel.com>
cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
v1: removed i915 depenancy from agp path for dma mask
Consolidated segment size and work arounds to the helper
v2: added r-b
---
drivers/char/agp/intel-gtt.c | 17 +++--
drivers/gpu/drm/i915/gt/intel_ggtt.c | 15 ----
drivers/gpu/drm/i915/i915_drv.c | 94 +++++++++++++++---------
drivers/gpu/drm/i915/i915_pci.c | 14 ++++
drivers/gpu/drm/i915/intel_device_info.c | 1 +
drivers/gpu/drm/i915/intel_device_info.h | 2 +
6 files changed, 87 insertions(+), 56 deletions(-)
diff --git a/drivers/char/agp/intel-gtt.c b/drivers/char/agp/intel-gtt.c
index 3d42fc4290bc..4b34a5195c65 100644
--- a/drivers/char/agp/intel-gtt.c
+++ b/drivers/char/agp/intel-gtt.c
@@ -1407,13 +1407,16 @@ int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev,
dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name);
- mask = intel_private.driver->dma_mask_size;
- if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
- dev_err(&intel_private.pcidev->dev,
- "set gfx device dma mask %d-bit failed!\n", mask);
- else
- pci_set_consistent_dma_mask(intel_private.pcidev,
- DMA_BIT_MASK(mask));
+ if (bridge) {
+ mask = intel_private.driver->dma_mask_size;
+ if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask)))
+ dev_err(&intel_private.pcidev->dev,
+ "set gfx device dma mask %d-bit failed!\n",
+ mask);
+ else
+ pci_set_consistent_dma_mask(intel_private.pcidev,
+ DMA_BIT_MASK(mask));
+ }
if (intel_gtt_init() != 0) {
intel_gmch_remove();
diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index eebd1190506f..66165b10256e 100644
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -840,7 +840,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
struct pci_dev *pdev = i915->drm.pdev;
unsigned int size;
u16 snb_gmch_ctl;
- int err;
/* TODO: We're not aware of mappable constraints on gen8 yet */
if (!IS_DGFX(i915)) {
@@ -848,13 +847,6 @@ static int gen8_gmch_probe(struct i915_ggtt *ggtt)
ggtt->mappable_end = resource_size(&ggtt->gmadr);
}
- err = pci_set_dma_mask(pdev, DMA_BIT_MASK(39));
- if (!err)
- err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
- if (err)
- drm_err(&i915->drm,
- "Can't set DMA mask/consistent mask (%d)\n", err);
-
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
if (IS_CHERRYVIEW(i915))
size = chv_get_total_gtt_size(snb_gmch_ctl);
@@ -990,7 +982,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
struct pci_dev *pdev = i915->drm.pdev;
unsigned int size;
u16 snb_gmch_ctl;
- int err;
ggtt->gmadr = pci_resource(pdev, 2);
ggtt->mappable_end = resource_size(&ggtt->gmadr);
@@ -1005,12 +996,6 @@ static int gen6_gmch_probe(struct i915_ggtt *ggtt)
return -ENXIO;
}
- err = pci_set_dma_mask(pdev, DMA_BIT_MASK(40));
- if (!err)
- err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(40));
- if (err)
- drm_err(&i915->drm,
- "Can't set DMA mask/consistent mask (%d)\n", err);
pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
size = gen6_get_total_gtt_size(snb_gmch_ctl);
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 641f5e03b661..21e30b30d9d6 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -566,6 +566,62 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
intel_gvt_sanitize_options(dev_priv);
}
+/**
+ * i915_set_dma_info - set all relevant PCI dma info as configured for the
+ * platform
+ * @i915: valid i915 instance
+ *
+ * Set the dma max segment size, device and coherent masks. The dma mask set
+ * needs to occur before i915_ggtt_probe_hw.
+ *
+ * A couple of platforms have special needs. Address them as well.
+ *
+ */
+static int i915_set_dma_info(struct drm_i915_private *i915)
+{
+ struct pci_dev *pdev = i915->drm.pdev;
+ unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
+ int ret;
+
+ GEM_BUG_ON(!mask_size);
+
+ /*
+ * We don't have a max segment size, so set it to the max so sg's
+ * debugging layer doesn't complain
+ */
+ dma_set_max_seg_size(&pdev->dev, UINT_MAX);
+
+ ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
+ if (ret)
+ goto mask_err;
+
+ /* overlay on gen2 is broken and can't address above 1G */
+ if (IS_GEN(i915, 2))
+ mask_size = 30;
+
+ /*
+ * 965GM sometimes incorrectly writes to hardware status page (HWS)
+ * using 32bit addressing, overwriting memory if HWS is located
+ * above 4GB.
+ *
+ * The documentation also mentions an issue with undefined
+ * behaviour if any general state is accessed within a page above 4GB,
+ * which also needs to be handled carefully.
+ */
+ if (IS_I965G(i915) || IS_I965GM(i915))
+ mask_size = 32;
+
+ ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(mask_size));
+ if (ret)
+ goto mask_err;
+
+ return 0;
+
+mask_err:
+ drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
+ return ret;
+}
+
/**
* i915_driver_hw_probe - setup state requiring device access
* @dev_priv: device private
@@ -611,6 +667,10 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
/* needs to be done before ggtt probe */
intel_dram_edram_detect(dev_priv);
+ ret = i915_set_dma_info(dev_priv);
+ if (ret)
+ return ret;
+
i915_perf_init(dev_priv);
ret = i915_ggtt_probe_hw(dev_priv);
@@ -639,40 +699,6 @@ static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
pci_set_master(pdev);
- /*
- * We don't have a max segment size, so set it to the max so sg's
- * debugging layer doesn't complain
- */
- dma_set_max_seg_size(&pdev->dev, UINT_MAX);
-
- /* overlay on gen2 is broken and can't address above 1G */
- if (IS_GEN(dev_priv, 2)) {
- ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(30));
- if (ret) {
- drm_err(&dev_priv->drm, "failed to set DMA mask\n");
-
- goto err_mem_regions;
- }
- }
-
- /* 965GM sometimes incorrectly writes to hardware status page (HWS)
- * using 32bit addressing, overwriting memory if HWS is located
- * above 4GB.
- *
- * The documentation also mentions an issue with undefined
- * behaviour if any general state is accessed within a page above 4GB,
- * which also needs to be handled carefully.
- */
- if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
- ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
-
- if (ret) {
- drm_err(&dev_priv->drm, "failed to set DMA mask\n");
-
- goto err_mem_regions;
- }
- }
-
cpu_latency_qos_add_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
intel_gt_init_workarounds(dev_priv);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 66738f2c4f28..2fc25ec12c3d 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -171,6 +171,7 @@
.engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
+ .dma_mask_size = 32, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
I9XX_COLORS, \
@@ -190,6 +191,7 @@
.engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = false, \
+ .dma_mask_size = 32, \
I845_PIPE_OFFSETS, \
I845_CURSOR_OFFSETS, \
I9XX_COLORS, \
@@ -226,6 +228,7 @@ static const struct intel_device_info i865g_info = {
.engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = true, \
+ .dma_mask_size = 32, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
I9XX_COLORS, \
@@ -286,6 +289,7 @@ static const struct intel_device_info g33_info = {
PLATFORM(INTEL_G33),
.display.has_hotplug = 1,
.display.has_overlay = 1,
+ .dma_mask_size = 36,
};
static const struct intel_device_info pnv_g_info = {
@@ -293,6 +297,7 @@ static const struct intel_device_info pnv_g_info = {
PLATFORM(INTEL_PINEVIEW),
.display.has_hotplug = 1,
.display.has_overlay = 1,
+ .dma_mask_size = 36,
};
static const struct intel_device_info pnv_m_info = {
@@ -301,6 +306,7 @@ static const struct intel_device_info pnv_m_info = {
.is_mobile = 1,
.display.has_hotplug = 1,
.display.has_overlay = 1,
+ .dma_mask_size = 36,
};
#define GEN4_FEATURES \
@@ -313,6 +319,7 @@ static const struct intel_device_info pnv_m_info = {
.engine_mask = BIT(RCS0), \
.has_snoop = true, \
.has_coherent_ggtt = true, \
+ .dma_mask_size = 36, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
I965_COLORS, \
@@ -365,6 +372,7 @@ static const struct intel_device_info gm45_info = {
.has_coherent_ggtt = true, \
/* ilk does support rc6, but we do not implement [power] contexts */ \
.has_rc6 = 0, \
+ .dma_mask_size = 36, \
I9XX_PIPE_OFFSETS, \
I9XX_CURSOR_OFFSETS, \
ILK_COLORS, \
@@ -395,6 +403,7 @@ static const struct intel_device_info ilk_m_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.has_rps = true, \
+ .dma_mask_size = 40, \
.ppgtt_type = INTEL_PPGTT_ALIASING, \
.ppgtt_size = 31, \
I9XX_PIPE_OFFSETS, \
@@ -445,6 +454,7 @@ static const struct intel_device_info snb_m_gt2_info = {
.has_rc6 = 1, \
.has_rc6p = 1, \
.has_rps = true, \
+ .dma_mask_size = 40, \
.ppgtt_type = INTEL_PPGTT_ALIASING, \
.ppgtt_size = 31, \
IVB_PIPE_OFFSETS, \
@@ -504,6 +514,7 @@ static const struct intel_device_info vlv_info = {
.has_rps = true,
.display.has_gmch = 1,
.display.has_hotplug = 1,
+ .dma_mask_size = 40,
.ppgtt_type = INTEL_PPGTT_ALIASING,
.ppgtt_size = 31,
.has_snoop = true,
@@ -554,6 +565,7 @@ static const struct intel_device_info hsw_gt3_info = {
G75_FEATURES, \
GEN(8), \
.has_logical_ring_contexts = 1, \
+ .dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
.has_64bit_reloc = 1, \
@@ -602,6 +614,7 @@ static const struct intel_device_info chv_info = {
.has_rps = true,
.has_logical_ring_contexts = 1,
.display.has_gmch = 1,
+ .dma_mask_size = 39,
.ppgtt_type = INTEL_PPGTT_ALIASING,
.ppgtt_size = 32,
.has_reset_engine = 1,
@@ -685,6 +698,7 @@ static const struct intel_device_info skl_gt4_info = {
.has_logical_ring_contexts = 1, \
.has_logical_ring_preemption = 1, \
.has_gt_uc = 1, \
+ .dma_mask_size = 39, \
.ppgtt_type = INTEL_PPGTT_FULL, \
.ppgtt_size = 48, \
.has_reset_engine = 1, \
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index db8496b4c38d..91bb7891c70c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -98,6 +98,7 @@ void intel_device_info_print_static(const struct intel_device_info *info,
drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
drm_printf(p, "ppgtt-size: %d\n", info->ppgtt_size);
drm_printf(p, "ppgtt-type: %d\n", info->ppgtt_type);
+ drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
#define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, yesno(info->name));
DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index cce6a72c5ebc..69c9257c6c6a 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -158,6 +158,8 @@ struct intel_device_info {
enum intel_platform platform;
+ unsigned int dma_mask_size; /* available DMA address bits */
+
enum intel_ppgtt_type ppgtt_type;
unsigned int ppgtt_size; /* log2, e.g. 31/32/48 bits */
--
2.21.0
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^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper
2020-04-17 19:51 [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper Michael J. Ruhl
@ 2020-04-17 19:55 ` Chris Wilson
2020-04-17 19:57 ` Ruhl, Michael J
2020-04-18 1:42 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor setting dma info to a common helper (rev2) Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Chris Wilson @ 2020-04-17 19:55 UTC (permalink / raw)
To: Michael J. Ruhl, intel-gfx
Quoting Michael J. Ruhl (2020-04-17 20:51:07)
> DMA_MASK bit values are different for different generations.
>
> This will become more difficult to manage over time with the open
> coded usage of different versions of the device.
>
> Fix by:
> disallow setting of dma mask in AGP path (< GEN(5) for i915,
> add dma_mask_size to the device info configuration,
> updating open code call sequence to the latest interface,
> refactoring into a common function for setting the dma segment
> and mask info
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
> cc: Brian Welty <brian.welty@intel.com>
> cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>
> ---
> v1: removed i915 depenancy from agp path for dma mask
> Consolidated segment size and work arounds to the helper
> v2: added r-b
You don't need to resend for adding r-b by itself, patchwork will do
that, and the committer should be checking the output from pw. dim then
double checks that we haven't missed anything vital.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper
2020-04-17 19:55 ` Chris Wilson
@ 2020-04-17 19:57 ` Ruhl, Michael J
0 siblings, 0 replies; 6+ messages in thread
From: Ruhl, Michael J @ 2020-04-17 19:57 UTC (permalink / raw)
To: Chris Wilson, intel-gfx
>-----Original Message-----
>From: Chris Wilson <chris@chris-wilson.co.uk>
>Sent: Friday, April 17, 2020 3:55 PM
>To: Ruhl, Michael J <michael.j.ruhl@intel.com>; intel-
>gfx@lists.freedesktop.org
>Subject: Re: [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a
>common helper
>
>Quoting Michael J. Ruhl (2020-04-17 20:51:07)
>> DMA_MASK bit values are different for different generations.
>>
>> This will become more difficult to manage over time with the open
>> coded usage of different versions of the device.
>>
>> Fix by:
>> disallow setting of dma mask in AGP path (< GEN(5) for i915,
>> add dma_mask_size to the device info configuration,
>> updating open code call sequence to the latest interface,
>> refactoring into a common function for setting the dma segment
>> and mask info
>>
>> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Michael J. Ruhl <michael.j.ruhl@intel.com>
>> cc: Brian Welty <brian.welty@intel.com>
>> cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>>
>> ---
>> v1: removed i915 depenancy from agp path for dma mask
>> Consolidated segment size and work arounds to the helper
>> v2: added r-b
>
>You don't need to resend for adding r-b by itself, patchwork will do
>that, and the committer should be checking the output from pw. dim then
>double checks that we haven't missed anything vital.
Cool.
I will refrain from future sends. 😊
M
>-Chris
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor setting dma info to a common helper (rev2)
2020-04-17 19:51 [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper Michael J. Ruhl
2020-04-17 19:55 ` Chris Wilson
@ 2020-04-18 1:42 ` Patchwork
2020-04-18 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-19 21:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-18 1:42 UTC (permalink / raw)
To: Ruhl, Michael J; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor setting dma info to a common helper (rev2)
URL : https://patchwork.freedesktop.org/series/76112/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
/home/cidrm/kernel/Documentation/gpu/i915.rst:610: WARNING: duplicate label gpu/i915:layout, other instance in /home/cidrm/kernel/Documentation/gpu/i915.rst
_______________________________________________
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^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Refactor setting dma info to a common helper (rev2)
2020-04-17 19:51 [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper Michael J. Ruhl
2020-04-17 19:55 ` Chris Wilson
2020-04-18 1:42 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor setting dma info to a common helper (rev2) Patchwork
@ 2020-04-18 1:49 ` Patchwork
2020-04-19 21:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-18 1:49 UTC (permalink / raw)
To: Ruhl, Michael J; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor setting dma info to a common helper (rev2)
URL : https://patchwork.freedesktop.org/series/76112/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8322 -> Patchwork_17359
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/index.html
Changes
-------
No changes found
Participating hosts (51 -> 46)
------------------------------
Additional (1): fi-cml-u2
Missing (6): fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8322 -> Patchwork_17359
CI-20190529: 20190529
CI_DRM_8322: fd447e6b1ee13e6a9731bddc7694552640e8a01e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5599: cdb07101dda33e2fcb0f4c2aa199c47159d88f35 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17359: 66afdcedc70c575c02edaab4d2e961a4f7813d90 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
66afdcedc70c drm/i915: Refactor setting dma info to a common helper
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/index.html
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Refactor setting dma info to a common helper (rev2)
2020-04-17 19:51 [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper Michael J. Ruhl
` (2 preceding siblings ...)
2020-04-18 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2020-04-19 21:10 ` Patchwork
3 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2020-04-19 21:10 UTC (permalink / raw)
To: Ruhl, Michael J; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor setting dma info to a common helper (rev2)
URL : https://patchwork.freedesktop.org/series/76112/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8322_full -> Patchwork_17359_full
====================================================
Summary
-------
**WARNING**
Minor unknown changes coming with Patchwork_17359_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17359_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17359_full:
### IGT changes ###
#### Warnings ####
* igt@gem_workarounds@suspend-resume-context:
- shard-kbl: [INCOMPLETE][1] ([i915#155]) -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl2/igt@gem_workarounds@suspend-resume-context.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl6/igt@gem_workarounds@suspend-resume-context.html
Known issues
------------
Here are the changes found in Patchwork_17359_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_suspend@debugfs-reader:
- shard-kbl: [PASS][3] -> [DMESG-WARN][4] ([i915#180])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl6/igt@i915_suspend@debugfs-reader.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl4/igt@i915_suspend@debugfs-reader.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-random:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#54] / [i915#93] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl1/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-128x42-random.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][7] -> [DMESG-WARN][8] ([i915#180]) +1 similar issue
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_dp_dsc@basic-dsc-enable-edp:
- shard-iclb: [PASS][9] -> [SKIP][10] ([fdo#109349])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-iclb2/igt@kms_dp_dsc@basic-dsc-enable-edp.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-iclb7/igt@kms_dp_dsc@basic-dsc-enable-edp.html
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-kbl: [PASS][11] -> [INCOMPLETE][12] ([i915#155])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl7/igt@kms_frontbuffer_tracking@fbc-suspend.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
- shard-apl: [PASS][13] -> [DMESG-WARN][14] ([i915#180] / [i915#95])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-apl2/igt@kms_frontbuffer_tracking@fbc-suspend.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html
* igt@kms_mmap_write_crc@main:
- shard-kbl: [PASS][15] -> [FAIL][16] ([i915#93] / [i915#95])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl4/igt@kms_mmap_write_crc@main.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl2/igt@kms_mmap_write_crc@main.html
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: [PASS][17] -> [SKIP][18] ([fdo#109441]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-iclb2/igt@kms_psr@psr2_cursor_render.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-iclb4/igt@kms_psr@psr2_cursor_render.html
* igt@kms_setmode@basic:
- shard-skl: [PASS][19] -> [FAIL][20] ([i915#31])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-skl7/igt@kms_setmode@basic.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-skl8/igt@kms_setmode@basic.html
- shard-kbl: [PASS][21] -> [FAIL][22] ([i915#31])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl6/igt@kms_setmode@basic.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl4/igt@kms_setmode@basic.html
#### Possible fixes ####
* igt@gen9_exec_parse@allowed-all:
- shard-glk: [DMESG-WARN][23] ([i915#716]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-glk8/igt@gen9_exec_parse@allowed-all.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-glk7/igt@gen9_exec_parse@allowed-all.html
* igt@kms_draw_crc@draw-method-rgb565-render-ytiled:
- shard-glk: [FAIL][25] ([i915#52] / [i915#54]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-glk6/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-glk5/igt@kms_draw_crc@draw-method-rgb565-render-ytiled.html
* {igt@kms_flip@flip-vs-expired-vblank@c-edp1}:
- shard-skl: [FAIL][27] ([i915#79]) -> [PASS][28]
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-skl3/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +4 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* {igt@kms_flip@plain-flip-ts-check@c-edp1}:
- shard-skl: [FAIL][31] ([i915#34]) -> [PASS][32]
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-skl9/igt@kms_flip@plain-flip-ts-check@c-edp1.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-skl1/igt@kms_flip@plain-flip-ts-check@c-edp1.html
* igt@kms_hdr@bpc-switch:
- shard-skl: [FAIL][33] ([i915#1188]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-skl1/igt@kms_hdr@bpc-switch.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-skl5/igt@kms_hdr@bpc-switch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- shard-kbl: [DMESG-WARN][35] ([i915#180]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-kbl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
* igt@kms_plane_alpha_blend@pipe-a-coverage-7efc:
- shard-skl: [FAIL][37] ([fdo#108145] / [i915#265]) -> [PASS][38] +1 similar issue
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-skl10/igt@kms_plane_alpha_blend@pipe-a-coverage-7efc.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-iclb: [SKIP][39] ([fdo#109441]) -> [PASS][40] +2 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html
* {igt@perf@polling-parameterized}:
- shard-tglb: [FAIL][41] ([i915#1542]) -> [PASS][42]
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-tglb6/igt@perf@polling-parameterized.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-tglb5/igt@perf@polling-parameterized.html
* {igt@perf@polling-small-buf}:
- shard-iclb: [FAIL][43] -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-iclb3/igt@perf@polling-small-buf.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-iclb6/igt@perf@polling-small-buf.html
* {igt@sysfs_timeslice_duration@timeout@vecs0}:
- shard-apl: [FAIL][45] -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-apl2/igt@sysfs_timeslice_duration@timeout@vecs0.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-apl4/igt@sysfs_timeslice_duration@timeout@vecs0.html
#### Warnings ####
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][47] ([i915#454]) -> [SKIP][48] ([i915#468])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8322/shard-tglb5/igt@i915_pm_dc@dc6-psr.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109349]: https://bugs.freedesktop.org/show_bug.cgi?id=109349
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#155]: https://gitlab.freedesktop.org/drm/intel/issues/155
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#34]: https://gitlab.freedesktop.org/drm/intel/issues/34
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
[i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8322 -> Patchwork_17359
CI-20190529: 20190529
CI_DRM_8322: fd447e6b1ee13e6a9731bddc7694552640e8a01e @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5599: cdb07101dda33e2fcb0f4c2aa199c47159d88f35 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17359: 66afdcedc70c575c02edaab4d2e961a4f7813d90 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17359/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2020-04-19 21:10 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-17 19:51 [Intel-gfx] [PATCH v2] drm/i915: Refactor setting dma info to a common helper Michael J. Ruhl
2020-04-17 19:55 ` Chris Wilson
2020-04-17 19:57 ` Ruhl, Michael J
2020-04-18 1:42 ` [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor setting dma info to a common helper (rev2) Patchwork
2020-04-18 1:49 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-04-19 21:10 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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