* [Intel-gfx] [PATCH v25 1/8] drm/i915: Introduce skl_plane_wm_level accessor.
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
` (9 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
For future Gen12 SAGV implementation we need to
seemlessly alter wm levels calculated, depending
on whether we are allowed to enable SAGV or not.
So this accessor will give additional flexibility
to do that.
Currently this accessor is still simply working
as "pass-through" function. This will be changed
in next coming patches from this series.
v2: - plane_id -> plane->id(Ville Syrjälä)
- Moved wm_level var to have more local scope
(Ville Syrjälä)
- Renamed yuv to color_plane(Ville Syrjälä) in
skl_plane_wm_level
v3: - plane->id -> plane_id(this time for real, Ville Syrjälä)
- Changed colorplane id type from boolean to int as index
(Ville Syrjälä)
- Moved crtc_state param so that it is first now
(Ville Syrjälä)
- Moved wm_level declaration to tigher scope in
skl_write_plane_wm(Ville Syrjälä)
v4: - Started to use enum values for color plane
- Do sizeof for a type what we are memset'ing
- Zero out wm_uv as well(Ville Syrjälä)
v5: - Fixed rebase conflict caused by COLOR_PLANE_*
enum removal
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 85 ++++++++++++++++++++++++++-------
1 file changed, 67 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d54833a1578f..b0810d76ad47 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -4574,6 +4574,18 @@ icl_get_total_relative_data_rate(struct intel_crtc_state *crtc_state,
return total_data_rate;
}
+static const struct skl_wm_level *
+skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
+ enum plane_id plane_id,
+ int level,
+ int color_plane)
+{
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -4633,22 +4645,28 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level = ilk_wm_max_level(dev_priv); level >= 0; level--) {
blocks = 0;
+
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
if (plane_id == PLANE_CURSOR) {
- if (wm->wm[level].min_ddb_alloc > total[PLANE_CURSOR]) {
+ if (wm_level->min_ddb_alloc > total[PLANE_CURSOR]) {
drm_WARN_ON(&dev_priv->drm,
- wm->wm[level].min_ddb_alloc != U16_MAX);
+ wm_level->min_ddb_alloc != U16_MAX);
blocks = U32_MAX;
break;
}
continue;
}
- blocks += wm->wm[level].min_ddb_alloc;
- blocks += wm->uv_wm[level].min_ddb_alloc;
+ blocks += wm_level->min_ddb_alloc;
+ blocks += wm_uv_level->min_ddb_alloc;
}
if (blocks <= alloc_size) {
@@ -4671,11 +4689,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* proportional to its relative data rate.
*/
for_each_plane_id_on_crtc(crtc, plane_id) {
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
u64 rate;
u16 extra;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
+
if (plane_id == PLANE_CURSOR)
continue;
@@ -4690,7 +4713,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- total[plane_id] = wm->wm[level].min_ddb_alloc + extra;
+ total[plane_id] = wm_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
@@ -4701,7 +4724,7 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
extra = min_t(u16, alloc_size,
DIV64_U64_ROUND_UP(alloc_size * rate,
total_data_rate));
- uv_total[plane_id] = wm->uv_wm[level].min_ddb_alloc + extra;
+ uv_total[plane_id] = wm_uv_level->min_ddb_alloc + extra;
alloc_size -= extra;
total_data_rate -= rate;
}
@@ -4744,9 +4767,16 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
for (level++; level <= ilk_wm_max_level(dev_priv); level++) {
for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_wm_level *wm_level;
+ const struct skl_wm_level *wm_uv_level;
struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane_id];
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 0);
+ wm_uv_level = skl_plane_wm_level(crtc_state, plane_id,
+ level, 1);
+
/*
* We only disable the watermarks for each plane if
* they exceed the ddb allocation of said plane. This
@@ -4759,9 +4789,13 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
* planes must be enabled before the level will be used."
* So this is actually safe to do.
*/
- if (wm->wm[level].min_ddb_alloc > total[plane_id] ||
- wm->uv_wm[level].min_ddb_alloc > uv_total[plane_id])
- memset(&wm->wm[level], 0, sizeof(wm->wm[level]));
+ if (wm_level->min_ddb_alloc > total[plane_id] ||
+ wm_uv_level->min_ddb_alloc > uv_total[plane_id]) {
+ memset(&wm->wm[level], 0,
+ sizeof(wm->wm[level]));
+ memset(&wm->uv_wm[level], 0,
+ sizeof(wm->uv_wm[level]));
+ }
/*
* Wa_1408961008:icl, ehl
@@ -4769,9 +4803,14 @@ skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
*/
if (IS_GEN(dev_priv, 11) &&
level == 1 && wm->wm[0].plane_en) {
- wm->wm[level].plane_res_b = wm->wm[0].plane_res_b;
- wm->wm[level].plane_res_l = wm->wm[0].plane_res_l;
- wm->wm[level].ignore_lines = wm->wm[0].ignore_lines;
+ wm_level = skl_plane_wm_level(crtc_state, plane_id,
+ 0, 0);
+ wm->wm[level].plane_res_b =
+ wm_level->plane_res_b;
+ wm->wm[level].plane_res_l =
+ wm_level->plane_res_l;
+ wm->wm[level].ignore_lines =
+ wm_level->ignore_lines;
}
}
}
@@ -5385,8 +5424,13 @@ void skl_write_plane_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_uv[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id),
&wm->trans_wm);
@@ -5419,8 +5463,13 @@ void skl_write_cursor_wm(struct intel_plane *plane,
&crtc_state->wm.skl.plane_ddb_y[plane_id];
for (level = 0; level <= max_level; level++) {
+ const struct skl_wm_level *wm_level;
+ int color_plane = 0;
+
+ wm_level = skl_plane_wm_level(crtc_state, plane_id, level, color_plane);
+
skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
- &wm->wm[level]);
+ wm_level);
}
skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 1/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-21 16:00 ` Ville Syrjälä
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 3/8] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
` (8 subsequent siblings)
10 siblings, 1 reply; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Future platforms require per-crtc SAGV evaluation
and serializing global state when those are changed
from different commits.
v2: - Add has_sagv check to intel_crtc_can_enable_sagv
so that it sets bit in reject mask.
- Use bw_state in intel_pre/post_plane_enable_sagv
instead of atomic state
v3: - Fixed rebase conflict, now using
intel_atomic_crtc_state_for_each_plane_state in
order to call it from atomic check
v4: - Use fb modifier from plane state
v5: - Make intel_has_sagv static again(Ville)
- Removed unnecessary NULL assignments(Ville)
- Removed unnecessary SAGV debug(Ville)
- Call intel_compute_sagv_mask only for modesets(Ville)
- Serialize global state only if sagv results change, but
not mask itself(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
drivers/gpu/drm/i915/intel_pm.h | 3 +-
3 files changed, 93 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ac004d6f4276..d6df91058223 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -18,6 +18,12 @@ struct intel_crtc_state;
struct intel_bw_state {
struct intel_global_state base;
+ /*
+ * Contains a bit mask, used to determine, whether correspondent
+ * pipe allows SAGV or not.
+ */
+ u8 pipe_sagv_reject;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index b0810d76ad47..d06a1a3713ed 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -43,6 +43,7 @@
#include "i915_fixed.h"
#include "i915_irq.h"
#include "i915_trace.h"
+#include "display/intel_bw.h"
#include "intel_pm.h"
#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
@@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
- if (!intel_can_enable_sagv(state))
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (!intel_can_enable_sagv(new_bw_state))
intel_disable_sagv(dev_priv);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ const struct intel_bw_state *new_bw_state;
- if (intel_can_enable_sagv(state))
+ /*
+ * Just return if we can't control SAGV or don't have it.
+ * This is different from situation when we have SAGV but just can't
+ * afford it due to DBuf limitation - in case if SAGV is completely
+ * disabled in a BIOS, we are not even allowed to send a PCode request,
+ * as it will throw an error. So have to check it here.
+ */
+ if (!intel_has_sagv(dev_priv))
+ return;
+
+ new_bw_state = intel_atomic_get_new_bw_state(state);
+ if (!new_bw_state)
+ return;
+
+ if (intel_can_enable_sagv(new_bw_state))
intel_enable_sagv(dev_priv);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct drm_device *dev = crtc_state->uapi.crtc->dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
+ const struct intel_plane_state *plane_state;
int level, latency;
+ if (!intel_has_sagv(dev_priv))
+ return false;
+
if (!crtc_state->hw.active)
return true;
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
- for_each_intel_plane_on_crtc(dev, crtc, plane) {
+ intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
const struct skl_plane_wm *wm =
&crtc_state->wm.skl.optimal.planes[plane->id];
@@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
latency = dev_priv->wm.skl_latency[level];
if (skl_needs_memory_bw_wa(dev_priv) &&
- plane->base.state->fb->modifier ==
+ plane_state->uapi.fb->modifier ==
I915_FORMAT_MOD_X_TILED)
latency += 15;
@@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
-bool intel_can_enable_sagv(struct intel_atomic_state *state)
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
- struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ return bw_state->pipe_sagv_reject == 0;
+}
+
+static int intel_compute_sagv_mask(struct intel_atomic_state *state)
+{
+ int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *crtc_state;
- enum pipe pipe;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_bw_state *new_bw_state = NULL;
+ const struct intel_bw_state *old_bw_state = NULL;
+ int i;
- if (!intel_has_sagv(dev_priv))
- return false;
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- /*
- * If there are no active CRTCs, no additional checks need be performed
- */
- if (hweight8(state->active_pipes) == 0)
- return true;
+ old_bw_state = intel_atomic_get_old_bw_state(state);
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
+ if (intel_crtc_can_enable_sagv(new_crtc_state))
+ new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
+ else
+ new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
+ }
- /* Since we're now guaranteed to only have one active CRTC... */
- pipe = ffs(state->active_pipes) - 1;
- crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
- crtc_state = to_intel_crtc_state(crtc->base.state);
+ if (!new_bw_state)
+ return 0;
- return intel_crtc_can_enable_sagv(crtc_state);
+ if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
/*
@@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
if (ret)
return ret;
+ if (state->modeset) {
+ ret = intel_compute_sagv_mask(state);
+ if (ret)
+ return ret;
+ }
+
/*
* skl_compute_ddb() will have adjusted the final watermarks
* based on how much ddb is available. Now we can actually
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index 9a6036ab0f90..fd1dc422e6c5 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -9,6 +9,7 @@
#include <linux/types.h>
#include "i915_reg.h"
+#include "display/intel_bw.h"
struct drm_device;
struct drm_i915_private;
@@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
-bool intel_can_enable_sagv(struct intel_atomic_state *state);
+bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
@ 2020-04-21 16:00 ` Ville Syrjälä
2020-04-22 7:50 ` Lisovskiy, Stanislav
0 siblings, 1 reply; 17+ messages in thread
From: Ville Syrjälä @ 2020-04-21 16:00 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: jani.nikula, intel-gfx
On Mon, Apr 20, 2020 at 02:14:10PM +0300, Stanislav Lisovskiy wrote:
> Future platforms require per-crtc SAGV evaluation
> and serializing global state when those are changed
> from different commits.
>
> v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> so that it sets bit in reject mask.
> - Use bw_state in intel_pre/post_plane_enable_sagv
> instead of atomic state
>
> v3: - Fixed rebase conflict, now using
> intel_atomic_crtc_state_for_each_plane_state in
> order to call it from atomic check
> v4: - Use fb modifier from plane state
>
> v5: - Make intel_has_sagv static again(Ville)
> - Removed unnecessary NULL assignments(Ville)
> - Removed unnecessary SAGV debug(Ville)
> - Call intel_compute_sagv_mask only for modesets(Ville)
> - Serialize global state only if sagv results change, but
> not mask itself(Ville)
>
> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> Cc: Ville Syrjälä <ville.syrjala@intel.com>
> Cc: James Ausmus <james.ausmus@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> drivers/gpu/drm/i915/intel_pm.h | 3 +-
> 3 files changed, 93 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> index ac004d6f4276..d6df91058223 100644
> --- a/drivers/gpu/drm/i915/display/intel_bw.h
> +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> @@ -18,6 +18,12 @@ struct intel_crtc_state;
> struct intel_bw_state {
> struct intel_global_state base;
>
> + /*
> + * Contains a bit mask, used to determine, whether correspondent
> + * pipe allows SAGV or not.
> + */
> + u8 pipe_sagv_reject;
> +
> unsigned int data_rate[I915_MAX_PIPES];
> u8 num_active_planes[I915_MAX_PIPES];
> };
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b0810d76ad47..d06a1a3713ed 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -43,6 +43,7 @@
> #include "i915_fixed.h"
> #include "i915_irq.h"
> #include "i915_trace.h"
> +#include "display/intel_bw.h"
> #include "intel_pm.h"
> #include "intel_sideband.h"
> #include "../../../platform/x86/intel_ips.h"
> @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_bw_state *new_bw_state;
>
> - if (!intel_can_enable_sagv(state))
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + * This is different from situation when we have SAGV but just can't
> + * afford it due to DBuf limitation - in case if SAGV is completely
> + * disabled in a BIOS, we are not even allowed to send a PCode request,
> + * as it will throw an error. So have to check it here.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> + if (!new_bw_state)
> + return;
> +
> + if (!intel_can_enable_sagv(new_bw_state))
> intel_disable_sagv(dev_priv);
> }
>
> void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + const struct intel_bw_state *new_bw_state;
>
> - if (intel_can_enable_sagv(state))
> + /*
> + * Just return if we can't control SAGV or don't have it.
> + * This is different from situation when we have SAGV but just can't
> + * afford it due to DBuf limitation - in case if SAGV is completely
> + * disabled in a BIOS, we are not even allowed to send a PCode request,
> + * as it will throw an error. So have to check it here.
> + */
> + if (!intel_has_sagv(dev_priv))
> + return;
> +
> + new_bw_state = intel_atomic_get_new_bw_state(state);
> + if (!new_bw_state)
> + return;
> +
> + if (intel_can_enable_sagv(new_bw_state))
> intel_enable_sagv(dev_priv);
> }
>
> static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> {
> - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> struct intel_plane *plane;
> + const struct intel_plane_state *plane_state;
> int level, latency;
>
> + if (!intel_has_sagv(dev_priv))
> + return false;
> +
> if (!crtc_state->hw.active)
> return true;
>
> + /*
> + * SKL+ workaround: bspec recommends we disable SAGV when we have
> + * more then one pipe enabled
> + */
> + if (hweight8(state->active_pipes) > 1)
> + return false;
> +
> if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> return false;
>
> - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> const struct skl_plane_wm *wm =
> &crtc_state->wm.skl.optimal.planes[plane->id];
>
> @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> latency = dev_priv->wm.skl_latency[level];
>
> if (skl_needs_memory_bw_wa(dev_priv) &&
> - plane->base.state->fb->modifier ==
> + plane_state->uapi.fb->modifier ==
> I915_FORMAT_MOD_X_TILED)
> latency += 15;
>
> @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> return true;
> }
>
> -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> + return bw_state->pipe_sagv_reject == 0;
> +}
> +
> +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> +{
> + int ret;
> struct intel_crtc *crtc;
> - const struct intel_crtc_state *crtc_state;
> - enum pipe pipe;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_bw_state *new_bw_state = NULL;
> + const struct intel_bw_state *old_bw_state = NULL;
> + int i;
>
> - if (!intel_has_sagv(dev_priv))
> - return false;
> + for_each_new_intel_crtc_in_state(state, crtc,
> + new_crtc_state, i) {
> + new_bw_state = intel_atomic_get_bw_state(state);
> + if (IS_ERR(new_bw_state))
> + return PTR_ERR(new_bw_state);
>
> - /*
> - * If there are no active CRTCs, no additional checks need be performed
> - */
> - if (hweight8(state->active_pipes) == 0)
> - return true;
> + old_bw_state = intel_atomic_get_old_bw_state(state);
>
> - /*
> - * SKL+ workaround: bspec recommends we disable SAGV when we have
> - * more then one pipe enabled
> - */
> - if (hweight8(state->active_pipes) > 1)
> - return false;
> + if (intel_crtc_can_enable_sagv(new_crtc_state))
> + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> + else
> + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> + }
>
> - /* Since we're now guaranteed to only have one active CRTC... */
> - pipe = ffs(state->active_pipes) - 1;
> - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> - crtc_state = to_intel_crtc_state(crtc->base.state);
> + if (!new_bw_state)
> + return 0;
>
> - return intel_crtc_can_enable_sagv(crtc_state);
> + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
Missing the lock_global_state() for the old_maks != new_mask case.
Otherwise seems fine.
Now I believe we need to separate state->modeset from sag, as I
mentioned in the previous review. Please take care of that stuff
before we continue with the rest of this series.
> + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> }
>
> /*
> @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> if (ret)
> return ret;
>
> + if (state->modeset) {
> + ret = intel_compute_sagv_mask(state);
> + if (ret)
> + return ret;
> + }
> +
> /*
> * skl_compute_ddb() will have adjusted the final watermarks
> * based on how much ddb is available. Now we can actually
> diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> index 9a6036ab0f90..fd1dc422e6c5 100644
> --- a/drivers/gpu/drm/i915/intel_pm.h
> +++ b/drivers/gpu/drm/i915/intel_pm.h
> @@ -9,6 +9,7 @@
> #include <linux/types.h>
>
> #include "i915_reg.h"
> +#include "display/intel_bw.h"
>
> struct drm_device;
> struct drm_i915_private;
> @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> struct skl_pipe_wm *out);
> void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> int intel_enable_sagv(struct drm_i915_private *dev_priv);
> int intel_disable_sagv(struct drm_i915_private *dev_priv);
> void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> --
> 2.24.1.485.gad05a3d8e5
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-21 16:00 ` Ville Syrjälä
@ 2020-04-22 7:50 ` Lisovskiy, Stanislav
2020-04-22 16:38 ` Ville Syrjälä
0 siblings, 1 reply; 17+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-22 7:50 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: jani.nikula, intel-gfx
On Tue, Apr 21, 2020 at 07:00:38PM +0300, Ville Syrjälä wrote:
> On Mon, Apr 20, 2020 at 02:14:10PM +0300, Stanislav Lisovskiy wrote:
> > Future platforms require per-crtc SAGV evaluation
> > and serializing global state when those are changed
> > from different commits.
> >
> > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > so that it sets bit in reject mask.
> > - Use bw_state in intel_pre/post_plane_enable_sagv
> > instead of atomic state
> >
> > v3: - Fixed rebase conflict, now using
> > intel_atomic_crtc_state_for_each_plane_state in
> > order to call it from atomic check
> > v4: - Use fb modifier from plane state
> >
> > v5: - Make intel_has_sagv static again(Ville)
> > - Removed unnecessary NULL assignments(Ville)
> > - Removed unnecessary SAGV debug(Ville)
> > - Call intel_compute_sagv_mask only for modesets(Ville)
> > - Serialize global state only if sagv results change, but
> > not mask itself(Ville)
> >
> > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > Cc: James Ausmus <james.ausmus@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > 3 files changed, 93 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > index ac004d6f4276..d6df91058223 100644
> > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > struct intel_bw_state {
> > struct intel_global_state base;
> >
> > + /*
> > + * Contains a bit mask, used to determine, whether correspondent
> > + * pipe allows SAGV or not.
> > + */
> > + u8 pipe_sagv_reject;
> > +
> > unsigned int data_rate[I915_MAX_PIPES];
> > u8 num_active_planes[I915_MAX_PIPES];
> > };
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index b0810d76ad47..d06a1a3713ed 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -43,6 +43,7 @@
> > #include "i915_fixed.h"
> > #include "i915_irq.h"
> > #include "i915_trace.h"
> > +#include "display/intel_bw.h"
> > #include "intel_pm.h"
> > #include "intel_sideband.h"
> > #include "../../../platform/x86/intel_ips.h"
> > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_bw_state *new_bw_state;
> >
> > - if (!intel_can_enable_sagv(state))
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + * This is different from situation when we have SAGV but just can't
> > + * afford it due to DBuf limitation - in case if SAGV is completely
> > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > + * as it will throw an error. So have to check it here.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > + if (!new_bw_state)
> > + return;
> > +
> > + if (!intel_can_enable_sagv(new_bw_state))
> > intel_disable_sagv(dev_priv);
> > }
> >
> > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + const struct intel_bw_state *new_bw_state;
> >
> > - if (intel_can_enable_sagv(state))
> > + /*
> > + * Just return if we can't control SAGV or don't have it.
> > + * This is different from situation when we have SAGV but just can't
> > + * afford it due to DBuf limitation - in case if SAGV is completely
> > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > + * as it will throw an error. So have to check it here.
> > + */
> > + if (!intel_has_sagv(dev_priv))
> > + return;
> > +
> > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > + if (!new_bw_state)
> > + return;
> > +
> > + if (intel_can_enable_sagv(new_bw_state))
> > intel_enable_sagv(dev_priv);
> > }
> >
> > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > {
> > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > - struct drm_i915_private *dev_priv = to_i915(dev);
> > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > struct intel_plane *plane;
> > + const struct intel_plane_state *plane_state;
> > int level, latency;
> >
> > + if (!intel_has_sagv(dev_priv))
> > + return false;
> > +
> > if (!crtc_state->hw.active)
> > return true;
> >
> > + /*
> > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > + * more then one pipe enabled
> > + */
> > + if (hweight8(state->active_pipes) > 1)
> > + return false;
> > +
> > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > return false;
> >
> > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > const struct skl_plane_wm *wm =
> > &crtc_state->wm.skl.optimal.planes[plane->id];
> >
> > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > latency = dev_priv->wm.skl_latency[level];
> >
> > if (skl_needs_memory_bw_wa(dev_priv) &&
> > - plane->base.state->fb->modifier ==
> > + plane_state->uapi.fb->modifier ==
> > I915_FORMAT_MOD_X_TILED)
> > latency += 15;
> >
> > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > return true;
> > }
> >
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > + return bw_state->pipe_sagv_reject == 0;
> > +}
> > +
> > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > +{
> > + int ret;
> > struct intel_crtc *crtc;
> > - const struct intel_crtc_state *crtc_state;
> > - enum pipe pipe;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_bw_state *new_bw_state = NULL;
> > + const struct intel_bw_state *old_bw_state = NULL;
> > + int i;
> >
> > - if (!intel_has_sagv(dev_priv))
> > - return false;
> > + for_each_new_intel_crtc_in_state(state, crtc,
> > + new_crtc_state, i) {
> > + new_bw_state = intel_atomic_get_bw_state(state);
> > + if (IS_ERR(new_bw_state))
> > + return PTR_ERR(new_bw_state);
> >
> > - /*
> > - * If there are no active CRTCs, no additional checks need be performed
> > - */
> > - if (hweight8(state->active_pipes) == 0)
> > - return true;
> > + old_bw_state = intel_atomic_get_old_bw_state(state);
> >
> > - /*
> > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > - * more then one pipe enabled
> > - */
> > - if (hweight8(state->active_pipes) > 1)
> > - return false;
> > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > + else
> > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > + }
> >
> > - /* Since we're now guaranteed to only have one active CRTC... */
> > - pipe = ffs(state->active_pipes) - 1;
> > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > + if (!new_bw_state)
> > + return 0;
> >
> > - return intel_crtc_can_enable_sagv(crtc_state);
> > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
>
> Missing the lock_global_state() for the old_maks != new_mask case.
> Otherwise seems fine.
Yep, however most likely if SAGV state had changed, allowed qgv points will change
and then you'll have to serialize commits anyway.
>
> Now I believe we need to separate state->modeset from sag, as I
> mentioned in the previous review. Please take care of that stuff
> before we continue with the rest of this series.
Ah it's this active_pipes discussion again.. So the problem is that
we set active_pipes only for modeset commits as I understand.
One thing which worries me here, is that duplication of active_pipes
in semantically different states seems redundant imo, i.e the more
states like bw_state, cdclk_state, dbuf_state and etc you are going
to introduce - the more this duplication will happen.
I think what is missing here(I mentioned this also in dbuf review)
is that we need a separate state containing active pipes, which can
be then queried, each time we need to get active_pipes.
In order to separate SAGV from modeset to use active_pipes, we basically
need to populate active pipes in a non-modeset commits, as we can't just
read it from dev_priv right away, we simply need one more global state
object containing this, which we can query just the same way we do for
cdclk_state and bw_state. I.e you just have one crtc lock grabbed and
copy this old global state to new state.
This would eliminate the need in duplicating that field in other states,
also reducing probability of some issues with that duplication.
Not sure, may be there are some arguments, why we have to duplicate it
- at least would like to know those then :D
IMO idea to split global state into a pool of separately maintainable objects
was great - this brings much more flexibility to driver code, so lets
utilize this.
Stan
>
> > + ret = intel_atomic_serialize_global_state(&new_bw_state->base);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > }
> >
> > /*
> > @@ -5860,6 +5911,12 @@ skl_compute_wm(struct intel_atomic_state *state)
> > if (ret)
> > return ret;
> >
> > + if (state->modeset) {
> > + ret = intel_compute_sagv_mask(state);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > /*
> > * skl_compute_ddb() will have adjusted the final watermarks
> > * based on how much ddb is available. Now we can actually
> > diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
> > index 9a6036ab0f90..fd1dc422e6c5 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.h
> > +++ b/drivers/gpu/drm/i915/intel_pm.h
> > @@ -9,6 +9,7 @@
> > #include <linux/types.h>
> >
> > #include "i915_reg.h"
> > +#include "display/intel_bw.h"
> >
> > struct drm_device;
> > struct drm_i915_private;
> > @@ -41,7 +42,7 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
> > struct skl_pipe_wm *out);
> > void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
> > void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
> > -bool intel_can_enable_sagv(struct intel_atomic_state *state);
> > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
> > int intel_enable_sagv(struct drm_i915_private *dev_priv);
> > int intel_disable_sagv(struct drm_i915_private *dev_priv);
> > void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
> > --
> > 2.24.1.485.gad05a3d8e5
>
> --
> Ville Syrjälä
> Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation
2020-04-22 7:50 ` Lisovskiy, Stanislav
@ 2020-04-22 16:38 ` Ville Syrjälä
0 siblings, 0 replies; 17+ messages in thread
From: Ville Syrjälä @ 2020-04-22 16:38 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: jani.nikula, intel-gfx
On Wed, Apr 22, 2020 at 10:50:22AM +0300, Lisovskiy, Stanislav wrote:
> On Tue, Apr 21, 2020 at 07:00:38PM +0300, Ville Syrjälä wrote:
> > On Mon, Apr 20, 2020 at 02:14:10PM +0300, Stanislav Lisovskiy wrote:
> > > Future platforms require per-crtc SAGV evaluation
> > > and serializing global state when those are changed
> > > from different commits.
> > >
> > > v2: - Add has_sagv check to intel_crtc_can_enable_sagv
> > > so that it sets bit in reject mask.
> > > - Use bw_state in intel_pre/post_plane_enable_sagv
> > > instead of atomic state
> > >
> > > v3: - Fixed rebase conflict, now using
> > > intel_atomic_crtc_state_for_each_plane_state in
> > > order to call it from atomic check
> > > v4: - Use fb modifier from plane state
> > >
> > > v5: - Make intel_has_sagv static again(Ville)
> > > - Removed unnecessary NULL assignments(Ville)
> > > - Removed unnecessary SAGV debug(Ville)
> > > - Call intel_compute_sagv_mask only for modesets(Ville)
> > > - Serialize global state only if sagv results change, but
> > > not mask itself(Ville)
> > >
> > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> > > Cc: Ville Syrjälä <ville.syrjala@intel.com>
> > > Cc: James Ausmus <james.ausmus@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/display/intel_bw.h | 6 ++
> > > drivers/gpu/drm/i915/intel_pm.c | 113 ++++++++++++++++++------
> > > drivers/gpu/drm/i915/intel_pm.h | 3 +-
> > > 3 files changed, 93 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
> > > index ac004d6f4276..d6df91058223 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_bw.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h
> > > @@ -18,6 +18,12 @@ struct intel_crtc_state;
> > > struct intel_bw_state {
> > > struct intel_global_state base;
> > >
> > > + /*
> > > + * Contains a bit mask, used to determine, whether correspondent
> > > + * pipe allows SAGV or not.
> > > + */
> > > + u8 pipe_sagv_reject;
> > > +
> > > unsigned int data_rate[I915_MAX_PIPES];
> > > u8 num_active_planes[I915_MAX_PIPES];
> > > };
> > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > > index b0810d76ad47..d06a1a3713ed 100644
> > > --- a/drivers/gpu/drm/i915/intel_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > > @@ -43,6 +43,7 @@
> > > #include "i915_fixed.h"
> > > #include "i915_irq.h"
> > > #include "i915_trace.h"
> > > +#include "display/intel_bw.h"
> > > #include "intel_pm.h"
> > > #include "intel_sideband.h"
> > > #include "../../../platform/x86/intel_ips.h"
> > > @@ -3760,34 +3761,75 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
> > > void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + const struct intel_bw_state *new_bw_state;
> > >
> > > - if (!intel_can_enable_sagv(state))
> > > + /*
> > > + * Just return if we can't control SAGV or don't have it.
> > > + * This is different from situation when we have SAGV but just can't
> > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > + * as it will throw an error. So have to check it here.
> > > + */
> > > + if (!intel_has_sagv(dev_priv))
> > > + return;
> > > +
> > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > + if (!new_bw_state)
> > > + return;
> > > +
> > > + if (!intel_can_enable_sagv(new_bw_state))
> > > intel_disable_sagv(dev_priv);
> > > }
> > >
> > > void intel_sagv_post_plane_update(struct intel_atomic_state *state)
> > > {
> > > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + const struct intel_bw_state *new_bw_state;
> > >
> > > - if (intel_can_enable_sagv(state))
> > > + /*
> > > + * Just return if we can't control SAGV or don't have it.
> > > + * This is different from situation when we have SAGV but just can't
> > > + * afford it due to DBuf limitation - in case if SAGV is completely
> > > + * disabled in a BIOS, we are not even allowed to send a PCode request,
> > > + * as it will throw an error. So have to check it here.
> > > + */
> > > + if (!intel_has_sagv(dev_priv))
> > > + return;
> > > +
> > > + new_bw_state = intel_atomic_get_new_bw_state(state);
> > > + if (!new_bw_state)
> > > + return;
> > > +
> > > + if (intel_can_enable_sagv(new_bw_state))
> > > intel_enable_sagv(dev_priv);
> > > }
> > >
> > > static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
> > > {
> > > - struct drm_device *dev = crtc_state->uapi.crtc->dev;
> > > - struct drm_i915_private *dev_priv = to_i915(dev);
> > > + struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
> > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > > struct intel_plane *plane;
> > > + const struct intel_plane_state *plane_state;
> > > int level, latency;
> > >
> > > + if (!intel_has_sagv(dev_priv))
> > > + return false;
> > > +
> > > if (!crtc_state->hw.active)
> > > return true;
> > >
> > > + /*
> > > + * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > + * more then one pipe enabled
> > > + */
> > > + if (hweight8(state->active_pipes) > 1)
> > > + return false;
> > > +
> > > if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
> > > return false;
> > >
> > > - for_each_intel_plane_on_crtc(dev, crtc, plane) {
> > > + intel_atomic_crtc_state_for_each_plane_state(plane, plane_state, crtc_state) {
> > > const struct skl_plane_wm *wm =
> > > &crtc_state->wm.skl.optimal.planes[plane->id];
> > >
> > > @@ -3803,7 +3845,7 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > latency = dev_priv->wm.skl_latency[level];
> > >
> > > if (skl_needs_memory_bw_wa(dev_priv) &&
> > > - plane->base.state->fb->modifier ==
> > > + plane_state->uapi.fb->modifier ==
> > > I915_FORMAT_MOD_X_TILED)
> > > latency += 15;
> > >
> > > @@ -3819,35 +3861,44 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
> > > return true;
> > > }
> > >
> > > -bool intel_can_enable_sagv(struct intel_atomic_state *state)
> > > +bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
> > > {
> > > - struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > > + return bw_state->pipe_sagv_reject == 0;
> > > +}
> > > +
> > > +static int intel_compute_sagv_mask(struct intel_atomic_state *state)
> > > +{
> > > + int ret;
> > > struct intel_crtc *crtc;
> > > - const struct intel_crtc_state *crtc_state;
> > > - enum pipe pipe;
> > > + struct intel_crtc_state *new_crtc_state;
> > > + struct intel_bw_state *new_bw_state = NULL;
> > > + const struct intel_bw_state *old_bw_state = NULL;
> > > + int i;
> > >
> > > - if (!intel_has_sagv(dev_priv))
> > > - return false;
> > > + for_each_new_intel_crtc_in_state(state, crtc,
> > > + new_crtc_state, i) {
> > > + new_bw_state = intel_atomic_get_bw_state(state);
> > > + if (IS_ERR(new_bw_state))
> > > + return PTR_ERR(new_bw_state);
> > >
> > > - /*
> > > - * If there are no active CRTCs, no additional checks need be performed
> > > - */
> > > - if (hweight8(state->active_pipes) == 0)
> > > - return true;
> > > + old_bw_state = intel_atomic_get_old_bw_state(state);
> > >
> > > - /*
> > > - * SKL+ workaround: bspec recommends we disable SAGV when we have
> > > - * more then one pipe enabled
> > > - */
> > > - if (hweight8(state->active_pipes) > 1)
> > > - return false;
> > > + if (intel_crtc_can_enable_sagv(new_crtc_state))
> > > + new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
> > > + else
> > > + new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
> > > + }
> > >
> > > - /* Since we're now guaranteed to only have one active CRTC... */
> > > - pipe = ffs(state->active_pipes) - 1;
> > > - crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
> > > - crtc_state = to_intel_crtc_state(crtc->base.state);
> > > + if (!new_bw_state)
> > > + return 0;
> > >
> > > - return intel_crtc_can_enable_sagv(crtc_state);
> > > + if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
> >
> > Missing the lock_global_state() for the old_maks != new_mask case.
> > Otherwise seems fine.
>
> Yep, however most likely if SAGV state had changed, allowed qgv points will change
> and then you'll have to serialize commits anyway.
>
> >
> > Now I believe we need to separate state->modeset from sag, as I
> > mentioned in the previous review. Please take care of that stuff
> > before we continue with the rest of this series.
>
> Ah it's this active_pipes discussion again.. So the problem is that
> we set active_pipes only for modeset commits as I understand.
>
> One thing which worries me here, is that duplication of active_pipes
> in semantically different states seems redundant imo, i.e the more
> states like bw_state, cdclk_state, dbuf_state and etc you are going
> to introduce - the more this duplication will happen.
>
> I think what is missing here(I mentioned this also in dbuf review)
> is that we need a separate state containing active pipes, which can
> be then queried, each time we need to get active_pipes.
>
> In order to separate SAGV from modeset to use active_pipes, we basically
> need to populate active pipes in a non-modeset commits, as we can't just
> read it from dev_priv right away, we simply need one more global state
> object containing this, which we can query just the same way we do for
> cdclk_state and bw_state. I.e you just have one crtc lock grabbed and
> copy this old global state to new state.
>
> This would eliminate the need in duplicating that field in other states,
> also reducing probability of some issues with that duplication.
>
> Not sure, may be there are some arguments, why we have to duplicate it
> - at least would like to know those then :D
>
> IMO idea to split global state into a pool of separately maintainable objects
> was great - this brings much more flexibility to driver code, so lets
> utilize this.
Introducing yet another state just for this little thing couples
everything together which I don't like. IMO duplicating is fine unless
we start to accumulate a more singificant chunk of state that also
needs to be shared across a lot of other places.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] [PATCH v25 3/8] drm/i915: Separate icl and skl SAGV checking
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 1/8] drm/i915: Introduce skl_plane_wm_level accessor Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 2/8] drm/i915: Use bw state for per crtc SAGV evaluation Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 4/8] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
` (7 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Introduce platform dependent SAGV checking in
combination with bandwidth state pipe SAGV mask.
v2, v3, v4: Fix rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 38 ++++++++++++++++++++++++---------
1 file changed, 28 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d06a1a3713ed..d720d40a178e 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3806,7 +3806,6 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
{
- struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
struct intel_plane *plane;
@@ -3819,13 +3818,6 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
if (!crtc_state->hw.active)
return true;
- /*
- * SKL+ workaround: bspec recommends we disable SAGV when we have
- * more then one pipe enabled
- */
- if (hweight8(state->active_pipes) > 1)
- return false;
-
if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
return false;
@@ -3861,6 +3853,24 @@ static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state
return true;
}
+static bool skl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
+ /*
+ * SKL+ workaround: bspec recommends we disable SAGV when we have
+ * more then one pipe enabled
+ */
+ if (hweight8(state->active_pipes) > 1)
+ return false;
+
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
+static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ return intel_crtc_can_enable_sagv(crtc_state);
+}
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3868,22 +3878,30 @@ bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
static int intel_compute_sagv_mask(struct intel_atomic_state *state)
{
+ struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- struct intel_crtc_state *new_crtc_state;
+ const struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
for_each_new_intel_crtc_in_state(state, crtc,
new_crtc_state, i) {
+ bool can_sagv;
+
new_bw_state = intel_atomic_get_bw_state(state);
if (IS_ERR(new_bw_state))
return PTR_ERR(new_bw_state);
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (intel_crtc_can_enable_sagv(new_crtc_state))
+ if (INTEL_GEN(dev_priv) >= 11)
+ can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
+ else
+ can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
+
+ if (can_sagv)
new_bw_state->pipe_sagv_reject &= ~BIT(crtc->pipe);
else
new_bw_state->pipe_sagv_reject |= BIT(crtc->pipe);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH v25 4/8] drm/i915: Add TGL+ SAGV support
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (2 preceding siblings ...)
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 3/8] drm/i915: Separate icl and skl SAGV checking Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
` (6 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.
v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4: Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 8 +-
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 128 +++++++++++++++++-
3 files changed, 130 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index bae1d89875d6..590b2f23159d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -13947,7 +13947,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
@@ -14002,7 +14004,9 @@ static void verify_wm_state(struct intel_crtc *crtc,
/* Watermarks */
for (level = 0; level <= max_level; level++) {
if (skl_wm_level_equals(&hw_plane_wm->wm[level],
- &sw_plane_wm->wm[level]))
+ &sw_plane_wm->wm[level]) ||
+ (level == 0 && skl_wm_level_equals(&hw_plane_wm->wm[level],
+ &sw_plane_wm->sagv_wm0)))
continue;
drm_err(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index ba8c08145c88..23a425e565a8 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -688,11 +688,14 @@ struct skl_plane_wm {
struct skl_wm_level wm[8];
struct skl_wm_level uv_wm[8];
struct skl_wm_level trans_wm;
+ struct skl_wm_level sagv_wm0;
+ struct skl_wm_level uv_sagv_wm0;
bool is_planar;
};
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
+ bool can_sagv;
};
enum vlv_wm_level {
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d720d40a178e..8c5be15be364 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3871,6 +3871,9 @@ static bool icl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
return intel_crtc_can_enable_sagv(crtc_state);
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
+
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state)
{
return bw_state->pipe_sagv_reject == 0;
@@ -3881,7 +3884,7 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
int ret;
struct intel_crtc *crtc;
- const struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
const struct intel_bw_state *old_bw_state = NULL;
int i;
@@ -3896,7 +3899,9 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
old_bw_state = intel_atomic_get_old_bw_state(state);
- if (INTEL_GEN(dev_priv) >= 11)
+ if (INTEL_GEN(dev_priv) >= 12)
+ can_sagv = tgl_crtc_can_enable_sagv(new_crtc_state);
+ else if (INTEL_GEN(dev_priv) >= 11)
can_sagv = icl_crtc_can_enable_sagv(new_crtc_state);
else
can_sagv = skl_crtc_can_enable_sagv(new_crtc_state);
@@ -3910,6 +3915,24 @@ static int intel_compute_sagv_mask(struct intel_atomic_state *state)
if (!new_bw_state)
return 0;
+ for_each_new_intel_crtc_in_state(state, crtc,
+ new_crtc_state, i) {
+ struct skl_pipe_wm *pipe_wm = &new_crtc_state->wm.skl.optimal;
+
+ /*
+ * Due to drm limitation at commit state, when
+ * changes are written the whole atomic state is
+ * zeroed away => which prevents from using it,
+ * so just sticking it into pipe wm state for
+ * keeping it simple - anyway this is related to wm.
+ * Proper way in ideal universe would be of course not
+ * to lose parent atomic state object from child crtc_state,
+ * and stick to OOP programming principles, which had been
+ * scientifically proven to work.
+ */
+ pipe_wm->can_sagv = intel_can_enable_sagv(new_bw_state);
+ }
+
if (intel_can_enable_sagv(new_bw_state) != intel_can_enable_sagv(old_bw_state)) {
ret = intel_atomic_serialize_global_state(&new_bw_state->base);
if (ret)
@@ -4649,12 +4672,39 @@ skl_plane_wm_level(const struct intel_crtc_state *crtc_state,
int level,
int color_plane)
{
- const struct skl_plane_wm *wm =
- &crtc_state->wm.skl.optimal.planes[plane_id];
+ const struct skl_pipe_wm *pipe_wm = &crtc_state->wm.skl.optimal;
+ const struct skl_plane_wm *wm = &pipe_wm->planes[plane_id];
+
+ if (!level) {
+ if (pipe_wm->can_sagv)
+ return color_plane == 0 ? &wm->sagv_wm0 : &wm->uv_sagv_wm0;
+ }
return color_plane == 0 ? &wm->wm[level] : &wm->uv_wm[level];
}
+static bool
+tgl_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
+{
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ enum plane_id plane_id;
+
+ if (!crtc_state->hw.active)
+ return true;
+
+ for_each_plane_id_on_crtc(crtc, plane_id) {
+ const struct skl_ddb_entry *plane_alloc =
+ &crtc_state->wm.skl.plane_ddb_y[plane_id];
+ const struct skl_plane_wm *wm =
+ &crtc_state->wm.skl.optimal.planes[plane_id];
+
+ if (skl_ddb_entry_size(plane_alloc) < wm->sagv_wm0.min_ddb_alloc)
+ return false;
+ }
+
+ return true;
+}
+
static int
skl_allocate_pipe_ddb(struct intel_crtc_state *crtc_state)
{
@@ -5236,10 +5286,17 @@ static void skl_compute_plane_wm(const struct intel_crtc_state *crtc_state,
static void
skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wm_params,
- struct skl_wm_level *levels)
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
int level, max_level = ilk_wm_max_level(dev_priv);
+ /*
+ * Check which kind of plane is it and based on that calculate
+ * correspondent WM levels.
+ */
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
struct skl_wm_level *result_prev = &levels[0];
for (level = 0; level <= max_level; level++) {
@@ -5253,6 +5310,40 @@ skl_compute_wm_levels(const struct intel_crtc_state *crtc_state,
}
}
+static void skl_compute_sagv_wm(const struct intel_crtc_state *crtc_state,
+ const struct skl_wm_params *wm_params,
+ struct skl_plane_wm *plane_wm,
+ int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
+ struct skl_wm_level *sagv_wm = color_plane == 1 ?
+ &plane_wm->uv_sagv_wm0 : &plane_wm->sagv_wm0;
+ struct skl_wm_level *levels = color_plane == 1 ?
+ plane_wm->uv_wm : plane_wm->wm;
+
+ /*
+ * For Gen12 if it is an L0 we need to also
+ * consider sagv_block_time when calculating
+ * L0 watermark - we will need that when making
+ * a decision whether enable SAGV or not.
+ * For older gens we agreed to copy L0 value for
+ * compatibility.
+ */
+ if ((INTEL_GEN(dev_priv) >= 12)) {
+ u32 latency = dev_priv->wm.skl_latency[0];
+
+ latency += dev_priv->sagv_block_time_us;
+ skl_compute_plane_wm(crtc_state, 0, latency,
+ wm_params, &levels[0],
+ sagv_wm);
+ DRM_DEBUG_KMS("%d L0 blocks required for SAGV vs %d for non-SAGV\n",
+ sagv_wm->min_ddb_alloc, levels[0].min_ddb_alloc);
+ } else {
+ /* Since all members are POD */
+ *sagv_wm = levels[0];
+ }
+}
+
static void skl_compute_transition_wm(const struct intel_crtc_state *crtc_state,
const struct skl_wm_params *wp,
struct skl_plane_wm *wm)
@@ -5333,7 +5424,8 @@ static int skl_build_plane_wm_single(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 0);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 0);
skl_compute_transition_wm(crtc_state, &wm_params, wm);
return 0;
@@ -5355,7 +5447,8 @@ static int skl_build_plane_wm_uv(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- skl_compute_wm_levels(crtc_state, &wm_params, wm->uv_wm);
+ skl_compute_wm_levels(crtc_state, &wm_params, wm, 1);
+ skl_compute_sagv_wm(crtc_state, &wm_params, wm, 1);
return 0;
}
@@ -5740,6 +5833,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
enast(new_wm->wm[7].ignore_lines), new_wm->wm[7].plane_res_l,
enast(new_wm->trans_wm.ignore_lines), new_wm->trans_wm.plane_res_l);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 lines %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_l,
+ new_wm->sagv_wm0.plane_res_l);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] blocks %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5755,6 +5854,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[6].plane_res_b, new_wm->wm[7].plane_res_b,
new_wm->trans_wm.plane_res_b);
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 blocks %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.plane_res_b,
+ new_wm->sagv_wm0.plane_res_b);
+
drm_dbg_kms(&dev_priv->drm,
"[PLANE:%d:%s] min_ddb %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d"
" -> %4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d,%4d\n",
@@ -5769,6 +5874,12 @@ skl_print_wm_changes(struct intel_atomic_state *state)
new_wm->wm[4].min_ddb_alloc, new_wm->wm[5].min_ddb_alloc,
new_wm->wm[6].min_ddb_alloc, new_wm->wm[7].min_ddb_alloc,
new_wm->trans_wm.min_ddb_alloc);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "[PLANE:%d:%s] sagv wm0 min ddb %4d -> %4d\n",
+ plane->base.base.id, plane->base.name,
+ old_wm->sagv_wm0.min_ddb_alloc,
+ new_wm->sagv_wm0.min_ddb_alloc);
}
}
}
@@ -6064,6 +6175,9 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
skl_wm_level_from_reg_val(val, &wm->wm[level]);
}
+ memcpy(&wm->sagv_wm0, &wm->wm[0],
+ sizeof(struct skl_wm_level));
+
if (plane_id != PLANE_CURSOR)
val = I915_READ(PLANE_WM_TRANS(pipe, plane_id));
else
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH v25 5/8] drm/i915: Added required new PCode commands
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (3 preceding siblings ...)
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 4/8] drm/i915: Add TGL+ SAGV support Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
` (5 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
We need a new PCode request commands and reply codes
to be added as a prepartion patch for QGV points
restricting for new SAGV support.
v2: - Extracted those changes into separate patch
(Ville Syrjälä)
v3: - Moved new PCode masks to another place from
PCode commands(Ville)
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 5 +++++
drivers/gpu/drm/i915/intel_sideband.c | 2 ++
2 files changed, 7 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 69332be5ac41..95de5327acf1 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9085,6 +9085,7 @@ enum {
#define GEN7_PCODE_ILLEGAL_DATA 0x3
#define GEN11_PCODE_ILLEGAL_SUBCOMMAND 0x4
#define GEN11_PCODE_LOCKED 0x6
+#define GEN11_PCODE_REJECTED 0x11
#define GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE 0x10
#define GEN6_PCODE_WRITE_RC6VIDS 0x4
#define GEN6_PCODE_READ_RC6VIDS 0x5
@@ -9106,6 +9107,7 @@ enum {
#define ICL_PCODE_MEM_SUBSYSYSTEM_INFO 0xd
#define ICL_PCODE_MEM_SS_READ_GLOBAL_INFO (0x0 << 8)
#define ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point) (((point) << 16) | (0x1 << 8))
+#define ICL_PCODE_SAGV_DE_MEM_SS_CONFIG 0xe
#define GEN6_PCODE_READ_D_COMP 0x10
#define GEN6_PCODE_WRITE_D_COMP 0x11
#define ICL_PCODE_EXIT_TCCOLD 0x12
@@ -9139,6 +9141,9 @@ enum {
#define GEN8_GT_SLICE_INFO _MMIO(0x138064)
#define GEN8_LSLICESTAT_MASK 0x7
+#define GEN11_PCODE_POINTS_RESTRICTED 0x0
+#define GEN11_PCODE_POINTS_RESTRICTED_MASK 0x1
+
#define CHV_POWER_SS0_SIG1 _MMIO(0xa720)
#define CHV_POWER_SS1_SIG1 _MMIO(0xa728)
#define CHV_SS_PG_ENABLE (1 << 1)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 3f13baaef058..b01f15017ae4 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -371,6 +371,8 @@ static inline int gen7_check_mailbox_status(u32 mbox)
return -ENXIO;
case GEN11_PCODE_LOCKED:
return -EBUSY;
+ case GEN11_PCODE_REJECTED:
+ return -EACCES;
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH v25 6/8] drm/i915: Rename bw_state to new_bw_state
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (4 preceding siblings ...)
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 5/8] drm/i915: Added required new PCode commands Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
` (4 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
That is a preparation patch before next one where we
introduce old_bw_state and a bunch of other changes
as well.
In a review comment it was suggested to split out
at least that renaming into a separate patch, what
is done here.
v2: Removed spurious space
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 24 ++++++++++++------------
1 file changed, 12 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 4aa54fcb0629..6e7cc3a4f1aa 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -414,7 +414,7 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
- struct intel_bw_state *bw_state = NULL;
+ struct intel_bw_state *new_bw_state = NULL;
unsigned int data_rate, max_data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
@@ -443,29 +443,29 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
old_active_planes == new_active_planes)
continue;
- bw_state = intel_atomic_get_bw_state(state);
- if (IS_ERR(bw_state))
- return PTR_ERR(bw_state);
+ new_bw_state = intel_atomic_get_bw_state(state);
+ if (IS_ERR(new_bw_state))
+ return PTR_ERR(new_bw_state);
- bw_state->data_rate[crtc->pipe] = new_data_rate;
- bw_state->num_active_planes[crtc->pipe] = new_active_planes;
+ new_bw_state->data_rate[crtc->pipe] = new_data_rate;
+ new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
drm_dbg_kms(&dev_priv->drm,
"pipe %c data rate %u num active planes %u\n",
pipe_name(crtc->pipe),
- bw_state->data_rate[crtc->pipe],
- bw_state->num_active_planes[crtc->pipe]);
+ new_bw_state->data_rate[crtc->pipe],
+ new_bw_state->num_active_planes[crtc->pipe]);
}
- if (!bw_state)
+ if (!new_bw_state)
return 0;
- ret = intel_atomic_lock_global_state(&bw_state->base);
+ ret = intel_atomic_lock_global_state(&new_bw_state->base);
if (ret)
return ret;
- data_rate = intel_bw_data_rate(dev_priv, bw_state);
- num_active_planes = intel_bw_num_active_planes(dev_priv, bw_state);
+ data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH v25 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth.
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (5 preceding siblings ...)
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 6/8] drm/i915: Rename bw_state to new_bw_state Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
` (3 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.
Currently we are just comparing against all of
those and take minimum(worst case).
v2: Fixed wrong PCode reply mask, removed hardcoded
values.
v3: Forbid simultaneous legacy SAGV PCode requests and
restricting qgv points. Put the actual restriction
to commit function, added serialization(thanks to Ville)
to prevent commit being applied out of order in case of
nonblocking and/or nomodeset commits.
v4:
- Minor code refactoring, fixed few typos(thanks to James Ausmus)
- Change the naming of qgv point
masking/unmasking functions(James Ausmus).
- Simplify the masking/unmasking operation itself,
as we don't need to mask only single point per request(James Ausmus)
- Reject and stick to highest bandwidth point if SAGV
can't be enabled(BSpec)
v5:
- Add new mailbox reply codes, which seems to happen during boot
time for TGL and indicate that QGV setting is not yet available.
v6:
- Increase number of supported QGV points to be in sync with BSpec.
v7: - Rebased and resolved conflict to fix build failure.
- Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)
v8: - Don't report an error if we can't restrict qgv points, as SAGV
can be disabled by BIOS, which is completely legal. So don't
make CI panic. Instead if we detect that there is only 1 QGV
point accessible just analyze if we can fit the required bandwidth
requirements, but no need in restricting.
v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
simultaneously.
v10: - Fix CDCLK corruption, because of global state getting serialized
without modeset, which caused copying of non-calculated cdclk
to be copied to dev_priv(thanks to Ville for the hint).
v11: - Remove unneeded headers and spaces(Matthew Roper)
- Remove unneeded intel_qgv_info qi struct from bw check and zero
out the needed one(Matthew Roper)
- Changed QGV error message to have more clear meaning(Matthew Roper)
- Use state->modeset_set instead of any_ms(Matthew Roper)
- Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
- Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
- Moved unrelated changes to other patch(using latency as parameter
for plane wm calculation, moved to SAGV refactoring patch)
v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
- Remove unnecessary mask being zero check when unmasking
qgv points as this is completely legal(Matt Roper)
- Check if we are setting the same mask as already being set
in hardware to prevent error from PCode.
- Fix error message when restricting/unrestricting qgv points
to "mask/unmask" which sounds more accurate(Matt Roper)
- Move sagv status setting to icl_get_bw_info from atomic check
as this should be calculated only once.(Matt Roper)
- Edited comments for the case when we can't enable SAGV and
use only 1 QGV point with highest bandwidth to be more
understandable.(Matt Roper)
v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
- Changed comment for zero new_mask in qgv points masking function
to better reflect reality(Ville Syrjälä)
- Simplified bit mask operation in qgv points masking function
(Ville Syrjälä)
- Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
however this still can't be under modeset condition(Ville Syrjälä)
- Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
(Ville Syrjälä)
- Extracted PCode changes to separate patch.(Ville Syrjälä)
- Now treat num_planes 0 same as 1 to avoid confusion and
returning max_bw as 0, which would prevent choosing QGV
point having max bandwidth in case if SAGV is not allowed,
as per BSpec(Ville Syrjälä)
- Do the actual qgv_points_mask swap in the same place as
all other global state parts like cdclk are swapped.
In the next patch, this all will be moved to bw state as
global state, once new global state patch series from Ville
lands
v14: - Now using global state to serialize access to qgv points
- Added global state locking back, otherwise we seem to read
bw state in a wrong way.
v15: - Added TODO comment for near atomic global state locking in
bw code.
v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
with Jani Nikula.
- Take bw_state_changed flag into use.
v17: - Moved qgv point related manipulations next to SAGV code, as
those are semantically related(Ville Syrjälä)
- Renamed those into intel_sagv_(pre)|(post)_plane_update
(Ville Syrjälä)
v18: - Move sagv related calls from commit tail into
intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)
v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
for commit tail stage.
v20: - Return max bandwidth for 0 planes(Ville)
- Constify old_bw_state in bw_atomic_check(Ville)
- Removed some debugs(Ville)
- Added data rate to debug print when no QGV points(Ville)
- Removed some comments(Ville)
v21, v22, v23: - Fixed rebase conflict
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
---
drivers/gpu/drm/i915/display/intel_bw.c | 139 +++++++++++++-----
drivers/gpu/drm/i915/display/intel_bw.h | 9 ++
.../drm/i915/display/intel_display_types.h | 3 +
drivers/gpu/drm/i915/intel_pm.c | 66 ++++++++-
drivers/gpu/drm/i915/intel_pm.h | 2 +
5 files changed, 181 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6e7cc3a4f1aa..f7c04f07b7cf 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -8,6 +8,9 @@
#include "intel_bw.h"
#include "intel_display_types.h"
#include "intel_sideband.h"
+#include "intel_atomic.h"
+#include "intel_pm.h"
+
/* Parameters for Qclk Geyserville (QGV) */
struct intel_qgv_point {
@@ -113,6 +116,26 @@ static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
return 0;
}
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask)
+{
+ int ret;
+
+ /* bspec says to keep retrying for at least 1 ms */
+ ret = skl_pcode_request(dev_priv, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
+ points_mask,
+ GEN11_PCODE_POINTS_RESTRICTED_MASK,
+ GEN11_PCODE_POINTS_RESTRICTED,
+ 1);
+
+ if (ret < 0) {
+ DRM_ERROR("Failed to disable qgv points (%d)\n", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
struct intel_qgv_info *qi)
{
@@ -240,6 +263,16 @@ static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel
break;
}
+ /*
+ * In case if SAGV is disabled in BIOS, we always get 1
+ * SAGV point, but we can't send PCode commands to restrict it
+ * as it will fail and pointless anyway.
+ */
+ if (qi.num_points == 1)
+ dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
+ else
+ dev_priv->sagv_status = I915_SAGV_ENABLED;
+
return 0;
}
@@ -248,6 +281,11 @@ static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
{
int i;
+ /*
+ * Let's return max bw for 0 planes
+ */
+ num_planes = max(1, num_planes);
+
for (i = 0; i < ARRAY_SIZE(dev_priv->max_bw); i++) {
const struct intel_bw_info *bi =
&dev_priv->max_bw[i];
@@ -277,34 +315,6 @@ void intel_bw_init_hw(struct drm_i915_private *dev_priv)
icl_get_bw_info(dev_priv, &icl_sa_info);
}
-static unsigned int intel_max_data_rate(struct drm_i915_private *dev_priv,
- int num_planes)
-{
- if (INTEL_GEN(dev_priv) >= 11) {
- /*
- * Any bw group has same amount of QGV points
- */
- const struct intel_bw_info *bi =
- &dev_priv->max_bw[0];
- unsigned int min_bw = UINT_MAX;
- int i;
-
- /*
- * FIXME with SAGV disabled maybe we can assume
- * point 1 will always be used? Seems to match
- * the behaviour observed in the wild.
- */
- for (i = 0; i < bi->num_qgv_points; i++) {
- unsigned int bw = icl_max_bw(dev_priv, num_planes, i);
-
- min_bw = min(bw, min_bw);
- }
- return min_bw;
- } else {
- return UINT_MAX;
- }
-}
-
static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
{
/*
@@ -415,10 +425,15 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_bw_state *new_bw_state = NULL;
- unsigned int data_rate, max_data_rate;
+ const struct intel_bw_state *old_bw_state = NULL;
+ unsigned int data_rate;
unsigned int num_active_planes;
struct intel_crtc *crtc;
int i, ret;
+ u32 allowed_points = 0;
+ unsigned int max_bw_point = 0, max_bw = 0;
+ unsigned int num_qgv_points = dev_priv->max_bw[0].num_qgv_points;
+ u32 mask = (1 << num_qgv_points) - 1;
/* FIXME earlier gens need some checks too */
if (INTEL_GEN(dev_priv) < 11)
@@ -465,19 +480,73 @@ int intel_bw_atomic_check(struct intel_atomic_state *state)
return ret;
data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
+ data_rate = DIV_ROUND_UP(data_rate, 1000);
+
num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
- max_data_rate = intel_max_data_rate(dev_priv, num_active_planes);
+ for (i = 0; i < num_qgv_points; i++) {
+ unsigned int max_data_rate;
- data_rate = DIV_ROUND_UP(data_rate, 1000);
+ max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
+ /*
+ * We need to know which qgv point gives us
+ * maximum bandwidth in order to disable SAGV
+ * if we find that we exceed SAGV block time
+ * with watermarks. By that moment we already
+ * have those, as it is calculated earlier in
+ * intel_atomic_check,
+ */
+ if (max_data_rate > max_bw) {
+ max_bw_point = i;
+ max_bw = max_data_rate;
+ }
+ if (max_data_rate >= data_rate)
+ allowed_points |= BIT(i);
+ DRM_DEBUG_KMS("QGV point %d: max bw %d required %d\n",
+ i, max_data_rate, data_rate);
+ }
- if (data_rate > max_data_rate) {
- drm_dbg_kms(&dev_priv->drm,
- "Bandwidth %u MB/s exceeds max available %d MB/s (%d active planes)\n",
- data_rate, max_data_rate, num_active_planes);
+ /*
+ * BSpec states that we always should have at least one allowed point
+ * left, so if we couldn't - simply reject the configuration for obvious
+ * reasons.
+ */
+ if (allowed_points == 0) {
+ DRM_DEBUG_KMS("No QGV points provide sufficient memory"
+ " bandwidth %d for display configuration.\n", data_rate);
return -EINVAL;
}
+ /*
+ * Leave only single point with highest bandwidth, if
+ * we can't enable SAGV due to the increased memory latency it may
+ * cause.
+ */
+ if (!intel_can_enable_sagv(new_bw_state)) {
+ allowed_points = BIT(max_bw_point);
+ DRM_DEBUG_KMS("No SAGV, using single QGV point %d\n",
+ max_bw_point);
+ }
+ /*
+ * We store the ones which need to be masked as that is what PCode
+ * actually accepts as a parameter.
+ */
+ new_bw_state->qgv_points_mask = (~allowed_points) & mask;
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return -EINVAL;
+
+ /*
+ * If the actual mask had changed we need to make sure that
+ * the commits are serialized(in case this is a nomodeset, nonblocking)
+ */
+ if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
+ ret = intel_atomic_serialize_global_state(&new_bw_state->base);
+ if (ret)
+ return ret;
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index d6df91058223..ecc086e1f30f 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -24,6 +24,13 @@ struct intel_bw_state {
*/
u8 pipe_sagv_reject;
+ /*
+ * Current QGV points mask, which restricts
+ * some particular SAGV states, not to confuse
+ * with pipe_sagv_mask.
+ */
+ u8 qgv_points_mask;
+
unsigned int data_rate[I915_MAX_PIPES];
u8 num_active_planes[I915_MAX_PIPES];
};
@@ -44,5 +51,7 @@ int intel_bw_init(struct drm_i915_private *dev_priv);
int intel_bw_atomic_check(struct intel_atomic_state *state);
void intel_bw_crtc_update(struct intel_bw_state *bw_state,
const struct intel_crtc_state *crtc_state);
+int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
+ u32 points_mask);
#endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 23a425e565a8..92db9b0ab381 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -693,6 +693,9 @@ struct skl_plane_wm {
bool is_planar;
};
+/* BSpec precisely defines this */
+#define NUM_SAGV_POINTS 8
+
struct skl_pipe_wm {
struct skl_plane_wm planes[I915_MAX_PLANES];
bool can_sagv;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 8c5be15be364..e4aef90c7364 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3761,7 +3761,10 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
@@ -3777,15 +3780,48 @@ void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (!intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && !intel_can_enable_sagv(new_bw_state)) {
intel_disable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to mask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+ /*
+ * If new mask is zero - means there is nothing to mask,
+ * we can only unmask, which should be done in unmask.
+ */
+ if (!new_mask)
+ return;
+
+ /*
+ * Restrict required qgv points before updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not mask required qgv points(%d)\n", ret);
}
void intel_sagv_post_plane_update(struct intel_atomic_state *state)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
+ int ret;
const struct intel_bw_state *new_bw_state;
-
+ const struct intel_bw_state *old_bw_state;
+ u32 new_mask = 0;
/*
* Just return if we can't control SAGV or don't have it.
* This is different from situation when we have SAGV but just can't
@@ -3800,8 +3836,32 @@ void intel_sagv_post_plane_update(struct intel_atomic_state *state)
if (!new_bw_state)
return;
- if (intel_can_enable_sagv(new_bw_state))
+ if (INTEL_GEN(dev_priv) < 11 && intel_can_enable_sagv(new_bw_state)) {
intel_enable_sagv(dev_priv);
+ return;
+ }
+
+ old_bw_state = intel_atomic_get_old_bw_state(state);
+ if (!old_bw_state)
+ return;
+
+ /*
+ * Nothing to unmask
+ */
+ if (new_bw_state->qgv_points_mask == old_bw_state->qgv_points_mask)
+ return;
+
+ new_mask = new_bw_state->qgv_points_mask;
+
+ /*
+ * Allow required qgv points after updating the configuration.
+ * According to BSpec we can't mask and unmask qgv points at the same
+ * time. Also masking should be done before updating the configuration
+ * and unmasking afterwards.
+ */
+ ret = icl_pcode_restrict_qgv_points(dev_priv, new_mask);
+ if (ret < 0)
+ drm_err(&dev_priv->drm, "Could not unmask required qgv points(%d)\n", ret);
}
static bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
diff --git a/drivers/gpu/drm/i915/intel_pm.h b/drivers/gpu/drm/i915/intel_pm.h
index fd1dc422e6c5..4ae91ad5d5b3 100644
--- a/drivers/gpu/drm/i915/intel_pm.h
+++ b/drivers/gpu/drm/i915/intel_pm.h
@@ -42,6 +42,8 @@ void skl_pipe_wm_get_hw_state(struct intel_crtc *crtc,
struct skl_pipe_wm *out);
void g4x_wm_sanitize(struct drm_i915_private *dev_priv);
void vlv_wm_sanitize(struct drm_i915_private *dev_priv);
+void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
+void intel_sagv_post_plane_update(struct intel_atomic_state *state);
bool intel_can_enable_sagv(const struct intel_bw_state *bw_state);
int intel_enable_sagv(struct drm_i915_private *dev_priv);
int intel_disable_sagv(struct drm_i915_private *dev_priv);
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] [PATCH v25 8/8] drm/i915: Enable SAGV support for Gen12
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (6 preceding siblings ...)
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 7/8] drm/i915: Restrict qgv points which don't have enough bandwidth Stanislav Lisovskiy
@ 2020-04-20 11:14 ` Stanislav Lisovskiy
2020-04-20 13:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev26) Patchwork
` (2 subsequent siblings)
10 siblings, 0 replies; 17+ messages in thread
From: Stanislav Lisovskiy @ 2020-04-20 11:14 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
Flip the switch and enable SAGV support
for Gen12 also.
Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index e4aef90c7364..75991467a375 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3638,10 +3638,6 @@ static bool skl_needs_memory_bw_wa(struct drm_i915_private *dev_priv)
static bool
intel_has_sagv(struct drm_i915_private *dev_priv)
{
- /* HACK! */
- if (IS_GEN(dev_priv, 12))
- return false;
-
return (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) &&
dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED;
}
--
2.24.1.485.gad05a3d8e5
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 17+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev26)
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (7 preceding siblings ...)
2020-04-20 11:14 ` [Intel-gfx] [PATCH v25 8/8] drm/i915: Enable SAGV support for Gen12 Stanislav Lisovskiy
@ 2020-04-20 13:38 ` Patchwork
2020-04-20 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-04-20 21:20 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-04-20 13:38 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev26)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328 -> Patchwork_17381
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/index.html
Known issues
------------
Here are the changes found in Patchwork_17381 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live@ring_submission:
- fi-bwr-2160: [PASS][1] -> [INCOMPLETE][2] ([i915#489])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/fi-bwr-2160/igt@i915_selftest@live@ring_submission.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/fi-bwr-2160/igt@i915_selftest@live@ring_submission.html
[i915#489]: https://gitlab.freedesktop.org/drm/intel/issues/489
Participating hosts (50 -> 43)
------------------------------
Missing (7): fi-cml-u2 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8328 -> Patchwork_17381
CI-20190529: 20190529
CI_DRM_8328: 77c1f57ceed8844ac2eccde781f540fae4e6604d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5602: a8fcccd15dcc2dd409edd23785a2d6f6e85fb682 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17381: 3089a6e31ac954dd2dbbe7f49c5dd799586dbea3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3089a6e31ac9 drm/i915: Enable SAGV support for Gen12
a3c414db7dab drm/i915: Restrict qgv points which don't have enough bandwidth.
0164812eddef drm/i915: Rename bw_state to new_bw_state
a24d98622eca drm/i915: Added required new PCode commands
289d9ff85260 drm/i915: Add TGL+ SAGV support
eaf658e36e57 drm/i915: Separate icl and skl SAGV checking
062f06f4d441 drm/i915: Use bw state for per crtc SAGV evaluation
a6d6c7f31154 drm/i915: Introduce skl_plane_wm_level accessor.
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev26)
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (8 preceding siblings ...)
2020-04-20 13:38 ` [Intel-gfx] ✓ Fi.CI.BAT: success for SAGV support for Gen12+ (rev26) Patchwork
@ 2020-04-20 17:16 ` Patchwork
2020-04-20 21:05 ` Lisovskiy, Stanislav
2020-04-20 21:20 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
10 siblings, 1 reply; 17+ messages in thread
From: Patchwork @ 2020-04-20 17:16 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev26)
URL : https://patchwork.freedesktop.org/series/75129/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8328_full -> Patchwork_17381_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17381_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17381_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17381_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_17381_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl5/igt@i915_pm_rpm@system-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl5/igt@i915_pm_rpm@system-suspend.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#1119] / [i915#93] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-0.html
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#1119] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl1/igt@kms_big_fb@linear-32bpp-rotate-0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#118] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-tglb: [PASS][13] -> [SKIP][14] ([i915#668]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
#### Possible fixes ####
* igt@gem_mmap_gtt@flink-race:
- shard-tglb: [INCOMPLETE][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb3/igt@gem_mmap_gtt@flink-race.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb5/igt@gem_mmap_gtt@flink-race.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][23] ([i915#180] / [i915#95]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-glk: [FAIL][25] ([i915#54]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][33] ([i915#31]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-hsw: [INCOMPLETE][35] ([i915#61]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-hsw6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-hsw4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-iclb: [FAIL][37] ([i915#1542]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb8/igt@perf@blocking-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][39] ([i915#658]) -> [SKIP][40] ([i915#588])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][41] ([i915#454]) -> [SKIP][42] ([i915#668])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@gem-mmap-type:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [INCOMPLETE][44] ([i915#82])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-snb6/igt@i915_pm_rpm@gem-mmap-type.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-snb5/igt@i915_pm_rpm@gem-mmap-type.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8328 -> Patchwork_17381
CI-20190529: 20190529
CI_DRM_8328: 77c1f57ceed8844ac2eccde781f540fae4e6604d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5602: a8fcccd15dcc2dd409edd23785a2d6f6e85fb682 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17381: 3089a6e31ac954dd2dbbe7f49c5dd799586dbea3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev26)
2020-04-20 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-04-20 21:05 ` Lisovskiy, Stanislav
2020-04-20 21:43 ` Vudum, Lakshminarayana
0 siblings, 1 reply; 17+ messages in thread
From: Lisovskiy, Stanislav @ 2020-04-20 21:05 UTC (permalink / raw)
To: intel-gfx, Vudum, Lakshminarayana
Seems to be unrelated to SAGV, as it can't break module_reload only..
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Monday, April 20, 2020 8:16:39 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev26)
== Series Details ==
Series: SAGV support for Gen12+ (rev26)
URL : https://patchwork.freedesktop.org/series/75129/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8328_full -> Patchwork_17381_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17381_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17381_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17381_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_17381_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl5/igt@i915_pm_rpm@system-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl5/igt@i915_pm_rpm@system-suspend.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#1119] / [i915#93] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-0.html
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#1119] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl1/igt@kms_big_fb@linear-32bpp-rotate-0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#118] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-tglb: [PASS][13] -> [SKIP][14] ([i915#668]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
#### Possible fixes ####
* igt@gem_mmap_gtt@flink-race:
- shard-tglb: [INCOMPLETE][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb3/igt@gem_mmap_gtt@flink-race.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb5/igt@gem_mmap_gtt@flink-race.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][23] ([i915#180] / [i915#95]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-glk: [FAIL][25] ([i915#54]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][33] ([i915#31]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-hsw: [INCOMPLETE][35] ([i915#61]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-hsw6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-hsw4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-iclb: [FAIL][37] ([i915#1542]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb8/igt@perf@blocking-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][39] ([i915#658]) -> [SKIP][40] ([i915#588])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][41] ([i915#454]) -> [SKIP][42] ([i915#668])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@gem-mmap-type:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [INCOMPLETE][44] ([i915#82])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-snb6/igt@i915_pm_rpm@gem-mmap-type.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-snb5/igt@i915_pm_rpm@gem-mmap-type.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8328 -> Patchwork_17381
CI-20190529: 20190529
CI_DRM_8328: 77c1f57ceed8844ac2eccde781f540fae4e6604d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5602: a8fcccd15dcc2dd409edd23785a2d6f6e85fb682 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17381: 3089a6e31ac954dd2dbbe7f49c5dd799586dbea3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread* Re: [Intel-gfx] ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev26)
2020-04-20 21:05 ` Lisovskiy, Stanislav
@ 2020-04-20 21:43 ` Vudum, Lakshminarayana
0 siblings, 0 replies; 17+ messages in thread
From: Vudum, Lakshminarayana @ 2020-04-20 21:43 UTC (permalink / raw)
To: Lisovskiy, Stanislav, intel-gfx
Stan, I have re-reported the results.
-----Original Message-----
From: Lisovskiy, Stanislav <stanislav.lisovskiy@intel.com>
Sent: Tuesday, April 21, 2020 12:05 AM
To: intel-gfx@lists.freedesktop.org; Vudum, Lakshminarayana <lakshminarayana.vudum@intel.com>
Subject: Re: ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev26)
Seems to be unrelated to SAGV, as it can't break module_reload only..
Best Regards,
Lisovskiy Stanislav
Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo
________________________________________
From: Patchwork <patchwork@emeril.freedesktop.org>
Sent: Monday, April 20, 2020 8:16:39 PM
To: Lisovskiy, Stanislav
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.IGT: failure for SAGV support for Gen12+ (rev26)
== Series Details ==
Series: SAGV support for Gen12+ (rev26)
URL : https://patchwork.freedesktop.org/series/75129/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_8328_full -> Patchwork_17381_full ====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_17381_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_17381_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_17381_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@i915_module_load@reload-with-fault-injection.html
Known issues
------------
Here are the changes found in Patchwork_17381_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl5/igt@i915_pm_rpm@system-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl5/igt@i915_pm_rpm@system-suspend.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#1119] / [i915#93] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-0.html
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#1119] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl1/igt@kms_big_fb@linear-32bpp-rotate-0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#118] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-tglb: [PASS][13] -> [SKIP][14] ([i915#668]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
#### Possible fixes ####
* igt@gem_mmap_gtt@flink-race:
- shard-tglb: [INCOMPLETE][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb3/igt@gem_mmap_gtt@flink-race.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb5/igt@gem_mmap_gtt@flink-race.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][23] ([i915#180] / [i915#95]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-glk: [FAIL][25] ([i915#54]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][33] ([i915#31]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-hsw: [INCOMPLETE][35] ([i915#61]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-hsw6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-hsw4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-iclb: [FAIL][37] ([i915#1542]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb8/igt@perf@blocking-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][39] ([i915#658]) -> [SKIP][40] ([i915#588])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][41] ([i915#454]) -> [SKIP][42] ([i915#668])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@gem-mmap-type:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [INCOMPLETE][44] ([i915#82])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-snb6/igt@i915_pm_rpm@gem-mmap-type.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-snb5/igt@i915_pm_rpm@gem-mmap-type.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8328 -> Patchwork_17381
CI-20190529: 20190529
CI_DRM_8328: 77c1f57ceed8844ac2eccde781f540fae4e6604d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5602: a8fcccd15dcc2dd409edd23785a2d6f6e85fb682 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17381: 3089a6e31ac954dd2dbbe7f49c5dd799586dbea3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/index.html
---------------------------------------------------------------------
Intel Finland Oy
Registered Address: PL 281, 00181 Helsinki
Business Identity Code: 0357606 - 4
Domiciled in Helsinki
This e-mail and any attachments may contain confidential material for
the sole use of the intended recipient(s). Any review or distribution
by others is strictly prohibited. If you are not the intended
recipient, please contact the sender and delete all copies.
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for SAGV support for Gen12+ (rev26)
2020-04-20 11:14 [Intel-gfx] [PATCH v25 0/8] SAGV support for Gen12+ Stanislav Lisovskiy
` (9 preceding siblings ...)
2020-04-20 17:16 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2020-04-20 21:20 ` Patchwork
10 siblings, 0 replies; 17+ messages in thread
From: Patchwork @ 2020-04-20 21:20 UTC (permalink / raw)
To: Stanislav Lisovskiy; +Cc: intel-gfx
== Series Details ==
Series: SAGV support for Gen12+ (rev26)
URL : https://patchwork.freedesktop.org/series/75129/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_8328_full -> Patchwork_17381_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_17381_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_module_load@reload-with-fault-injection:
- shard-kbl: [PASS][1] -> [INCOMPLETE][2] ([i915#1373])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@i915_module_load@reload-with-fault-injection.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@i915_module_load@reload-with-fault-injection.html
* igt@i915_pm_rpm@system-suspend:
- shard-skl: [PASS][3] -> [INCOMPLETE][4] ([i915#151] / [i915#69])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl5/igt@i915_pm_rpm@system-suspend.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl5/igt@i915_pm_rpm@system-suspend.html
* igt@kms_big_fb@linear-32bpp-rotate-0:
- shard-kbl: [PASS][5] -> [FAIL][6] ([i915#1119] / [i915#93] / [i915#95])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl3/igt@kms_big_fb@linear-32bpp-rotate-0.html
- shard-apl: [PASS][7] -> [FAIL][8] ([i915#1119] / [i915#95])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl1/igt@kms_big_fb@linear-32bpp-rotate-0.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl4/igt@kms_big_fb@linear-32bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-a-cursor-suspend:
- shard-kbl: [PASS][9] -> [DMESG-WARN][10] ([i915#180]) +4 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl7/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-suspend.html
* igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw:
- shard-glk: [PASS][11] -> [FAIL][12] ([i915#118] / [i915#95])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk7/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk4/igt@kms_frontbuffer_tracking@fbc-2p-pri-indfb-multidraw.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen:
- shard-tglb: [PASS][13] -> [SKIP][14] ([i915#668]) +6 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-fullscreen.html
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: [PASS][15] -> [DMESG-WARN][16] ([i915#180]) +1 similar issue
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl1/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][17] -> [FAIL][18] ([fdo#108145] / [i915#265])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-skl10/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: [PASS][19] -> [SKIP][20] ([fdo#109441]) +1 similar issue
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb6/igt@kms_psr@psr2_cursor_plane_move.html
#### Possible fixes ####
* igt@gem_mmap_gtt@flink-race:
- shard-tglb: [INCOMPLETE][21] -> [PASS][22]
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb3/igt@gem_mmap_gtt@flink-race.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb5/igt@gem_mmap_gtt@flink-race.html
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: [DMESG-WARN][23] ([i915#180] / [i915#95]) -> [PASS][24]
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl4/igt@i915_suspend@fence-restore-tiled2untiled.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl6/igt@i915_suspend@fence-restore-tiled2untiled.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen:
- shard-glk: [FAIL][25] ([i915#54]) -> [PASS][26]
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-glk8/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-glk1/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][27] ([i915#180]) -> [PASS][28] +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-kbl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* {igt@kms_flip@flip-vs-suspend-interruptible@c-dp1}:
- shard-apl: [DMESG-WARN][29] ([i915#180]) -> [PASS][30] +5 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl2/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][31] ([fdo#109441]) -> [PASS][32] +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_setmode@basic:
- shard-apl: [FAIL][33] ([i915#31]) -> [PASS][34]
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-apl8/igt@kms_setmode@basic.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-apl8/igt@kms_setmode@basic.html
* igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend:
- shard-hsw: [INCOMPLETE][35] ([i915#61]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-hsw6/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-hsw4/igt@kms_vblank@pipe-c-ts-continuation-dpms-suspend.html
* {igt@perf@blocking-parameterized}:
- shard-iclb: [FAIL][37] ([i915#1542]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb8/igt@perf@blocking-parameterized.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb1/igt@perf@blocking-parameterized.html
#### Warnings ####
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][39] ([i915#658]) -> [SKIP][40] ([i915#588])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-iclb7/igt@i915_pm_dc@dc3co-vpb-simulation.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_dc@dc6-psr:
- shard-tglb: [FAIL][41] ([i915#454]) -> [SKIP][42] ([i915#668])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-tglb1/igt@i915_pm_dc@dc6-psr.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-tglb6/igt@i915_pm_dc@dc6-psr.html
* igt@i915_pm_rpm@gem-mmap-type:
- shard-snb: [SKIP][43] ([fdo#109271]) -> [INCOMPLETE][44] ([i915#82])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_8328/shard-snb6/igt@i915_pm_rpm@gem-mmap-type.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/shard-snb5/igt@i915_pm_rpm@gem-mmap-type.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[i915#1119]: https://gitlab.freedesktop.org/drm/intel/issues/1119
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#1373]: https://gitlab.freedesktop.org/drm/intel/issues/1373
[i915#151]: https://gitlab.freedesktop.org/drm/intel/issues/151
[i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31
[i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
[i915#46]: https://gitlab.freedesktop.org/drm/intel/issues/46
[i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#61]: https://gitlab.freedesktop.org/drm/intel/issues/61
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#668]: https://gitlab.freedesktop.org/drm/intel/issues/668
[i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
[i915#82]: https://gitlab.freedesktop.org/drm/intel/issues/82
[i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
[i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95
Participating hosts (10 -> 10)
------------------------------
No changes in participating hosts
Build changes
-------------
* CI: CI-20190529 -> None
* Linux: CI_DRM_8328 -> Patchwork_17381
CI-20190529: 20190529
CI_DRM_8328: 77c1f57ceed8844ac2eccde781f540fae4e6604d @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_5602: a8fcccd15dcc2dd409edd23785a2d6f6e85fb682 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_17381: 3089a6e31ac954dd2dbbe7f49c5dd799586dbea3 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_17381/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 17+ messages in thread