* [PATCH v2 0/11] Add R8A7745/SK-RZG1E board support
@ 2016-11-04 21:42 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:42 UTC (permalink / raw)
To: linux-arm-kernel
Hello.
Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
'renesas-devel-201611104-v4.9-rc3' tag plus the R8A7743/SK-RZG1M patch series
posted earlier. I'm adding the device tree support for the R8A7745-based
SK-RZG1E board. The SoC is close to R8A7794 and the board seems identical to the
R8A7794/SILK board. The device tree patches depend on the R8A7745 CPG/MSSR
driver series in order to compile and work.
[01/11] ARM: shmobile: r8a7745: add power domain index macros
[02/11] soc: renesas: rcar-sysc: add R8A7745 support
[03/11] ARM: shmobile: r8a7745: basic SoC support
[04/11] ARM: dts: r8a7745: initial SoC device tree
[05/11] ARM: dts: r8a7745: add SYS-DMAC support
[06/11] ARM: dts: r8a7745: add [H]SCIF{|A|B} support
[07/11] ARM: dts: r8a7745: add Ether support
[08/11] ARM: dts: r8a7745: add IRQC support
[09/11] ARM: shmobile: document SK-RZG1E board
[10/11] ARM: dts: sk-rzg1e: initial device tree
[11/11] ARM: dts: sk-rzg1e: add Ether support
WBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 02/11] soc: renesas: rcar-sysc: add R8A7745 support
2016-11-04 21:42 ` Sergei Shtylyov
(?)
@ 2016-11-04 21:46 ` Sergei Shtylyov
2016-11-14 15:54 ` Rob Herring
-1 siblings, 1 reply; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:46 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Add support for RZ/G1E (R8A7745) SoC power areas to the R-Car SYSC driver.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1
drivers/soc/renesas/Makefile | 1
drivers/soc/renesas/r8a7745-sysc.c | 32 ++++++++++
drivers/soc/renesas/rcar-sysc.c | 3
drivers/soc/renesas/rcar-sysc.h | 1
5 files changed, 38 insertions(+)
Index: renesas/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
+++ renesas/Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt
@@ -8,6 +8,7 @@ and various coprocessors.
Required properties:
- compatible: Must contain exactly one of the following:
- "renesas,r8a7743-sysc" (RZ/G1M)
+ - "renesas,r8a7745-sysc" (RZ/G1E)
- "renesas,r8a7779-sysc" (R-Car H1)
- "renesas,r8a7790-sysc" (R-Car H2)
- "renesas,r8a7791-sysc" (R-Car M2-W)
Index: renesas/drivers/soc/renesas/Makefile
===================================================================
--- renesas.orig/drivers/soc/renesas/Makefile
+++ renesas/drivers/soc/renesas/Makefile
@@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_R8A7795) += rcar-rst.o
obj-$(CONFIG_ARCH_R8A7796) += rcar-rst.o
obj-$(CONFIG_ARCH_R8A7743) += rcar-sysc.o r8a7743-sysc.o
+obj-$(CONFIG_ARCH_R8A7745) += rcar-sysc.o r8a7745-sysc.o
obj-$(CONFIG_ARCH_R8A7779) += rcar-sysc.o r8a7779-sysc.o
obj-$(CONFIG_ARCH_R8A7790) += rcar-sysc.o r8a7790-sysc.o
obj-$(CONFIG_ARCH_R8A7791) += rcar-sysc.o r8a7791-sysc.o
Index: renesas/drivers/soc/renesas/r8a7745-sysc.c
===================================================================
--- /dev/null
+++ renesas/drivers/soc/renesas/r8a7745-sysc.c
@@ -0,0 +1,32 @@
+/*
+ * Renesas RZ/G1E System Controller
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation; of the License.
+ */
+
+#include <linux/bug.h>
+#include <linux/kernel.h>
+
+#include <dt-bindings/power/r8a7745-sysc.h>
+
+#include "rcar-sysc.h"
+
+static const struct rcar_sysc_area r8a7745_areas[] __initconst = {
+ { "always-on", 0, 0, R8A7745_PD_ALWAYS_ON, -1, PD_ALWAYS_ON },
+ { "ca7-scu", 0x100, 0, R8A7745_PD_CA7_SCU, R8A7745_PD_ALWAYS_ON,
+ PD_SCU },
+ { "ca7-cpu0", 0x1c0, 0, R8A7745_PD_CA7_CPU0, R8A7745_PD_CA7_SCU,
+ PD_CPU_NOCR },
+ { "ca7-cpu1", 0x1c0, 1, R8A7745_PD_CA7_CPU1, R8A7745_PD_CA7_SCU,
+ PD_CPU_NOCR },
+ { "sgx", 0xc0, 0, R8A7745_PD_SGX, R8A7745_PD_ALWAYS_ON },
+};
+
+const struct rcar_sysc_info r8a7745_sysc_info __initconst = {
+ .areas = r8a7745_areas,
+ .num_areas = ARRAY_SIZE(r8a7745_areas),
+};
Index: renesas/drivers/soc/renesas/rcar-sysc.c
===================================================================
--- renesas.orig/drivers/soc/renesas/rcar-sysc.c
+++ renesas/drivers/soc/renesas/rcar-sysc.c
@@ -278,6 +278,9 @@ static const struct of_device_id rcar_sy
#ifdef CONFIG_ARCH_R8A7743
{ .compatible = "renesas,r8a7743-sysc", .data = &r8a7743_sysc_info },
#endif
+#ifdef CONFIG_ARCH_R8A7745
+ { .compatible = "renesas,r8a7745-sysc", .data = &r8a7745_sysc_info },
+#endif
#ifdef CONFIG_ARCH_R8A7779
{ .compatible = "renesas,r8a7779-sysc", .data = &r8a7779_sysc_info },
#endif
Index: renesas/drivers/soc/renesas/rcar-sysc.h
===================================================================
--- renesas.orig/drivers/soc/renesas/rcar-sysc.h
+++ renesas/drivers/soc/renesas/rcar-sysc.h
@@ -51,6 +51,7 @@ struct rcar_sysc_info {
};
extern const struct rcar_sysc_info r8a7743_sysc_info;
+extern const struct rcar_sysc_info r8a7745_sysc_info;
extern const struct rcar_sysc_info r8a7779_sysc_info;
extern const struct rcar_sysc_info r8a7790_sysc_info;
extern const struct rcar_sysc_info r8a7791_sysc_info;
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH v2 02/11] soc: renesas: rcar-sysc: add R8A7745 support
2016-11-04 21:46 ` [PATCH v2 02/11] soc: renesas: rcar-sysc: add R8A7745 support Sergei Shtylyov
@ 2016-11-14 15:54 ` Rob Herring
0 siblings, 0 replies; 103+ messages in thread
From: Rob Herring @ 2016-11-14 15:54 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: horms, linux-renesas-soc, mark.rutland, devicetree
On Sat, Nov 05, 2016 at 12:46:13AM +0300, Sergei Shtylyov wrote:
> Add support for RZ/G1E (R8A7745) SoC power areas to the R-Car SYSC driver.
>
> Based on the original (and large) patch by Dmitry Shifrin
> <dmitry.shifrin@cogentembedded.com>.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 2:
> - added Geert's tag.
>
> Documentation/devicetree/bindings/power/renesas,rcar-sysc.txt | 1
Acked-by: Rob Herring <robh@kernel.org>
> drivers/soc/renesas/Makefile | 1
> drivers/soc/renesas/r8a7745-sysc.c | 32 ++++++++++
> drivers/soc/renesas/rcar-sysc.c | 3
> drivers/soc/renesas/rcar-sysc.h | 1
> 5 files changed, 38 insertions(+)
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 04/11] ARM: dts: r8a7745: initial SoC device tree
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 21:53 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:53 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- reformatted the "interrupts" props of the GIC/timer device nodes;
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for the r8a7745 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
+#include <dt-bindings/power/r8a7745-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7745";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
+ power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA7: cache-controller@0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7745_PD_CA7_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller@e6150000 {
+ compatible = "renesas,r8a7745-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller@e6180000 {
+ compatible = "renesas,r8a7745-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ rst: reset-controller@e6160000 {
+ compatible = "renesas,r8a7745-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 04/11] ARM: dts: r8a7745: initial SoC device tree
@ 2016-11-04 21:53 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:53 UTC (permalink / raw)
To: linux-arm-kernel
The initial R8A7745 SoC device tree including CPU0, GIC, timer, SYSC, RST,
CPG, and the required clock descriptions.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- reformatted the "interrupts" props of the GIC/timer device nodes;
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 120 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 120 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -0,0 +1,120 @@
+/*
+ * Device Tree Source for the r8a7745 SoC
+ *
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/r8a7745-cpg-mssr.h>
+#include <dt-bindings/power/r8a7745-sysc.h>
+
+/ {
+ compatible = "renesas,r8a7745";
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu at 0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a7";
+ reg = <0>;
+ clock-frequency = <1000000000>;
+ clocks = <&cpg CPG_CORE R8A7745_CLK_Z2>;
+ power-domains = <&sysc R8A7745_PD_CA7_CPU0>;
+ next-level-cache = <&L2_CA7>;
+ };
+
+ L2_CA7: cache-controller at 0 {
+ compatible = "cache";
+ reg = <0>;
+ cache-unified;
+ cache-level = <2>;
+ power-domains = <&sysc R8A7745_PD_CA7_SCU>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ interrupt-parent = <&gic>;
+
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller at f1001000 {
+ compatible = "arm,gic-400";
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ interrupt-controller;
+ reg = <0 0xf1001000 0 0x1000>,
+ <0 0xf1002000 0 0x1000>,
+ <0 0xf1004000 0 0x2000>,
+ <0 0xf1006000 0 0x2000>;
+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_HIGH)>;
+ };
+
+ timer {
+ compatible = "arm,armv7-timer";
+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
+ IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ cpg: clock-controller at e6150000 {
+ compatible = "renesas,r8a7745-cpg-mssr";
+ reg = <0 0xe6150000 0 0x1000>;
+ clocks = <&extal_clk>, <&usb_extal_clk>;
+ clock-names = "extal", "usb_extal";
+ #clock-cells = <2>;
+ #power-domain-cells = <0>;
+ };
+
+ sysc: system-controller at e6180000 {
+ compatible = "renesas,r8a7745-sysc";
+ reg = <0 0xe6180000 0 0x200>;
+ #power-domain-cells = <1>;
+ };
+
+ rst: reset-controller at e6160000 {
+ compatible = "renesas,r8a7745-rst";
+ reg = <0 0xe6160000 0 0x100>;
+ };
+ };
+
+ /* External root clock */
+ extal_clk: extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+
+ /* External USB clock - can be overridden by the board */
+ usb_extal_clk: usb_extal {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <48000000>;
+ };
+
+ /* External SCIF clock */
+ scif_clk: scif {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ /* This value must be overridden by the board. */
+ clock-frequency = <0>;
+ };
+};
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 05/11] ARM: dts: r8a7745: add SYS-DMAC support
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 21:54 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:54 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Describe SYS-DMAC0/1 in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
arch/arm/boot/dts/r8a7745.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -93,6 +93,70 @@
compatible = "renesas,r8a7745-rst";
reg = <0 0xe6160000 0 0x0200>;
};
+
+ dmac0: dma-controller@e6700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller@e6720000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
};
/* External root clock */
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 05/11] ARM: dts: r8a7745: add SYS-DMAC support
@ 2016-11-04 21:54 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:54 UTC (permalink / raw)
To: linux-arm-kernel
Describe SYS-DMAC0/1 in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
arch/arm/boot/dts/r8a7745.dtsi | 64 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 64 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -93,6 +93,70 @@
compatible = "renesas,r8a7745-rst";
reg = <0 0xe6160000 0 0x0200>;
};
+
+ dmac0: dma-controller at e6700000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6700000 0 0x20000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 219>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
+
+ dmac1: dma-controller at e6720000 {
+ compatible = "renesas,dmac-r8a7745",
+ "renesas,rcar-dmac";
+ reg = <0 0xe6720000 0 0x20000>;
+ interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error",
+ "ch0", "ch1", "ch2", "ch3",
+ "ch4", "ch5", "ch6", "ch7",
+ "ch8", "ch9", "ch10", "ch11",
+ "ch12", "ch13", "ch14";
+ clocks = <&cpg CPG_MOD 218>;
+ clock-names = "fck";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ #dma-cells = <1>;
+ dma-channels = <15>;
+ };
};
/* External root clock */
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 06/11] ARM: dts: r8a7745: add [H]SCIF{|A|B} support
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 21:55 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:55 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Describe [H]SCIF{|A|B} ports in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- used the R-Car gen2 bindings instead of the RZ/G family ones;
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 261 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -157,6 +157,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+ scifa0: serial@e6c40000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa1: serial@e6c50000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa2: serial@e6c60000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa3: serial@e6c70000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa4: serial@e6c78000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa5: serial@e6c80000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb0: serial@e6c20000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb1: serial@e6c30000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb2: serial@e6ce0000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif0: serial@e6e60000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial@e6e68000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial@e6e58000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial@e6ea8000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial@e6ee0000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial@e6ee8000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial@e62c0000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial@e62c8000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial@e62d0000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 06/11] ARM: dts: r8a7745: add [H]SCIF{|A|B} support
@ 2016-11-04 21:55 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:55 UTC (permalink / raw)
To: linux-arm-kernel
Describe [H]SCIF{|A|B} ports in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- used the R-Car gen2 bindings instead of the RZ/G family ones;
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 261 +++++++++++++++++++++++++++++++++++++++++
1 file changed, 261 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -157,6 +157,267 @@
#dma-cells = <1>;
dma-channels = <15>;
};
+
+ scifa0: serial at e6c40000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c40000 0 0x40>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 204>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x21>, <&dmac0 0x22>,
+ <&dmac1 0x21>, <&dmac1 0x22>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa1: serial at e6c50000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c50000 0 0x40>;
+ interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 203>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x25>, <&dmac0 0x26>,
+ <&dmac1 0x25>, <&dmac1 0x26>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa2: serial at e6c60000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c60000 0 0x40>;
+ interrupts = <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 202>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x27>, <&dmac0 0x28>,
+ <&dmac1 0x27>, <&dmac1 0x28>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa3: serial at e6c70000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c70000 0 0x40>;
+ interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1106>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1b>, <&dmac0 0x1c>,
+ <&dmac1 0x1b>, <&dmac1 0x1c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa4: serial at e6c78000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c78000 0 0x40>;
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1107>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1f>, <&dmac0 0x20>,
+ <&dmac1 0x1f>, <&dmac1 0x20>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifa5: serial at e6c80000 {
+ compatible = "renesas,scifa-r8a7745",
+ "renesas,rcar-gen2-scifa", "renesas,scifa";
+ reg = <0 0xe6c80000 0 0x40>;
+ interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 1108>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x23>, <&dmac0 0x24>,
+ <&dmac1 0x23>, <&dmac1 0x24>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb0: serial at e6c20000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c20000 0 0x100>;
+ interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 206>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x3d>, <&dmac0 0x3e>,
+ <&dmac1 0x3d>, <&dmac1 0x3e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb1: serial at e6c30000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6c30000 0 0x100>;
+ interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 207>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x19>, <&dmac0 0x1a>,
+ <&dmac1 0x19>, <&dmac1 0x1a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scifb2: serial at e6ce0000 {
+ compatible = "renesas,scifb-r8a7745",
+ "renesas,rcar-gen2-scifb", "renesas,scifb";
+ reg = <0 0xe6ce0000 0 0x100>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 216>;
+ clock-names = "fck";
+ dmas = <&dmac0 0x1d>, <&dmac0 0x1e>,
+ <&dmac1 0x1d>, <&dmac1 0x1e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif0: serial at e6e60000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e60000 0 0x40>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 721>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x29>, <&dmac0 0x2a>,
+ <&dmac1 0x29>, <&dmac1 0x2a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif1: serial at e6e68000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e68000 0 0x40>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 720>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2d>, <&dmac0 0x2e>,
+ <&dmac1 0x2d>, <&dmac1 0x2e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif2: serial at e6e58000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6e58000 0 0x40>;
+ interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 719>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2b>, <&dmac0 0x2c>,
+ <&dmac1 0x2b>, <&dmac1 0x2c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif3: serial at e6ea8000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ea8000 0 0x40>;
+ interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 718>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x2f>, <&dmac0 0x30>,
+ <&dmac1 0x2f>, <&dmac1 0x30>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif4: serial at e6ee0000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee0000 0 0x40>;
+ interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfb>, <&dmac0 0xfc>,
+ <&dmac1 0xfb>, <&dmac1 0xfc>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ scif5: serial at e6ee8000 {
+ compatible = "renesas,scif-r8a7745",
+ "renesas,rcar-gen2-scif", "renesas,scif";
+ reg = <0 0xe6ee8000 0 0x40>;
+ interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 714>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0xfd>, <&dmac0 0xfe>,
+ <&dmac1 0xfd>, <&dmac1 0xfe>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif0: serial at e62c0000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c0000 0 0x60>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 717>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x39>, <&dmac0 0x3a>,
+ <&dmac1 0x39>, <&dmac1 0x3a>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif1: serial at e62c8000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62c8000 0 0x60>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x4d>, <&dmac0 0x4e>,
+ <&dmac1 0x4d>, <&dmac1 0x4e>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
+
+ hscif2: serial at e62d0000 {
+ compatible = "renesas,hscif-r8a7745",
+ "renesas,rcar-gen2-hscif", "renesas,hscif";
+ reg = <0 0xe62d0000 0 0x60>;
+ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 713>,
+ <&cpg CPG_CORE R8A7745_CLK_ZS>, <&scif_clk>;
+ clock-names = "fck", "brg_int", "scif_clk";
+ dmas = <&dmac0 0x3b>, <&dmac0 0x3c>,
+ <&dmac1 0x3b>, <&dmac1 0x3c>;
+ dma-names = "tx", "rx", "tx", "rx";
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 07/11] ARM: dts: r8a7745: add Ether support
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 21:57 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:57 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Define the generic R8A7745 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet@ee700000 {
+ compatible = "renesas,ether-r8a7745";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 07/11] ARM: dts: r8a7745: add Ether support
@ 2016-11-04 21:57 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:57 UTC (permalink / raw)
To: linux-arm-kernel
Define the generic R8A7745 part of the Ether device node.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7745.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -418,6 +418,18 @@
power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
status = "disabled";
};
+
+ ether: ethernet at ee700000 {
+ compatible = "renesas,ether-r8a7745";
+ reg = <0 0xee700000 0 0x400>;
+ interrupts = <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 813>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ phy-mode = "rmii";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
};
/* External root clock */
^ permalink raw reply [flat|nested] 103+ messages in thread
[parent not found: <2368353.xfo5beGC5E-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>]
* [PATCH v2 01/11] ARM: shmobile: r8a7745: add power domain index macros
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 21:44 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:44 UTC (permalink / raw)
To: horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA
Add macros usable by the device tree sources to reference R8A7745 SYSC power
domains by index.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
Changes in version 2:
- added Geert's tag.
include/dt-bindings/power/r8a7745-sysc.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
Index: renesas/include/dt-bindings/power/r8a7745-sysc.h
===================================================================
--- /dev/null
+++ renesas/include/dt-bindings/power/r8a7745-sysc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7745_PD_CA7_CPU0 5
+#define R8A7745_PD_CA7_CPU1 6
+#define R8A7745_PD_SGX 20
+#define R8A7745_PD_CA7_SCU 21
+
+/* Always-on power area */
+#define R8A7745_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 01/11] ARM: shmobile: r8a7745: add power domain index macros
@ 2016-11-04 21:44 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:44 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Add macros usable by the device tree sources to reference R8A7745 SYSC power
domains by index.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
include/dt-bindings/power/r8a7745-sysc.h | 25 +++++++++++++++++++++++++
1 file changed, 25 insertions(+)
Index: renesas/include/dt-bindings/power/r8a7745-sysc.h
===================================================================
--- /dev/null
+++ renesas/include/dt-bindings/power/r8a7745-sysc.h
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2016 Cogent Embedded Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+#ifndef __DT_BINDINGS_POWER_R8A7745_SYSC_H__
+#define __DT_BINDINGS_POWER_R8A7745_SYSC_H__
+
+/*
+ * These power domain indices match the numbers of the interrupt bits
+ * representing the power areas in the various Interrupt Registers
+ * (e.g. SYSCISR, Interrupt Status Register)
+ */
+
+#define R8A7745_PD_CA7_CPU0 5
+#define R8A7745_PD_CA7_CPU1 6
+#define R8A7745_PD_SGX 20
+#define R8A7745_PD_CA7_SCU 21
+
+/* Always-on power area */
+#define R8A7745_PD_ALWAYS_ON 32
+
+#endif /* __DT_BINDINGS_POWER_R8A7745_SYSC_H__ */
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 03/11] ARM: shmobile: r8a7745: basic SoC support
2016-11-04 21:42 ` Sergei Shtylyov
(?)
@ 2016-11-04 21:49 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:49 UTC (permalink / raw)
To: horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Add minimal support for the RZ/G1E (R8A7745) SoC.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
arch/arm/mach-shmobile/Kconfig | 4 ++++
arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
3 files changed, 7 insertions(+)
Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -15,6 +15,8 @@ SoCs:
compatible = "renesas,r8a7740"
- RZ/G1M (R8A77430)
compatible = "renesas,r8a7743"
+ - RZ/G1E (R8A77450)
+ compatible = "renesas,r8a7745"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
Index: renesas/arch/arm/mach-shmobile/Kconfig
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/Kconfig
+++ renesas/arch/arm/mach-shmobile/Kconfig
@@ -73,6 +73,10 @@ config ARCH_R8A7743
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+config ARCH_R8A7745
+ bool "RZ/G1E (R8A77450)"
+ select ARCH_RCAR_GEN2
+
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
Index: renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -227,6 +227,7 @@ MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
"renesas,r8a7743",
+ "renesas,r8a7745",
NULL,
};
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
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^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 03/11] ARM: shmobile: r8a7745: basic SoC support
@ 2016-11-04 21:49 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:49 UTC (permalink / raw)
To: linux-arm-kernel
Add minimal support for the RZ/G1E (R8A7745) SoC.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
arch/arm/mach-shmobile/Kconfig | 4 ++++
arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
3 files changed, 7 insertions(+)
Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -15,6 +15,8 @@ SoCs:
compatible = "renesas,r8a7740"
- RZ/G1M (R8A77430)
compatible = "renesas,r8a7743"
+ - RZ/G1E (R8A77450)
+ compatible = "renesas,r8a7745"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
Index: renesas/arch/arm/mach-shmobile/Kconfig
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/Kconfig
+++ renesas/arch/arm/mach-shmobile/Kconfig
@@ -73,6 +73,10 @@ config ARCH_R8A7743
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+config ARCH_R8A7745
+ bool "RZ/G1E (R8A77450)"
+ select ARCH_RCAR_GEN2
+
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
Index: renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -227,6 +227,7 @@ MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
"renesas,r8a7743",
+ "renesas,r8a7745",
NULL,
};
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 03/11] ARM: shmobile: r8a7745: basic SoC support
@ 2016-11-04 21:49 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:49 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Add minimal support for the RZ/G1E (R8A7745) SoC.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
arch/arm/mach-shmobile/Kconfig | 4 ++++
arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
3 files changed, 7 insertions(+)
Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -15,6 +15,8 @@ SoCs:
compatible = "renesas,r8a7740"
- RZ/G1M (R8A77430)
compatible = "renesas,r8a7743"
+ - RZ/G1E (R8A77450)
+ compatible = "renesas,r8a7745"
- R-Car M1A (R8A77781)
compatible = "renesas,r8a7778"
- R-Car H1 (R8A77790)
Index: renesas/arch/arm/mach-shmobile/Kconfig
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/Kconfig
+++ renesas/arch/arm/mach-shmobile/Kconfig
@@ -73,6 +73,10 @@ config ARCH_R8A7743
select ARCH_RCAR_GEN2
select ARM_ERRATA_798181 if SMP
+config ARCH_R8A7745
+ bool "RZ/G1E (R8A77450)"
+ select ARCH_RCAR_GEN2
+
config ARCH_R8A7778
bool "R-Car M1A (R8A77781)"
select ARCH_RCAR_GEN1
Index: renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c
===================================================================
--- renesas.orig/arch/arm/mach-shmobile/setup-rcar-gen2.c
+++ renesas/arch/arm/mach-shmobile/setup-rcar-gen2.c
@@ -227,6 +227,7 @@ MACHINE_END
static const char * const rz_g1_boards_compat_dt[] __initconst = {
"renesas,r8a7743",
+ "renesas,r8a7745",
NULL,
};
^ permalink raw reply [flat|nested] 103+ messages in thread[parent not found: <1611958.qRQu5pdJd3-gHKXc3Y1Z8zGSmamagVegGFoWSdPRAKMAL8bYrjMMd8@public.gmane.org>]
* Re: [PATCH v2 03/11] ARM: shmobile: r8a7745: basic SoC support
2016-11-04 21:49 ` Sergei Shtylyov
(?)
@ 2016-11-14 15:55 ` Rob Herring
-1 siblings, 0 replies; 103+ messages in thread
From: Rob Herring @ 2016-11-14 15:55 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
mark.rutland-5wv7dgnIgG8, devicetree-u79uwXL29TY76Z2rM5mHXA,
magnus.damm-Re5JQEeQqe8AvxtiuMwx3w, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
On Sat, Nov 05, 2016 at 12:49:55AM +0300, Sergei Shtylyov wrote:
> Add minimal support for the RZ/G1E (R8A7745) SoC.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
> Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
>
> ---
> Changes in version 2:
> - added Geert's tag;
> - refreshed the patch.
>
> Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
> arch/arm/mach-shmobile/Kconfig | 4 ++++
> arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
> 3 files changed, 7 insertions(+)
Acked-by: Rob Herring <robh-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 03/11] ARM: shmobile: r8a7745: basic SoC support
@ 2016-11-14 15:55 ` Rob Herring
0 siblings, 0 replies; 103+ messages in thread
From: Rob Herring @ 2016-11-14 15:55 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Nov 05, 2016 at 12:49:55AM +0300, Sergei Shtylyov wrote:
> Add minimal support for the RZ/G1E (R8A7745) SoC.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 2:
> - added Geert's tag;
> - refreshed the patch.
>
> Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
> arch/arm/mach-shmobile/Kconfig | 4 ++++
> arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
> 3 files changed, 7 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH v2 03/11] ARM: shmobile: r8a7745: basic SoC support
@ 2016-11-14 15:55 ` Rob Herring
0 siblings, 0 replies; 103+ messages in thread
From: Rob Herring @ 2016-11-14 15:55 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: horms, linux-renesas-soc, mark.rutland, devicetree, magnus.damm,
linux, linux-arm-kernel
On Sat, Nov 05, 2016 at 12:49:55AM +0300, Sergei Shtylyov wrote:
> Add minimal support for the RZ/G1E (R8A7745) SoC.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 2:
> - added Geert's tag;
> - refreshed the patch.
>
> Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
> arch/arm/mach-shmobile/Kconfig | 4 ++++
> arch/arm/mach-shmobile/setup-rcar-gen2.c | 1 +
> 3 files changed, 7 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 08/11] ARM: dts: r8a7745: add IRQC support
2016-11-04 21:42 ` Sergei Shtylyov
(?)
@ 2016-11-04 21:59 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:59 UTC (permalink / raw)
To: horms-/R6kz+dDXgpPR4JQBCEnsQ,
linux-renesas-soc-u79uwXL29TY76Z2rM5mHXA,
robh+dt-DgEjT+Ai2ygdnm+yROfE0A, mark.rutland-5wv7dgnIgG8,
devicetree-u79uwXL29TY76Z2rM5mHXA
Cc: magnus.damm-Re5JQEeQqe8AvxtiuMwx3w, linux-lFZ/pmaqli7XmaaqVzeoHQ,
linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r
Describe the IRQC interrupt controller in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov-M4DtvfQ/ZS1MRgGoP+s0PdBPR1lH4CV8@public.gmane.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas-gXvu3+zWzMSzQB+pC5nmwQ@public.gmane.org>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
--
To unsubscribe from this list: send the line "unsubscribe devicetree" in
the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 08/11] ARM: dts: r8a7745: add IRQC support
@ 2016-11-04 21:59 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:59 UTC (permalink / raw)
To: linux-arm-kernel
Describe the IRQC interrupt controller in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller at e61c0000 {
+ compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 08/11] ARM: dts: r8a7745: add IRQC support
@ 2016-11-04 21:59 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 21:59 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Describe the IRQC interrupt controller in the R8A7745 device tree.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag;
- refreshed the patch.
arch/arm/boot/dts/r8a7745.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
Index: renesas/arch/arm/boot/dts/r8a7745.dtsi
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745.dtsi
+++ renesas/arch/arm/boot/dts/r8a7745.dtsi
@@ -62,6 +62,25 @@
IRQ_TYPE_LEVEL_HIGH)>;
};
+ irqc: interrupt-controller@e61c0000 {
+ compatible = "renesas,irqc-r8a7745", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A7745_PD_ALWAYS_ON>;
+ };
+
timer {
compatible = "arm,armv7-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 09/11] ARM: shmobile: document SK-RZG1E board
2016-11-04 21:42 ` Sergei Shtylyov
` (6 preceding siblings ...)
(?)
@ 2016-11-04 22:02 ` Sergei Shtylyov
2016-11-14 15:56 ` Rob Herring
-1 siblings, 1 reply; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 22:02 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Document the SK-RZG1E device tree bindings, listing it as a supported board.
This allows to use checkpatch.pl to validate .dts files referring to the
SK-RZG1E board.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- fixed the subject;
- added Geert's tag.
Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
1 file changed, 2 insertions(+)
Index: renesas/Documentation/devicetree/bindings/arm/shmobile.txt
===================================================================
--- renesas.orig/Documentation/devicetree/bindings/arm/shmobile.txt
+++ renesas/Documentation/devicetree/bindings/arm/shmobile.txt
@@ -77,6 +77,8 @@ Boards:
compatible = "renesas,salvator-x", "renesas,r8a7796";
- SILK (RTP0RC7794LCB00011S)
compatible = "renesas,silk", "renesas,r8a7794"
+ - SK-RZG1E (YR8A77450S000BE)
+ compatible = "renesas,sk-rzg1e", "renesas,r8a7745"
- SK-RZG1M (YR8A77430S000BE)
compatible = "renesas,sk-rzg1m", "renesas,r8a7743"
- Wheat
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH v2 09/11] ARM: shmobile: document SK-RZG1E board
2016-11-04 22:02 ` [PATCH v2 09/11] ARM: shmobile: document SK-RZG1E board Sergei Shtylyov
@ 2016-11-14 15:56 ` Rob Herring
0 siblings, 0 replies; 103+ messages in thread
From: Rob Herring @ 2016-11-14 15:56 UTC (permalink / raw)
To: Sergei Shtylyov; +Cc: horms, linux-renesas-soc, mark.rutland, devicetree
On Sat, Nov 05, 2016 at 01:02:25AM +0300, Sergei Shtylyov wrote:
> Document the SK-RZG1E device tree bindings, listing it as a supported board.
>
> This allows to use checkpatch.pl to validate .dts files referring to the
> SK-RZG1E board.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> ---
> Changes in version 2:
> - fixed the subject;
> - added Geert's tag.
>
> Documentation/devicetree/bindings/arm/shmobile.txt | 2 ++
> 1 file changed, 2 insertions(+)
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 10/11] ARM: dts: sk-rzg1e: initial device tree
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 22:04 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 22:04 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Add the initial device tree for the R8A7745 SoC based SK-RZG1E board.
The board has 1 debug serial port (SCIF2); include support for it,
so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/Makefile | 1
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 +++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for the SK-RZG1E board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7745.dtsi"
+
+/ {
+ model = "SK-RZG1E";
+ compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 10/11] ARM: dts: sk-rzg1e: initial device tree
@ 2016-11-04 22:04 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 22:04 UTC (permalink / raw)
To: linux-arm-kernel
Add the initial device tree for the R8A7745 SoC based SK-RZG1E board.
The board has 1 debug serial port (SCIF2); include support for it,
so that the serial console can work.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/Makefile | 1
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 39 +++++++++++++++++++++++++++++++++
2 files changed, 40 insertions(+)
Index: renesas/arch/arm/boot/dts/Makefile
===================================================================
--- renesas.orig/arch/arm/boot/dts/Makefile
+++ renesas/arch/arm/boot/dts/Makefile
@@ -678,6 +678,7 @@ dtb-$(CONFIG_ARCH_SHMOBILE_MULTI) += \
r8a73a4-ape6evm.dtb \
r8a7740-armadillo800eva.dtb \
r8a7743-sk-rzg1m.dtb \
+ r8a7745-sk-rzg1e.dtb \
r8a7778-bockw.dtb \
r8a7779-marzen.dtb \
r8a7790-lager.dtb \
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- /dev/null
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -0,0 +1,39 @@
+/*
+ * Device Tree Source for the SK-RZG1E board
+ *
+ * Copyright (C) 2016 Cogent Embedded, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2. This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+/dts-v1/;
+#include "r8a7745.dtsi"
+
+/ {
+ model = "SK-RZG1E";
+ compatible = "renesas,sk-rzg1e", "renesas,r8a7745";
+
+ aliases {
+ serial0 = &scif2;
+ };
+
+ chosen {
+ bootargs = "ignore_loglevel";
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory at 40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x40000000>;
+ };
+};
+
+&extal_clk {
+ clock-frequency = <20000000>;
+};
+
+&scif2 {
+ status = "okay";
+};
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 11/11] ARM: dts: sk-rzg1e: add Ether support
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-04 22:05 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 22:05 UTC (permalink / raw)
To: horms, linux-renesas-soc, robh+dt, mark.rutland, devicetree
Cc: magnus.damm, linux, linux-arm-kernel
Define the SK-RZG1E board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -37,3 +37,16 @@
&scif2 {
status = "okay";
};
+
+ðer {
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy@1 {
+ reg = <1>;
+ interrupt-parent = <&irqc>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH v2 11/11] ARM: dts: sk-rzg1e: add Ether support
@ 2016-11-04 22:05 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2016-11-04 22:05 UTC (permalink / raw)
To: linux-arm-kernel
Define the SK-RZG1E board dependent part of the Ether device node.
Enable DHCP and NFS root for the kernel booting.
Based on the original (and large) patch by Dmitry Shifrin
<dmitry.shifrin@cogentembedded.com>.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
Changes in version 2:
- added Geert's tag.
arch/arm/boot/dts/r8a7745-sk-rzg1e.dts | 15 ++++++++++++++-
1 file changed, 14 insertions(+), 1 deletion(-)
Index: renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
===================================================================
--- renesas.orig/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
+++ renesas/arch/arm/boot/dts/r8a7745-sk-rzg1e.dts
@@ -20,7 +20,7 @@
};
chosen {
- bootargs = "ignore_loglevel";
+ bootargs = "ignore_loglevel rw root=/dev/nfs ip=dhcp";
stdout-path = "serial0:115200n8";
};
@@ -37,3 +37,16 @@
&scif2 {
status = "okay";
};
+
+ðer {
+ phy-handle = <&phy1>;
+ renesas,ether-link-active-low;
+ status = "okay";
+
+ phy1: ethernet-phy at 1 {
+ reg = <1>;
+ interrupt-parent = <&irqc>;
+ interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
+ micrel,led-mode = <1>;
+ };
+};
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH v2 0/11] Add R8A7745/SK-RZG1E board support
2016-11-04 21:42 ` Sergei Shtylyov
@ 2016-11-15 17:55 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2016-11-15 17:55 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, robh+dt, mark.rutland, devicetree,
magnus.damm, linux, linux-arm-kernel
On Sat, Nov 05, 2016 at 12:42:33AM +0300, Sergei Shtylyov wrote:
> Hello.
>
> Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-201611104-v4.9-rc3' tag plus the R8A7743/SK-RZG1M patch series
> posted earlier. I'm adding the device tree support for the R8A7745-based
> SK-RZG1E board. The SoC is close to R8A7794 and the board seems identical to the
> R8A7794/SILK board. The device tree patches depend on the R8A7745 CPG/MSSR
> driver series in order to compile and work.
Thanks, I have queued this up.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH v2 0/11] Add R8A7745/SK-RZG1E board support
@ 2016-11-15 17:55 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2016-11-15 17:55 UTC (permalink / raw)
To: linux-arm-kernel
On Sat, Nov 05, 2016 at 12:42:33AM +0300, Sergei Shtylyov wrote:
> Hello.
>
> Here's the set of 11 patches against Simon Horman's 'renesas.git' repo's
> 'renesas-devel-201611104-v4.9-rc3' tag plus the R8A7743/SK-RZG1M patch series
> posted earlier. I'm adding the device tree support for the R8A7745-based
> SK-RZG1E board. The SoC is close to R8A7794 and the board seems identical to the
> R8A7794/SILK board. The device tree patches depend on the R8A7745 CPG/MSSR
> driver series in order to compile and work.
Thanks, I have queued this up.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
2016-11-04 21:42 ` Sergei Shtylyov
(?)
@ 2018-07-17 20:08 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-17 20:08 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, Mark Rutland, devicetree
Cc: Will Deacon, Catalin Marinas, Magnus Damm, linux-arm-kernel
Describe the INTC-EX interrupt controller in the R8A77980 device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180717-v4.18-rc5' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -234,6 +234,22 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77980",
"renesas,rcar-gen3-i2c";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
@ 2018-07-17 20:08 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-17 20:08 UTC (permalink / raw)
To: linux-arm-kernel
Describe the INTC-EX interrupt controller in the R8A77980 device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180717-v4.18-rc5' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -234,6 +234,22 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller at e61c0000 {
+ compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
i2c0: i2c at e6500000 {
compatible = "renesas,i2c-r8a77980",
"renesas,rcar-gen3-i2c";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
@ 2018-07-17 20:08 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-17 20:08 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, Mark Rutland, devicetree
Cc: Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
Describe the INTC-EX interrupt controller in the R8A77980 device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180717-v4.18-rc5' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -234,6 +234,22 @@
#power-domain-cells = <1>;
};
+ intc_ex: interrupt-controller@e61c0000 {
+ compatible = "renesas,intc-ex-r8a77980", "renesas,irqc";
+ #interrupt-cells = <2>;
+ interrupt-controller;
+ reg = <0 0xe61c0000 0 0x200>;
+ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH
+ GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 407>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 407>;
+ };
+
i2c0: i2c@e6500000 {
compatible = "renesas,i2c-r8a77980",
"renesas,rcar-gen3-i2c";
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
2018-07-17 20:08 ` Sergei Shtylyov
(?)
@ 2018-07-18 8:55 ` Geert Uytterhoeven
-1 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-18 8:55 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Magnus Damm, Rob Herring, Linux-Renesas,
Simon Horman, Will Deacon, Linux ARM
On Tue, Jul 17, 2018 at 10:08 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the INTC-EX interrupt controller in the R8A77980 device tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
@ 2018-07-18 8:55 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-18 8:55 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 17, 2018 at 10:08 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the INTC-EX interrupt controller in the R8A77980 device tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
@ 2018-07-18 8:55 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-18 8:55 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Linux-Renesas, Rob Herring, Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Linux ARM, Catalin Marinas, Will Deacon
On Tue, Jul 17, 2018 at 10:08 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the INTC-EX interrupt controller in the R8A77980 device tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
2018-07-17 20:08 ` Sergei Shtylyov
(?)
@ 2018-07-18 9:51 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-18 9:51 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Tue, Jul 17, 2018 at 11:08:27PM +0300, Sergei Shtylyov wrote:
> Describe the INTC-EX interrupt controller in the R8A77980 device tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
@ 2018-07-18 9:51 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-18 9:51 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 17, 2018 at 11:08:27PM +0300, Sergei Shtylyov wrote:
> Describe the INTC-EX interrupt controller in the R8A77980 device tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied.
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add INTC-EX support
@ 2018-07-18 9:51 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-18 9:51 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Rob Herring, Mark Rutland, devicetree,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On Tue, Jul 17, 2018 at 11:08:27PM +0300, Sergei Shtylyov wrote:
> Describe the INTC-EX interrupt controller in the R8A77980 device tree.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2016-11-04 21:42 ` Sergei Shtylyov
(?)
@ 2018-07-20 19:21 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-20 19:21 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree
Cc: Mark Rutland, Catalin Marinas, Magnus Damm, Will Deacon,
linux-arm-kernel
Describe RWDT in the R8A77980 SoC device tree.
Enable RWDT on the Condor and V3H Starter Kit boards.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
(adding the RWDT clock) in order to work...
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 10 ++++++++++
3 files changed, 20 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -262,6 +262,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -191,6 +191,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -118,6 +118,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77980-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77980",
"renesas,rcar-gen3-gpio";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-20 19:21 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-20 19:21 UTC (permalink / raw)
To: linux-arm-kernel
Describe RWDT in the R8A77980 SoC device tree.
Enable RWDT on the Condor and V3H Starter Kit boards.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
(adding the RWDT clock) in order to work...
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 10 ++++++++++
3 files changed, 20 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -262,6 +262,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -191,6 +191,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -118,6 +118,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog at e6020000 {
+ compatible = "renesas,r8a77980-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio at e6050000 {
compatible = "renesas,gpio-r8a77980",
"renesas,rcar-gen3-gpio";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-20 19:21 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-20 19:21 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel, Catalin Marinas,
Will Deacon
Describe RWDT in the R8A77980 SoC device tree.
Enable RWDT on the Condor and V3H Starter Kit boards.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
(adding the RWDT clock) in order to work...
arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts | 5 +++++
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 10 ++++++++++
3 files changed, 20 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
@@ -262,6 +262,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980-v3hsk.dts
@@ -191,6 +191,11 @@
};
};
+&rwdt {
+ timeout-sec = <60>;
+ status = "okay";
+};
+
&scif0 {
pinctrl-0 = <&scif0_pins>, <&scif_clk_pins>;
pinctrl-names = "default";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -118,6 +118,16 @@
#size-cells = <2>;
ranges;
+ rwdt: watchdog@e6020000 {
+ compatible = "renesas,r8a77980-wdt",
+ "renesas,rcar-gen3-wdt";
+ reg = <0 0xe6020000 0 0x0c>;
+ clocks = <&cpg CPG_MOD 402>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 402>;
+ status = "disabled";
+ };
+
gpio0: gpio@e6050000 {
compatible = "renesas,gpio-r8a77980",
"renesas,rcar-gen3-gpio";
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2018-07-20 19:21 ` Sergei Shtylyov
(?)
@ 2018-07-23 16:08 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-23 16:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Fri, Jul 20, 2018 at 10:21:45PM +0300, Sergei Shtylyov wrote:
> Describe RWDT in the R8A77980 SoC device tree.
>
> Enable RWDT on the Condor and V3H Starter Kit boards.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
> (adding the RWDT clock) in order to work...
But it is safe to apply without those patches, right?
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-23 16:08 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-23 16:08 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 20, 2018 at 10:21:45PM +0300, Sergei Shtylyov wrote:
> Describe RWDT in the R8A77980 SoC device tree.
>
> Enable RWDT on the Condor and V3H Starter Kit boards.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
> (adding the RWDT clock) in order to work...
But it is safe to apply without those patches, right?
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-23 16:08 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-23 16:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On Fri, Jul 20, 2018 at 10:21:45PM +0300, Sergei Shtylyov wrote:
> Describe RWDT in the R8A77980 SoC device tree.
>
> Enable RWDT on the Condor and V3H Starter Kit boards.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
> (adding the RWDT clock) in order to work...
But it is safe to apply without those patches, right?
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2018-07-23 16:08 ` Simon Horman
(?)
@ 2018-07-23 16:14 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-23 16:14 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On 07/23/2018 07:08 PM, Simon Horman wrote:
>> Describe RWDT in the R8A77980 SoC device tree.
>>
>> Enable RWDT on the Condor and V3H Starter Kit boards.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
>> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
>> (adding the RWDT clock) in order to work...
>
> But it is safe to apply without those patches, right?
The RWDT driver should just fail to probe with -ENOENT.
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
TY!
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-23 16:14 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-23 16:14 UTC (permalink / raw)
To: linux-arm-kernel
On 07/23/2018 07:08 PM, Simon Horman wrote:
>> Describe RWDT in the R8A77980 SoC device tree.
>>
>> Enable RWDT on the Condor and V3H Starter Kit boards.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
>> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
>> (adding the RWDT clock) in order to work...
>
> But it is safe to apply without those patches, right?
The RWDT driver should just fail to probe with -ENOENT.
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
TY!
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-23 16:14 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-23 16:14 UTC (permalink / raw)
To: Simon Horman
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On 07/23/2018 07:08 PM, Simon Horman wrote:
>> Describe RWDT in the R8A77980 SoC device tree.
>>
>> Enable RWDT on the Condor and V3H Starter Kit boards.
>>
>> Based on the original (and large) patch by Vladimir Barinov.
>>
>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
>> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
>> (adding the RWDT clock) in order to work...
>
> But it is safe to apply without those patches, right?
The RWDT driver should just fail to probe with -ENOENT.
> Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
TY!
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2018-07-23 16:14 ` Sergei Shtylyov
(?)
@ 2018-07-24 11:45 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-24 11:45 UTC (permalink / raw)
To: Sergei Shtylyov, Geert Uytterhoeven
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Mon, Jul 23, 2018 at 07:14:28PM +0300, Sergei Shtylyov wrote:
> On 07/23/2018 07:08 PM, Simon Horman wrote:
>
> >> Describe RWDT in the R8A77980 SoC device tree.
> >>
> >> Enable RWDT on the Condor and V3H Starter Kit boards.
> >>
> >> Based on the original (and large) patch by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
> >> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
> >> (adding the RWDT clock) in order to work...
> >
> > But it is safe to apply without those patches, right?
>
> The RWDT driver should just fail to probe with -ENOENT.
...
On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe RWDT in the R8A77980 SoC device tree.
> >
> > Enable RWDT on the Condor and V3H Starter Kit boards.
> >
> > Based on the original (and large) patch by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-24 11:45 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-24 11:45 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 23, 2018 at 07:14:28PM +0300, Sergei Shtylyov wrote:
> On 07/23/2018 07:08 PM, Simon Horman wrote:
>
> >> Describe RWDT in the R8A77980 SoC device tree.
> >>
> >> Enable RWDT on the Condor and V3H Starter Kit boards.
> >>
> >> Based on the original (and large) patch by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
> >> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
> >> (adding the RWDT clock) in order to work...
> >
> > But it is safe to apply without those patches, right?
>
> The RWDT driver should just fail to probe with -ENOENT.
...
On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe RWDT in the R8A77980 SoC device tree.
> >
> > Enable RWDT on the Condor and V3H Starter Kit boards.
> >
> > Based on the original (and large) patch by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-24 11:45 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-24 11:45 UTC (permalink / raw)
To: Sergei Shtylyov, Geert Uytterhoeven
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On Mon, Jul 23, 2018 at 07:14:28PM +0300, Sergei Shtylyov wrote:
> On 07/23/2018 07:08 PM, Simon Horman wrote:
>
> >> Describe RWDT in the R8A77980 SoC device tree.
> >>
> >> Enable RWDT on the Condor and V3H Starter Kit boards.
> >>
> >> Based on the original (and large) patch by Vladimir Barinov.
> >>
> >> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> The patch is against the 'renesas-devel-20180720-v4.18-rc5' of Simon Horman's
> >> 'renesas.git' repo. It depends on Geert Uytterhoeven's clock driver patches
> >> (adding the RWDT clock) in order to work...
> >
> > But it is safe to apply without those patches, right?
>
> The RWDT driver should just fail to probe with -ENOENT.
...
On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe RWDT in the R8A77980 SoC device tree.
> >
> > Enable RWDT on the Condor and V3H Starter Kit boards.
> >
> > Based on the original (and large) patch by Vladimir Barinov.
> >
> > Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2018-07-24 11:45 ` Simon Horman
(?)
@ 2018-07-25 15:08 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-25 15:08 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
Hello!
On 07/24/2018 02:45 PM, Simon Horman wrote:
[...]
> On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
>> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
>> <sergei.shtylyov@cogentembedded.com> wrote:
>>> Describe RWDT in the R8A77980 SoC device tree.
>>>
>>> Enable RWDT on the Condor and V3H Starter Kit boards.
>>>
>>> Based on the original (and large) patch by Vladimir Barinov.
>>>
>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks, applied for v4.20.
Sorry, still not seeing any 'devel' branch updates... forgot to push?
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-25 15:08 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-25 15:08 UTC (permalink / raw)
To: linux-arm-kernel
Hello!
On 07/24/2018 02:45 PM, Simon Horman wrote:
[...]
> On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
>> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
>> <sergei.shtylyov@cogentembedded.com> wrote:
>>> Describe RWDT in the R8A77980 SoC device tree.
>>>
>>> Enable RWDT on the Condor and V3H Starter Kit boards.
>>>
>>> Based on the original (and large) patch by Vladimir Barinov.
>>>
>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks, applied for v4.20.
Sorry, still not seeing any 'devel' branch updates... forgot to push?
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-25 15:08 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-25 15:08 UTC (permalink / raw)
To: Simon Horman, Geert Uytterhoeven
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
Hello!
On 07/24/2018 02:45 PM, Simon Horman wrote:
[...]
> On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
>> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
>> <sergei.shtylyov@cogentembedded.com> wrote:
>>> Describe RWDT in the R8A77980 SoC device tree.
>>>
>>> Enable RWDT on the Condor and V3H Starter Kit boards.
>>>
>>> Based on the original (and large) patch by Vladimir Barinov.
>>>
>>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Thanks, applied for v4.20.
Sorry, still not seeing any 'devel' branch updates... forgot to push?
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2018-07-25 15:08 ` Sergei Shtylyov
(?)
@ 2018-07-25 16:08 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-25 16:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, Geert Uytterhoeven,
linux-arm-kernel
On Wed, Jul 25, 2018 at 06:08:21PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 07/24/2018 02:45 PM, Simon Horman wrote:
>
> [...]
> > On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> >> <sergei.shtylyov@cogentembedded.com> wrote:
> >>> Describe RWDT in the R8A77980 SoC device tree.
> >>>
> >>> Enable RWDT on the Condor and V3H Starter Kit boards.
> >>>
> >>> Based on the original (and large) patch by Vladimir Barinov.
> >>>
> >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Thanks, applied for v4.20.
>
> Sorry, still not seeing any 'devel' branch updates... forgot to push?
I did push but, as discussed elsewhere, it seems that there was a glitch
in The Matrix. Updates are now there after repushing them.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-25 16:08 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-25 16:08 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 25, 2018 at 06:08:21PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 07/24/2018 02:45 PM, Simon Horman wrote:
>
> [...]
> > On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> >> <sergei.shtylyov@cogentembedded.com> wrote:
> >>> Describe RWDT in the R8A77980 SoC device tree.
> >>>
> >>> Enable RWDT on the Condor and V3H Starter Kit boards.
> >>>
> >>> Based on the original (and large) patch by Vladimir Barinov.
> >>>
> >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Thanks, applied for v4.20.
>
> Sorry, still not seeing any 'devel' branch updates... forgot to push?
I did push but, as discussed elsewhere, it seems that there was a glitch
in The Matrix. Updates are now there after repushing them.
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-25 16:08 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-25 16:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Geert Uytterhoeven, linux-renesas-soc, Rob Herring, devicetree,
Mark Rutland, Magnus Damm, linux-arm-kernel, Catalin Marinas,
Will Deacon
On Wed, Jul 25, 2018 at 06:08:21PM +0300, Sergei Shtylyov wrote:
> Hello!
>
> On 07/24/2018 02:45 PM, Simon Horman wrote:
>
> [...]
> > On Tue, Jul 24, 2018 at 09:01:59AM +0200, Geert Uytterhoeven wrote:
> >> On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
> >> <sergei.shtylyov@cogentembedded.com> wrote:
> >>> Describe RWDT in the R8A77980 SoC device tree.
> >>>
> >>> Enable RWDT on the Condor and V3H Starter Kit boards.
> >>>
> >>> Based on the original (and large) patch by Vladimir Barinov.
> >>>
> >>> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> >>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> >
> > Thanks, applied for v4.20.
>
> Sorry, still not seeing any 'devel' branch updates... forgot to push?
I did push but, as discussed elsewhere, it seems that there was a glitch
in The Matrix. Updates are now there after repushing them.
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
2018-07-20 19:21 ` Sergei Shtylyov
(?)
@ 2018-07-24 7:01 ` Geert Uytterhoeven
-1 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-24 7:01 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Magnus Damm, Rob Herring, Linux-Renesas,
Simon Horman, Will Deacon, Linux ARM
On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe RWDT in the R8A77980 SoC device tree.
>
> Enable RWDT on the Condor and V3H Starter Kit boards.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-24 7:01 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-24 7:01 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe RWDT in the R8A77980 SoC device tree.
>
> Enable RWDT on the Condor and V3H Starter Kit boards.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add RWDT support
@ 2018-07-24 7:01 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-24 7:01 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Linux-Renesas, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Mark Rutland, Magnus Damm, Linux ARM, Catalin Marinas,
Will Deacon
On Fri, Jul 20, 2018 at 9:21 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe RWDT in the R8A77980 SoC device tree.
>
> Enable RWDT on the Condor and V3H Starter Kit boards.
>
> Based on the original (and large) patch by Vladimir Barinov.
>
> Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
2016-11-04 21:42 ` Sergei Shtylyov
@ 2018-07-25 16:43 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-25 16:43 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree,
Catalin Marinas, Will Deacon
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77970 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180724-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,15 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-25 16:43 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-25 16:43 UTC (permalink / raw)
To: linux-arm-kernel
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77970 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180724-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,15 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
2018-07-25 16:43 ` Sergei Shtylyov
(?)
@ 2018-07-25 17:34 ` Geert Uytterhoeven
-1 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-25 17:34 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> the R8A77970 SoC's device tree.
8?
Can you hack up a check in checkpatch.pl to catch such mistakes? ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-25 17:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-25 17:34 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> the R8A77970 SoC's device tree.
8?
Can you hack up a check in checkpatch.pl to catch such mistakes? ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-25 17:34 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-25 17:34 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Linux-Renesas, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Will Deacon, Mark Rutland, Magnus Damm,
Linux ARM
On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> the R8A77970 SoC's device tree.
8?
Can you hack up a check in checkpatch.pl to catch such mistakes? ;-)
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
2018-07-25 17:34 ` Geert Uytterhoeven
(?)
@ 2018-07-26 12:33 ` Geert Uytterhoeven
-1 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-26 12:33 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > the R8A77970 SoC's device tree.
>
> 8?
With that fixes:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-26 12:33 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-26 12:33 UTC (permalink / raw)
To: linux-arm-kernel
On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > the R8A77970 SoC's device tree.
>
> 8?
With that fixes:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-26 12:33 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-26 12:33 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Linux-Renesas, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Will Deacon, Mark Rutland, Magnus Damm,
Linux ARM
On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > the R8A77970 SoC's device tree.
>
> 8?
With that fixes:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
2018-07-26 12:33 ` Geert Uytterhoeven
(?)
@ 2018-07-26 13:53 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-26 13:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Sergei Shtylyov, Catalin Marinas, Will Deacon,
Linux-Renesas, Rob Herring, Linux ARM
On Thu, Jul 26, 2018 at 02:33:55PM +0200, Geert Uytterhoeven wrote:
> On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> > <sergei.shtylyov@cogentembedded.com> wrote:
> > > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > > the R8A77970 SoC's device tree.
> >
> > 8?
>
> With that fixes:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have applied the following for v4.20.
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77980 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index d3532fd4c94a..1013da3e2ec4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,15 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.11.0
^ permalink raw reply related [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-26 13:53 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-26 13:53 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 26, 2018 at 02:33:55PM +0200, Geert Uytterhoeven wrote:
> On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> > <sergei.shtylyov@cogentembedded.com> wrote:
> > > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > > the R8A77970 SoC's device tree.
> >
> > 8?
>
> With that fixes:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have applied the following for v4.20.
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77980 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index d3532fd4c94a..1013da3e2ec4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,15 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.11.0
^ permalink raw reply related [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
@ 2018-07-26 13:53 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-26 13:53 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Linux-Renesas, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Will Deacon, Mark Rutland, Magnus Damm,
Linux ARM
On Thu, Jul 26, 2018 at 02:33:55PM +0200, Geert Uytterhoeven wrote:
> On Wed, Jul 25, 2018 at 7:34 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
> > On Wed, Jul 25, 2018 at 6:44 PM Sergei Shtylyov
> > <sergei.shtylyov@cogentembedded.com> wrote:
> > > Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
> > > the R8A77970 SoC's device tree.
> >
> > 8?
>
> With that fixes:
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, I have applied the following for v4.20.
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Subject: [PATCH] arm64: dts: renesas: r8a77980: add Cortex-A53 PMU support
Describe the performance monitor unit (PMU) for the Cortex-A53 cores in
the R8A77980 SoC's device tree.
Based on the original (and large) patch by Vladimir Barinov.
Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com>
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index d3532fd4c94a..1013da3e2ec4 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -98,6 +98,15 @@
clock-frequency = <0>;
};
+ pmu_a53 {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>,
+ <&gic GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&a53_0>, <&a53_1>, <&a53_2>, <&a53_3>;
+ };
+
psci {
compatible = "arm,psci-1.0", "arm,psci-0.2";
method = "smc";
--
2.11.0
^ permalink raw reply related [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: move IPMMU nodes
2016-11-04 21:42 ` Sergei Shtylyov
@ 2018-07-26 18:51 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-26 18:51 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree,
Catalin Marinas, Will Deacon
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
The IPMMU nodes should follow the GEther node, not the CAN-FD node,
according to the <unit-address> part of the startng IPMMU-DS1 node.
While moving the nodes, also do sort them by label alphanumerically...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 126 +++++++++++++++---------------
1 file changed, 63 insertions(+), 63 deletions(-)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -462,69 +462,6 @@
};
};
- ipmmu_ds1: mmu@e7740000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip0: mmu@e7b00000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7b00000 0 0x1000>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip1: mmu@e7960000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7960000 0 0x1000>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: mmu@ff8b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xff8b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
- power-domains = <&sysc R8A77980_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: mmu@e67b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: mmu@ffc80000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: mmu@fe6b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: mmu@febd0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
avb: ethernet@e6800000 {
compatible = "renesas,etheravb-r8a77980",
"renesas,etheravb-rcar-gen3";
@@ -722,6 +659,69 @@
status = "disabled";
};
+ ipmmu_ds1: mmu@e7740000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ir: mmu@ff8b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xff8b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 3>;
+ power-domains = <&sysc R8A77980_PD_A3IR>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: mmu@e67b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_rt: mmu@ffc80000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xffc80000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: mmu@fe6b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: mmu@febd0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip0: mmu@e7b00000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7b00000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip1: mmu@e7960000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7960000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
mmc0: mmc@ee140000 {
compatible = "renesas,sdhi-r8a77980",
"renesas,rcar-gen3-sdhi";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: move IPMMU nodes
@ 2018-07-26 18:51 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-26 18:51 UTC (permalink / raw)
To: linux-arm-kernel
The IPMMU nodes should follow the GEther node, not the CAN-FD node,
according to the <unit-address> part of the startng IPMMU-DS1 node.
While moving the nodes, also do sort them by label alphanumerically...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 126 +++++++++++++++---------------
1 file changed, 63 insertions(+), 63 deletions(-)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -462,69 +462,6 @@
};
};
- ipmmu_ds1: mmu at e7740000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7740000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 0>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip0: mmu at e7b00000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7b00000 0 0x1000>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vip1: mmu at e7960000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe7960000 0 0x1000>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_ir: mmu at ff8b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xff8b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 3>;
- power-domains = <&sysc R8A77980_PD_A3IR>;
- #iommu-cells = <1>;
- };
-
- ipmmu_mm: mmu at e67b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xe67b0000 0 0x1000>;
- interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_rt: mmu at ffc80000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xffc80000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 10>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vc0: mmu at fe6b0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xfe6b0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 12>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
- ipmmu_vi0: mmu at febd0000 {
- compatible = "renesas,ipmmu-r8a77980";
- reg = <0 0xfebd0000 0 0x1000>;
- renesas,ipmmu-main = <&ipmmu_mm 14>;
- power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
- #iommu-cells = <1>;
- };
-
avb: ethernet at e6800000 {
compatible = "renesas,etheravb-r8a77980",
"renesas,etheravb-rcar-gen3";
@@ -722,6 +659,69 @@
status = "disabled";
};
+ ipmmu_ds1: mmu at e7740000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7740000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 0>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_ir: mmu at ff8b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xff8b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 3>;
+ power-domains = <&sysc R8A77980_PD_A3IR>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_mm: mmu at e67b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe67b0000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_rt: mmu at ffc80000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xffc80000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 10>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vc0: mmu at fe6b0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfe6b0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 12>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vi0: mmu at febd0000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xfebd0000 0 0x1000>;
+ renesas,ipmmu-main = <&ipmmu_mm 14>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip0: mmu at e7b00000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7b00000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
+ ipmmu_vip1: mmu at e7960000 {
+ compatible = "renesas,ipmmu-r8a77980";
+ reg = <0 0xe7960000 0 0x1000>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ #iommu-cells = <1>;
+ };
+
mmc0: mmc at ee140000 {
compatible = "renesas,sdhi-r8a77980",
"renesas,rcar-gen3-sdhi";
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: move IPMMU nodes
2018-07-26 18:51 ` Sergei Shtylyov
(?)
@ 2018-07-31 10:24 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-31 10:24 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Magnus Damm, Catalin Marinas,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Thu, Jul 26, 2018 at 09:51:18PM +0300, Sergei Shtylyov wrote:
> The IPMMU nodes should follow the GEther node, not the CAN-FD node,
> according to the <unit-address> part of the startng IPMMU-DS1 node.
> While moving the nodes, also do sort them by label alphanumerically...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: move IPMMU nodes
@ 2018-07-31 10:24 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-31 10:24 UTC (permalink / raw)
To: linux-arm-kernel
On Thu, Jul 26, 2018 at 09:51:18PM +0300, Sergei Shtylyov wrote:
> The IPMMU nodes should follow the GEther node, not the CAN-FD node,
> according to the <unit-address> part of the startng IPMMU-DS1 node.
> While moving the nodes, also do sort them by label alphanumerically...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* Re: [PATCH] arm64: dts: renesas: r8a77980: move IPMMU nodes
@ 2018-07-31 10:24 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-31 10:24 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Rob Herring, devicetree, Catalin Marinas,
Will Deacon, Mark Rutland, Magnus Damm, linux-arm-kernel
On Thu, Jul 26, 2018 at 09:51:18PM +0300, Sergei Shtylyov wrote:
> The IPMMU nodes should follow the GEther node, not the CAN-FD node,
> according to the <unit-address> part of the startng IPMMU-DS1 node.
> While moving the nodes, also do sort them by label alphanumerically...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Thanks Sergei, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
2016-11-04 21:42 ` Sergei Shtylyov
@ 2018-07-30 18:22 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-30 18:22 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree,
Catalin Marinas, Will Deacon
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device trees, according to the alphanumeric node sorting rule...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 14 +++++++-------
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -24,6 +24,13 @@
i2c4 = &i2c4;
};
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,13 +89,6 @@
method = "smc";
};
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -25,6 +25,13 @@
i2c5 = &i2c5;
};
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -77,13 +84,6 @@
};
};
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
@ 2018-07-30 18:22 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-07-30 18:22 UTC (permalink / raw)
To: linux-arm-kernel
The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
device trees, according to the alphanumeric node sorting rule...
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
The patch is against the 'renesas-devel-20180726-v4.18-rc6' tag of Simon
Horman's 'renesas.git' repo.
arch/arm64/boot/dts/renesas/r8a77970.dtsi | 14 +++++++-------
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 14 +++++++-------
2 files changed, 14 insertions(+), 14 deletions(-)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77970.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77970.dtsi
@@ -24,6 +24,13 @@
i2c4 = &i2c4;
};
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -82,13 +89,6 @@
method = "smc";
};
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
/* External SCIF clock - to be overridden by boards that provide it */
scif_clk: scif {
compatible = "fixed-clock";
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -25,6 +25,13 @@
i2c5 = &i2c5;
};
+ /* External CAN clock - to be overridden by boards that provide it */
+ can_clk: can {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <0>;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -77,13 +84,6 @@
};
};
- /* External CAN clock - to be overridden by boards that provide it */
- can_clk: can {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <0>;
- };
-
extal_clk: extal {
compatible = "fixed-clock";
#clock-cells = <0>;
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
2018-07-30 18:22 ` Sergei Shtylyov
(?)
@ 2018-07-31 6:45 ` Geert Uytterhoeven
-1 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-31 6:45 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Catalin Marinas, Will Deacon, Rob Herring,
Linux-Renesas, Simon Horman, Linux ARM
On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> device trees, according to the alphanumeric node sorting rule...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
@ 2018-07-31 6:45 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-31 6:45 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> device trees, according to the alphanumeric node sorting rule...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert at linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
@ 2018-07-31 6:45 ` Geert Uytterhoeven
0 siblings, 0 replies; 103+ messages in thread
From: Geert Uytterhoeven @ 2018-07-31 6:45 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Simon Horman, Linux-Renesas, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Will Deacon, Mark Rutland, Magnus Damm,
Linux ARM
On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
<sergei.shtylyov@cogentembedded.com> wrote:
> The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> device trees, according to the alphanumeric node sorting rule...
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
2018-07-31 6:45 ` Geert Uytterhoeven
(?)
@ 2018-07-31 10:25 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-31 10:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Mark Rutland,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Magnus Damm, Sergei Shtylyov, Catalin Marinas, Will Deacon,
Linux-Renesas, Rob Herring, Linux ARM
On Tue, Jul 31, 2018 at 08:45:11AM +0200, Geert Uytterhoeven wrote:
> On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> > device trees, according to the alphanumeric node sorting rule...
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
@ 2018-07-31 10:25 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-31 10:25 UTC (permalink / raw)
To: linux-arm-kernel
On Tue, Jul 31, 2018 at 08:45:11AM +0200, Geert Uytterhoeven wrote:
> On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> > device trees, according to the alphanumeric node sorting rule...
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a779{7|8}0: move CAN clock node
@ 2018-07-31 10:25 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-07-31 10:25 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Sergei Shtylyov, Linux-Renesas, Rob Herring,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Catalin Marinas, Will Deacon, Mark Rutland, Magnus Damm,
Linux ARM
On Tue, Jul 31, 2018 at 08:45:11AM +0200, Geert Uytterhoeven wrote:
> On Mon, Jul 30, 2018 at 8:22 PM Sergei Shtylyov
> <sergei.shtylyov@cogentembedded.com> wrote:
> > The CAN clock node should precede the "cpus" node in the R8A779{7|8}0
> > device trees, according to the alphanumeric node sorting rule...
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Thanks, applied for v4.20.
^ permalink raw reply [flat|nested] 103+ messages in thread
* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
2016-11-04 21:42 ` Sergei Shtylyov
(?)
@ 2018-08-06 19:55 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-06 19:55 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree
Cc: Mark Rutland, Catalin Marinas, Magnus Damm, Will Deacon,
linux-arm-kernel
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
Simon Horman's 'renesas.git' repo.
The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-06 19:55 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-06 19:55 UTC (permalink / raw)
To: linux-arm-kernel
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
Simon Horman's 'renesas.git' repo.
The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video at e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video at e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video at e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video at e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video at e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video at e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video at e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video at e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video at e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video at e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video at e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller at e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2 at feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display at feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-06 19:55 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-06 19:55 UTC (permalink / raw)
To: Simon Horman, linux-renesas-soc, Rob Herring, devicetree
Cc: Mark Rutland, Magnus Damm, linux-arm-kernel, Catalin Marinas,
Will Deacon
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
---
This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
Simon Horman's 'renesas.git' repo.
The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
===================================================================
--- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
2018-08-06 19:55 ` Sergei Shtylyov
(?)
@ 2018-08-09 13:08 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-09 13:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Mon, Aug 06, 2018 at 10:55:00PM +0300, Sergei Shtylyov wrote:
> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> Simon Horman's 'renesas.git' repo.
>
> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> 1 file changed, 374 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -579,6 +579,302 @@
> status = "disabled";
> };
>
> + vin0: video@e6ef0000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef0000 0 0x1000>;
> + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 811>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 811>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin0csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin0>;
> + };
> + };
> + };
> + };
> +
> + vin1: video@e6ef1000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef1000 0 0x1000>;
> + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 810>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + status = "disabled";
> + resets = <&cpg 810>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin1csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin1>;
> + };
> + };
> + };
> + };
> +
> + vin2: video@e6ef2000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef2000 0 0x1000>;
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 809>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 809>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin2csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin2>;
> + };
> + };
> + };
> + };
> +
> + vin3: video@e6ef3000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef3000 0 0x1000>;
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 808>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 808>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin3csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin3>;
> + };
> + };
> + };
> + };
> +
> + vin4: video@e6ef4000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef4000 0 0x1000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 807>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 807>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin4csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin4>;
> + };
> + };
> + };
> + };
> +
> + vin5: video@e6ef5000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef5000 0 0x1000>;
> + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 806>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 806>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin5csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin5>;
> + };
> + };
> + };
> + };
> +
> + vin6: video@e6ef6000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef6000 0 0x1000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 805>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 805>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin6csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin6>;
> + };
> + };
> + };
> + };
> +
> + vin7: video@e6ef7000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef7000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 804>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 804>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin7csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin7>;
> + };
> + };
> + };
> + };
> +
> + vin8: video@e6ef8000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef8000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 628>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 628>;
> + status = "disabled";
> + };
> +
> + vin9: video@e6ef9000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef9000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 627>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 627>;
> + status = "disabled";
> + };
> +
> + vin10: video@e6efa000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efa000 0 0x1000>;
> + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 625>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 625>;
> + status = "disabled";
> + };
> +
> + vin11: video@e6efb000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efb000 0 0x1000>;
> + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 618>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 618>;
> + status = "disabled";
> + };
> +
> + vin12: video@e6efc000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efc000 0 0x1000>;
> + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 612>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 612>;
> + status = "disabled";
> + };
> +
> + vin13: video@e6efd000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efd000 0 0x1000>;
> + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 608>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 608>;
> + status = "disabled";
> + };
> +
> + vin14: video@e6efe000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efe000 0 0x1000>;
> + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 605>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 605>;
> + status = "disabled";
> + };
> +
> + vin15: video@e6eff000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6eff000 0 0x1000>;
> + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 604>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 604>;
> + status = "disabled";
> + };
> +
> dmac1: dma-controller@e7300000 {
> compatible = "renesas,dmac-r8a77980",
> "renesas,rcar-dmac";
> @@ -769,6 +1065,84 @@
> resets = <&cpg 603>;
> };
>
> + csi40: csi2@feaa0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeaa0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 716>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi40vin0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vin0csi40>;
> + };
> + csi40vin1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vin1csi40>;
> + };
> + csi40vin2: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&vin2csi40>;
> + };
> + csi40vin3: endpoint@3 {
> + reg = <3>;
> + remote-endpoint = <&vin3csi40>;
> + };
> + };
> + };
> + };
> +
> + csi41: csi2@feab0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeab0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
Is this intentional?
> + clocks = <&cpg CPG_MOD 716>;
Should this clock be 715 rather than 716?
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi41vin4: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vin4csi41>;
> + };
> + csi41vin5: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vin5csi41>;
> + };
> + csi41vin6: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&vin6csi41>;
> + };
> + csi41vin7: endpoint@3 {
> + reg = <3>;
> + remote-endpoint = <&vin7csi41>;
> + };
> + };
> + };
> + };
> +
> du: display@feb00000 {
> compatible = "renesas,du-r8a77980",
> "renesas,du-r8a77970";
>
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-09 13:08 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-09 13:08 UTC (permalink / raw)
To: linux-arm-kernel
On Mon, Aug 06, 2018 at 10:55:00PM +0300, Sergei Shtylyov wrote:
> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> Simon Horman's 'renesas.git' repo.
>
> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> 1 file changed, 374 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -579,6 +579,302 @@
> status = "disabled";
> };
>
> + vin0: video at e6ef0000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef0000 0 0x1000>;
> + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 811>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 811>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin0csi40: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin0>;
> + };
> + };
> + };
> + };
> +
> + vin1: video at e6ef1000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef1000 0 0x1000>;
> + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 810>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + status = "disabled";
> + resets = <&cpg 810>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin1csi40: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin1>;
> + };
> + };
> + };
> + };
> +
> + vin2: video at e6ef2000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef2000 0 0x1000>;
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 809>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 809>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin2csi40: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin2>;
> + };
> + };
> + };
> + };
> +
> + vin3: video at e6ef3000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef3000 0 0x1000>;
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 808>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 808>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin3csi40: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin3>;
> + };
> + };
> + };
> + };
> +
> + vin4: video at e6ef4000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef4000 0 0x1000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 807>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 807>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin4csi41: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin4>;
> + };
> + };
> + };
> + };
> +
> + vin5: video at e6ef5000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef5000 0 0x1000>;
> + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 806>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 806>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin5csi41: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin5>;
> + };
> + };
> + };
> + };
> +
> + vin6: video at e6ef6000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef6000 0 0x1000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 805>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 805>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin6csi41: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin6>;
> + };
> + };
> + };
> + };
> +
> + vin7: video at e6ef7000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef7000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 804>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 804>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin7csi41: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin7>;
> + };
> + };
> + };
> + };
> +
> + vin8: video at e6ef8000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef8000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 628>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 628>;
> + status = "disabled";
> + };
> +
> + vin9: video at e6ef9000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef9000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 627>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 627>;
> + status = "disabled";
> + };
> +
> + vin10: video at e6efa000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efa000 0 0x1000>;
> + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 625>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 625>;
> + status = "disabled";
> + };
> +
> + vin11: video at e6efb000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efb000 0 0x1000>;
> + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 618>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 618>;
> + status = "disabled";
> + };
> +
> + vin12: video at e6efc000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efc000 0 0x1000>;
> + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 612>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 612>;
> + status = "disabled";
> + };
> +
> + vin13: video at e6efd000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efd000 0 0x1000>;
> + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 608>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 608>;
> + status = "disabled";
> + };
> +
> + vin14: video at e6efe000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efe000 0 0x1000>;
> + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 605>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 605>;
> + status = "disabled";
> + };
> +
> + vin15: video at e6eff000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6eff000 0 0x1000>;
> + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 604>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 604>;
> + status = "disabled";
> + };
> +
> dmac1: dma-controller at e7300000 {
> compatible = "renesas,dmac-r8a77980",
> "renesas,rcar-dmac";
> @@ -769,6 +1065,84 @@
> resets = <&cpg 603>;
> };
>
> + csi40: csi2 at feaa0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeaa0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 716>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi40vin0: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&vin0csi40>;
> + };
> + csi40vin1: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&vin1csi40>;
> + };
> + csi40vin2: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint = <&vin2csi40>;
> + };
> + csi40vin3: endpoint at 3 {
> + reg = <3>;
> + remote-endpoint = <&vin3csi40>;
> + };
> + };
> + };
> + };
> +
> + csi41: csi2 at feab0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeab0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
Is this intentional?
> + clocks = <&cpg CPG_MOD 716>;
Should this clock be 715 rather than 716?
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi41vin4: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&vin4csi41>;
> + };
> + csi41vin5: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&vin5csi41>;
> + };
> + csi41vin6: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint = <&vin6csi41>;
> + };
> + csi41vin7: endpoint at 3 {
> + reg = <3>;
> + remote-endpoint = <&vin7csi41>;
> + };
> + };
> + };
> + };
> +
> du: display at feb00000 {
> compatible = "renesas,du-r8a77980",
> "renesas,du-r8a77970";
>
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-09 13:08 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-09 13:08 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On Mon, Aug 06, 2018 at 10:55:00PM +0300, Sergei Shtylyov wrote:
> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> Simon Horman's 'renesas.git' repo.
>
> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> 1 file changed, 374 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> @@ -579,6 +579,302 @@
> status = "disabled";
> };
>
> + vin0: video@e6ef0000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef0000 0 0x1000>;
> + interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 811>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 811>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin0csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin0>;
> + };
> + };
> + };
> + };
> +
> + vin1: video@e6ef1000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef1000 0 0x1000>;
> + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 810>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + status = "disabled";
> + resets = <&cpg 810>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin1csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin1>;
> + };
> + };
> + };
> + };
> +
> + vin2: video@e6ef2000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef2000 0 0x1000>;
> + interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 809>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 809>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin2csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin2>;
> + };
> + };
> + };
> + };
> +
> + vin3: video@e6ef3000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef3000 0 0x1000>;
> + interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 808>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 808>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin3csi40: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi40vin3>;
> + };
> + };
> + };
> + };
> +
> + vin4: video@e6ef4000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef4000 0 0x1000>;
> + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 807>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 807>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin4csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin4>;
> + };
> + };
> + };
> + };
> +
> + vin5: video@e6ef5000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef5000 0 0x1000>;
> + interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 806>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 806>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin5csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin5>;
> + };
> + };
> + };
> + };
> +
> + vin6: video@e6ef6000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef6000 0 0x1000>;
> + interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 805>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 805>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin6csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin6>;
> + };
> + };
> + };
> + };
> +
> + vin7: video@e6ef7000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef7000 0 0x1000>;
> + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 804>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 804>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + vin7csi41: endpoint@2 {
> + reg = <2>;
> + remote-endpoint= <&csi41vin7>;
> + };
> + };
> + };
> + };
> +
> + vin8: video@e6ef8000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef8000 0 0x1000>;
> + interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 628>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 628>;
> + status = "disabled";
> + };
> +
> + vin9: video@e6ef9000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6ef9000 0 0x1000>;
> + interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 627>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 627>;
> + status = "disabled";
> + };
> +
> + vin10: video@e6efa000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efa000 0 0x1000>;
> + interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 625>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 625>;
> + status = "disabled";
> + };
> +
> + vin11: video@e6efb000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efb000 0 0x1000>;
> + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 618>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 618>;
> + status = "disabled";
> + };
> +
> + vin12: video@e6efc000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efc000 0 0x1000>;
> + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 612>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 612>;
> + status = "disabled";
> + };
> +
> + vin13: video@e6efd000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efd000 0 0x1000>;
> + interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 608>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 608>;
> + status = "disabled";
> + };
> +
> + vin14: video@e6efe000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6efe000 0 0x1000>;
> + interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 605>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 605>;
> + status = "disabled";
> + };
> +
> + vin15: video@e6eff000 {
> + compatible = "renesas,vin-r8a77980";
> + reg = <0 0xe6eff000 0 0x1000>;
> + interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 604>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 604>;
> + status = "disabled";
> + };
> +
> dmac1: dma-controller@e7300000 {
> compatible = "renesas,dmac-r8a77980",
> "renesas,rcar-dmac";
> @@ -769,6 +1065,84 @@
> resets = <&cpg 603>;
> };
>
> + csi40: csi2@feaa0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeaa0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 716>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi40vin0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vin0csi40>;
> + };
> + csi40vin1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vin1csi40>;
> + };
> + csi40vin2: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&vin2csi40>;
> + };
> + csi40vin3: endpoint@3 {
> + reg = <3>;
> + remote-endpoint = <&vin3csi40>;
> + };
> + };
> + };
> + };
> +
> + csi41: csi2@feab0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeab0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
Is this intentional?
> + clocks = <&cpg CPG_MOD 716>;
Should this clock be 715 rather than 716?
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi41vin4: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vin4csi41>;
> + };
> + csi41vin5: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vin5csi41>;
> + };
> + csi41vin6: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&vin6csi41>;
> + };
> + csi41vin7: endpoint@3 {
> + reg = <3>;
> + remote-endpoint = <&vin7csi41>;
> + };
> + };
> + };
> + };
> +
> du: display@feb00000 {
> compatible = "renesas,du-r8a77980",
> "renesas,du-r8a77970";
>
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
2018-08-09 13:08 ` Simon Horman
(?)
@ 2018-08-10 15:53 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-10 15:53 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On 08/09/2018 04:08 PM, Simon Horman wrote:
>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
>> Simon Horman's 'renesas.git' repo.
>>
>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>>
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
>> 1 file changed, 374 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -769,6 +1065,84 @@
>> resets = <&cpg 603>;
>> };
>>
>> + csi40: csi2@feaa0000 {
>> + compatible = "renesas,r8a77980-csi2";
>> + reg = <0 0xfeaa0000 0 0x10000>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 716>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 716>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + reg = <1>;
>> +
>> + csi40vin0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&vin0csi40>;
>> + };
>> + csi40vin1: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&vin1csi40>;
>> + };
>> + csi40vin2: endpoint@2 {
>> + reg = <2>;
>> + remote-endpoint = <&vin2csi40>;
>> + };
>> + csi40vin3: endpoint@3 {
>> + reg = <3>;
>> + remote-endpoint = <&vin3csi40>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + csi41: csi2@feab0000 {
>> + compatible = "renesas,r8a77980-csi2";
>> + reg = <0 0xfeab0000 0 0x10000>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>
> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> Is this intentional?
No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>> + clocks = <&cpg CPG_MOD 716>;
>
> Should this clock be 715 rather than 716?
Yes, sure.
I'm seeing this patch merged despite your remarks. Please either fix it up or
pull it out!
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-10 15:53 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-10 15:53 UTC (permalink / raw)
To: linux-arm-kernel
On 08/09/2018 04:08 PM, Simon Horman wrote:
>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
>> Simon Horman's 'renesas.git' repo.
>>
>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>>
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
>> 1 file changed, 374 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -769,6 +1065,84 @@
>> resets = <&cpg 603>;
>> };
>>
>> + csi40: csi2 at feaa0000 {
>> + compatible = "renesas,r8a77980-csi2";
>> + reg = <0 0xfeaa0000 0 0x10000>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 716>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 716>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port at 1 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + reg = <1>;
>> +
>> + csi40vin0: endpoint at 0 {
>> + reg = <0>;
>> + remote-endpoint = <&vin0csi40>;
>> + };
>> + csi40vin1: endpoint at 1 {
>> + reg = <1>;
>> + remote-endpoint = <&vin1csi40>;
>> + };
>> + csi40vin2: endpoint at 2 {
>> + reg = <2>;
>> + remote-endpoint = <&vin2csi40>;
>> + };
>> + csi40vin3: endpoint at 3 {
>> + reg = <3>;
>> + remote-endpoint = <&vin3csi40>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + csi41: csi2 at feab0000 {
>> + compatible = "renesas,r8a77980-csi2";
>> + reg = <0 0xfeab0000 0 0x10000>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>
> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> Is this intentional?
No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>> + clocks = <&cpg CPG_MOD 716>;
>
> Should this clock be 715 rather than 716?
Yes, sure.
I'm seeing this patch merged despite your remarks. Please either fix it up or
pull it out!
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-10 15:53 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-10 15:53 UTC (permalink / raw)
To: Simon Horman
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On 08/09/2018 04:08 PM, Simon Horman wrote:
>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
>> device tree.
>>
>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>
>> ---
>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
>> Simon Horman's 'renesas.git' repo.
>>
>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>>
>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
>> 1 file changed, 374 insertions(+)
>>
>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> ===================================================================
>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>> @@ -769,6 +1065,84 @@
>> resets = <&cpg 603>;
>> };
>>
>> + csi40: csi2@feaa0000 {
>> + compatible = "renesas,r8a77980-csi2";
>> + reg = <0 0xfeaa0000 0 0x10000>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>> + clocks = <&cpg CPG_MOD 716>;
>> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
>> + resets = <&cpg 716>;
>> + status = "disabled";
>> +
>> + ports {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + port@1 {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + reg = <1>;
>> +
>> + csi40vin0: endpoint@0 {
>> + reg = <0>;
>> + remote-endpoint = <&vin0csi40>;
>> + };
>> + csi40vin1: endpoint@1 {
>> + reg = <1>;
>> + remote-endpoint = <&vin1csi40>;
>> + };
>> + csi40vin2: endpoint@2 {
>> + reg = <2>;
>> + remote-endpoint = <&vin2csi40>;
>> + };
>> + csi40vin3: endpoint@3 {
>> + reg = <3>;
>> + remote-endpoint = <&vin3csi40>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + csi41: csi2@feab0000 {
>> + compatible = "renesas,r8a77980-csi2";
>> + reg = <0 0xfeab0000 0 0x10000>;
>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>
> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> Is this intentional?
No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>> + clocks = <&cpg CPG_MOD 716>;
>
> Should this clock be 715 rather than 716?
Yes, sure.
I'm seeing this patch merged despite your remarks. Please either fix it up or
pull it out!
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
2018-08-10 15:53 ` Sergei Shtylyov
(?)
@ 2018-08-17 8:51 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-17 8:51 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Fri, Aug 10, 2018 at 06:53:38PM +0300, Sergei Shtylyov wrote:
> On 08/09/2018 04:08 PM, Simon Horman wrote:
>
> >> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >> device tree.
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> >> Simon Horman's 'renesas.git' repo.
> >>
> >> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
> >>
> >> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> >> 1 file changed, 374 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> >> @@ -769,6 +1065,84 @@
> >> resets = <&cpg 603>;
> >> };
> >>
> >> + csi40: csi2@feaa0000 {
> >> + compatible = "renesas,r8a77980-csi2";
> >> + reg = <0 0xfeaa0000 0 0x10000>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 716>;
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 716>;
> >> + status = "disabled";
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@1 {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + reg = <1>;
> >> +
> >> + csi40vin0: endpoint@0 {
> >> + reg = <0>;
> >> + remote-endpoint = <&vin0csi40>;
> >> + };
> >> + csi40vin1: endpoint@1 {
> >> + reg = <1>;
> >> + remote-endpoint = <&vin1csi40>;
> >> + };
> >> + csi40vin2: endpoint@2 {
> >> + reg = <2>;
> >> + remote-endpoint = <&vin2csi40>;
> >> + };
> >> + csi40vin3: endpoint@3 {
> >> + reg = <3>;
> >> + remote-endpoint = <&vin3csi40>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + csi41: csi2@feab0000 {
> >> + compatible = "renesas,r8a77980-csi2";
> >> + reg = <0 0xfeab0000 0 0x10000>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >
> > The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> > Is this intentional?
>
> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>
> >> + clocks = <&cpg CPG_MOD 716>;
> >
> > Should this clock be 715 rather than 716?
>
> Yes, sure.
>
> I'm seeing this patch merged despite your remarks. Please either fix it up or
> pull it out!
Oops, that was not intended.
I have fixed up the patch as you suggested.
The result is as follows:
>From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 6 Aug 2018 22:55:00 +0300
Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..71636fd1a819 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
--
2.11.0
^ permalink raw reply related [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-17 8:51 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-17 8:51 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 10, 2018 at 06:53:38PM +0300, Sergei Shtylyov wrote:
> On 08/09/2018 04:08 PM, Simon Horman wrote:
>
> >> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >> device tree.
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> >> Simon Horman's 'renesas.git' repo.
> >>
> >> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
> >>
> >> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> >> 1 file changed, 374 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> >> @@ -769,6 +1065,84 @@
> >> resets = <&cpg 603>;
> >> };
> >>
> >> + csi40: csi2 at feaa0000 {
> >> + compatible = "renesas,r8a77980-csi2";
> >> + reg = <0 0xfeaa0000 0 0x10000>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 716>;
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 716>;
> >> + status = "disabled";
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port at 1 {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + reg = <1>;
> >> +
> >> + csi40vin0: endpoint at 0 {
> >> + reg = <0>;
> >> + remote-endpoint = <&vin0csi40>;
> >> + };
> >> + csi40vin1: endpoint at 1 {
> >> + reg = <1>;
> >> + remote-endpoint = <&vin1csi40>;
> >> + };
> >> + csi40vin2: endpoint at 2 {
> >> + reg = <2>;
> >> + remote-endpoint = <&vin2csi40>;
> >> + };
> >> + csi40vin3: endpoint at 3 {
> >> + reg = <3>;
> >> + remote-endpoint = <&vin3csi40>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + csi41: csi2 at feab0000 {
> >> + compatible = "renesas,r8a77980-csi2";
> >> + reg = <0 0xfeab0000 0 0x10000>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >
> > The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> > Is this intentional?
>
> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>
> >> + clocks = <&cpg CPG_MOD 716>;
> >
> > Should this clock be 715 rather than 716?
>
> Yes, sure.
>
> I'm seeing this patch merged despite your remarks. Please either fix it up or
> pull it out!
Oops, that was not intended.
I have fixed up the patch as you suggested.
The result is as follows:
>From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 6 Aug 2018 22:55:00 +0300
Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..71636fd1a819 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video at e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video at e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video at e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video at e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video at e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video at e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video at e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video at e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video at e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video at e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video at e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller at e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2 at feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display at feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
--
2.11.0
^ permalink raw reply related [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-17 8:51 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-17 8:51 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On Fri, Aug 10, 2018 at 06:53:38PM +0300, Sergei Shtylyov wrote:
> On 08/09/2018 04:08 PM, Simon Horman wrote:
>
> >> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >> device tree.
> >>
> >> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>
> >> ---
> >> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> >> Simon Horman's 'renesas.git' repo.
> >>
> >> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
> >>
> >> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> >> 1 file changed, 374 insertions(+)
> >>
> >> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> ===================================================================
> >> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> >> @@ -769,6 +1065,84 @@
> >> resets = <&cpg 603>;
> >> };
> >>
> >> + csi40: csi2@feaa0000 {
> >> + compatible = "renesas,r8a77980-csi2";
> >> + reg = <0 0xfeaa0000 0 0x10000>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >> + clocks = <&cpg CPG_MOD 716>;
> >> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> >> + resets = <&cpg 716>;
> >> + status = "disabled";
> >> +
> >> + ports {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + port@1 {
> >> + #address-cells = <1>;
> >> + #size-cells = <0>;
> >> +
> >> + reg = <1>;
> >> +
> >> + csi40vin0: endpoint@0 {
> >> + reg = <0>;
> >> + remote-endpoint = <&vin0csi40>;
> >> + };
> >> + csi40vin1: endpoint@1 {
> >> + reg = <1>;
> >> + remote-endpoint = <&vin1csi40>;
> >> + };
> >> + csi40vin2: endpoint@2 {
> >> + reg = <2>;
> >> + remote-endpoint = <&vin2csi40>;
> >> + };
> >> + csi40vin3: endpoint@3 {
> >> + reg = <3>;
> >> + remote-endpoint = <&vin3csi40>;
> >> + };
> >> + };
> >> + };
> >> + };
> >> +
> >> + csi41: csi2@feab0000 {
> >> + compatible = "renesas,r8a77980-csi2";
> >> + reg = <0 0xfeab0000 0 0x10000>;
> >> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >
> > The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> > Is this intentional?
>
> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>
> >> + clocks = <&cpg CPG_MOD 716>;
> >
> > Should this clock be 715 rather than 716?
>
> Yes, sure.
>
> I'm seeing this patch merged despite your remarks. Please either fix it up or
> pull it out!
Oops, that was not intended.
I have fixed up the patch as you suggested.
The result is as follows:
>From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 6 Aug 2018 22:55:00 +0300
Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..71636fd1a819 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
--
2.11.0
^ permalink raw reply related [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
2018-08-17 8:51 ` Simon Horman
(?)
@ 2018-08-17 11:13 ` Sergei Shtylyov
-1 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-17 11:13 UTC (permalink / raw)
To: Simon Horman
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On 08/17/2018 11:51 AM, Simon Horman wrote:
>>>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
>>>> device tree.
>>>>
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>
>>>> ---
>>>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
>>>> Simon Horman's 'renesas.git' repo.
>>>>
>>>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>>>>
>>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
>>>> 1 file changed, 374 insertions(+)
>>>>
>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>>>> ===================================================================
>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>>>> + csi41: csi2@feab0000 {
>>>> + compatible = "renesas,r8a77980-csi2";
>>>> + reg = <0 0xfeab0000 0 0x10000>;
>>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
>>> Is this intentional?
>>
>> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>>
>>>> + clocks = <&cpg CPG_MOD 716>;
>>>
>>> Should this clock be 715 rather than 716?
>>
>> Yes, sure.
>>
>> I'm seeing this patch merged despite your remarks. Please either fix it up or
>> pull it out!
>
> Oops, that was not intended.
>
> I have fixed up the patch as you suggested.
> The result is as follows:
Still buggy... :-)
> From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Date: Mon, 6 Aug 2018 22:55:00 +0300
> Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
>
> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> 1 file changed, 374 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> index 4bc99d6763ce..71636fd1a819 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
> @@ -769,6 +1065,84 @@
> resets = <&cpg 603>;
> };
>
> + csi40: csi2@feaa0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeaa0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 716>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi40vin0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vin0csi40>;
> + };
> + csi40vin1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vin1csi40>;
> + };
> + csi40vin2: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&vin2csi40>;
> + };
> + csi40vin3: endpoint@3 {
> + reg = <3>;
> + remote-endpoint = <&vin3csi40>;
> + };
> + };
> + };
> + };
> +
> + csi41: csi2@feab0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeab0000 0 0x10000>;
> + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 715>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
You forgot to fix up this prop...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-17 11:13 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-17 11:13 UTC (permalink / raw)
To: linux-arm-kernel
On 08/17/2018 11:51 AM, Simon Horman wrote:
>>>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
>>>> device tree.
>>>>
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>
>>>> ---
>>>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
>>>> Simon Horman's 'renesas.git' repo.
>>>>
>>>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>>>>
>>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
>>>> 1 file changed, 374 insertions(+)
>>>>
>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>>>> ===================================================================
>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>>>> + csi41: csi2 at feab0000 {
>>>> + compatible = "renesas,r8a77980-csi2";
>>>> + reg = <0 0xfeab0000 0 0x10000>;
>>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
>>> Is this intentional?
>>
>> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>>
>>>> + clocks = <&cpg CPG_MOD 716>;
>>>
>>> Should this clock be 715 rather than 716?
>>
>> Yes, sure.
>>
>> I'm seeing this patch merged despite your remarks. Please either fix it up or
>> pull it out!
>
> Oops, that was not intended.
>
> I have fixed up the patch as you suggested.
> The result is as follows:
Still buggy... :-)
> From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Date: Mon, 6 Aug 2018 22:55:00 +0300
> Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
>
> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> 1 file changed, 374 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> index 4bc99d6763ce..71636fd1a819 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
> @@ -769,6 +1065,84 @@
> resets = <&cpg 603>;
> };
>
> + csi40: csi2 at feaa0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeaa0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 716>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port at 1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi40vin0: endpoint at 0 {
> + reg = <0>;
> + remote-endpoint = <&vin0csi40>;
> + };
> + csi40vin1: endpoint at 1 {
> + reg = <1>;
> + remote-endpoint = <&vin1csi40>;
> + };
> + csi40vin2: endpoint at 2 {
> + reg = <2>;
> + remote-endpoint = <&vin2csi40>;
> + };
> + csi40vin3: endpoint at 3 {
> + reg = <3>;
> + remote-endpoint = <&vin3csi40>;
> + };
> + };
> + };
> + };
> +
> + csi41: csi2 at feab0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeab0000 0 0x10000>;
> + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 715>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
You forgot to fix up this prop...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-17 11:13 ` Sergei Shtylyov
0 siblings, 0 replies; 103+ messages in thread
From: Sergei Shtylyov @ 2018-08-17 11:13 UTC (permalink / raw)
To: Simon Horman
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On 08/17/2018 11:51 AM, Simon Horman wrote:
>>>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
>>>> device tree.
>>>>
>>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>>>>
>>>> ---
>>>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
>>>> Simon Horman's 'renesas.git' repo.
>>>>
>>>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
>>>>
>>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
>>>> 1 file changed, 374 insertions(+)
>>>>
>>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>>>> ===================================================================
>>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
>>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
>>>> + csi41: csi2@feab0000 {
>>>> + compatible = "renesas,r8a77980-csi2";
>>>> + reg = <0 0xfeab0000 0 0x10000>;
>>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
>>>
>>> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
>>> Is this intentional?
>>
>> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
>>
>>>> + clocks = <&cpg CPG_MOD 716>;
>>>
>>> Should this clock be 715 rather than 716?
>>
>> Yes, sure.
>>
>> I'm seeing this patch merged despite your remarks. Please either fix it up or
>> pull it out!
>
> Oops, that was not intended.
>
> I have fixed up the patch as you suggested.
> The result is as follows:
Still buggy... :-)
> From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
> From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Date: Mon, 6 Aug 2018 22:55:00 +0300
> Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
>
> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> device tree.
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> ---
> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> 1 file changed, 374 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> index 4bc99d6763ce..71636fd1a819 100644
> --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
[...]
> @@ -769,6 +1065,84 @@
> resets = <&cpg 603>;
> };
>
> + csi40: csi2@feaa0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeaa0000 0 0x10000>;
> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 716>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
> + status = "disabled";
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + reg = <1>;
> +
> + csi40vin0: endpoint@0 {
> + reg = <0>;
> + remote-endpoint = <&vin0csi40>;
> + };
> + csi40vin1: endpoint@1 {
> + reg = <1>;
> + remote-endpoint = <&vin1csi40>;
> + };
> + csi40vin2: endpoint@2 {
> + reg = <2>;
> + remote-endpoint = <&vin2csi40>;
> + };
> + csi40vin3: endpoint@3 {
> + reg = <3>;
> + remote-endpoint = <&vin3csi40>;
> + };
> + };
> + };
> + };
> +
> + csi41: csi2@feab0000 {
> + compatible = "renesas,r8a77980-csi2";
> + reg = <0 0xfeab0000 0 0x10000>;
> + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cpg CPG_MOD 715>;
> + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> + resets = <&cpg 716>;
You forgot to fix up this prop...
[...]
MBR, Sergei
^ permalink raw reply [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
2018-08-17 11:13 ` Sergei Shtylyov
(?)
@ 2018-08-22 10:00 ` Simon Horman
-1 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-22 10:00 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: Mark Rutland, devicetree, Catalin Marinas, Magnus Damm,
Will Deacon, linux-renesas-soc, Rob Herring, linux-arm-kernel
On Fri, Aug 17, 2018 at 02:13:55PM +0300, Sergei Shtylyov wrote:
> On 08/17/2018 11:51 AM, Simon Horman wrote:
>
> >>>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >>>> device tree.
> >>>>
> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>>>
> >>>> ---
> >>>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> >>>> Simon Horman's 'renesas.git' repo.
> >>>>
> >>>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
> >>>>
> >>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> >>>> 1 file changed, 374 insertions(+)
> >>>>
> >>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >>>> ===================================================================
> >>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> >>>> + csi41: csi2@feab0000 {
> >>>> + compatible = "renesas,r8a77980-csi2";
> >>>> + reg = <0 0xfeab0000 0 0x10000>;
> >>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >>>
> >>> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> >>> Is this intentional?
> >>
> >> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
> >>
> >>>> + clocks = <&cpg CPG_MOD 716>;
> >>>
> >>> Should this clock be 715 rather than 716?
> >>
> >> Yes, sure.
> >>
> >> I'm seeing this patch merged despite your remarks. Please either fix it up or
> >> pull it out!
> >
> > Oops, that was not intended.
> >
> > I have fixed up the patch as you suggested.
> > The result is as follows:
>
> Still buggy... :-)
>
> > From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
> > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Date: Mon, 6 Aug 2018 22:55:00 +0300
> > Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
> >
> > Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> > device tree.
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> > 1 file changed, 374 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > index 4bc99d6763ce..71636fd1a819 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> > @@ -769,6 +1065,84 @@
> > resets = <&cpg 603>;
> > };
> >
> > + csi40: csi2@feaa0000 {
> > + compatible = "renesas,r8a77980-csi2";
> > + reg = <0 0xfeaa0000 0 0x10000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 716>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 716>;
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg = <1>;
> > +
> > + csi40vin0: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&vin0csi40>;
> > + };
> > + csi40vin1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&vin1csi40>;
> > + };
> > + csi40vin2: endpoint@2 {
> > + reg = <2>;
> > + remote-endpoint = <&vin2csi40>;
> > + };
> > + csi40vin3: endpoint@3 {
> > + reg = <3>;
> > + remote-endpoint = <&vin3csi40>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + csi41: csi2@feab0000 {
> > + compatible = "renesas,r8a77980-csi2";
> > + reg = <0 0xfeab0000 0 0x10000>;
> > + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 715>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 716>;
>
> You forgot to fix up this prop...
Thanks, I now have the following in my tree:
From f3e8d4c1e3c3a826310a220d7373ac7c076e7120 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 6 Aug 2018 22:55:00 +0300
Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..c099053cf5fe 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
--
2.11.0
ATCH] Ñ\x06
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^ permalink raw reply related [flat|nested] 103+ messages in thread* [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-22 10:00 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-22 10:00 UTC (permalink / raw)
To: linux-arm-kernel
On Fri, Aug 17, 2018 at 02:13:55PM +0300, Sergei Shtylyov wrote:
> On 08/17/2018 11:51 AM, Simon Horman wrote:
>
> >>>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >>>> device tree.
> >>>>
> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>>>
> >>>> ---
> >>>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> >>>> Simon Horman's 'renesas.git' repo.
> >>>>
> >>>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
> >>>>
> >>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> >>>> 1 file changed, 374 insertions(+)
> >>>>
> >>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >>>> ===================================================================
> >>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> >>>> + csi41: csi2 at feab0000 {
> >>>> + compatible = "renesas,r8a77980-csi2";
> >>>> + reg = <0 0xfeab0000 0 0x10000>;
> >>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >>>
> >>> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> >>> Is this intentional?
> >>
> >> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
> >>
> >>>> + clocks = <&cpg CPG_MOD 716>;
> >>>
> >>> Should this clock be 715 rather than 716?
> >>
> >> Yes, sure.
> >>
> >> I'm seeing this patch merged despite your remarks. Please either fix it up or
> >> pull it out!
> >
> > Oops, that was not intended.
> >
> > I have fixed up the patch as you suggested.
> > The result is as follows:
>
> Still buggy... :-)
>
> > From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
> > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Date: Mon, 6 Aug 2018 22:55:00 +0300
> > Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
> >
> > Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> > device tree.
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> > 1 file changed, 374 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > index 4bc99d6763ce..71636fd1a819 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> > @@ -769,6 +1065,84 @@
> > resets = <&cpg 603>;
> > };
> >
> > + csi40: csi2 at feaa0000 {
> > + compatible = "renesas,r8a77980-csi2";
> > + reg = <0 0xfeaa0000 0 0x10000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 716>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 716>;
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port at 1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg = <1>;
> > +
> > + csi40vin0: endpoint at 0 {
> > + reg = <0>;
> > + remote-endpoint = <&vin0csi40>;
> > + };
> > + csi40vin1: endpoint at 1 {
> > + reg = <1>;
> > + remote-endpoint = <&vin1csi40>;
> > + };
> > + csi40vin2: endpoint at 2 {
> > + reg = <2>;
> > + remote-endpoint = <&vin2csi40>;
> > + };
> > + csi40vin3: endpoint at 3 {
> > + reg = <3>;
> > + remote-endpoint = <&vin3csi40>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + csi41: csi2 at feab0000 {
> > + compatible = "renesas,r8a77980-csi2";
> > + reg = <0 0xfeab0000 0 0x10000>;
> > + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 715>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 716>;
>
> You forgot to fix up this prop...
Thanks, I now have the following in my tree:
>From f3e8d4c1e3c3a826310a220d7373ac7c076e7120 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 6 Aug 2018 22:55:00 +0300
Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..c099053cf5fe 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video at e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video at e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video at e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video at e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video at e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video at e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video at e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video at e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video at e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video at e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video at e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video at e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video at e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video at e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video at e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video at e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller at e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2 at feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2 at feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port at 1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint at 0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint at 1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint at 2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint at 3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display at feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
--
2.11.0
ATCH] ?\x06
^ permalink raw reply related [flat|nested] 103+ messages in thread* Re: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
@ 2018-08-22 10:00 ` Simon Horman
0 siblings, 0 replies; 103+ messages in thread
From: Simon Horman @ 2018-08-22 10:00 UTC (permalink / raw)
To: Sergei Shtylyov
Cc: linux-renesas-soc, Rob Herring, devicetree, Mark Rutland,
Magnus Damm, linux-arm-kernel, Catalin Marinas, Will Deacon
On Fri, Aug 17, 2018 at 02:13:55PM +0300, Sergei Shtylyov wrote:
> On 08/17/2018 11:51 AM, Simon Horman wrote:
>
> >>>> Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> >>>> device tree.
> >>>>
> >>>> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> >>>>
> >>>> ---
> >>>> This patch is against the 'renesas-devel-20180802v2-v4.18-rc7' branch of
> >>>> Simon Horman's 'renesas.git' repo.
> >>>>
> >>>> The R8A77980 CSI2/VIN DT binding updates have been posted earlier today...
> >>>>
> >>>> arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> >>>> 1 file changed, 374 insertions(+)
> >>>>
> >>>> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >>>> ===================================================================
> >>>> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> >>>> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> >>>> + csi41: csi2@feab0000 {
> >>>> + compatible = "renesas,r8a77980-csi2";
> >>>> + reg = <0 0xfeab0000 0 0x10000>;
> >>>> + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> >>>
> >>> The use of GIC_SPI 246 for both csi40 and csi41 seems suspicious.
> >>> Is this intentional?
> >>
> >> No, must be copy/paste artefact... Sorry about that, it should be 241 instead.
> >>
> >>>> + clocks = <&cpg CPG_MOD 716>;
> >>>
> >>> Should this clock be 715 rather than 716?
> >>
> >> Yes, sure.
> >>
> >> I'm seeing this patch merged despite your remarks. Please either fix it up or
> >> pull it out!
> >
> > Oops, that was not intended.
> >
> > I have fixed up the patch as you suggested.
> > The result is as follows:
>
> Still buggy... :-)
>
> > From c703c196b847c654b392f027d3fa995e378792ac Mon Sep 17 00:00:00 2001
> > From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Date: Mon, 6 Aug 2018 22:55:00 +0300
> > Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
> >
> > Describe the CSI2 and VIN (and their interconnections) in the R8A77980
> > device tree.
> >
> > Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
> > Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
> > ---
> > arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
> > 1 file changed, 374 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > index 4bc99d6763ce..71636fd1a819 100644
> > --- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
> [...]
> > @@ -769,6 +1065,84 @@
> > resets = <&cpg 603>;
> > };
> >
> > + csi40: csi2@feaa0000 {
> > + compatible = "renesas,r8a77980-csi2";
> > + reg = <0 0xfeaa0000 0 0x10000>;
> > + interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 716>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 716>;
> > + status = "disabled";
> > +
> > + ports {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + port@1 {
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > +
> > + reg = <1>;
> > +
> > + csi40vin0: endpoint@0 {
> > + reg = <0>;
> > + remote-endpoint = <&vin0csi40>;
> > + };
> > + csi40vin1: endpoint@1 {
> > + reg = <1>;
> > + remote-endpoint = <&vin1csi40>;
> > + };
> > + csi40vin2: endpoint@2 {
> > + reg = <2>;
> > + remote-endpoint = <&vin2csi40>;
> > + };
> > + csi40vin3: endpoint@3 {
> > + reg = <3>;
> > + remote-endpoint = <&vin3csi40>;
> > + };
> > + };
> > + };
> > + };
> > +
> > + csi41: csi2@feab0000 {
> > + compatible = "renesas,r8a77980-csi2";
> > + reg = <0 0xfeab0000 0 0x10000>;
> > + interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
> > + clocks = <&cpg CPG_MOD 715>;
> > + power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
> > + resets = <&cpg 716>;
>
> You forgot to fix up this prop...
Thanks, I now have the following in my tree:
From f3e8d4c1e3c3a826310a220d7373ac7c076e7120 Mon Sep 17 00:00:00 2001
From: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Date: Mon, 6 Aug 2018 22:55:00 +0300
Subject: [PATCH] arm64: dts: renesas: r8a77980: add CSI2/VIN support
Describe the CSI2 and VIN (and their interconnections) in the R8A77980
device tree.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
---
arch/arm64/boot/dts/renesas/r8a77980.dtsi | 374 ++++++++++++++++++++++++++++++
1 file changed, 374 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r8a77980.dtsi b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
index 4bc99d6763ce..c099053cf5fe 100644
--- a/arch/arm64/boot/dts/renesas/r8a77980.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77980.dtsi
@@ -579,6 +579,302 @@
status = "disabled";
};
+ vin0: video@e6ef0000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef0000 0 0x1000>;
+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 811>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 811>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin0csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin0>;
+ };
+ };
+ };
+ };
+
+ vin1: video@e6ef1000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef1000 0 0x1000>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 810>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ status = "disabled";
+ resets = <&cpg 810>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin1csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin1>;
+ };
+ };
+ };
+ };
+
+ vin2: video@e6ef2000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef2000 0 0x1000>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 809>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 809>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin2csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin2>;
+ };
+ };
+ };
+ };
+
+ vin3: video@e6ef3000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef3000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 808>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 808>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin3csi40: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi40vin3>;
+ };
+ };
+ };
+ };
+
+ vin4: video@e6ef4000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef4000 0 0x1000>;
+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 807>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 807>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin4csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin4>;
+ };
+ };
+ };
+ };
+
+ vin5: video@e6ef5000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef5000 0 0x1000>;
+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 806>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 806>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin5csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin5>;
+ };
+ };
+ };
+ };
+
+ vin6: video@e6ef6000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef6000 0 0x1000>;
+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 805>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 805>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin6csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin6>;
+ };
+ };
+ };
+ };
+
+ vin7: video@e6ef7000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef7000 0 0x1000>;
+ interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 804>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 804>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ vin7csi41: endpoint@2 {
+ reg = <2>;
+ remote-endpoint= <&csi41vin7>;
+ };
+ };
+ };
+ };
+
+ vin8: video@e6ef8000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef8000 0 0x1000>;
+ interrupts = <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 628>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 628>;
+ status = "disabled";
+ };
+
+ vin9: video@e6ef9000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6ef9000 0 0x1000>;
+ interrupts = <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 627>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 627>;
+ status = "disabled";
+ };
+
+ vin10: video@e6efa000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efa000 0 0x1000>;
+ interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 625>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 625>;
+ status = "disabled";
+ };
+
+ vin11: video@e6efb000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efb000 0 0x1000>;
+ interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 618>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 618>;
+ status = "disabled";
+ };
+
+ vin12: video@e6efc000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efc000 0 0x1000>;
+ interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 612>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 612>;
+ status = "disabled";
+ };
+
+ vin13: video@e6efd000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efd000 0 0x1000>;
+ interrupts = <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 608>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 608>;
+ status = "disabled";
+ };
+
+ vin14: video@e6efe000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6efe000 0 0x1000>;
+ interrupts = <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 605>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 605>;
+ status = "disabled";
+ };
+
+ vin15: video@e6eff000 {
+ compatible = "renesas,vin-r8a77980";
+ reg = <0 0xe6eff000 0 0x1000>;
+ interrupts = <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 604>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 604>;
+ status = "disabled";
+ };
+
dmac1: dma-controller@e7300000 {
compatible = "renesas,dmac-r8a77980",
"renesas,rcar-dmac";
@@ -769,6 +1065,84 @@
resets = <&cpg 603>;
};
+ csi40: csi2@feaa0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeaa0000 0 0x10000>;
+ interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 716>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 716>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi40vin0: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin0csi40>;
+ };
+ csi40vin1: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin1csi40>;
+ };
+ csi40vin2: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin2csi40>;
+ };
+ csi40vin3: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin3csi40>;
+ };
+ };
+ };
+ };
+
+ csi41: csi2@feab0000 {
+ compatible = "renesas,r8a77980-csi2";
+ reg = <0 0xfeab0000 0 0x10000>;
+ interrupts = <GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD 715>;
+ power-domains = <&sysc R8A77980_PD_ALWAYS_ON>;
+ resets = <&cpg 715>;
+ status = "disabled";
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ reg = <1>;
+
+ csi41vin4: endpoint@0 {
+ reg = <0>;
+ remote-endpoint = <&vin4csi41>;
+ };
+ csi41vin5: endpoint@1 {
+ reg = <1>;
+ remote-endpoint = <&vin5csi41>;
+ };
+ csi41vin6: endpoint@2 {
+ reg = <2>;
+ remote-endpoint = <&vin6csi41>;
+ };
+ csi41vin7: endpoint@3 {
+ reg = <3>;
+ remote-endpoint = <&vin7csi41>;
+ };
+ };
+ };
+ };
+
du: display@feb00000 {
compatible = "renesas,du-r8a77980",
"renesas,du-r8a77970";
--
2.11.0
ATCH] Ñ\x06
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