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From: Huacai Chen <chenhc@lemote.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Cc: linux-mips@vger.kernel.org, Fuxin Zhang <zhangfx@lemote.com>,
	Zhangjin Wu <wuzhangjin@gmail.com>,
	Huacai Chen <chenhuacai@gmail.com>,
	Jiaxun Yang <jiaxun.yang@flygoat.com>, chenj <chenj@lemote.com>
Subject: [PATCH 1/2] MIPS: Loongson-3: Enable COP2 usage in kernel
Date: Wed, 29 Apr 2020 17:38:40 +0800	[thread overview]
Message-ID: <1588153121-28507-1-git-send-email-chenhc@lemote.com> (raw)

From: chenj <chenj@lemote.com>

Loongson-3's COP2 is Multi-Media coprocessor, it is disabled in kernel
mode by default. However, gslq/gssq (16-bytes load/store instructions)
overrides the instruction format of lwc2/swc2. If we wan't to use gslq/
gssq for optimization in kernel, we should enable COP2 usage in kernel.
---
 arch/mips/boot/compressed/head.S   |  7 +++++++
 arch/mips/include/asm/mipsregs.h   |  1 +
 arch/mips/include/asm/stackframe.h | 12 ++++++++++++
 arch/mips/kernel/head.S            | 16 ++++++++++++++++
 arch/mips/kernel/r4k_switch.S      |  3 +++
 arch/mips/kernel/traps.c           |  3 +++
 6 files changed, 42 insertions(+)

diff --git a/arch/mips/boot/compressed/head.S b/arch/mips/boot/compressed/head.S
index 409cb48..855ca8c 100644
--- a/arch/mips/boot/compressed/head.S
+++ b/arch/mips/boot/compressed/head.S
@@ -14,11 +14,18 @@
 
 #include <asm/asm.h>
 #include <asm/regdef.h>
+#include <asm/mipsregs.h>
 
 	.set noreorder
 	.cprestore
 	LEAF(start)
 start:
+#ifdef CONFIG_CPU_LOONGSON64
+	mfc0    t0, CP0_STATUS
+	or	t0, ST0_MM
+	mtc0    t0, CP0_STATUS
+#endif
+
 	/* Save boot rom start args */
 	move	s0, a0
 	move	s1, a1
diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index ce40fbf..0f71540 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -386,6 +386,7 @@
 #define ST0_CU1			0x20000000
 #define ST0_CU2			0x40000000
 #define ST0_CU3			0x80000000
+#define ST0_MM			0x40000000	/* Loongson-3 naming */
 #define ST0_XX			0x80000000	/* MIPS IV naming */
 
 /*
diff --git a/arch/mips/include/asm/stackframe.h b/arch/mips/include/asm/stackframe.h
index 4d6ad90..c204850 100644
--- a/arch/mips/include/asm/stackframe.h
+++ b/arch/mips/include/asm/stackframe.h
@@ -450,7 +450,11 @@
  */
 		.macro	CLI
 		mfc0	t0, CP0_STATUS
+#ifdef CONFIG_CPU_LOONGSON64
+		li	t1, ST0_CU0 | ST0_MM | STATMASK
+#else
 		li	t1, ST0_CU0 | STATMASK
+#endif
 		or	t0, t1
 		xori	t0, STATMASK
 		mtc0	t0, CP0_STATUS
@@ -463,7 +467,11 @@
  */
 		.macro	STI
 		mfc0	t0, CP0_STATUS
+#ifdef CONFIG_CPU_LOONGSON64
+		li	t1, ST0_CU0 | ST0_MM | STATMASK
+#else
 		li	t1, ST0_CU0 | STATMASK
+#endif
 		or	t0, t1
 		xori	t0, STATMASK & ~1
 		mtc0	t0, CP0_STATUS
@@ -477,7 +485,11 @@
  */
 		.macro	KMODE
 		mfc0	t0, CP0_STATUS
+#ifdef CONFIG_CPU_LOONGSON64
+		li	t1, ST0_CU0 | ST0_MM | (STATMASK & ~1)
+#else
 		li	t1, ST0_CU0 | (STATMASK & ~1)
+#endif
 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
 		andi	t2, t0, ST0_IEP
 		srl	t2, 2
diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
index 3b02ffe..cdac82d 100644
--- a/arch/mips/kernel/head.S
+++ b/arch/mips/kernel/head.S
@@ -45,18 +45,34 @@
 
 	.macro	setup_c0_status_pri
 #ifdef CONFIG_64BIT
+#ifdef CONFIG_CPU_LOONGSON64
+	setup_c0_status ST0_KX|ST0_MM 0
+#else
 	setup_c0_status ST0_KX 0
+#endif
+#else
+#ifdef CONFIG_CPU_LOONGSON64
+	setup_c0_status ST0_MM 0
 #else
 	setup_c0_status 0 0
 #endif
+#endif
 	.endm
 
 	.macro	setup_c0_status_sec
 #ifdef CONFIG_64BIT
+#ifdef CONFIG_CPU_LOONGSON64
+	setup_c0_status ST0_KX|ST0_MM ST0_BEV
+#else
 	setup_c0_status ST0_KX ST0_BEV
+#endif
+#else
+#ifdef CONFIG_CPU_LOONGSON64
+	setup_c0_status ST0_MM ST0_BEV
 #else
 	setup_c0_status 0 ST0_BEV
 #endif
+#endif
 	.endm
 
 #ifndef CONFIG_NO_EXCEPT_FILL
diff --git a/arch/mips/kernel/r4k_switch.S b/arch/mips/kernel/r4k_switch.S
index 58232ae..154ae7d 100644
--- a/arch/mips/kernel/r4k_switch.S
+++ b/arch/mips/kernel/r4k_switch.S
@@ -53,6 +53,9 @@
 	nor	a3, $0, a3
 	and	a2, a3
 	or	a2, t1
+#ifdef CONFIG_CPU_LOONGSON64
+	or	a2, ST0_MM
+#endif
 	mtc0	a2, CP0_STATUS
 	move	v0, a0
 	jr	ra
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 31968cb..1731436 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2114,6 +2114,9 @@ static void configure_status(void)
 #ifdef CONFIG_64BIT
 	status_set |= ST0_FR|ST0_KX|ST0_SX|ST0_UX;
 #endif
+#ifdef CONFIG_CPU_LOONGSON64
+	status_set |= ST0_MM;
+#endif
 	if (current_cpu_data.isa_level & MIPS_CPU_ISA_IV)
 		status_set |= ST0_XX;
 	if (cpu_has_dsp)
-- 
2.7.0


             reply	other threads:[~2020-04-29  9:38 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-04-29  9:38 Huacai Chen [this message]
2020-04-29  9:38 ` [PATCH 2/2] MIPS: Loongson-3: Calculate ra properly when unwinding the stack Huacai Chen
2020-04-29 18:33 ` [PATCH 1/2] MIPS: Loongson-3: Enable COP2 usage in kernel Thomas Bogendoerfer
2020-04-30  7:54   ` Huacai Chen
2020-05-01  0:44     ` Maciej W. Rozycki
2020-05-14  5:44       ` Huacai Chen

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