From: Patchwork <patchwork@emeril.freedesktop.org>
To: "D Scott Phillips" <d.scott.phillips@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
Date: Tue, 05 May 2020 00:25:18 -0000 [thread overview]
Message-ID: <158863831885.25914.14973792184619540275@emeril.freedesktop.org> (raw)
In-Reply-To: <20200505000146.2295525-1-d.scott.phillips@intel.com>
== Series Details ==
Series: drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
URL : https://patchwork.freedesktop.org/series/76925/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
f3eb1ee5e0b9 drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
-:112: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#112: FILE: drivers/gpu/drm/i915/gt/intel_lrc.c:4767:
+ cs = gen12_emit_ggtt_write_rcs(cs,
request->fence.seqno,
total: 0 errors, 0 warnings, 1 checks, 93 lines checked
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next prev parent reply other threads:[~2020-05-05 0:25 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-05 0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
2020-05-05 0:09 ` D Scott Phillips
2020-05-05 7:27 ` Lionel Landwerlin
2020-05-05 16:32 ` D Scott Phillips
2020-05-05 0:25 ` Patchwork [this message]
2020-05-05 0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success for " Patchwork
2020-05-05 0:57 ` [Intel-gfx] [PATCH] " Kenneth Graunke
2020-05-05 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork
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