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From: D Scott Phillips <d.scott.phillips@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Subject: Re: [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword
Date: Mon, 04 May 2020 17:09:13 -0700	[thread overview]
Message-ID: <874ksvtf86.fsf@intel.com> (raw)
In-Reply-To: <20200505000146.2295525-1-d.scott.phillips@intel.com>

D Scott Phillips <d.scott.phillips@intel.com> writes:

> Previously we set HDC_PIPELINE_FLUSH in dword 1 of gen12
> pipe_control commands. HDC Pipeline flush actually resides in
> dword 0, and the bit we were setting in dword 1 was Indirect State
> Pointers Disable, which invalidates indirect state in the render
> context. This causes failures for userspace, as things like push
> constant state gets invalidated.
>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: D Scott Phillips <d.scott.phillips@intel.com>

also,

Fixes: 4aa0b5d457f5 ("drm/i915/tgl: Add HDC Pipeline Flush")
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  reply	other threads:[~2020-05-05  0:11 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-05-05  0:01 [Intel-gfx] [PATCH] drm/i915/tgl: Put HDC flush pipe_control bit in the right dword D Scott Phillips
2020-05-05  0:09 ` D Scott Phillips [this message]
2020-05-05  7:27   ` Lionel Landwerlin
2020-05-05 16:32     ` D Scott Phillips
2020-05-05  0:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2020-05-05  0:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-05-05  0:57 ` [Intel-gfx] [PATCH] " Kenneth Graunke
2020-05-05 14:17 ` [Intel-gfx] ✓ Fi.CI.IGT: success for " Patchwork

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