From: John Garry <john.garry@huawei.com> To: <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>, <mark.rutland@arm.com>, <alexander.shishkin@linux.intel.com>, <jolsa@redhat.com>, <namhyung@kernel.org> Cc: <will@kernel.org>, <ak@linux.intel.com>, <linuxarm@huawei.com>, <linux-kernel@vger.kernel.org>, <qiangqing.zhang@nxp.com>, <irogers@google.com>, <robin.murphy@arm.com>, <zhangshaokun@hisilicon.com>, <linux-arm-kernel@lists.infradead.org>, John Garry <john.garry@huawei.com> Subject: [PATCH RFC v3 05/12] perf vendor events arm64: Add hip08 SMMUv3 PMCG events Date: Thu, 7 May 2020 19:57:44 +0800 [thread overview] Message-ID: <1588852671-61996-6-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1588852671-61996-1-git-send-email-john.garry@huawei.com> Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip08 platform. This contains a mix of architected and IMP def events Signed-off-by: John Garry <john.garry@huawei.com> --- .../arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json new file mode 100644 index 000000000000..f2a1cb0332a6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json @@ -0,0 +1,42 @@ +[ + { + "ArchStdEvent": "smmuv3_pmcg.CYCLES" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.TRANSACTION" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.TLB_MISS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED" + "Compat": "hip08" + }, + { + "EventCode": "0x8a", + "EventName": "smmuv3_pmcg.L1_TLB", + "BriefDescription": "SMMUv3 PMCG L1 TABLE transation", + "PublicDescription": "SMMUv3 PMCG L1 TABLE transation", + "Unit": "smmuv3_pmcg", + "Compat": "hip08" + }, +] -- 2.16.4
WARNING: multiple messages have this Message-ID (diff)
From: John Garry <john.garry@huawei.com> To: <peterz@infradead.org>, <mingo@redhat.com>, <acme@kernel.org>, <mark.rutland@arm.com>, <alexander.shishkin@linux.intel.com>, <jolsa@redhat.com>, <namhyung@kernel.org> Cc: irogers@google.com, ak@linux.intel.com, linux-kernel@vger.kernel.org, John Garry <john.garry@huawei.com>, qiangqing.zhang@nxp.com, linuxarm@huawei.com, zhangshaokun@hisilicon.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, robin.murphy@arm.com Subject: [PATCH RFC v3 05/12] perf vendor events arm64: Add hip08 SMMUv3 PMCG events Date: Thu, 7 May 2020 19:57:44 +0800 [thread overview] Message-ID: <1588852671-61996-6-git-send-email-john.garry@huawei.com> (raw) In-Reply-To: <1588852671-61996-1-git-send-email-john.garry@huawei.com> Add the SMMUv3 PMCG (Performance Monitor Event Group) events for hip08 platform. This contains a mix of architected and IMP def events Signed-off-by: John Garry <john.garry@huawei.com> --- .../arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json diff --git a/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json new file mode 100644 index 000000000000..f2a1cb0332a6 --- /dev/null +++ b/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/sys/smmu-v3-pmcg.json @@ -0,0 +1,42 @@ +[ + { + "ArchStdEvent": "smmuv3_pmcg.CYCLES" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.TRANSACTION" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.TLB_MISS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.CONFIG_CACHE_MISS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.TRANS_TABLE_WALK_ACCESS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.CONFIG_STRUCT_ACCESS" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_RQ" + "Compat": "hip08" + }, + { + "ArchStdEvent": "smmuv3_pmcg.PCIE_ATS_TRANS_PASSED" + "Compat": "hip08" + }, + { + "EventCode": "0x8a", + "EventName": "smmuv3_pmcg.L1_TLB", + "BriefDescription": "SMMUv3 PMCG L1 TABLE transation", + "PublicDescription": "SMMUv3 PMCG L1 TABLE transation", + "Unit": "smmuv3_pmcg", + "Compat": "hip08" + }, +] -- 2.16.4 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2020-05-07 12:02 UTC|newest] Thread overview: 54+ messages / expand[flat|nested] mbox.gz Atom feed top 2020-05-07 11:57 [PATCH RFC v3 00/12] perf pmu-events: Support event aliasing for system PMUs John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 01/12] perf jevents: Add support for an extra directory level John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 02/12] perf jevents: Add support for system events tables John Garry 2020-05-07 11:57 ` John Garry 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 14:52 ` John Garry 2020-05-11 14:52 ` John Garry 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 15:02 ` John Garry 2020-05-11 15:02 ` John Garry 2020-05-11 16:21 ` Ian Rogers 2020-05-11 16:21 ` Ian Rogers 2020-05-12 10:29 ` Jiri Olsa 2020-05-12 10:29 ` Jiri Olsa 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 11:01 ` Jiri Olsa 2020-05-07 11:57 ` [PATCH RFC v3 03/12] perf vendor events arm64: Relocate hip08 events John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 04/12] perf vendor events arm64: Add Architected events smmuv3-pmcg.json John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` John Garry [this message] 2020-05-07 11:57 ` [PATCH RFC v3 05/12] perf vendor events arm64: Add hip08 SMMUv3 PMCG events John Garry 2020-05-07 11:57 ` [PATCH RFC v3 06/12] perf pmu: Add pmu_id() John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 07/12] perf pmu: Add pmu_add_sys_aliases() John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 08/12] perf vendor events: Add JSON metrics for imx8mm DDR Perf John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 09/12] perf metricgroup: Split up metricgroup__add_metric() John Garry 2020-05-07 11:57 ` John Garry 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 11:01 ` Jiri Olsa 2020-05-11 11:25 ` John Garry 2020-05-11 11:25 ` John Garry 2020-05-11 11:35 ` Joakim Zhang 2020-05-11 11:35 ` Joakim Zhang 2020-05-07 11:57 ` [PATCH RFC v3 10/12] perf metricgroup: Split up metricgroup__print() John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 11/12] perf metricgroup: Support printing metric groups for system PMUs John Garry 2020-05-07 11:57 ` John Garry 2020-05-07 11:57 ` [PATCH RFC v3 12/12] perf metricgroup: Support adding metrics " John Garry 2020-05-07 11:57 ` John Garry 2020-05-08 2:55 ` [PATCH RFC v3 00/12] perf pmu-events: Support event aliasing " Joakim Zhang 2020-05-08 2:55 ` Joakim Zhang 2020-05-12 8:02 ` Joakim Zhang 2020-05-12 8:02 ` Joakim Zhang 2020-05-12 10:13 ` John Garry 2020-05-12 10:13 ` John Garry 2020-05-12 10:30 ` Joakim Zhang 2020-05-12 10:30 ` Joakim Zhang
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=1588852671-61996-6-git-send-email-john.garry@huawei.com \ --to=john.garry@huawei.com \ --cc=acme@kernel.org \ --cc=ak@linux.intel.com \ --cc=alexander.shishkin@linux.intel.com \ --cc=irogers@google.com \ --cc=jolsa@redhat.com \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=linux-kernel@vger.kernel.org \ --cc=linuxarm@huawei.com \ --cc=mark.rutland@arm.com \ --cc=mingo@redhat.com \ --cc=namhyung@kernel.org \ --cc=peterz@infradead.org \ --cc=qiangqing.zhang@nxp.com \ --cc=robin.murphy@arm.com \ --cc=will@kernel.org \ --cc=zhangshaokun@hisilicon.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.