[igt-dev] [PATCH i-g-t 0/6] Make gpgpu fill tests libdrm independent

[igt-dev] [PATCH i-g-t 0/6] Make gpgpu fill tests libdrm independent

[Zbigniew Kempczyński]

This series is likely begin of the journey to make all gpgpu code
(and then media and render copy) libdrm free. 

I've introduced intel_bb which is very simplified version of libdrm
powered intel_batchbuffer. Currently it supports simple relocation
but it is enough to cover all gpgpu fill needs. Other (fenced) 
relocation will be added when I will have to face with such pipelines /
batchbuffers.

I think there're two possibilities - iterate until functions with 
suffix "_v2" will be ready to be replaced older libdrm versions or when 
patch will be mature enough to merge and add other gens one by one
with final replacement of "_v2" to "" on the end. I'm looking forward
review comments and suggestions. 

Cc: Chris Wilson <chris@chris-wilson.co.uk>
 
Zbigniew Kempczyński (6):
  lib/intel_bufops: Add bufops reference and relaxate stride requirement
  lib/intel_batchbuffer: Introduce intel_bb
  lib/intel_batchbuffer: Introduce temporary igt_fillfunc_v2_t
  lib/gpu_cmds: Add gpgpu pipeline functions based on intel_bb
  lib/gpgpu_fill: libdrm-free gpgpu pipeline creation for gen7
  tests/gem_gpgpu_fill: Add gen7 version without libdrm dependency

 lib/gpgpu_fill.c            |  48 +++++
 lib/gpgpu_fill.h            |   8 +
 lib/gpu_cmds.c              | 340 ++++++++++++++++++++++++++++++++++++
 lib/gpu_cmds.h              |  33 ++++
 lib/intel_batchbuffer.c     | 221 +++++++++++++++++++++++
 lib/intel_batchbuffer.h     |  86 +++++++++
 lib/intel_bufops.c          |  20 ++-
 lib/intel_bufops.h          |   3 +
 tests/i915/gem_gpgpu_fill.c | 125 ++++++++++---
 9 files changed, 856 insertions(+), 28 deletions(-)

-- 
2.26.0

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[igt-dev] [PATCH i-g-t 1/6] lib/intel_bufops: Add bufops reference and relaxate stride requirement

[Zbigniew Kempczyński]

Add bufops reference to intel_buf to allow acquire drm fd against which
buffer was created.

Relax stride limitation for intel_buf for non-tiled buffers.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_bufops.c | 20 +++++++++++++++++++-
 lib/intel_bufops.h |  3 +++
 2 files changed, 22 insertions(+), 1 deletion(-)

diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
index 804b2a0a..cdf6b114 100644
--- a/lib/intel_bufops.c
+++ b/lib/intel_bufops.c
@@ -686,6 +686,8 @@ static void __intel_buf_init(struct buf_ops *bops,
 
 	memset(buf, 0, sizeof(*buf));
 
+	buf->bops = bops;
+
 	if (compression) {
 		int aux_width, aux_height;
 
@@ -721,7 +723,10 @@ static void __intel_buf_init(struct buf_ops *bops,
 		size = buf->aux.offset + aux_width * aux_height;
 
 	} else {
-		buf->stride = ALIGN(width * (bpp / 8), 128);
+		if (buf->tiling)
+			buf->stride = ALIGN(width * (bpp / 8), 128);
+		else
+			buf->stride = width * (bpp / 8);
 		buf->size = buf->stride * height;
 		buf->tiling = tiling;
 		buf->bpp = bpp;
@@ -1038,6 +1043,19 @@ void buf_ops_destroy(struct buf_ops *bops)
 	free(bops);
 }
 
+/**
+ * buf_ops_getfd
+ * @bops: pointer to buf_ops
+ *
+ * Returns: drm fd
+ */
+int buf_ops_getfd(struct buf_ops *bops)
+{
+	igt_assert(bops);
+
+	return bops->fd;
+}
+
 /**
  * buf_ops_set_software_tiling
  * @bops: pointer to buf_ops
diff --git a/lib/intel_bufops.h b/lib/intel_bufops.h
index f3d6aed8..cd7b74bd 100644
--- a/lib/intel_bufops.h
+++ b/lib/intel_bufops.h
@@ -2,10 +2,12 @@
 #define __INTEL_BUFOPS_H__
 
 #include <stdint.h>
+#include "igt_aux.h"
 
 struct buf_ops;
 
 struct intel_buf {
+	struct buf_ops *bops;
 	uint32_t handle;
 	uint32_t stride;
 	uint32_t tiling;
@@ -58,6 +60,7 @@ intel_buf_aux_height(int gen, const struct intel_buf *buf)
 
 struct buf_ops *buf_ops_create(int fd);
 void buf_ops_destroy(struct buf_ops *bops);
+int buf_ops_getfd(struct buf_ops *bops);
 
 bool buf_ops_set_software_tiling(struct buf_ops *bops,
 				 uint32_t tiling,
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 2/6] lib/intel_batchbuffer: Introduce intel_bb

[Zbigniew Kempczyński]

Simple batchbuffer facility which gathers and outputs relocations.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 202 ++++++++++++++++++++++++++++++++++++++++
 lib/intel_batchbuffer.h |  78 ++++++++++++++++
 2 files changed, 280 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index f1a45b47..c7f52f01 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -41,6 +41,7 @@
 #include "rendercopy.h"
 #include "media_fill.h"
 #include "ioctl_wrappers.h"
+#include "i915/gem_mman.h"
 #include "media_spin.h"
 #include "gpgpu_fill.h"
 #include "igt_aux.h"
@@ -1171,3 +1172,204 @@ igt_media_spinfunc_t igt_get_media_spinfunc(int devid)
 
 	return spin;
 }
+
+/* Intel batchbuffer v2 */
+struct intel_bb *intel_bb_create(int i915, uint32_t size)
+{
+	struct intel_bb *ibb = calloc(1, sizeof(*ibb));
+
+	igt_assert(ibb);
+
+	ibb->i915 = i915;
+	ibb->devid = intel_get_drm_devid(i915);
+	ibb->gen = intel_gen(ibb->devid);
+	ibb->handle = gem_create(i915, size);
+	ibb->size = size;
+	ibb->batch = gem_mmap__cpu_coherent(i915, ibb->handle, 0, size,
+					    PROT_READ | PROT_WRITE);
+	memset(ibb->batch, 0, size);
+	ibb->ptr = ibb->batch;
+	ibb->objects = NULL;
+
+	return ibb;
+}
+
+void intel_bb_destroy(struct intel_bb *ibb)
+{
+	uint32_t i;
+
+	igt_assert(ibb);
+
+	/* Free relocations */
+	for (i = 0; i < ibb->num_objects; i++) {
+		if ((void *) ibb->objects->relocs_ptr)
+			free((void *) ibb->objects->relocs_ptr);
+	}
+
+	free(ibb->objects);
+
+	munmap(ibb->batch, ibb->size);
+	gem_close(ibb->i915, ibb->handle);
+
+	free(ibb);
+}
+
+void intel_bb_set_debug(struct intel_bb *ibb, bool debug)
+{
+	ibb->debug = debug;
+}
+
+static void intel_bb_add_handle(struct intel_bb *ibb, uint32_t handle)
+{
+	uint32_t i;
+
+	igt_assert(ibb);
+
+	/* Skip bb as object, it will be added before exec */
+	if (ibb->handle == handle)
+		return;
+
+	for (i = 0; i < ibb->num_objects; i++)
+		if (ibb->objects[i].handle == handle)
+			return;
+
+	i = ibb->num_objects;
+	ibb->objects = realloc(ibb->objects,
+			       sizeof(*ibb->objects) * (i + 1));
+	igt_assert(ibb->objects);
+
+	memset(&ibb->objects[i], 0, sizeof(*ibb->objects));
+	ibb->objects[i].handle = handle;
+
+	ibb->num_objects++;
+}
+
+static void intel_bb_emit_reloc(struct intel_bb *ibb,
+				uint32_t handle,
+				uint32_t read_domains,
+				uint32_t write_domain,
+				uint64_t delta,
+				uint64_t offset,
+				bool use_offset,
+				bool out)
+
+{
+	struct drm_i915_gem_relocation_entry *relocs;
+	uint32_t i;
+
+	intel_bb_add_handle(ibb, handle);
+
+	relocs = ibb->relocs;
+	if (ibb->num_relocs == ibb->allocated_relocs) {
+		ibb->allocated_relocs += 4096 / sizeof(*relocs);
+		relocs = realloc(relocs, sizeof(*relocs) * ibb->allocated_relocs);
+		igt_assert(relocs);
+		ibb->relocs = relocs;
+	}
+
+	i = ibb->num_relocs++;
+	memset(&relocs[i], 0, sizeof(*relocs));
+	relocs[i].target_handle = handle;
+	relocs[i].read_domains = read_domains;
+	relocs[i].write_domain = write_domain;
+	relocs[i].delta = delta;
+	if (use_offset)
+		relocs[i].offset = offset;
+	else
+		relocs[i].offset = intel_bb_offset(ibb);
+
+	if (out) {
+		intel_bb_out(ibb, delta);
+		if (ibb->gen >= 8)
+			intel_bb_out(ibb, delta >> 32);
+	}
+}
+
+void intel_bb_out_reloc(struct intel_bb *ibb,
+			uint32_t read_domains,
+			uint32_t write_domain,
+			uint64_t delta)
+
+{
+	igt_assert(ibb);
+
+	intel_bb_emit_reloc(ibb, ibb->handle, read_domains, write_domain,
+			    delta, intel_bb_offset(ibb),
+			    false, true);
+}
+
+void intel_bb_offset_reloc(struct intel_bb *ibb, uint32_t handle,
+			   uint32_t offset,
+			   uint32_t read_domains,
+			   uint32_t write_domain)
+{
+	igt_assert(ibb);
+
+	intel_bb_emit_reloc(ibb, handle, read_domains, write_domain,
+			    0, offset, true, false);
+}
+
+static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
+{
+	struct drm_i915_gem_exec_object2 *objects;
+	struct drm_i915_gem_relocation_entry *relocs, *reloc;
+	int i, j;
+
+	igt_info("execbuf batch len: %u, start offset: 0x%x, "
+		 "DR1: 0x%x, DR4: 0x%x, "
+		 "num clip: %u, clipptr: 0x%llx, "
+		 "flags: 0x%llx, rsvd1: 0x%llx, rsvd2: 0x%llx\n",
+		 execbuf->batch_len, execbuf->batch_start_offset,
+		 execbuf->DR1, execbuf->DR4,
+		 execbuf->num_cliprects, execbuf->cliprects_ptr,
+		 execbuf->flags, execbuf->rsvd1, execbuf->rsvd2);
+
+	igt_info("execbuf buffer_count: %d\n", execbuf->buffer_count);
+	for (i = 0; i < execbuf->buffer_count; i++) {
+		objects = &((struct drm_i915_gem_exec_object2 *) execbuf->buffers_ptr)[i];
+		relocs = (struct drm_i915_gem_relocation_entry *) objects->relocs_ptr;
+		igt_info(" [%d] <handle: %u, reloc_count: %d, reloc_ptr: %p, "
+			 "align: %llx, offset: %llx, flags: %llx, rsvd1: %llx, rsvd2: %llx\n",
+			 i, objects->handle, objects->relocation_count,
+			 (void *) objects->relocs_ptr, objects->alignment, objects->offset,
+			 objects->flags, objects->rsvd1, objects->rsvd2);
+		if (objects->relocation_count) {
+			igt_info("execbuf relocs:\n");
+			for (j = 0; j < objects->relocation_count; j++) {
+				reloc = &relocs[j];
+				igt_info(" [%d] <target handle: %u, delta: %x, offset: %llx, "
+					 "presumed_offset: %llx, read_domains: %x, write_domain: %x\n",
+				j, reloc->target_handle, reloc->delta, reloc->offset,
+				reloc->presumed_offset, reloc->read_domains, reloc->write_domain);
+			}
+		}
+	}
+}
+
+void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset)
+{
+	struct drm_i915_gem_execbuffer2 execbuf;
+	uint32_t i;
+	int64_t timeout = NSEC_PER_SEC / 2;
+
+	i = ibb->num_objects++;
+	ibb->objects = realloc(ibb->objects, sizeof(*ibb->objects) * (i + 1));
+	igt_assert(ibb->objects);
+
+	memset(&ibb->objects[i], 0, sizeof(*ibb->objects));
+	ibb->objects[i].relocs_ptr = to_user_pointer(ibb->relocs);
+	ibb->objects[i].relocation_count = ibb->num_relocs;
+	ibb->objects[i].handle = ibb->handle;
+
+	memset(&execbuf, 0, sizeof(execbuf));
+	execbuf.buffers_ptr = (uintptr_t) ibb->objects;
+	execbuf.buffer_count = ibb->num_objects;
+	execbuf.batch_len = end_offset;
+	execbuf.flags = I915_EXEC_DEFAULT;
+
+	gem_execbuf(ibb->i915, &execbuf);
+	gem_wait(ibb->i915, ibb->handle, &timeout);
+
+	if (ibb->debug)
+		intel_bb_dump_execbuf(&execbuf);
+}
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 442f3a18..82e3fd91 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -7,6 +7,7 @@
 
 #include "igt_core.h"
 #include "intel_reg.h"
+#include "drmtest.h"
 
 #define BATCH_SZ 4096
 #define BATCH_RESERVED 16
@@ -422,4 +423,81 @@ typedef void (*igt_media_spinfunc_t)(struct intel_batchbuffer *batch,
 
 igt_media_spinfunc_t igt_get_media_spinfunc(int devid);
 
+
+/*
+ * Batchbuffer without libdrm dependency
+ */
+struct intel_bb {
+	int i915;
+	int gen;
+	bool debug;
+	uint32_t devid;
+	uint32_t handle;
+	uint32_t size;
+	uint32_t *batch;
+	uint32_t *ptr;
+
+	struct drm_i915_gem_exec_object2 *objects;
+	uint32_t num_objects;
+
+	struct drm_i915_gem_relocation_entry *relocs;
+	uint32_t num_relocs;
+	uint32_t allocated_relocs;
+};
+
+struct intel_bb *intel_bb_create(int i915, uint32_t size);
+void intel_bb_destroy(struct intel_bb *ibb);
+void intel_bb_set_debug(struct intel_bb *ibb, bool debug);
+
+inline uint32_t intel_bb_offset(struct intel_bb *ibb)
+{
+	return (uint32_t) ((uint8_t *) ibb->ptr - (uint8_t *) ibb->batch);
+}
+
+inline void intel_bb_ptr_set(struct intel_bb *ibb, uint32_t offset)
+{
+	ibb->ptr = (void *) ((uint8_t *) ibb->batch + offset);
+
+	igt_assert(intel_bb_offset(ibb) < ibb->size);
+}
+
+inline void intel_bb_ptr_add(struct intel_bb *ibb, uint32_t offset)
+{
+	ibb->ptr = (void *) ((uint8_t *) ibb->ptr + offset);
+
+	igt_assert(intel_bb_offset(ibb) < ibb->size);
+}
+
+inline void intel_bb_ptr_align(struct intel_bb *ibb, uint32_t alignment)
+{
+	ibb->ptr = (void *) ALIGN((uintptr_t) ibb->ptr, (uintptr_t) alignment);
+
+	igt_assert(intel_bb_offset(ibb) < ibb->size);
+}
+
+inline void *intel_bb_ptr(struct intel_bb *ibb)
+{
+	return (void *) ibb->ptr;
+}
+
+inline void intel_bb_out(struct intel_bb *ibb, uint32_t dword)
+{
+	*ibb->ptr = dword;
+	ibb->ptr++;
+
+	igt_assert(intel_bb_offset(ibb) < ibb->size);
+}
+
+void intel_bb_out_reloc(struct intel_bb *ibb,
+			uint32_t read_domains,
+			uint32_t write_domain,
+			uint64_t delta);
+
+void intel_bb_offset_reloc(struct intel_bb *ibb, uint32_t handle,
+			   uint32_t offset,
+			   uint32_t read_domains,
+			   uint32_t write_domain);
+
+void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset);
+
 #endif
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 3/6] lib/intel_batchbuffer: Introduce temporary igt_fillfunc_v2_t

[Zbigniew Kempczyński]

gem_gpgpu_fill test is spread over different generations (gen >= 7)
so some transitional state is required until all gens will be
rewritten to new intel_bb code without libdrm dependency.

So, let's define new igt_fillfunc_v2_t to be new fill function.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/intel_batchbuffer.c | 19 +++++++++++++++++++
 lib/intel_batchbuffer.h |  8 ++++++++
 2 files changed, 27 insertions(+)

diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index c7f52f01..20f48f51 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -1152,6 +1152,25 @@ igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid)
 	return fill;
 }
 
+/**
+ * igt_get_gpgpu_fillfunc_v2:
+ * @devid: pci device id
+ *
+ * Returns:
+ *
+ * The platform-specific gpgpu fill function pointer for the device specified
+ * with @devid. Will return NULL when no gpgpu fill function is implemented.
+ */
+igt_fillfunc_v2_t igt_get_gpgpu_fillfunc_v2(int devid)
+{
+	igt_fillfunc_v2_t fill = NULL;
+
+	if (IS_GEN7(devid))
+		fill = gen7_gpgpu_fillfunc_v2;
+
+	return fill;
+}
+
 /**
  * igt_get_media_spinfunc:
  * @devid: pci device id
diff --git a/lib/intel_batchbuffer.h b/lib/intel_batchbuffer.h
index 82e3fd91..21c7af0b 100644
--- a/lib/intel_batchbuffer.h
+++ b/lib/intel_batchbuffer.h
@@ -391,8 +391,16 @@ typedef void (*igt_fillfunc_t)(struct intel_batchbuffer *batch,
 			       unsigned width, unsigned height,
 			       uint8_t color);
 
+struct intel_buf;
+typedef void (*igt_fillfunc_v2_t)(int i915,
+				  struct intel_buf *buf,
+				  unsigned x, unsigned y,
+				  unsigned width, unsigned height,
+				  uint8_t color);
+
 igt_fillfunc_t igt_get_media_fillfunc(int devid);
 igt_fillfunc_t igt_get_gpgpu_fillfunc(int devid);
+igt_fillfunc_v2_t igt_get_gpgpu_fillfunc_v2(int devid);
 
 typedef void (*igt_vme_func_t)(struct intel_batchbuffer *batch,
 			       const struct igt_buf *src,
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 4/6] lib/gpu_cmds: Add gpgpu pipeline functions based on intel_bb

[Zbigniew Kempczyński]

Add no-libdrm functions which will replace libdrm version in the
final version.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/gpu_cmds.c | 340 +++++++++++++++++++++++++++++++++++++++++++++++++
 lib/gpu_cmds.h |  33 +++++
 2 files changed, 373 insertions(+)

diff --git a/lib/gpu_cmds.c b/lib/gpu_cmds.c
index dc0ae96c..c5d5e809 100644
--- a/lib/gpu_cmds.c
+++ b/lib/gpu_cmds.c
@@ -768,3 +768,343 @@ gen9_emit_state_base_address(struct intel_batchbuffer *batch)
 	OUT_BATCH(0);
 	OUT_BATCH(0xfffff000);
 }
+
+/*
+ * Here we start version of the gpgpu fill pipeline creation which is based
+ * on intel_bb.
+ */
+uint32_t
+gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb, uint8_t color)
+{
+	uint32_t *curbe_buffer;
+	uint32_t offset;
+
+	intel_bb_ptr_align(ibb, 64);
+	curbe_buffer = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	*curbe_buffer = color;
+	intel_bb_ptr_add(ibb, 32);
+
+	return offset;
+}
+
+static uint32_t
+gen7_fill_kernel_v2(struct intel_bb *ibb,
+		    const uint32_t kernel[][4],
+		    size_t size)
+{
+	uint32_t *kernel_dst;
+	uint32_t offset;
+
+	intel_bb_ptr_align(ibb, 64);
+	kernel_dst = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	memcpy(kernel_dst, kernel, size);
+
+	intel_bb_ptr_add(ibb, size);
+
+	return offset;
+}
+
+static uint32_t
+gen7_fill_surface_state_v2(struct intel_bb *ibb,
+			   struct intel_buf *buf,
+			   uint32_t format,
+			   int is_dst)
+{
+	struct gen7_surface_state *ss;
+	uint32_t write_domain, read_domain, offset;
+
+	if (is_dst) {
+		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domain = I915_GEM_DOMAIN_SAMPLER;
+	}
+
+	intel_bb_ptr_align(ibb, 64);
+	offset = intel_bb_offset(ibb);
+	ss = intel_bb_ptr(ibb);
+	intel_bb_ptr_add(ibb, 64);
+
+	ss->ss0.surface_type = SURFACE_2D;
+	ss->ss0.surface_format = format;
+	ss->ss0.render_cache_read_write = 1;
+
+	if (buf->tiling == I915_TILING_X)
+		ss->ss0.tiled_mode = 2;
+	else if (buf->tiling == I915_TILING_Y)
+		ss->ss0.tiled_mode = 3;
+
+	ss->ss1.base_addr = 0;
+
+	intel_bb_offset_reloc(ibb, buf->handle, offset + 4,
+			      read_domain, write_domain);
+
+	ss->ss2.height = intel_buf_height(buf) - 1;
+	ss->ss2.width  = intel_buf_width(buf) - 1;
+	ss->ss3.pitch  = buf->stride - 1;
+
+	ss->ss7.shader_chanel_select_r = 4;
+	ss->ss7.shader_chanel_select_g = 5;
+	ss->ss7.shader_chanel_select_b = 6;
+	ss->ss7.shader_chanel_select_a = 7;
+
+	return offset;
+}
+
+static uint32_t
+gen8_fill_surface_state_v2(struct intel_bb *ibb,
+			   struct intel_buf *buf,
+			   uint32_t format,
+			   int is_dst)
+{
+	struct gen8_surface_state *ss;
+	uint32_t write_domain, read_domain, offset;
+
+	if (is_dst) {
+		write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+	} else {
+		write_domain = 0;
+		read_domain = I915_GEM_DOMAIN_SAMPLER;
+	}
+
+	intel_bb_ptr_align(ibb, 64);
+	offset = intel_bb_offset(ibb);
+	ss = intel_bb_ptr(ibb);
+	intel_bb_ptr_add(ibb, 64);
+
+	ss->ss0.surface_type = SURFACE_2D;
+	ss->ss0.surface_format = format;
+	ss->ss0.render_cache_read_write = 1;
+	ss->ss0.vertical_alignment = 1; /* align 4 */
+	ss->ss0.horizontal_alignment = 1; /* align 4 */
+
+	if (buf->tiling == I915_TILING_X)
+		ss->ss0.tiled_mode = 2;
+	else if (buf->tiling == I915_TILING_Y)
+		ss->ss0.tiled_mode = 3;
+
+	ss->ss8.base_addr = 0;
+
+	intel_bb_offset_reloc(ibb, buf->handle, offset + 4,
+			      read_domain, write_domain);
+
+	ss->ss2.height = intel_buf_height(buf) - 1;
+	ss->ss2.width  = intel_buf_width(buf) - 1;
+	ss->ss3.pitch  = buf->stride - 1;
+
+	ss->ss7.shader_chanel_select_r = 4;
+	ss->ss7.shader_chanel_select_g = 5;
+	ss->ss7.shader_chanel_select_b = 6;
+	ss->ss7.shader_chanel_select_a = 7;
+
+	return offset;
+}
+
+static uint32_t
+gen7_fill_binding_table_v2(struct intel_bb *ibb,
+			   struct intel_buf *buf)
+{
+	uint32_t binding_table_offset;
+	uint32_t *binding_table;
+	uint32_t devid = intel_get_drm_devid(ibb->i915);
+
+	intel_bb_ptr_align(ibb, 64);
+	binding_table_offset = intel_bb_offset(ibb);
+	binding_table = intel_bb_ptr(ibb);
+	intel_bb_ptr_add(ibb, 64);
+
+	if (IS_GEN7(devid))
+		binding_table[0] = gen7_fill_surface_state_v2(ibb, buf,
+							      SURFACEFORMAT_R8_UNORM, 1);
+
+	else
+		binding_table[0] = gen8_fill_surface_state_v2(ibb, buf,
+							      SURFACEFORMAT_R8_UNORM, 1);
+
+	return binding_table_offset;
+}
+
+uint32_t
+gen7_fill_interface_descriptor_v2(struct intel_bb *ibb,
+				  struct intel_buf *buf,
+				  const uint32_t kernel[][4],
+				  size_t size)
+{
+	struct gen7_interface_descriptor_data *idd;
+	uint32_t offset;
+	uint32_t binding_table_offset, kernel_offset;
+
+	binding_table_offset = gen7_fill_binding_table_v2(ibb, buf);
+	kernel_offset = gen7_fill_kernel_v2(ibb, kernel, size);
+
+	intel_bb_ptr_align(ibb, 64);
+	idd = intel_bb_ptr(ibb);
+	offset = intel_bb_offset(ibb);
+
+	idd->desc0.kernel_start_pointer = (kernel_offset >> 6);
+
+	idd->desc1.single_program_flow = 1;
+	idd->desc1.floating_point_mode = GEN7_FLOATING_POINT_IEEE_754;
+
+	idd->desc2.sampler_count = 0;      /* 0 samplers used */
+	idd->desc2.sampler_state_pointer = 0;
+
+	idd->desc3.binding_table_entry_count = 0;
+	idd->desc3.binding_table_pointer = (binding_table_offset >> 5);
+
+	idd->desc4.constant_urb_entry_read_offset = 0;
+	idd->desc4.constant_urb_entry_read_length = 1; /* grf 1 */
+
+	intel_bb_ptr_add(ibb, sizeof(*idd));
+
+	return offset;
+}
+
+void
+gen7_emit_state_base_address_v2(struct intel_bb *ibb)
+{
+	intel_bb_out(ibb, GEN7_STATE_BASE_ADDRESS | (10 - 2));
+
+	/* general */
+	intel_bb_out(ibb, 0);
+
+	/* surface */
+	intel_bb_out_reloc(ibb,
+			   I915_GEM_DOMAIN_INSTRUCTION, 0,
+			   BASE_ADDRESS_MODIFY);
+
+	/* dynamic */
+	intel_bb_out_reloc(ibb,
+			   I915_GEM_DOMAIN_INSTRUCTION, 0,
+			   BASE_ADDRESS_MODIFY);
+
+	/* indirect */
+	intel_bb_out(ibb, 0);
+
+	/* instruction */
+	intel_bb_out_reloc(ibb,
+			   I915_GEM_DOMAIN_INSTRUCTION, 0,
+			   BASE_ADDRESS_MODIFY);
+
+	/* general/dynamic/indirect/instruction access Bound */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0 | BASE_ADDRESS_MODIFY);
+}
+
+void
+gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads,
+		       uint32_t urb_entries, uint32_t urb_size,
+		       uint32_t curbe_size, uint32_t mode)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_VFE_STATE | (8 - 2));
+
+	/* scratch buffer */
+	intel_bb_out(ibb, 0);
+
+	/* number of threads & urb entries */
+	intel_bb_out(ibb, threads << 16 |
+		     urb_entries << 8 |
+		     mode << 2); /* GPGPU vs media mode */
+
+	intel_bb_out(ibb, 0);
+
+	/* urb entry size & curbe size */
+	intel_bb_out(ibb, urb_size << 16 |	/* in 256 bits unit */
+		     curbe_size);		/* in 256 bits unit */
+
+	/* scoreboard */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 0);
+}
+
+void
+gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_CURBE_LOAD | (4 - 2));
+	intel_bb_out(ibb, 0);
+	/* curbe total data length */
+	intel_bb_out(ibb, 64);
+	/* curbe data start address, is relative to the dynamics base address */
+	intel_bb_out(ibb, curbe_buffer);
+}
+
+void
+gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb,
+				       uint32_t interface_descriptor)
+{
+	intel_bb_out(ibb, GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD | (4 - 2));
+	intel_bb_out(ibb, 0);
+	/* interface descriptor data length */
+	if (ibb->gen == 7)
+		intel_bb_out(ibb, sizeof(struct gen7_interface_descriptor_data));
+	else
+		intel_bb_out(ibb, sizeof(struct gen8_interface_descriptor_data));
+	/* interface descriptor address, is relative to the dynamics base
+	 * address
+	 */
+	intel_bb_out(ibb, interface_descriptor);
+}
+
+void
+gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb,
+			unsigned int x, unsigned int y,
+			unsigned int width, unsigned int height)
+{
+	uint32_t x_dim, y_dim, tmp, right_mask;
+
+	/*
+	 * Simply do SIMD16 based dispatch, so every thread uses
+	 * SIMD16 channels.
+	 *
+	 * Define our own thread group size, e.g 16x1 for every group, then
+	 * will have 1 thread each group in SIMD16 dispatch. So thread
+	 * width/height/depth are all 1.
+	 *
+	 * Then thread group X = width / 16 (aligned to 16)
+	 * thread group Y = height;
+	 */
+	x_dim = (width + 15) / 16;
+	y_dim = height;
+
+	tmp = width & 15;
+	if (tmp == 0)
+		right_mask = (1 << 16) - 1;
+	else
+		right_mask = (1 << tmp) - 1;
+
+	intel_bb_out(ibb, GEN7_GPGPU_WALKER | 9);
+
+	/* interface descriptor offset */
+	intel_bb_out(ibb, 0);
+
+	/* SIMD size, thread w/h/d */
+	intel_bb_out(ibb, 1 << 30 | /* SIMD16 */
+		  0 << 16 | /* depth:1 */
+		  0 << 8 | /* height:1 */
+		  0); /* width:1 */
+
+	/* thread group X */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, x_dim);
+
+	/* thread group Y */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, y_dim);
+
+	/* thread group Z */
+	intel_bb_out(ibb, 0);
+	intel_bb_out(ibb, 1);
+
+	/* right mask */
+	intel_bb_out(ibb, right_mask);
+
+	/* bottom mask, height 1, always 0xffffffff */
+	intel_bb_out(ibb, 0xffffffff);
+}
diff --git a/lib/gpu_cmds.h b/lib/gpu_cmds.h
index 1321af44..728b4e68 100644
--- a/lib/gpu_cmds.h
+++ b/lib/gpu_cmds.h
@@ -35,6 +35,7 @@
 #include "drmtest.h"
 #include "intel_batchbuffer.h"
 #include "intel_chipset.h"
+#include "intel_bufops.h"
 #include <assert.h>
 
 void
@@ -148,4 +149,36 @@ gen_emit_media_object(struct intel_batchbuffer *batch, unsigned int xoffset,
 void
 gen9_emit_state_base_address(struct intel_batchbuffer *batch);
 
+
+/* No libdrm */
+uint32_t
+gen7_fill_curbe_buffer_data_v2(struct intel_bb *ibb,
+			       uint8_t color);
+
+uint32_t
+gen7_fill_interface_descriptor_v2(struct intel_bb *ibb,
+				  struct intel_buf *buf,
+				  const uint32_t kernel[][4],
+				  size_t size);
+
+void
+gen7_emit_state_base_address_v2(struct intel_bb *ibb);
+
+void
+gen7_emit_vfe_state_v2(struct intel_bb *ibb, uint32_t threads,
+		       uint32_t urb_entries, uint32_t urb_size,
+		       uint32_t curbe_size, uint32_t mode);
+
+void
+gen7_emit_curbe_load_v2(struct intel_bb *ibb, uint32_t curbe_buffer);
+
+void
+gen7_emit_interface_descriptor_load_v2(struct intel_bb *ibb,
+				       uint32_t interface_descriptor);
+
+void
+gen7_emit_gpgpu_walk_v2(struct intel_bb *ibb,
+			unsigned int x, unsigned int y,
+			unsigned int width, unsigned int height);
+
 #endif /* GPU_CMDS_H */
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 5/6] lib/gpgpu_fill: libdrm-free gpgpu pipeline creation for gen7

[Zbigniew Kempczyński]

Provide pipeline for gpgpu fill for gen7.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 lib/gpgpu_fill.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
 lib/gpgpu_fill.h |  8 ++++++++
 2 files changed, 56 insertions(+)

diff --git a/lib/gpgpu_fill.c b/lib/gpgpu_fill.c
index 5660d4c0..09a3756e 100644
--- a/lib/gpgpu_fill.c
+++ b/lib/gpgpu_fill.c
@@ -120,6 +120,7 @@ static const uint32_t gen12_gpgpu_kernel[][4] = {
  *
  */
 
+#define PAGE_SIZE 4096
 #define BATCH_STATE_SPLIT 2048
 /* VFE STATE params */
 #define THREADS 1
@@ -178,6 +179,53 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 	intel_batchbuffer_reset(batch);
 }
 
+void
+gen7_gpgpu_fillfunc_v2(int i915,
+		       struct intel_buf *buf,
+		       unsigned x, unsigned y,
+		       unsigned width, unsigned height,
+		       uint8_t color)
+{
+	struct intel_bb *ibb;
+	uint32_t curbe_buffer, interface_descriptor;
+
+	ibb = intel_bb_create(i915, PAGE_SIZE);
+	intel_bb_ptr_set(ibb, BATCH_STATE_SPLIT);
+
+	/* Fill curbe buffer data */
+	curbe_buffer = gen7_fill_curbe_buffer_data_v2(ibb, color);
+
+	/*
+	 * const buffer needs to fill for every thread, but as we have just 1
+	 * thread per every group, so need only one curbe data.
+	 * For each thread, just use thread group ID for buffer offset.
+	 */
+	interface_descriptor =
+			gen7_fill_interface_descriptor_v2(ibb, buf,
+							  gen7_gpgpu_kernel,
+							  sizeof(gen7_gpgpu_kernel));
+
+	intel_bb_ptr_set(ibb, 0);
+
+	/* GPGPU pipeline */
+	intel_bb_out(ibb, GEN7_PIPELINE_SELECT | PIPELINE_SELECT_GPGPU);
+
+	gen7_emit_state_base_address_v2(ibb);
+	gen7_emit_vfe_state_v2(ibb, THREADS, GEN7_GPGPU_URB_ENTRIES,
+			       GPGPU_URB_SIZE, GPGPU_CURBE_SIZE,
+			       GEN7_VFE_STATE_GPGPU_MODE);
+	gen7_emit_curbe_load_v2(ibb, curbe_buffer);
+	gen7_emit_interface_descriptor_load_v2(ibb, interface_descriptor);
+	gen7_emit_gpgpu_walk_v2(ibb, x, y, width, height);
+
+	intel_bb_out(ibb, MI_BATCH_BUFFER_END);
+	intel_bb_ptr_align(ibb, 32);
+
+	intel_bb_exec(ibb, intel_bb_offset(ibb));
+
+	intel_bb_destroy(ibb);
+}
+
 void
 gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
diff --git a/lib/gpgpu_fill.h b/lib/gpgpu_fill.h
index da7d646f..0ba3d033 100644
--- a/lib/gpgpu_fill.h
+++ b/lib/gpgpu_fill.h
@@ -28,6 +28,7 @@
 #define GPGPU_FILL_H
 
 #include "intel_batchbuffer.h"
+#include "intel_bufops.h"
 
 void
 gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
@@ -36,6 +37,13 @@ gen7_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    unsigned int width, unsigned int height,
 		    uint8_t color);
 
+void
+gen7_gpgpu_fillfunc_v2(int i915,
+		       struct intel_buf *buf,
+		       unsigned x, unsigned y,
+		       unsigned width, unsigned height,
+		       uint8_t color);
+
 void
 gen8_gpgpu_fillfunc(struct intel_batchbuffer *batch,
 		    const struct igt_buf *dst,
-- 
2.26.0

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[igt-dev] [PATCH i-g-t 6/6] tests/gem_gpgpu_fill: Add gen7 version without libdrm dependency

[Zbigniew Kempczyński]

Rewriting all gpgpu tests is time consuming, so provide single
gen7 version which can be litmus paper does change goes toward
appropriate direction or not. Gpgpu pipeline creation is a little
bit coupled (some functions are used in other gens) so providing
"v2" version of the same functions is necessary unless former
will have full replacement.

So gpgpu fill prefers now "newer" version of the same pipeline
creation which is libdrm-free.

Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/i915/gem_gpgpu_fill.c | 125 ++++++++++++++++++++++++++++--------
 1 file changed, 98 insertions(+), 27 deletions(-)

diff --git a/tests/i915/gem_gpgpu_fill.c b/tests/i915/gem_gpgpu_fill.c
index fb1758bd..e35d40a1 100644
--- a/tests/i915/gem_gpgpu_fill.c
+++ b/tests/i915/gem_gpgpu_fill.c
@@ -46,6 +46,7 @@
 #include "i915/gem.h"
 #include "igt.h"
 #include "intel_bufmgr.h"
+#include "intel_bufops.h"
 
 #define WIDTH 64
 #define HEIGHT 64
@@ -60,6 +61,7 @@ typedef struct {
 	uint32_t devid;
 	drm_intel_bufmgr *bufmgr;
 	uint8_t linear[WIDTH * HEIGHT];
+	struct buf_ops *bops;
 } data_t;
 
 static void scratch_buf_init(data_t *data, struct igt_buf *buf,
@@ -83,6 +85,33 @@ static void scratch_buf_init(data_t *data, struct igt_buf *buf,
 	buf->bpp = 32;
 }
 
+static struct intel_buf *
+create_buf(data_t *data, int width, int height, uint8_t color)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	int i;
+
+	buf = calloc(1, sizeof(*buf));
+	igt_assert(buf);
+
+	/*
+	 * Legacy code uses 32 bpp after buffer creation.
+	 * Let's do the same due to keep shader intact.
+	 */
+	intel_buf_init(data->bops, buf, width/4, height, 32, I915_TILING_NONE, 0);
+
+	ptr = gem_mmap__cpu_coherent(data->drm_fd,
+				     buf->handle, 0, buf->size, PROT_WRITE);
+
+	for (i = 0; i < buf->size; i++)
+		ptr[i] = color;
+
+	munmap(ptr, buf->size);
+
+	return buf;
+}
+
 static void
 scratch_buf_check(data_t *data, struct igt_buf *buf, int x, int y,
 		uint8_t color)
@@ -97,47 +126,89 @@ scratch_buf_check(data_t *data, struct igt_buf *buf, int x, int y,
 		     color, val, x, y);
 }
 
-igt_simple_main
+static void buf_check(uint8_t *ptr, int x, int y, uint8_t color)
+{
+	uint8_t val;
+
+	val = ptr[y * WIDTH + x];
+	igt_assert_f(val == color,
+		     "Expected 0x%02x, found 0x%02x at (%d,%d)\n",
+		     color, val, x, y);
+}
+
+static void no_libdrm(data_t *data, igt_fillfunc_v2_t fill)
+{
+	struct intel_buf *buf;
+	uint8_t *ptr;
+	int i, j;
+
+	buf = create_buf(data, WIDTH, HEIGHT, COLOR_C4);
+	ptr = gem_mmap__cpu_coherent(data->drm_fd, buf->handle,
+				     0, buf->size, PROT_READ);
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			buf_check(ptr, i, j, COLOR_C4);
+
+	fill(data->drm_fd, buf, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			if (i < WIDTH / 2 && j < HEIGHT / 2)
+				buf_check(ptr, i, j, COLOR_4C);
+			else
+				buf_check(ptr, i, j, COLOR_C4);
+
+	munmap(ptr, buf->size);
+}
+
+static void with_libdrm(data_t *data, igt_fillfunc_t fill)
 {
-	data_t data = {0, };
 	struct intel_batchbuffer *batch = NULL;
 	struct igt_buf dst;
-	igt_fillfunc_t gpgpu_fill = NULL;
 	int i, j;
 
+	batch = intel_batchbuffer_alloc(data->bufmgr, data->devid);
+	igt_assert(batch);
+
+	scratch_buf_init(data, &dst, WIDTH, HEIGHT, STRIDE, COLOR_C4);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			scratch_buf_check(data, &dst, i, j, COLOR_C4);
+
+	fill(batch, &dst, 0, 0, WIDTH / 2, HEIGHT / 2, COLOR_4C);
+
+	for (i = 0; i < WIDTH; i++)
+		for (j = 0; j < HEIGHT; j++)
+			if (i < WIDTH / 2 && j < HEIGHT / 2)
+				scratch_buf_check(data, &dst, i, j, COLOR_4C);
+			else
+				scratch_buf_check(data, &dst, i, j, COLOR_C4);
+
+}
+
+igt_simple_main
+{
+	data_t data = {0, };
+	igt_fillfunc_t gpgpu_fill = NULL;
+	igt_fillfunc_v2_t gpgpu_fill_v2 = NULL;
+
 	data.drm_fd = drm_open_driver_render(DRIVER_INTEL);
 	data.devid = intel_get_drm_devid(data.drm_fd);
 	igt_require_gem(data.drm_fd);
+	data.bops = buf_ops_create(data.drm_fd);
 
 	data.bufmgr = drm_intel_bufmgr_gem_init(data.drm_fd, 4096);
 	igt_assert(data.bufmgr);
 
 	gpgpu_fill = igt_get_gpgpu_fillfunc(data.devid);
+	gpgpu_fill_v2 = igt_get_gpgpu_fillfunc_v2(data.devid);
 
-	igt_require_f(gpgpu_fill,
+	igt_require_f(gpgpu_fill || gpgpu_fill_v2,
 		      "no gpgpu-fill function\n");
 
-	batch = intel_batchbuffer_alloc(data.bufmgr, data.devid);
-	igt_assert(batch);
-
-	scratch_buf_init(&data, &dst, WIDTH, HEIGHT, STRIDE, COLOR_C4);
-
-	for (i = 0; i < WIDTH; i++) {
-		for (j = 0; j < HEIGHT; j++) {
-			scratch_buf_check(&data, &dst, i, j, COLOR_C4);
-		}
-	}
-
-	gpgpu_fill(batch,
-		   &dst, 0, 0, WIDTH / 2, HEIGHT / 2,
-		   COLOR_4C);
-
-	for (i = 0; i < WIDTH; i++) {
-		for (j = 0; j < HEIGHT; j++) {
-			if (i < WIDTH / 2 && j < HEIGHT / 2)
-				scratch_buf_check(&data, &dst, i, j, COLOR_4C);
-			else
-				scratch_buf_check(&data, &dst, i, j, COLOR_C4);
-		}
-	}
+	if (gpgpu_fill_v2)
+		no_libdrm(&data, gpgpu_fill_v2);
+	else
+		with_libdrm(&data, gpgpu_fill);
 }
-- 
2.26.0

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[igt-dev] ✓ Fi.CI.BAT: success for Make gpgpu fill tests libdrm independent

[Patchwork]

== Series Details ==

Series: Make gpgpu fill tests libdrm independent
URL   : https://patchwork.freedesktop.org/series/77175/
State : success

== Summary ==

CI Bug Log - changes from IGT_5651 -> IGTPW_4559
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/index.html

Known issues
------------

  Here are the changes found in IGTPW_4559 that come from known issues:

### IGT changes ###

#### Possible fixes ####

  * igt@i915_selftest@live@execlists:
    - fi-skl-guc:         [INCOMPLETE][1] ([i915#1874]) -> [PASS][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/fi-skl-guc/igt@i915_selftest@live@execlists.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/fi-skl-guc/igt@i915_selftest@live@execlists.html
    - fi-skl-6700k2:      [INCOMPLETE][3] ([i915#1874]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/fi-skl-6700k2/igt@i915_selftest@live@execlists.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/fi-skl-6700k2/igt@i915_selftest@live@execlists.html

  
  [i915#1874]: https://gitlab.freedesktop.org/drm/intel/issues/1874


Participating hosts (50 -> 43)
------------------------------

  Missing    (7): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-kbl-7560u fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5651 -> IGTPW_4559

  CI-20190529: 20190529
  CI_DRM_8467: 1a0f0c378117fc90f421a692698ad85963ecdb3a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4559: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/index.html
  IGT_5651: e54e2642f1967ca3c488db32264607df670d1dfb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/index.html
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Re: [igt-dev] [PATCH i-g-t 1/6] lib/intel_bufops: Add bufops reference and relaxate stride requirement

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-12 09:23:57)
> Add bufops reference to intel_buf to allow acquire drm fd against which
> buffer was created.
> 
> Relax stride limitation for intel_buf for non-tiled buffers.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  lib/intel_bufops.c | 20 +++++++++++++++++++-
>  lib/intel_bufops.h |  3 +++
>  2 files changed, 22 insertions(+), 1 deletion(-)
> 
> diff --git a/lib/intel_bufops.c b/lib/intel_bufops.c
> index 804b2a0a..cdf6b114 100644
> --- a/lib/intel_bufops.c
> +++ b/lib/intel_bufops.c
> @@ -686,6 +686,8 @@ static void __intel_buf_init(struct buf_ops *bops,
>  
>         memset(buf, 0, sizeof(*buf));
>  
> +       buf->bops = bops;
> +
>         if (compression) {
>                 int aux_width, aux_height;
>  
> @@ -721,7 +723,10 @@ static void __intel_buf_init(struct buf_ops *bops,
>                 size = buf->aux.offset + aux_width * aux_height;
>  
>         } else {
> -               buf->stride = ALIGN(width * (bpp / 8), 128);
> +               if (buf->tiling)
> +                       buf->stride = ALIGN(width * (bpp / 8), 128);
> +               else
> +                       buf->stride = width * (bpp / 8);

There might be a chicken-and-egg problem here for intermixing bufops
with igt_fb. For a linear scanout buffer, we need stride aligned to 64B.

If there is [or will be] a buf_init_for_data() that will take in the
handle, size and stride, and should allow for interop.
-Chris
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Re: [igt-dev] [PATCH i-g-t 2/6] lib/intel_batchbuffer: Introduce intel_bb

[Chris Wilson]

Quoting Zbigniew Kempczyński (2020-05-12 09:23:58)
> Simple batchbuffer facility which gathers and outputs relocations.
> 
> Signed-off-by: Zbigniew Kempczyński <zbigniew.kempczynski@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>  lib/intel_batchbuffer.c | 202 ++++++++++++++++++++++++++++++++++++++++
>  lib/intel_batchbuffer.h |  78 ++++++++++++++++
>  2 files changed, 280 insertions(+)
> 
> diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
> index f1a45b47..c7f52f01 100644
> --- a/lib/intel_batchbuffer.c
> +++ b/lib/intel_batchbuffer.c
> @@ -41,6 +41,7 @@
>  #include "rendercopy.h"
>  #include "media_fill.h"
>  #include "ioctl_wrappers.h"
> +#include "i915/gem_mman.h"
>  #include "media_spin.h"
>  #include "gpgpu_fill.h"
>  #include "igt_aux.h"
> @@ -1171,3 +1172,204 @@ igt_media_spinfunc_t igt_get_media_spinfunc(int devid)
>  
>         return spin;
>  }
> +
> +/* Intel batchbuffer v2 */
> +struct intel_bb *intel_bb_create(int i915, uint32_t size)
> +{
> +       struct intel_bb *ibb = calloc(1, sizeof(*ibb));
> +
> +       igt_assert(ibb);
> +
> +       ibb->i915 = i915;
> +       ibb->devid = intel_get_drm_devid(i915);
> +       ibb->gen = intel_gen(ibb->devid);
> +       ibb->handle = gem_create(i915, size);
> +       ibb->size = size;
> +       ibb->batch = gem_mmap__cpu_coherent(i915, ibb->handle, 0, size,
> +                                           PROT_READ | PROT_WRITE);

cpu coherent? There should be no read backs, and emission should be
linear?

> +       memset(ibb->batch, 0, size);

No need, it's zero by ABI.

> +       ibb->ptr = ibb->batch;
> +       ibb->objects = NULL;
> +
> +       return ibb;
> +}
> +
> +void intel_bb_destroy(struct intel_bb *ibb)
> +{
> +       uint32_t i;
> +
> +       igt_assert(ibb);
> +
> +       /* Free relocations */
> +       for (i = 0; i < ibb->num_objects; i++) {
> +               if ((void *) ibb->objects->relocs_ptr)

void *ptr = from_user_pointer(ibb->objects->relocs_ptr);

> +                       free((void *) ibb->objects->relocs_ptr);
> +       }
> +
> +       free(ibb->objects);
> +
> +       munmap(ibb->batch, ibb->size);
> +       gem_close(ibb->i915, ibb->handle);
> +
> +       free(ibb);
> +}
> +
> +void intel_bb_set_debug(struct intel_bb *ibb, bool debug)
> +{
> +       ibb->debug = debug;
> +}
> +
> +static void intel_bb_add_handle(struct intel_bb *ibb, uint32_t handle)
> +{
> +       uint32_t i;
> +
> +       igt_assert(ibb);
> +
> +       /* Skip bb as object, it will be added before exec */
> +       if (ibb->handle == handle)
> +               return;
> +
> +       for (i = 0; i < ibb->num_objects; i++)
> +               if (ibb->objects[i].handle == handle)
> +                       return;
> +
> +       i = ibb->num_objects;
> +       ibb->objects = realloc(ibb->objects,
> +                              sizeof(*ibb->objects) * (i + 1));
> +       igt_assert(ibb->objects);
> +
> +       memset(&ibb->objects[i], 0, sizeof(*ibb->objects));
> +       ibb->objects[i].handle = handle;
> +
> +       ibb->num_objects++;
> +}
> +
> +static void intel_bb_emit_reloc(struct intel_bb *ibb,
> +                               uint32_t handle,
> +                               uint32_t read_domains,
> +                               uint32_t write_domain,
> +                               uint64_t delta,
> +                               uint64_t offset,
> +                               bool use_offset,
> +                               bool out)
> +
> +{
> +       struct drm_i915_gem_relocation_entry *relocs;
> +       uint32_t i;
> +
> +       intel_bb_add_handle(ibb, handle);

For bonus points, you can use LUT.

> +       relocs = ibb->relocs;
> +       if (ibb->num_relocs == ibb->allocated_relocs) {
> +               ibb->allocated_relocs += 4096 / sizeof(*relocs);
> +               relocs = realloc(relocs, sizeof(*relocs) * ibb->allocated_relocs);
> +               igt_assert(relocs);
> +               ibb->relocs = relocs;
> +       }
> +
> +       i = ibb->num_relocs++;
> +       memset(&relocs[i], 0, sizeof(*relocs));
> +       relocs[i].target_handle = handle;
> +       relocs[i].read_domains = read_domains;
> +       relocs[i].write_domain = write_domain;
> +       relocs[i].delta = delta;
> +       if (use_offset)
> +               relocs[i].offset = offset;
> +       else
> +               relocs[i].offset = intel_bb_offset(ibb);
> +
> +       if (out) {
> +               intel_bb_out(ibb, delta);
> +               if (ibb->gen >= 8)
> +                       intel_bb_out(ibb, delta >> 32);
> +       }
> +}
> +
> +void intel_bb_out_reloc(struct intel_bb *ibb,
> +                       uint32_t read_domains,
> +                       uint32_t write_domain,
> +                       uint64_t delta)
> +
> +{
> +       igt_assert(ibb);
> +
> +       intel_bb_emit_reloc(ibb, ibb->handle, read_domains, write_domain,
> +                           delta, intel_bb_offset(ibb),
> +                           false, true);
> +}
> +
> +void intel_bb_offset_reloc(struct intel_bb *ibb, uint32_t handle,
> +                          uint32_t offset,
> +                          uint32_t read_domains,
> +                          uint32_t write_domain)
> +{
> +       igt_assert(ibb);
> +
> +       intel_bb_emit_reloc(ibb, handle, read_domains, write_domain,
> +                           0, offset, true, false);
> +}

Experience says this is inverted and we want

intel_bb_emit_reloc() {
	address = intel_bb_add_reloc(...);
	EMIT(lower_32_bits(address));
	if (bb->reloc_64b)
		EMIT(upper_32_bits(address));
}

> +
> +static void intel_bb_dump_execbuf(struct drm_i915_gem_execbuffer2 *execbuf)
> +{
> +       struct drm_i915_gem_exec_object2 *objects;
> +       struct drm_i915_gem_relocation_entry *relocs, *reloc;
> +       int i, j;
> +
> +       igt_info("execbuf batch len: %u, start offset: 0x%x, "
> +                "DR1: 0x%x, DR4: 0x%x, "
> +                "num clip: %u, clipptr: 0x%llx, "
> +                "flags: 0x%llx, rsvd1: 0x%llx, rsvd2: 0x%llx\n",
> +                execbuf->batch_len, execbuf->batch_start_offset,
> +                execbuf->DR1, execbuf->DR4,
> +                execbuf->num_cliprects, execbuf->cliprects_ptr,
> +                execbuf->flags, execbuf->rsvd1, execbuf->rsvd2);
> +
> +       igt_info("execbuf buffer_count: %d\n", execbuf->buffer_count);
> +       for (i = 0; i < execbuf->buffer_count; i++) {
> +               objects = &((struct drm_i915_gem_exec_object2 *) execbuf->buffers_ptr)[i];
> +               relocs = (struct drm_i915_gem_relocation_entry *) objects->relocs_ptr;
> +               igt_info(" [%d] <handle: %u, reloc_count: %d, reloc_ptr: %p, "
> +                        "align: %llx, offset: %llx, flags: %llx, rsvd1: %llx, rsvd2: %llx\n",
> +                        i, objects->handle, objects->relocation_count,
> +                        (void *) objects->relocs_ptr, objects->alignment, objects->offset,
> +                        objects->flags, objects->rsvd1, objects->rsvd2);
> +               if (objects->relocation_count) {
> +                       igt_info("execbuf relocs:\n");
> +                       for (j = 0; j < objects->relocation_count; j++) {
> +                               reloc = &relocs[j];
> +                               igt_info(" [%d] <target handle: %u, delta: %x, offset: %llx, "
> +                                        "presumed_offset: %llx, read_domains: %x, write_domain: %x\n",
> +                               j, reloc->target_handle, reloc->delta, reloc->offset,
> +                               reloc->presumed_offset, reloc->read_domains, reloc->write_domain);
> +                       }
> +               }
> +       }
> +}
> +
> +void intel_bb_exec(struct intel_bb *ibb, uint32_t end_offset)
> +{
> +       struct drm_i915_gem_execbuffer2 execbuf;
> +       uint32_t i;
> +       int64_t timeout = NSEC_PER_SEC / 2;
> +
> +       i = ibb->num_objects++;
> +       ibb->objects = realloc(ibb->objects, sizeof(*ibb->objects) * (i + 1));
> +       igt_assert(ibb->objects);
> +
> +       memset(&ibb->objects[i], 0, sizeof(*ibb->objects));
> +       ibb->objects[i].relocs_ptr = to_user_pointer(ibb->relocs);
> +       ibb->objects[i].relocation_count = ibb->num_relocs;
> +       ibb->objects[i].handle = ibb->handle;
> +
> +       memset(&execbuf, 0, sizeof(execbuf));
> +       execbuf.buffers_ptr = (uintptr_t) ibb->objects;
> +       execbuf.buffer_count = ibb->num_objects;
> +       execbuf.batch_len = end_offset;
> +       execbuf.flags = I915_EXEC_DEFAULT;

You should be at least fulfilling the contract for NORELOC or else
something is very wrong with the framework.

> +
> +       gem_execbuf(ibb->i915, &execbuf);

> +       gem_wait(ibb->i915, ibb->handle, &timeout);

NO!!!!!
-Chris
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[igt-dev] ✓ Fi.CI.IGT: success for Make gpgpu fill tests libdrm independent

[Patchwork]

== Series Details ==

Series: Make gpgpu fill tests libdrm independent
URL   : https://patchwork.freedesktop.org/series/77175/
State : success

== Summary ==

CI Bug Log - changes from IGT_5651_full -> IGTPW_4559_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in IGTPW_4559_full:

### IGT changes ###

#### Suppressed ####

  The following results come from untrusted machines, tests, or statuses.
  They do not affect the overall result.

  * {igt@sysfs_timeslice_duration@timeout@bcs0}:
    - shard-iclb:         [PASS][1] -> [FAIL][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-iclb8/igt@sysfs_timeslice_duration@timeout@bcs0.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-iclb7/igt@sysfs_timeslice_duration@timeout@bcs0.html

  
Known issues
------------

  Here are the changes found in IGTPW_4559_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@kms_cursor_crc@pipe-b-cursor-size-change:
    - shard-kbl:          [PASS][3] -> [FAIL][4] ([i915#54])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl1/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl7/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
    - shard-apl:          [PASS][5] -> [FAIL][6] ([i915#54])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-apl7/igt@kms_cursor_crc@pipe-b-cursor-size-change.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-apl4/igt@kms_cursor_crc@pipe-b-cursor-size-change.html

  * igt@kms_cursor_crc@pipe-d-cursor-suspend:
    - shard-tglb:         [PASS][7] -> [INCOMPLETE][8] ([i915#1602])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb5/igt@kms_cursor_crc@pipe-d-cursor-suspend.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb7/igt@kms_cursor_crc@pipe-d-cursor-suspend.html

  * igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled:
    - shard-apl:          [PASS][9] -> [FAIL][10] ([i915#52] / [i915#54] / [i915#95])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-apl2/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-apl4/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
    - shard-kbl:          [PASS][11] -> [FAIL][12] ([i915#177] / [i915#52] / [i915#54] / [i915#93] / [i915#95])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl1/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl6/igt@kms_draw_crc@draw-method-xrgb8888-blt-untiled.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
    - shard-iclb:         [PASS][13] -> [INCOMPLETE][14] ([i915#1185] / [i915#250])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-iclb8/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-iclb3/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html

  * igt@kms_psr@psr2_no_drrs:
    - shard-iclb:         [PASS][15] -> [SKIP][16] ([fdo#109441]) +1 similar issue
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-iclb2/igt@kms_psr@psr2_no_drrs.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-iclb6/igt@kms_psr@psr2_no_drrs.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][17] -> [DMESG-WARN][18] ([i915#180]) +2 similar issues
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl3/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  
#### Possible fixes ####

  * {igt@gem_exec_schedule@smoketest@bcs0}:
    - shard-tglb:         [INCOMPLETE][19] -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb8/igt@gem_exec_schedule@smoketest@bcs0.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb1/igt@gem_exec_schedule@smoketest@bcs0.html

  * igt@i915_suspend@forcewake:
    - shard-apl:          [DMESG-WARN][21] ([i915#180]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-apl1/igt@i915_suspend@forcewake.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-apl6/igt@i915_suspend@forcewake.html

  * igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen:
    - shard-kbl:          [FAIL][23] ([i915#54] / [i915#93] / [i915#95]) -> [PASS][24] +2 similar issues
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl6/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl2/igt@kms_cursor_crc@pipe-a-cursor-256x85-offscreen.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-tglb:         [INCOMPLETE][25] ([i915#1602] / [i915#456]) -> [PASS][26]
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb8/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_fbcon_fbt@fbc:
    - shard-tglb:         [FAIL][27] ([i915#64]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb6/igt@kms_fbcon_fbt@fbc.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb6/igt@kms_fbcon_fbt@fbc.html

  * igt@kms_hdmi_inject@inject-audio:
    - shard-tglb:         [SKIP][29] ([i915#433]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb8/igt@kms_hdmi_inject@inject-audio.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb3/igt@kms_hdmi_inject@inject-audio.html

  * igt@kms_hdr@bpc-switch-suspend:
    - shard-kbl:          [DMESG-WARN][31] ([i915#180]) -> [PASS][32] +4 similar issues
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl4/igt@kms_hdr@bpc-switch-suspend.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl3/igt@kms_hdr@bpc-switch-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
    - shard-kbl:          [FAIL][33] ([i915#53] / [i915#93] / [i915#95]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl7/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
    - shard-apl:          [FAIL][35] ([i915#53] / [i915#95]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-apl1/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-apl3/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html

  * igt@kms_plane_cursor@pipe-a-viewport-size-64:
    - shard-kbl:          [FAIL][37] ([i915#1559] / [i915#93] / [i915#95]) -> [PASS][38]
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl6/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl7/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
    - shard-apl:          [FAIL][39] ([i915#1559] / [i915#95]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-apl2/igt@kms_plane_cursor@pipe-a-viewport-size-64.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-apl8/igt@kms_plane_cursor@pipe-a-viewport-size-64.html

  * igt@kms_psr2_su@frontbuffer:
    - shard-iclb:         [SKIP][41] ([fdo#109642] / [fdo#111068]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-iclb6/igt@kms_psr2_su@frontbuffer.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-iclb2/igt@kms_psr2_su@frontbuffer.html

  * igt@kms_psr@psr2_cursor_plane_move:
    - shard-iclb:         [SKIP][43] ([fdo#109441]) -> [PASS][44] +2 similar issues
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-iclb3/igt@kms_psr@psr2_cursor_plane_move.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-iclb2/igt@kms_psr@psr2_cursor_plane_move.html

  * {igt@perf@blocking-parameterized}:
    - shard-iclb:         [FAIL][45] ([i915#1542]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-iclb8/igt@perf@blocking-parameterized.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-iclb6/igt@perf@blocking-parameterized.html

  
#### Warnings ####

  * igt@i915_pm_dc@dc6-dpms:
    - shard-tglb:         [FAIL][47] ([i915#454]) -> [SKIP][48] ([i915#468])
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb5/igt@i915_pm_dc@dc6-dpms.html
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb2/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-tglb:         [SKIP][49] ([i915#468]) -> [FAIL][50] ([i915#454])
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-tglb2/igt@i915_pm_dc@dc6-psr.html
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-tglb3/igt@i915_pm_dc@dc6-psr.html

  * igt@kms_content_protection@atomic-dpms:
    - shard-kbl:          [TIMEOUT][51] ([i915#1319]) -> [FAIL][52] ([fdo#110321] / [fdo#110336] / [i915#93] / [i915#95])
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/IGT_5651/shard-kbl3/igt@kms_content_protection@atomic-dpms.html
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/shard-kbl2/igt@kms_content_protection@atomic-dpms.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
  [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
  [fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
  [fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
  [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
  [i915#1185]: https://gitlab.freedesktop.org/drm/intel/issues/1185
  [i915#1319]: https://gitlab.freedesktop.org/drm/intel/issues/1319
  [i915#1542]: https://gitlab.freedesktop.org/drm/intel/issues/1542
  [i915#1559]: https://gitlab.freedesktop.org/drm/intel/issues/1559
  [i915#1602]: https://gitlab.freedesktop.org/drm/intel/issues/1602
  [i915#177]: https://gitlab.freedesktop.org/drm/intel/issues/177
  [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
  [i915#250]: https://gitlab.freedesktop.org/drm/intel/issues/250
  [i915#433]: https://gitlab.freedesktop.org/drm/intel/issues/433
  [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454
  [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456
  [i915#468]: https://gitlab.freedesktop.org/drm/intel/issues/468
  [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52
  [i915#53]: https://gitlab.freedesktop.org/drm/intel/issues/53
  [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54
  [i915#64]: https://gitlab.freedesktop.org/drm/intel/issues/64
  [i915#93]: https://gitlab.freedesktop.org/drm/intel/issues/93
  [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95


Participating hosts (8 -> 8)
------------------------------

  No changes in participating hosts


Build changes
-------------

  * CI: CI-20190529 -> None
  * IGT: IGT_5651 -> IGTPW_4559

  CI-20190529: 20190529
  CI_DRM_8467: 1a0f0c378117fc90f421a692698ad85963ecdb3a @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_4559: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/index.html
  IGT_5651: e54e2642f1967ca3c488db32264607df670d1dfb @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_4559/index.html
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