* [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150
@ 2020-04-24 4:43 Vinod Koul
2020-04-24 4:43 ` [PATCH 2/2] clk: qcom: gcc: Add missing UFS " Vinod Koul
2020-04-25 19:10 ` [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU " Stephen Boyd
0 siblings, 2 replies; 8+ messages in thread
From: Vinod Koul @ 2020-04-24 4:43 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
Add the GPU and NPU clocks for SM8150. They were missed in earlier
addition of clock driver.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/clk/qcom/gcc-sm8150.c | 72 +++++++++++++++++++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index ef98fdc51755..5c3dc34c955e 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -1617,6 +1617,40 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
},
};
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_gpu_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(15),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll0.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* these are external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(16),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_gpu_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_gpu_gpll0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_gpu_iref_clk = {
.halt_reg = 0x8c010,
.halt_check = BRANCH_HALT,
@@ -1699,6 +1733,40 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
},
};
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_npu_gpll0_clk_src = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(18),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_gpll0_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gpll0.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_npu_gpll0_div_clk_src = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x52004,
+ .enable_mask = BIT(19),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_npu_gpll0_div_clk_src",
+ .parent_hws = (const struct clk_hw *[]){
+ &gcc_npu_gpll0_clk_src.clkr.hw },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_npu_trig_clk = {
.halt_reg = 0x4d00c,
.halt_check = BRANCH_VOTED,
@@ -3375,12 +3443,16 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_GP3_CLK] = &gcc_gp3_clk.clkr,
[GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr,
[GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr,
+ [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr,
+ [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr,
[GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr,
[GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr,
[GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr,
[GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr,
[GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr,
[GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr,
+ [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr,
+ [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr,
[GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr,
[GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr,
[GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] clk: qcom: gcc: Add missing UFS clocks for SM8150
2020-04-24 4:43 [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150 Vinod Koul
@ 2020-04-24 4:43 ` Vinod Koul
2020-04-25 19:11 ` Stephen Boyd
2020-04-25 19:10 ` [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU " Stephen Boyd
1 sibling, 1 reply; 8+ messages in thread
From: Vinod Koul @ 2020-04-24 4:43 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
Add the missing ufs card and ufs phy clocks for SM8150. They were missed
in earlier addition of clock driver.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
---
drivers/clk/qcom/gcc-sm8150.c | 84 +++++++++++++++++++++++++++++++++++
1 file changed, 84 insertions(+)
diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
index 5c3dc34c955e..4354620fa12d 100644
--- a/drivers/clk/qcom/gcc-sm8150.c
+++ b/drivers/clk/qcom/gcc-sm8150.c
@@ -2881,6 +2881,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
},
};
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7501c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_card_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x750ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_card_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x75018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_card_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ufs_card_unipro_core_clk = {
.halt_reg = 0x75058,
.halt_check = BRANCH_HALT,
@@ -3061,6 +3100,45 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = {
},
};
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x7701c,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_rx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x770ac,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_rx_symbol_1_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
+/* external clocks so add BRANCH_HALT_SKIP */
+static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
+ .halt_check = BRANCH_HALT_SKIP,
+ .clkr = {
+ .enable_reg = 0x77018,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gcc_ufs_phy_tx_symbol_0_clk",
+ .ops = &clk_branch2_ops,
+ },
+ },
+};
+
static struct clk_branch gcc_ufs_phy_unipro_core_clk = {
.halt_reg = 0x77058,
.halt_check = BRANCH_HALT,
@@ -3557,6 +3635,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr,
[GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK] =
&gcc_ufs_card_phy_aux_hw_ctl_clk.clkr,
+ [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr,
+ [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr,
+ [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr,
[GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_card_unipro_core_clk_src.clkr,
@@ -3574,6 +3655,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = {
[GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr,
[GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr,
[GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr,
+ [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr,
+ [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr,
+ [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr,
[GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC] =
&gcc_ufs_phy_unipro_core_clk_src.clkr,
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150
2020-04-24 4:43 [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150 Vinod Koul
2020-04-24 4:43 ` [PATCH 2/2] clk: qcom: gcc: Add missing UFS " Vinod Koul
@ 2020-04-25 19:10 ` Stephen Boyd
2020-04-27 4:41 ` Vinod Koul
1 sibling, 1 reply; 8+ messages in thread
From: Stephen Boyd @ 2020-04-25 19:10 UTC (permalink / raw)
To: Michael Turquette, Vinod Koul
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
Quoting Vinod Koul (2020-04-23 21:43:10)
> Add the GPU and NPU clocks for SM8150. They were missed in earlier
> addition of clock driver.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
Fixes tag? That way backporters know they're missing this.
> ---
> drivers/clk/qcom/gcc-sm8150.c | 72 +++++++++++++++++++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index ef98fdc51755..5c3dc34c955e 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -1617,6 +1617,40 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = {
> },
> };
>
> +/* external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_gpu_gpll0_clk_src = {
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(15),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_gpll0_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gpll0.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +/* these are external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_gpu_gpll0_div_clk_src = {
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(16),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_gpu_gpll0_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_gpu_gpll0_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static struct clk_branch gcc_gpu_iref_clk = {
> .halt_reg = 0x8c010,
> .halt_check = BRANCH_HALT,
> @@ -1699,6 +1733,40 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = {
> },
> };
>
> +/* external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_npu_gpll0_clk_src = {
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(18),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_npu_gpll0_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gpll0.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +/* external clocks so add BRANCH_HALT_SKIP */
None of these look external. The parents are all inside this driver. Why
are we skipping the halt check?
> +static struct clk_branch gcc_npu_gpll0_div_clk_src = {
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x52004,
> + .enable_mask = BIT(19),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_npu_gpll0_div_clk_src",
> + .parent_hws = (const struct clk_hw *[]){
> + &gcc_npu_gpll0_clk_src.clkr.hw },
> + .num_parents = 1,
> + .flags = CLK_SET_RATE_PARENT,
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> static struct clk_branch gcc_npu_trig_clk = {
> .halt_reg = 0x4d00c,
> .halt_check = BRANCH_VOTED,
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: qcom: gcc: Add missing UFS clocks for SM8150
2020-04-24 4:43 ` [PATCH 2/2] clk: qcom: gcc: Add missing UFS " Vinod Koul
@ 2020-04-25 19:11 ` Stephen Boyd
2020-04-27 4:55 ` Vinod Koul
0 siblings, 1 reply; 8+ messages in thread
From: Stephen Boyd @ 2020-04-25 19:11 UTC (permalink / raw)
To: Michael Turquette, Vinod Koul
Cc: linux-arm-msm, Bjorn Andersson, Vinod Koul, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
Quoting Vinod Koul (2020-04-23 21:43:11)
> Add the missing ufs card and ufs phy clocks for SM8150. They were missed
> in earlier addition of clock driver.
>
> Signed-off-by: Vinod Koul <vkoul@kernel.org>
> ---
> drivers/clk/qcom/gcc-sm8150.c | 84 +++++++++++++++++++++++++++++++++++
> 1 file changed, 84 insertions(+)
>
> diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> index 5c3dc34c955e..4354620fa12d 100644
> --- a/drivers/clk/qcom/gcc-sm8150.c
> +++ b/drivers/clk/qcom/gcc-sm8150.c
> @@ -2881,6 +2881,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
> },
> };
>
> +/* external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x7501c,
> + .enable_mask = BIT(0),
> + .hw.init = &(struct clk_init_data){
> + .name = "gcc_ufs_card_rx_symbol_0_clk",
Any reason to not use .fw_name?
> + .ops = &clk_branch2_ops,
> + },
> + },
> +};
> +
> +/* external clocks so add BRANCH_HALT_SKIP */
> +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = {
> + .halt_check = BRANCH_HALT_SKIP,
> + .clkr = {
> + .enable_reg = 0x750ac,
> + .enable_mask = BIT(0),
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150
2020-04-25 19:10 ` [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU " Stephen Boyd
@ 2020-04-27 4:41 ` Vinod Koul
0 siblings, 0 replies; 8+ messages in thread
From: Vinod Koul @ 2020-04-27 4:41 UTC (permalink / raw)
To: Stephen Boyd
Cc: Michael Turquette, linux-arm-msm, Bjorn Andersson, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
On 25-04-20, 12:10, Stephen Boyd wrote:
> Quoting Vinod Koul (2020-04-23 21:43:10)
> > Add the GPU and NPU clocks for SM8150. They were missed in earlier
> > addition of clock driver.
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
>
> Fixes tag? That way backporters know they're missing this.
Yes it makes sense to add here, will add.
> > +/* external clocks so add BRANCH_HALT_SKIP */
> > +static struct clk_branch gcc_npu_gpll0_clk_src = {
> > + .halt_check = BRANCH_HALT_SKIP,
> > + .clkr = {
> > + .enable_reg = 0x52004,
> > + .enable_mask = BIT(18),
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gcc_npu_gpll0_clk_src",
> > + .parent_hws = (const struct clk_hw *[]){
> > + &gpll0.clkr.hw },
> > + .num_parents = 1,
> > + .flags = CLK_SET_RATE_PARENT,
> > + .ops = &clk_branch2_ops,
> > + },
> > + },
> > +};
> > +
> > +/* external clocks so add BRANCH_HALT_SKIP */
>
> None of these look external. The parents are all inside this driver. Why
> are we skipping the halt check?
yeah not sure why this got added here, tested and these look fine. I
will update these and send update.
Thanks for the review
--
~Vinod
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: qcom: gcc: Add missing UFS clocks for SM8150
2020-04-25 19:11 ` Stephen Boyd
@ 2020-04-27 4:55 ` Vinod Koul
2020-05-13 1:25 ` Stephen Boyd
0 siblings, 1 reply; 8+ messages in thread
From: Vinod Koul @ 2020-04-27 4:55 UTC (permalink / raw)
To: Stephen Boyd
Cc: Michael Turquette, linux-arm-msm, Bjorn Andersson, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
On 25-04-20, 12:11, Stephen Boyd wrote:
> Quoting Vinod Koul (2020-04-23 21:43:11)
> > Add the missing ufs card and ufs phy clocks for SM8150. They were missed
> > in earlier addition of clock driver.
> >
> > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > ---
> > drivers/clk/qcom/gcc-sm8150.c | 84 +++++++++++++++++++++++++++++++++++
> > 1 file changed, 84 insertions(+)
> >
> > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > index 5c3dc34c955e..4354620fa12d 100644
> > --- a/drivers/clk/qcom/gcc-sm8150.c
> > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > @@ -2881,6 +2881,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
> > },
> > };
> >
> > +/* external clocks so add BRANCH_HALT_SKIP */
> > +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
> > + .halt_check = BRANCH_HALT_SKIP,
> > + .clkr = {
> > + .enable_reg = 0x7501c,
> > + .enable_mask = BIT(0),
> > + .hw.init = &(struct clk_init_data){
> > + .name = "gcc_ufs_card_rx_symbol_0_clk",
>
> Any reason to not use .fw_name?
Did i understand it correct that you would like these to have .fw_name
for parent? Should we start adding these clocks in DT description?
--
~Vinod
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: qcom: gcc: Add missing UFS clocks for SM8150
2020-04-27 4:55 ` Vinod Koul
@ 2020-05-13 1:25 ` Stephen Boyd
2020-05-13 5:51 ` Vinod Koul
0 siblings, 1 reply; 8+ messages in thread
From: Stephen Boyd @ 2020-05-13 1:25 UTC (permalink / raw)
To: Vinod Koul
Cc: Michael Turquette, linux-arm-msm, Bjorn Andersson, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
Quoting Vinod Koul (2020-04-26 21:55:34)
> On 25-04-20, 12:11, Stephen Boyd wrote:
> > Quoting Vinod Koul (2020-04-23 21:43:11)
> > > Add the missing ufs card and ufs phy clocks for SM8150. They were missed
> > > in earlier addition of clock driver.
> > >
> > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > ---
> > > drivers/clk/qcom/gcc-sm8150.c | 84 +++++++++++++++++++++++++++++++++++
> > > 1 file changed, 84 insertions(+)
> > >
> > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > index 5c3dc34c955e..4354620fa12d 100644
> > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > @@ -2881,6 +2881,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
> > > },
> > > };
> > >
> > > +/* external clocks so add BRANCH_HALT_SKIP */
> > > +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
> > > + .halt_check = BRANCH_HALT_SKIP,
> > > + .clkr = {
> > > + .enable_reg = 0x7501c,
> > > + .enable_mask = BIT(0),
> > > + .hw.init = &(struct clk_init_data){
> > > + .name = "gcc_ufs_card_rx_symbol_0_clk",
> >
> > Any reason to not use .fw_name?
>
> Did i understand it correct that you would like these to have .fw_name
> for parent? Should we start adding these clocks in DT description?
>
Sorry I misread the patch. This isn't a parent name description so .name
is correct here.
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] clk: qcom: gcc: Add missing UFS clocks for SM8150
2020-05-13 1:25 ` Stephen Boyd
@ 2020-05-13 5:51 ` Vinod Koul
0 siblings, 0 replies; 8+ messages in thread
From: Vinod Koul @ 2020-05-13 5:51 UTC (permalink / raw)
To: Stephen Boyd
Cc: Michael Turquette, linux-arm-msm, Bjorn Andersson, Andy Gross,
Jonathan Marek, linux-clk, linux-kernel
On 12-05-20, 18:25, Stephen Boyd wrote:
> Quoting Vinod Koul (2020-04-26 21:55:34)
> > On 25-04-20, 12:11, Stephen Boyd wrote:
> > > Quoting Vinod Koul (2020-04-23 21:43:11)
> > > > Add the missing ufs card and ufs phy clocks for SM8150. They were missed
> > > > in earlier addition of clock driver.
> > > >
> > > > Signed-off-by: Vinod Koul <vkoul@kernel.org>
> > > > ---
> > > > drivers/clk/qcom/gcc-sm8150.c | 84 +++++++++++++++++++++++++++++++++++
> > > > 1 file changed, 84 insertions(+)
> > > >
> > > > diff --git a/drivers/clk/qcom/gcc-sm8150.c b/drivers/clk/qcom/gcc-sm8150.c
> > > > index 5c3dc34c955e..4354620fa12d 100644
> > > > --- a/drivers/clk/qcom/gcc-sm8150.c
> > > > +++ b/drivers/clk/qcom/gcc-sm8150.c
> > > > @@ -2881,6 +2881,45 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = {
> > > > },
> > > > };
> > > >
> > > > +/* external clocks so add BRANCH_HALT_SKIP */
> > > > +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = {
> > > > + .halt_check = BRANCH_HALT_SKIP,
> > > > + .clkr = {
> > > > + .enable_reg = 0x7501c,
> > > > + .enable_mask = BIT(0),
> > > > + .hw.init = &(struct clk_init_data){
> > > > + .name = "gcc_ufs_card_rx_symbol_0_clk",
> > >
> > > Any reason to not use .fw_name?
> >
> > Did i understand it correct that you would like these to have .fw_name
> > for parent? Should we start adding these clocks in DT description?
>
> Sorry I misread the patch. This isn't a parent name description so .name
> is correct here.
No worries, I will add fixes and send the update
Thanks
--
~Vinod
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2020-05-13 5:51 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-04-24 4:43 [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU clocks for SM8150 Vinod Koul
2020-04-24 4:43 ` [PATCH 2/2] clk: qcom: gcc: Add missing UFS " Vinod Koul
2020-04-25 19:11 ` Stephen Boyd
2020-04-27 4:55 ` Vinod Koul
2020-05-13 1:25 ` Stephen Boyd
2020-05-13 5:51 ` Vinod Koul
2020-04-25 19:10 ` [PATCH 1/2] clk: qcom: gcc: Add GPU and NPU " Stephen Boyd
2020-04-27 4:41 ` Vinod Koul
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